TLE8110ED [INFINEON]
采用智能电源技术中的 10 通道低端开关，具有串行外设接口和 10 个开漏 DMOS 输出级。TLE8110ED 由嵌入式保护功能提供保护，设计用于汽车和工业应用。输出级通过并联输入引脚控制，用于 PWM 或 SPI 接口。TLE8110ED 特别适用于发动机管理和动力系统。;
| 型号： | TLE8110ED |
| 厂家： | 
Infineon |
| 描述： | 采用智能电源技术中的 10 通道低端开关，具有串行外设接口和 10 个开漏 DMOS 输出级。TLE8110ED 由嵌入式保护功能提供保护，设计用于汽车和工业应用。输出级通过并联输入引脚控制，用于 PWM 或 SPI 接口。TLE8110ED 特别适用于发动机管理和动力系统。 开关 驱动 光电二极管 接口集成电路 |
| 文件： | 总74页 (文件大小：2388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI
Interface
1
Overview
Features
•
•
•
•
•
•
•
•
Overvoltage, Overtemperature, ESD-Protection
Direct Parallel PWM Control of all Channels
safeCOMMUNICATION (SPI and Parallel)
Efficient Communication Mode: compactCONTROL
Compatible with 3.3V- and 5V- Micro Controllers I/O ports
clampSAFE for highly efficient parallel use of the channels
Green Product
AEC Qualified
Potential applications
•
Power Switch Automotive and Industrial Systems switching Solenoids, Relays and Resistive Loads
Product validation
Qualified for Automotive Applications. Product Validation according to AEC-Q100/101.
Description
10-channel Low-Side Switch in Smart Power Technology [SPT] with Serial Peripheral Interface [SPI] and 10
open drain DMOS output stages. The TLE8110ED is protected by embedded protection functions and designed
for automotive and industrial applications. The output stages are controlled via Parallel Input Pins for PWM
use or SPI Interface. The TLE8110ED is particularly suitable for Engine Management and Powertrain Systems.
Type
Package
Marking
TLE8110ED
PG-DSO-36-72
TLE8110ED
Data Sheet
www.infineon.com
1
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Overview
Table 1
Product Summary
Parameter
Symbol
VDD
Value
4.50 ... 5.50
3.00 ... 5.50
55
Unit
V
Analogue Suppy Voltage
Digital Supply Voltage
VCC
V
Clamping Voltage (CH 1-10)
On Resistance maximum at Tj = 25oC and IDnom
VDS(CL)typ
RON1-4
RON5-6
RON7-10
RON1-4
RON5-6
RON7-10
IDnom
V
0.30
Ω
Ω
Ω
Ω
Ω
Ω
A
0.25
0.60
On Resistance maximum at T = 150oC and IDnom
0.60
j
0.50
1.20
Nominal Output current (CH 1-4)
1.50
Nominal Output current (CH 5-6)
IDnom
1.70
A
Nominal Output current (CH 7-10)
IDnom
0.75
A
Output Current Shut-down Threshold (CH 1-4) min.
Output Current Shut-down Threshold (CH 5-6) min.
Output Current Shut-down Threshold (CH 7-10) min.
IDSD(low)
IDSD(low)
IDSD(low)
2.60
A
3.70
A
1.70
A
VBatt
VDD = typ. 5V
Supply IC
VCC = typ. 3.3….5V
RST
Micro
Controller
TLE8110
I/O
I/O
EN
4 to 6
Injectors
or Solenoids
IN1
OUT1
General purpose
Channels in
parallel connection
I/O
IN10
OUT10
SPI_SI
SPI_SO
SPI_CLK
SPI_CS
SPI_SO
General purpose
Channels for Relays
SPI_SI
SPI_CLK
SPI_CS
Appl _Diag_10ch_TLE8110 .vsd
Figure 1
Block Diagram TLE8110ED
Data Sheet
2
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
3.2
3.3
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
4.2
4.3
5
5.1
5.2
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Description Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
6.1
6.2
Reset and Enable Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Description Reset and Enable Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical Characteristics Reset Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Description Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Description of the Clamping Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Electrical Characteristics Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Parallel Connection of the Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1
7.2
7.3
7.4
8
8.1
8.1.1
8.1.2
8.2
Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Diagnosis Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Open Load diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Overcurrent / Overtemperature diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9
9.1
9.2
Parallel Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Description Parallel Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Electrical Characteristics Parallel Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10
Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.1
Electrical Characteristics Overload Protection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11
16 bit SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Description 16 bit SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Electrical Characteristics 16 bit SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.1
11.2
11.3
12
12.1
12.2
12.2.1
12.2.2
12.2.3
Control of the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SPI Interface. Signals and Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Description 16 bit SPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Daisy Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data Sheet
3
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
12.2.3.1
12.2.3.2
12.2.3.3
12.2.3.4
12.2.4
12.2.4.1
12.2.4.2
12.3
16-bit protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2x8-bit protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
16- and 2x8-bit protocol mixed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Daisy-Chain and 2x8-bit protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
safeCOMMUNICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Encoding of the commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Modulo-8 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Register and Command - Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
CMD - Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CMD_RSD - Command: Return Short Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
CMD_RSDS - Command: Return Short Diagnosis and Device Status . . . . . . . . . . . . . . . . . . . . . . . 54
CMD_RPC - Command: Return Pattern Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
CMD_RINx - Command: Return Input Pin (INx) - Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DCC - Diagnosis Registers and compactCONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DRx - Diagnosis Registers Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
DRx - Return on DRx Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
DMSx/OPSx - Diagnosis Mode Set / Output Pin Set Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
OUTx - Output Control Register CHx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
ISx - INPUT or Serial Mode Control Register, Bank A and Bank B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PMx - Parallel Mode Register CHx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DEVS - Device Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
12.3.1
12.3.1.1
12.3.1.2
12.3.1.3
12.3.1.4
12.3.2
12.3.2.1
12.3.2.2
12.3.2.3
12.3.3
12.3.4
12.3.5
12.3.6
13
14
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Data Sheet
4
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Block Diagram
2
Block Diagram
VDD
RST
EN
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
analogue
control,
diagnostic
and protective
functions
temperature
sensor
Input Control
(TTL or CMOS)
short circuit
detection
gate
control
input
register
S_CS
S_CLK
SPI
(TTL or
CMOS)
Logic
control
unit
open load
detection
diagnosis
register
S_SI
S_SO
short to GND
detection
control
register
VCC
Block_diag_10ch_TLE8110.vsd
GND
Figure 2
Block Diagram
2.1
Description
Communication
The TLE8110ED is a 10-channel low-side switch in PG-DSO-36-72 package providing embedded protection
functions. The 16-bit serial peripheral interface (SPI) can be utilized for control and diagnosis of the device and
the loads. The SPI interface provides daisy-chain capability in order to assemble multiple devices in one SPI
chain by using the same number of micro-controller pins 1).
The analogue and the digital part of the device is supplied by 5V. Logic Input and Output Signals are then
compatible to 5V logic level [TTL - level]. Optionally, the logic part can be supplied with lower voltages to
achieve signal compatibility with e.g. 3.3V logic level [CMOS - level].
The TLE8110ED is equipped with 10 parallel input pins that are routed to each output channel. This allows
control of the channels for loads driven by Pulse Width Modulation (PWM). The output channels can also be
controlled by SPI.
Reset
The device is equipped with one Reset Pin and one Enable. Reset [RST] serves the whole device, Enable [EN]
serves only the Output Control Unit and the Power Stages.
1) Daisy Chain
Data Sheet
5
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Block Diagram
Diagnosis
The device provides diagnosis of the load, including open load, short to GND as well as short circuit to VBatt
detection and over-load/ over-temperature indication. The SPI diagnosis flags indicates if latched fault
conditions may have occurred.
Protection
Each output stage is protected against short circuit. In case of over load, the affected channel is switched off.
The switching off reaction time is dependent on two switching thresholds. Restart of the channel is done by
clearing the Diagnosis Register 1). This feature protects the device against uncontrolled repetitive short
circuits.
There is a temperature sensor available for each channel to protect the device in case of over temperature. In
case of over temperature the affected channel is switched off and the Over-Temperature Flag is set. Restart of
the channel is done by deleting the Flag. This feature protects the device against uncontrolled temperature
toggling.
Parallel Connection of Channels
The device is featured with a central clamping structure, so-called CLAMPsafe. This feature ensures a balanced
clamping between the channels and allows in case of parallel connection of channels a high efficient usage of
the channel capabilities. This parallel mode is additionally featured by best possible parameter- and thermal
matching of the channels and by controlling the channels accordingly.
1) Restart after Clear
Data Sheet
6
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
1
2
3
4
5
6
7
8
9
GND
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GND
OUT7
OUT8
P_IN1
P_IN2
EN
N.C.
GND
RST
P_IN3
P_IN4
VDD
OUT5
OUT1
OUT2
P_IN5
VCC
P_IN10
P_IN9
OUT3
OUT4
OUT6
Exposed Pad
(back-side)
10
11
12
13
14
15
16
17
18
S_SO
S_CLK
S_CS
S_SI
GND
N.C.
P_IN6
P_IN7
P_IN8
GND
OUT10
OUT9
GND
Figure 3
Pin Configuration
3.2
Pin Definitions and Functions
Pin
1
Symbol
Function
GND
Ground
2
P_IN1
P_IN2
EN
Parallel Input Pin 1. Default assignment to Output Channel 1
Parallel Input Pin 2. Default assignment to Output Channel 2
Enable Input Pin. If not needed, connect with Pull-up resistor to VCC
Reset Input Pin (active low). If not needed, connect with Pull-up resistor to VCC
Parallel Input Pin 3. Default assignment to Output Channel 3
Parallel Input Pin 4. Default assignment to Output Channel 4
Analogue Supply Voltage
3
4
5
RST
6
P_IN3
P_IN4
VDD
7
8
9
P_IN5
VCC
Parallel Input Pin 5. Default assignment to Output Channel 5
Digital Supply Voltage
10
11
12
13
14
15
S_SO
S_CLK
S_CS
S_SI
Serial Peripheral Interface [SPI], Serial Output
Serial Peripheral Interface [SPI], Clock Input
Serial Peripheral Interface [SPI], Chip Select (active low)
Serial Peripheral Interface [SPI], Serial Input
P_IN6
Parallel Input Pin 6. Default assignment to Output Channel 6
Data Sheet
7
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Pin Configuration
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
P_IN7
P_IN8
GND
Function
Parallel Input Pin 7. Default assignment to Output Channel 7
Parallel Input Pin 8. Default assignment to Output Channel 8
Ground
GND
Ground
OUT9
OUT10
N.C.
Drain of Power Transistor Channel 9
Drain of Power Transistor Channel 10
internally not connected, connect to Ground
Ground
GND
OUT6
OUT4
OUT3
P_IN9
P_IN10
OUT2
OUT1
OUT5
GND
Drain of Power Transistor Channel 6
Drain of Power Transistor Channel 4
Drain of Power Transistor Channel 3
Parallel Input Pin 9. Default assignment to Output Channel 9
Parallel Input Pin 10. Default assignment to Output Channel 10
Drain of Power Transistor Channel 2
Drain of Power Transistor Channel 1
Drain of Power Transistor Channel 5
Ground
N.C.
internally not connected, connect to Ground
Drain of Power Transistor Channel 8
Drain of Power Transistor Channel 7
Ground
OUT8
OUT7
GND
Exposed
Pad
internally not connected, connect to Ground
Note:
The exposed pad of TLE8110ED is not connected to ground pins internally. It is highly recommended
to connect the exposed pad to GND pins on the PCB.
Data Sheet
8
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Pin Configuration
3.3
Terms
VBatt
PG-DSO-36
1
GND
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GND
OUT7
OUT8
IOUT7
IOUT8
IP_IN1
IP_IN
VP_IN1
VP_IN2
VEN
VOUT7
2
P_IN1
P_IN2
2
VOUT8
3
IEN
IRST
4
EN
N.C.
VRST
VP_IN3
VP_IN4
VVDD
5
RST
GND
IP_IN
IP_IN
IVDD
IP_IN5
IVCC
IOUT5
IOUT1
IOUT2
IP_IN10
IP_IN9
3
4
VOUT5
6
P_IN3
P_IN4
VDD
OUT5
OUT1
OUT2
P_IN10
P_IN9
OUT3
OUT4
OUT6
VOUT1
VOUT2
7
8
VP_IN10
VP_IN9
VOUT3
VOUT4
VOUT6
VP_IN5
VVCC
Exposed
Pad
(back-side)
9
P_IN5
VCC
10
11
12
13
14
15
16
17
18
IS_SO
IS_CLK
IS_CS
IS_SI
IOUT3
IOUT4
VS_SO
VS_CLK
VS_CS
S_SO
S_CLK
S_CS
IOUT6
VS_SI
VP_IN6
S_SI
GND
N.C.
IP_IN6
IP_IN7
P_IN6
IOUT10
IOUT9
VP_IN7
VOUT10
P_IN7
P_IN8
GND
OUT10
OUT9
GND
IP_IN8
VP_IN
VOUT9
8
Top View
Terms_TLE8110 .vsd
Figure 4
Terms
Data Sheet
9
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Table 2
Absolute Maximum Ratings 1)
Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
Supply Voltages
Digital Supply voltage
Digital Supply voltage
Analogue Supply voltage
Analogue Supply voltage
Power Stages
VCC
VCC
VDD
VDD
-0.3
-0.3
-0.3
-0.3
–
–
–
–
5.5
6.2
5.5
6.2
V
V
V
V
permanent
t < 10s
P_4.1.1
P_4.1.2
P_4.1.3
P_4.1.4
permanent
t < 10s
Load Current (CH 1 to 10)
IDn
–
–
–
–
–
IDSD(low)
A
A
A
V
–
–
–
–
P_4.1.5
P_4.1.6
P_4.1.7
P_4.1.8
Reverse Current Output (CH 1- 10) IDn
-IDSD(low)
-20
-
Total Ground Current
IGND
VDSn
20
45
Continuous Drain Source Voltage
(Channel 1 to 10)
-0.3
maximum Voltage for short circuit VDSn
protection on Output
–
–
24
V
one event on one
single channel
P_4.1.9
Clamping Energy - Single Pulse 2) 3)
Single Clamping Energy
Channel Group 1-4
EAS
EAS
EAS
–
–
–
–
–
–
29
31
11
mJ ID = 2.6A,
1 single pulse
mJ ID = 3.7A,
1 single pulse
mJ ID = 1.7A,
1 single pulse
P_4.1.10
P_4.1.11
P_4.1.12
Single Clamping Energy
Channel Group 5-6
Single Clamping Energy
Channel Group 7-10
Logic Pins (SPI, INn, EN, RST)
Input Voltage at all Logic Pin
Input Voltage at all Logic Pin
Vx
Vx
-0.3
-0.3
-0.3
–
–
–
5.5
6.2
45
V
V
V
permanent
P_4.1.13
P_4.1.14
P_4.1.15
t < 10s
Input Voltage at Pin 27, 28 (IN9, 10) Vx
permanent
Temperatures
Junction Temperature
Junction Temperature
Tj
Tj
-40
-40
–
–
150
175
oC
oC
–
P_4.1.16
P_4.1.17
max. 100hrs
cumulative
Storage Temperature
Tstg
-55
–
150
oC
–
P_4.1.18
ESD Robustness
Data Sheet
10
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
General Product Characteristics
Table 2
Absolute Maximum Ratings 1) (cont’d)
Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
Electro Static Discharge Voltage
“Human Body Model - HBM”
VESD
-4
–
4
kV All Pins
HBM, 4)
P_4.1.19
1.5KOhm, 100pF
Electro Static Discharge Voltage
“Charged Device Model - CDM”
VESD
VESD
-500
-750
–
–
500
750
V
V
All Pins
P_4.1.20
P_4.1.21
CDM 5)
Electro Static Discharge Voltage
“Charged Device Model - CDM”
Pin 1, 18, 19, 36
(corner pins)
CDM 5)
1) Not subject to production test, specified by design.
2) One single channel per time.
3) Triangular Pulse Shape (inductance discharge): ID(t) = ID(0)·(1 - t / tpulse); 0 < t < tpulse
.
4) ESD susceptibility, HBM according to EIA/JESD 22-A114-B.
5) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101-C.
Note:
Stresses above the ones listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
1. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
4.2
Functional Range
Table 3
Functional Range
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Supply Voltages
Analogue Supply Voltage
Digital Supply Voltage
Digital Supply Voltage
VDD
VCC
VCC
4.5
3
–
–
–
5.5
VDD
5.5
V
V
V
–
–
P_4.2.1
P_4.2.2
VDD
leakage Currents (ICC) might P_4.2.3
increase if VCC > VDD
Power Stages
Ground Current
IGND_typ
9
A
resistive loads 1)
P_4.2.4
Temperatures
Junction Temperature
Junction Temperature
Tj
Tj
-40
-40
–
–
150 oC
175 oC
–
P_4.2.5
P_4.2.6
for 100hrs 1)
1) Not subject to production test, specified by design
Data Sheet
11
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
General Product Characteristics
Note:
Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
4.3
Thermal Resistance
Table 4
Thermal Resistance
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Junction to Soldering Point
Junction to ambient
RthJC
1
1.50
K/W Pvtot = 3W 1) 2)
P_4.3.1
P_4.3.2
3)
Rth_JA
21.5 22
K/W
1) Not subject to production test, specified by design.
2) Homogenous power distribution over all channels (all power stages equally heated), dependent on cooling set-up.
3) Specified Rth_JAvalue is according to JEDEC JESD51 -5, -7 at natural convection on FR4 2s2p board; the product (chip
and package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 μm, 2 x 35 μm CU).
Data Sheet
12
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Power Supply
5
Power Supply
5.1
Description Power Supply
The TLE8110ED is supplied by analogue power supply line VDD which is used for the analogue functions of the
device, such as the gate control of the power stages. The digital power supply line VCC is used to supply the
digital part and offers the possibility to adapt the logic level of the serial output pins to lower logic levels.
VCC
VDD
EN
RST
VCC
VDD
Under
Under
Voltage
Monitor
Voltage
Monitor
or
or
input
register
OUTx
Input
analogue
control,
diagnostic
and protective
functions
and
Serial
Inter-
face
Logic
control
unit
diagnosis
register
Fault
Detection
Gate Control
control
register
GND
Block_diag_Supply_Reset.vsd
Figure 5
Block Diagram Supply and Reset
Description Supply
The Supply Voltage Pins are monitored during the power-on phase and under normal operating conditions for
under voltage.
If during Power-on the increasing supply voltage exceeds the Supply Power-on Switching Threshold, the
internal Reset is released after an internal delay has expired.
In case of under voltage, a device internal reset is performed. The Switching Threshold for this case is the
Power-on Switching threshold minus the Switching Hysteresis.
In case of under voltage on the analogue supply line VDD the outputs are turned off but the content of the
registers and the functionality of the logic part is kept alive. In case of under voltage on the digital supply VCC
line, a complete reset including the registers is performed.
After returning back to normal supply voltage and an internal delay, the related functional blocks are turned
on again. For more details, refer to the chapter “Reset”.
The device internal under-voltage set will set the related bits in SDS (Short Diagnosis and Device Status) to
allow the micro controller to detect this reset. For more information, refer to the chapter “Control of the
Device”.
Data Sheet
13
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Power Supply
5.2
Electrical Characteristics Power Supply
Table 5
Electrical Characteristics: Power Supply
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Digital Supply and Power-on Reset
Digital Supply Voltage
VCC
3
–
–
5.5
20
V
–
P_5.2.1
Digital Supply Current during Reset
ICCstb
15
µA fSCLK = 0Hz,
P_5.2.2
a)
(VCC < VCCpo
)
S_CS = VCC
Tj = 85°C,
,
VCC = 2.0 V,
V
DD > VCC,
1)
b)
–
–
20
2
40
5
µA
fSCLK = 0Hz,
S_CS = VCC
,
Tj = 150°C,
V
V
CC = 2.0V,
DD > VCC
Digital Supply Current during Reset
ICCstb
µA fSCLK = 0Hz,
P_5.2.3
a)
( VRST > VRSTI)
S_CS = VCC
Tj = 85°C,
,
VDD > VCC
,
1)
b)
–
–
–
5
15
2
µA
fSCLK = 0Hz,
S_CS = VCC
Tj = 150°C,
,
V
DD > VCC
Digital Supply Operating Current
ICC
0.15
0.5
0.25
mA fSCLK = 0Hz,
T j= 150°C,
P_5.2.4
a)
VCC = 3.3V
all Channels ON,
1)
b)
5
mA
f
SCLK= 5MHz,
Tj = 150°C,
all Channels ON,
1) 2)
Digital Supply Operating Current
ICC
–
–
2
mA fSCLK = 0Hz,
Tj = 150°C,
P_5.2.5
a)
VCC = 5.5V
all Channels ON
b)
0.8 10
mA
fSCLK = 5MHz,
Tj = 150°C,
all Channels ON,
1) 2)
Digital Supply Power-on Switching
Threshold
VCCpo
1.9 2.8
3
V
VCC increasing
P_5.2.6
Data Sheet
14
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Power Supply
Table 5
Electrical Characteristics: Power Supply
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
P_5.2.7
P_5.2.8
Min. Typ. Max.
100 300 500 mV
1)
Digital Supply Switching Hysteresis
Analogue Supply and Power-on Reset
Analogue Supply Voltage
VCChy
VDD
4.5
–
–
5.5
20
V
–
Analogue Supply Current during Reset
(VDD < VDDpo
IDDstb
10
µA fSCLK = 0Hz,
Tj = 85°C,
P_5.2.9
a)
)
V
DD = 2V,
1)
b)
–
–
15
1
40
5
µA
f
SCLK = 0Hz,
Tj = 150°C,
V
DD = 2V
Analogue Supply Current during Reset
( VEN < VENI
IDDstb
µA fSCLK = 0Hz,
P_5.2.10
a)
)
Tj = 85°C,
1)
b)
–
–
2
8
15
25
µA
f
SCLK = 0Hz,
Tj = 150°C
Analogue Supply Operating Current
IDD
mA fSCLK = 0...5MHz,
Tj = 150°C,
P_5.2.11
all Channels ON,
1)
Analogue Supply Power-on Switching
Threshold
VDDpo
3
4.2 4.5
V
VDD increasing
P_5.2.12
1)
Analogue Supply Switching Hysteresis
Analogue Supply Power-on Delay Time
VDDhy
100 200 400 mV
P_5.2.13
P_5.2.14
tVDDpo
-
100 200 µs VDD increasing,
1)
1) Parameter not subject to production test. Specified by design.
2) C = 50pF connected to S_SO.
Data Sheet
15
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Reset and Enable Inputs
6
Reset and Enable Inputs
6.1
Description Reset and Enable Inputs
The TLE8110ED contains one Reset- and one Enable Input Pin as can be seen in Figure 5.
Description:
Reset Pin [RST] is the main reset and acts as the internal under voltage reset monitoring of the digital supply
voltage VCC: As soon as RST is pulled low, the whole device including the control registers is reset.
The Enable Pin [EN] resets only the Output channels and the control circuits. The content of the all registers is
kept. This functions offers the possibility of a “soft” reset turning off only the Output lines but keeping alive
the SPI communication and the contents of the control registers. This allows the read out of the diagnosis and
setting up the device during or directly after Reset.
6.2
Electrical Characteristics Reset Inputs
Table 6
Electrical Characteristics: Reset Inputs
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit
Note or
Number
Test Condition
Min.
Typ. Max.
Reset Input Pin [RST]
Low Level of RST
VRSTl
-0.3
–
–
V CC*0.2
VCC
V
–
P_6.2.1
P_6.2.2
P_6.2.3
P_6.2.4
High Level of RST
VRSTh
VRSThy
VCC*0.4
20
V
–
1)
RST Switching Hysteresis
Reset Pin pull-down Current
100 300
mV
µA
µA
IRSTresh 20
40
–
85
–
VRST = 5V
IRSTresl
2.4
VRST = 0.6 V,
1)
1)
Required Reset Duration time RST
Enable Input Pin [EN]
Low Level of EN
tRSTmin
2
–
–
µs
P_6.2.5
VENl
-0.3
VCC *0.4
20
-
V *0.2
VCC
300
85
VCC*0.2 –
P_6.2.6
P_6.2.7
P_6.2.8
P_6.2.9
High Level of EN
VENh
-
V
–
1)
EN Switching Hysteresis
Enable Pin pull-down Current
VENhy
IENresh
IENresl
60
35
–
mV
µA
µA
5
VEN = 5V
2.4
–
VEN = 0.6V,
1)
1)
Enable Reaction Time
(reaction of OUTx)
tENrr
–
2
4
–
–
–
µs
µs
P_6.2.10
P_6.2.11
1)
Required Enable Duration time EN
tENmin
1) Parameter not subject to production test. Specified by design.
Data Sheet
16
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Reset and Enable Inputs
VDD
t
Enable
not valid
Enable
valid
VEN
Device OFF
Device ON
VENhy
VENh
VENl
T<
tENmin
t
t
OUTx
Enable of
Output
OUTx OFF
Device
operating
tENrr
tVDDpo
External _reset. vsd
Figure 6
Timing
Data Sheet
17
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Power Outputs
7
Power Outputs
7.1
Description Power Outputs
The TLE8110ED is a 10 channel low-side powertrain switch. The power stages are built by N-channel power
MOSFET transistors. The device is a universal multichannel switch but mostly suited for the use in Engine
Management Systems [EMS]. Within an EMS, the best fit of the channels to the typical loads is:
•
•
•
Channel 1 to 4 for Injector valves or mid-sized solenoids with a nominal current requirement of 1.5A,
Channel 5 to 6 for mid-sized solenoids or Injector valves with nominal current requirement of 1.7A,
Channel 7 to 10 for small solenoids or relays with a nominal current requirement of 0.75A.
Channel 1 to 10 provide enhanced clamping capabilities of typically 55V best suited for inductive loads such
as injectors and valves. It is recommended in case of an inductive load, to connect an external free wheeling-
or clamping diode, where-ever possible to reduce power dissipation.
All channels can be connected in parallel. Channels 1 to 4, 5 to 6 and 7 to 10 are prepared by matching for
parallel connection with the possibility to use a high portion of the capability of each single channel also in
parallel mode (refer to Chapter 7.4).
Channel 5 and 6 have a higher current shut down threshold to allow to connect in parallel mode a load with
high inrush-current, such as a lambda sensor heater.
VCC
VDD
RST
EN
OUT1
OUT2
OUT3
OUT4
IN1
IN2
IN3
gate
control CH1
gate
control CH2
temperature
sensor
OUT5
OUT6
INx
short circuit
detection
input
register
Serial and
Parallel Input
control
(for details , see
Chapter „Control
of the device“ )
OUT7
OUT8
OUT9
OUT10
open load
detection
diagnosis
register
short to GND
detection
control
register
GND
Block _diag_10ch_TLE8x10_Outputs.vsd
Figure 7
Block Diagram of Control and Power Outputs
Data Sheet
18
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Power Outputs
7.2
Description of the Clamping Structure
When switching off inductive loads, the potential at pin OUT rises to VDS(CL) potential, because the inductance
intends to continue driving the current. The clamping voltage is necessary to prevent destruction of the
device, see Figure 8 for the clamping circuit principle. Nevertheless, the maximum allowed load inductance is
limited.
Vbat
L,
RL
ID
OUT
V
DS
V
DScl
GND
OutputClamp.vsd
Figure 8
Internal Clamping Principle
Clamping Energy
During demagnetization of inductive loads, energy has to be dissipated in the device. This energy can be
calculated with following equation:
RL IL
LL
------
RL
VDS(CL) – VBAT
---------------------------------------
RL
æ
ö
ø
----------------------------------------
VDS(CL) – VBAT
E = VDS(CL)
IL –
ln 1 +
(7.1)
è
The maximum energy, which is converted into heat, is limited by the thermal design of the component.
Attention: It is strongly recommended to measure the load Energy and Current under operating
conditions, example of measurement setup is shown in Figure 9. Load small-signal parameters
might not reflect the real load behavior under operating conditions, see Figure 10. For more
details please refer to the Application Note “Switching Inductive Loads”.
Data Sheet
19
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Power Outputs
Temperature Chamber
Oscilloscope
T=TL
Low-Side Switch
OUT
Inductive Load
VCL
iL(t)
LL
RL
vD(t)
Ctrl
VBAT
GND
Load Measurement Setup
Figure 9
ECL measurement setup
Increasing Inductance with IL
Decreasing Inductance with IL
(Relays and some Valve types)
(Injectors, Valves)
Ctrl ON OFF
Ctrl ON OFF
vD, iL
vD, iL
VCL
VCL
IL
ILm
IL
ILm
VBAT
VBAT
VON
VON
t
t
calculated
calculated
measured
R-Temp.
Effect
R-Temp.
Effect
vD · iL
vD · iL
measured
ECL
L-Saturation
Effect
ECL
µ-increase
Effect
ECLm
ECLm
0
0
tF
tFm
t
tFm
tF
t
Deviation from measured values
Figure 10 Deviation of calculation from measurement
Data Sheet
20
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Power Outputs
7.3
Electrical Characteristics Power Outputs
Table 7
Electrical Characteristics: Power Outputs
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Output Channel Resistance
On State Resistance
Channel Group 1-4
RDSon
–
–
–
–
–
–
0.3
0.45 0.6
0.25
0.35 0.5
0.6
0.85 1.2
–
Ohm IDnom = 1.5A,
P_7.3.1
Tj = 25°C 1)
Ohm IDnom = 1.5A,
Tj = 150°C
On State Resistance
Channel Group 5-6
RDSon
–
Ohm IDnom = 1.7A,
Tj = 25°C 1)
P_7.3.2
P_7.3.3
Ohm IDnom = 1.7A,
Tj = 150°C
On State Resistance
Channel Group 7-10
RDSon
–
Ohm IDnom = 0.75A,
Tj = 25°C 1)
Ohm IDnom=0.75A,
Tj = 150°C
Clamping Energy - Repetitive1)2)3)4)
Channel Group 1-4
Repetitive Clamping Energy
EAR
EAR
EAR
–
–
–
–
–
–
11
12
15
mJ
mJ
mJ
ID = 1.0A,
P_7.3.4
P_7.3.5
P_7.3.6
109 cycles
ID = 2.1A,
104 cycles
ID = 2.6A,
10 cycles 5)
Channel 5-6
Repetitive Clamping Energy
–
–
–
–
–
–
13
15
20
mJ
mJ
mJ
ID = 1.3A,
109 cycles
ID = 2.7A,
104 cycles
ID = 3.2A,
10 cycles 5)
Channel 7-10
Repetitive Clamping Energy
–
–
–
–
–
–
4
4
5
mJ
mJ
mJ
ID = 0.7A,
109 cycles
ID = 1.4A,
104 cycles
ID = 1.7A,
10 cycles 5)
Data Sheet
21
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Power Outputs
Table 7
Electrical Characteristics: Power Outputs (cont’d)
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Leakage Current
Output Leakage Current in standby
mode, Channel 1 to 4
IDoff
–
–
–
–
–
–
–
–
–
–
–
–
3
µA
µA
µA
µA
µA
µA
VDS = 13.5V,
VDD = 5V,
P_7.3.7
Tj = 85°C 1)
8
V
V
DS = 13.5V,
DD = 5V,
Tj = 150°C
Output Leakage Current in standby
mode, Channel 5 to 6
IDoff
6
VDS = 13.5V,
P_7.3.8
P_7.3.9
V
DD = 5V,
Tj = 85°C1)
12
2
VDS = 13.5V,
VDD = 5V,
Tj = 150°C
Output Leakage Current in standby
mode, Channel 7 to 10
IDoff
VDS = 13.5V,
V
DD = 5V,
Tj = 85°C1)
5
VDS = 13.5V,
VDD = 5V,
Tj = 150°C
Clamping Voltage
Output Clamping Voltage, Channel 1 to VDScl
10
45
55
60
V
–
P_7.3.10
P_7.3.11
Timing
1)
Output Switching Frequency
fOUTx
–
–
–
5
20
10
kHz
µs
resistive load,
duty cycle > 25%
Turn-on Time
tdON
VDS = 20% of Vbatt P_7.3.12
Vbatt = 13.5V,
IDS1 to IDS6 = 1A,
IDS7 to IDS10 = 0.5A,
resistive load
Turn-off Time
tdOFF
–
5
10
µs
VDS = 80% of Vbatt P_7.3.13
Vbatt = 13.5V,
IDS1 to IDS6 = 1A,
IDS7 to IDS10 = 0.5A,
resistive load
1) Parameter is not subject to production test, specified by design.
2) Either one of the values has to be considered as worst case limitation. Cumulative scenario and wide range of
operating conditions are treated in the Application Note “Switching Inductive Loads - TLE8110 addendum”.
Data Sheet
22
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Power Outputs
3) This lifetime statement is an anticipation based on an extrapolation of Infineon's qualification test results. The actual
lifetime of a component depends on its form of application and type of use etc. and may deviate from such statement.
The lifetime statement shall in no event extend the agreed warranty period.
4) Triangular Pulse Shape (inductance discharge): ID(t) = ID(0)·(1 - t / tpulse); 0 < t < tpulse
.
5) Repetitive operation not allowed. Starting Tj must be kept within specs. In case of high energy pulse an immediate
switch-off strategy is recommended.
RDS_ON /
Ohm
0,6
RON_vs_Tj_CH1-4,6.vsd
RDS_ON vs. Tj: CH 1-4 (VDD=5V)
0,5
0,4
0,3
0,2
-40 -20
0
20 40 60 80 100 120 140 Tj/°C
Figure 11 CH 1-4: typical behavior of RDS_ON versus the junction temperature Tj
RDS_ON /
Ohm
0,5
RON_vs_Tj_CH5-6.vsd
RDS_ON vs. Tj: CH 5-6 (VDD=5V)
0,4
0,3
0,2
0,1
-40 -20
0
20 40 60 80 100 120 140 Tj/°C
Figure 12 CH5-6: typical behavior of RDS_ON versus the junction temperature Tj
Data Sheet
23
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Power Outputs
RDS_ON /
Ohm
1.2
RON_vs_Tj_CH7-10.vsd
RDS_ON vs. Tj: CH 7-10 (VDD=5V)
1.0
0.8
0.6
0.4
-40 -20
0
20 40 60 80 100 120 140 Tj/°C
Figure 13 CH7-10: typical behavior of RDS_ON versus the junction temperature Tj
VCL_vs_Tj_all_CH.vsd
VCL / V
VCLn vs. Tj: all Channels
57
56
55
54
53
-40 -20
0
20 40 60 80 100 120 140 Tj/°C
Figure 14 All Channels: typical behavior of the clamping voltage versus the junction temperature
Data Sheet
24
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Power Outputs
VIN x
VINh
VIN l
VOUTx
t
VBATT
80%
20%
t
tdON
tdOFF
Timing_Power_Outx _res1.vsd
Figure 15 Timing of Output Channel switching (resistive load)
7.4
Parallel Connection of the Power Stages
The TLE8110ED is equipped with a structure which improves the capability of parallel-connected channels.
The device can be “informed” via the PMx.PMx - bits (see chapter “Control of the device”) which of the
channels are connected in parallel. The input channels can be mapped to the parallel connected output
channels in order to apply the PWM signals. This feature allows a flexible adaptation to different load
situations within the same hardware setup.
In case of overload the ground current and the power dissipation is increasing. The application has to take into
account that all maximum ratings are observed (e.g. operating temperature TJ and total ground current IGND
,
see Maximum Ratings). In case of parallel connection of channels with or w/o PM-bit set, the defined
maximum clamping energy must not be exceeded.
All stages are switched on and off simultaneously. The µC has to ensure that the stages which are connected
in parallel have always the same state (on or off). The PM-bit should be set according to the parallel connected
power stages in order to achieve the best possible performance.
The PM-bit is set to its default value in case of a Reset event (Reset pin Low or at Digital Supply undervoltage),
that means the improved Parallel Mode is no longer active. In the event of reset the channels will be switched
off causing the clamping energy to be dissipated with low performance of the current sharing as without PM-
bit set, for more details please refer to the Application Note Switching Inductive Loads - TLE8110 addendum.
The performance during parallel connection of channels is specified by design and not subject to the
production test. All channels at the same junction temperature level.
ON-Resistance
The typical ON-Resistance RDSsum(typ) of parallel connected channels is given by:
–1
1
1
----------------------------- ------------------------------------
RDSsum(typ)
=
+
(7.2)
RDSon, n(typ) RDSon, n + 1(typ)
Data Sheet
25
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Power Outputs
Table 8
Performance 1) 2) 3) 4) in case of Parallel Connection of Channels: related PM-Bit set
Parameter
Symbol
Channels in Parallel Unit Conditions
Number
2x
3x
4x
Channel Group 1-4
Maximum overall current before
reaching lower limit threshold
IDsum(low)
EARsum
5.1
37
17
–
7.6
–
10.1
–
A
P_7.4.1
P_7.4.2
Maximum overall Repetitive
Clamping Energy
mJ ID = 1.0A,
109 cycles
38
23
–
69
42
33
mJ ID = 1.75A,
109 cycles
mJ ID = 2.5A,
109 cycles
–
mJ ID = 3.0A,
109 cycles
Channel Group 5-6
Maximum overall current before
reaching lower limit threshold
IDsum(low)
EARsum
7.2
43
21
–
–
–
–
–
–
A
–
P_7.4.3
P_7.4.4
Maximum overall Repetitive
Clamping Energy
mJ ID = 1.3A,
109 cycles
mJ ID = 2.2A,
109 cycles
Channel Group 7-10
Maximum overall current before
reaching lower limit threshold
IDsum(low)
EARsum
3.3
15
6
5.0
–
6.6
–
A
–
P_7.4.5
P_7.4.6
Maximum overall Repetitive
Clamping Energy
mJ ID = 0.7A,
109 cycles
15
9
30
18
11
mJ ID = 1.2A,
109 cycles
–
mJ ID = 1.6A,
109 cycles
–
–
mJ ID = 2.1A,
109 cycles
1) The performance during parallel connection of channels is specified by design and not subject to the production test.
2) Homogenous power distribution over all channels (all power stages equally heated), dependent on cooling set-up.
3) This lifetime statement is an anticipation based on an extrapolation of Infineon's qualification test results. The actual
lifetime of a component depends on its form of application and type of use etc. and may deviate from such statement.
The lifetime statement shall in no event extend the agreed warranty period.
4) Triangular Pulse Shape (inductance discharge): ID(t) = ID(0)·(1 - t / tpulse); 0 < t < tpulse
.
Data Sheet
26
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Power Outputs
Table 9
Performance 1) 2) 3) 4) in case of Parallel Connection of Channels: related PM-Bit NOT set
Parameter
Symbol
Channels in Parallel Unit Conditions
Number
2x
3x
4x
Channel Group 1-4
Maximum overall current before
reaching lower limit threshold
IDsum(low)
EARsum
5.1
18
8
7.6
–
10.1
–
A
P_7.5.1
P_7.5.2
Maximum overall Repetitive
Clamping Energy
mJ ID = 1.0A,
109 cycles
13
8
19
11
9
mJ ID = 1.75A,
109 cycles
–
mJ ID = 2.5A,
109 cycles
–
–
mJ ID = 3.0A,
109 cycles
Channel Group 5-6
Maximum overall current before
reaching lower limit threshold
IDsum(low)
EARsum
7.2
22
11
–
–
–
–
–
–
A
–
P_7.5.3
P_7.5.4
Maximum overall Repetitive
Clamping Energy
mJ ID = 1.3A,
109 cycles
mJ ID = 2.2A,
109 cycles
Channel Group 7-10
Maximum overall current before
reaching lower limit threshold
IDsum(low)
EARsum
3.3
7
5.0
–
6.6
–
A
–
P_7.5.5
P_7.5.6
Maximum overall Repetitive
Clamping Energy
mJ ID = 0.7A,
109 cycles
3
4
7
mJ ID = 1.2A,
109 cycles
–
3
4
mJ ID = 1.6A,
109 cycles
–
–
3
mJ ID = 2.1A,
109 cycles
1) The performance during parallel connection of channels is specified by design and not subject to the production test.
2) Homogenous power distribution over all channels (all power stages equally heated), dependent on cooling set-up.
3) This lifetime statement is an anticipation based on an extrapolation of Infineon's qualification test results. The actual
lifetime of a component depends on its form of application and type of use etc. and may deviate from such statement.
The lifetime statement shall in no event extend the agreed warranty period.
4) Triangular Pulse Shape (inductance discharge): ID(t) = ID(0)·(1 - t / tpulse); 0 < t < tpulse
.
Data Sheet
27
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Diagnosis
8
Diagnosis
8.1
Diagnosis Description
The TLE8110ED provides diagnosis information about the device and about the load. Following diagnosis flags
have been implemented for each channel:
Diagnosis 1)
Symbol DRn[1:0]x Device reaction
Confirmation
Procedure 3)
2)
Short to Ground
No Fault
SCG
OK
00B
11B
01B
10B
-
-
-
-
-
Open Load
OL
Chapter 8.1.1
Chapter 8.1.2
Overcurrent/
Overtemperature
OCT
Switch-off of related
channel
1) No priority scheme is implemented for the diagnosis detection, any new diagnosis entry will override the previous one.
2) Diagnosis Register (A/B banks) bit configuration, see Chapter 12.3.2.1.
3) For some diagnosis a confirmation procedure is required for a safe operation of the device, refer to Figure 16.
Updating of the Diagnosis is based on a filter-dependent standard delay time (td) of 220µs max. This value is
set as a default. Refer to Figure 17 for details.
If SCG or OL condition is asserted and before the Diagnosis Delay Time (td) is elapsed a condition change
occurs, OL-to-SCG or SCG-to-OL, filter timer is not reset and latest condition before td expiration will be stored
into the diagnosis register.
•
Application Hint: It is recommended to avoid OFF periods of the channel shorter than td(max) (220µs) in
order to ensure the filter time is expired and the correct diagnosis information is stored.
•
Application Hint: In specific application cases - such as driving Uni-Polar Stepper Motor - it might be
possible, that reverse currents flow for a short time, which possibly can disturb the diagnosis circuit at
neighboring channels and cause wrong diagnosis results of those channels. To reduce the possibility, that
this effect appears in a certain timing range, the filter time of Channels 7 to 10 can be extended to typ.
2.5ms or typ. 5ms by setting the “Diagnosis Blind Time” - Bits (DBTx). If Channels 7 to 10 are used for driving
loads causing reverse currents, they influence each other and additionally might affect Channels 5 and 6.
It is recommended to use the channels 7 + 8 and 9 + 10 as pairs for anti-parallel control signals, such as for
the stepper motors. For logic setting details, see chapter “Control of the Device”.
8.1.1
Open Load diagnosis
If an OL is read out of the Diagnosis Register, the following procedure is required in order to confirm the
channel status and ensure a safe operation of the device:
After reading the OL [01B] in the diagnosis register (Chapter 12.3.2)
1. Switch-OFF for t ≥ td(max) the related channel (via serial or direct control, see (Chapter 12.3.3) and
(Chapter 12.3.4),
2. Read again the diagnosis register
a) If OL is confirmed Then take actions according to system implementation,
3. Continue normal operation.
Data Sheet
28
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Diagnosis
Refer to Figure 16 for the procedure flow-chart.
8.1.2
Overcurrent / Overtemperature diagnosis
After an OCT assertion the related channel is switched OFF for safety reasons. If an OCT is read out of the
Diagnosis Register, the following procedure is required in order to confirm the channel status and ensure a
safe operation of the device:
After reading the OCT [10B] in the diagnosis register (Chapter 12.3.2 )
1. Set related bit DEVS.DCCx = 0 to disable OFF-diagnosis, see (Chapter 12.3.6),
2. Clear the Diagnosis issuing a DCC.DRxCL command, see (Chapter 12.3.2),
3. Switch-ON for t ≥ tOFFcl_l(max) the related channel,
4. Read again the diagnosis register
a) If OCT is confirmed Then take actions according to system implementation,
5. Set related bit DEVS.DCCx = 1 to enable OFF-diagnosis,
6. Continue normal operation.
Refer to Figure 16 for the procedure flow-chart.
DCC.DRx
(read diagnosis)
yes
yes
yes
no actions
OK
?
no
no
no
SCG
?
take SCG action
OL
?
wait td
with
(max)
Channel OFF
DCC.DRx
(read Diagnosis)
yes
OL
?
take OL action
no
yes
OCT
?
DEVS.DCCx=0
(disable OFF-diag)
no
DCC.DRxCL
(clear diagnosis)
wait tOFFcl_l(max) with
Channel ON
DCC.DRx
(read Diagnosis)
yes
OCT
?
take OCT action
no
DEVS.DCCx=1
(enable OFF-diag)
Diagnosis Confirmation
Figure 16 Diagnosis Confirmation procedure
Data Sheet
29
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Diagnosis
VDD
IDSsg
MUX
00
01
Diagnosis
Register
OUTn
Latch
Latch
10
IDSpd
VDSsg
VDSol
Temp.
Sensor
gate control
n
n
protective functions
OR
Latch
GND
Diagnosis-serial.vsd
Figure 17 Block Diagram of Diagnosis
8.2
Electrical Characteristics Diagnosis
Table 10
Electrical Characteristics: Diagnosis
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Open Load Diagnosis
Open load detection threshold voltage
VDSol
IDpd
2.00 2.60 3.20
V
–
P_8.2.1
P_8.2.2
Output pull-down diagnosis current per
channel (low level)
50 90
150 µA VDS = 13.5 V
Open Load Diagnosis Delay Time
(all channels)
td
td
100
–
220 µs DEVS.DBT1 = 0
DEVS.DBT2
P_8.2.3
= 1 or 0
Channel 7-10:
1.65 2.5 3.45 ms DEVS.DBT1 = 1
DEVS.DBT2 = 0
P_8.2.4
a)
b)
Open Load Diagnosis Delay Time “Diagnosis
Blind Time” see chapter “Control of the
device”,Figure 18, Figure 19
3.3
5
7.3 ms DEVS.DBT1 = 1
DEVS.DBT2 = 1
Short to GND Diagnosis
Short to ground detection threshold
voltage
VDSsg
IDsg
td
1.00 1.50 2.00
V
–
P_8.2.5
P_8.2.6
P_8.2.7
Output diagnosis current for short to
ground per channel (low level)
-150 -100 -50 µA VDS = 0V
Short to GND Diagnosis Delay Time
100
–
220 µs DEVS.DBT1 = 0
DEVS.DBT2
= 1 or 0
Data Sheet
30
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Diagnosis
Table 10
Electrical Characteristics: Diagnosis
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Channel 7-10:
td
1.65 2.5 3.45 ms DEVS.DBT1 = 1
DEVS.DBT2 = 0
P_8.2.8
a)
b)
Short to GND Diagnosis Delay Time.
“Diagnosis Blind Time” see chapter
“Control of the device”,Figure 18,
Figure 19
3.3
5
7.3 ms DEVS.DBT1 = 1
DEVS.DBT2 = 1
Diagnosis Blind Time[DBT] activation
DBT is triggered by Open Load [OL] or Short-to-Ground [SG] -detection during OFF-condition of CH7-10.
DBT is activated by DEVS.DBT1, DEVS.DBT2 (see „Control of the device“).
INx Signal
Channel 7 - 10
OFF
OL, SG -Diagnosis active
ON
Output
Voltage
Incident - e.g.
temporal „short to GND“
[SG]
Diagnosis Blind Time
[DBT]
triggered by
Diagnostic Incident
Diagnosis Blind Time
Diagnostic Register Entry,
because Failure present
after ending DBT
[DBT]
active
DBT
terr
tDBT
<
terr<
tDBT
terr >
tDBT
„Blind“ window finishes as
soon as the error
disappears within the DBT
Diagnosis Register:
11: No Error
10: Over Load
01: Open Load
00: Short to Ground
1 1
1
1
1 1
0 0
DBT.vsd
Figure 18 Diagnosis Blind Time
Data Sheet
31
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Diagnosis
Channel
OFF
YES
OL, SG-
Error
present?
YES
OL, SG-
Error
detected
DBT
Counter
SET 0 = tDBT
Decrement
DBT Counter
OL, SG-
Error
present?
Reset Counter
(finish DBT-
frame)
No
Yes
No
Counter
t > tDBT
Yes
Failure detected
=> Register Entry
DBT_Flow.vsd
Figure 19 Diagnosis Blind Time - Logic Flow
Data Sheet
32
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Parallel Inputs
9
Parallel Inputs
9.1
Description Parallel Inputs
There are 10 input pins available are on TLE8110ED to control the output stages.
Each input signal controls the output stages of its assigned channel. For example, IN1 controls OUT1, IN2
controls OUT2, etc.
A “Low”-Signal at INx switches the related Output Channel off. The zener diode protects the input circuit
against ESD pulses.
For details about the Boolean operation, refer to the chapter “Control of the device”, for details about timing
refer to Figure 11.
9.2
Electrical Characteristics Parallel Inputs
Table 11
Electrical Characteristics: Parallel Inputs
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
Parallel Inputs
Low Level of parallel Input pin
VINxl
-0.3
–
VCC*0.2 V
–
P_9.2.1
High Level of Parallel Input pin
VINxh
VCC*0.4 –
VCC
V
–
P_9.2.2
P_9.2.3
1)
Parallel Input Pin Switching Hysteresis
VINxhy
–
15
20
2.4
60
300
mV
Input Pin pull-down Current
IINxh
40
–
85
–
µA VINx = 5V
P_9.2.4
a)
b)
IINxl
µA VINx = 0.6V 1)
1) Parameter not subject to production test. Specified by design.
Data Sheet
33
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Protection Functions
10
Protection Functions
The device provides embedded protective functions. Integrated protection functions are designed to prevent
IC destruction under fault conditions described in this Document. Fault conditions are considered “outside”
the normal operating range. Protection functions are not designed for continuous repetitive operation.
There is an over load and over temperature protection implemented in the TLE8110ED.
If a protection function becomes active during the write cycle of Diagnosis Information into the Diagnosis
Register, the information is latched and stored into the diagnosis register after the write process.
In order to achieve a maximum protection, the affected channel with over current or over temperature (OCT)
is switched and latched OFF, channel can be turned ON again after the diagnosis register is cleared
(Chapter 12.3.2).
For the failure condition of Reverse Currents, the device contains a “Reverse Current Protection Comparator”
[RCP]. This RCP can optionally be activated by setting the DEVS.RCP Bit.
In case the comparator is activated, it detects a reverse current and switches ON the related output channel.
The channel is kept ON up to a reverse current channel dependent threshold IRCP_off. This threshold is defined
by regulators target value to keep the output voltage at >/~-0.3V. If the current exceeds a defined value, the
comparator switches OFF and other protection functions are protecting the circuit against reverse current.
That means that at higher currents / or in case RCP is de-activated / not activated, the reverse current is
flowing through the body diode of the DMOS. In that case, the voltage drops to typically -0.6V according the
voltage of the body diode. In case the comparator threshold has been exceeded and the RCP has been
switched OFF, the functions remains OFF until the reverse current arrives back to zero reverse current. Only
then, the comparator can be activated again after a delay time tRCP_on_delay
.
This function reduces the un-wanted influence of a reverse current to the analogue part of the circuit (such as
the diagnosis). For more details about the functionality, see Figure 22 and Figure 23 and concerning the
settings and the related registers, refer to Chapter “Control of the Device”.
RCP
Ref.
-300mV
Logic
Ctrl.
temperature
sensor
OUTx
T
gate
control
Serial
control
short circuit
detection
Block_diag_Protection.vsd
Figure 20 Block Diagram Protection Functions
Data Sheet
34
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Protection Functions
IDS
tOFFcl_l
tOFFcl_h
switch-off after tOFFcl_h (short) with
switch-off after tOFFcl_l (long)
I >IDSD(high)
if I falls below IDSD(high) before tOFFcl_h
IDSD(high)
switch-off after tOFFcl_l (long) with I >IDSD(low)
immediate switch-off if I=IDSD(high) after tOFFcl_h
IDSD(low)
no switch-off with I <IDSD(low)
t
Filter timer is started at IDSD(low) threshold and stopped:
•
at
t
t
=
tOFFcl_h if at IDSD(high)
t
=
tOFFcl_h
I
>
•
at
=tOFFcl_l if IDSD(low) < I < IDSD(high)
Overload shutdown thresholds and delay times
Figure 21 Overload shutdown thresholds and delay times
10.1
Electrical Characteristics Overload Protection Function
Table 12
Electrical Characteristics: Overload Protection Function
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Min. Typ.
Unit Note or
Test Condition
Number
Max.
Over Current Protection
Output Current Shut-down
Threshold Low (Channel 1 to 4)
IDSD(low) 2.6 3.8
5
A
A
A
A
A
A
–
P_10.1.1
P_10.1.2
P_10.1.3
P_10.1.4
P_10.1.5
P_10.1.6
Output Current Shut-down
Threshold Low (Channel 5 to 6)
IDSD(low) 3.70 4.85
IDSD(low) 1.7 2.3
6.00
2.9
–
–
Output Current Shut-down
Threshold Low (Channel 7 to 10)
–
1)
Output Current Shut-down
Threshold High (Channel 1 to 4)
IDSD(high)
IDSD(high)
IDSD(high)
–
–
–
5
1.5 * IDSD (low)
1.5 * IDSD (low)
1.5 * IDSD (low)
21
1)
1)
Output Current Shut-down
Threshold High (Channel 5 to 6)
–
Output Current Shut-down
Threshold High (Channel 7 to 10)
–
Short Overload shutdown Delay tOFFcl_h
Time (all Channels)
40
µs valid for “Output P_10.1.7
Current Threshold
High” 1)
Data Sheet
35
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Protection Functions
Table 12
Electrical Characteristics: Overload Protection Function (cont’d)
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Min. Typ.
Unit Note or
Test Condition
Number
Max.
Long Overload shutdown Delay tOFFcl_l
Time (all Channels)
10 40
70
µs valid for “Output P_10.1.8
Current Threshold
Low”
Over Temperature Protection
1)
Thermal Shut Down Temperature TjSD
175 190
205 °C
P_10.1.9
1)
Thermal Shut Down Hysteresis
TjSDh
10
–
20
K
P_10.1.10
Reverse Current Protection
Reverse Current Comparator
Switch-off Current level CH 1 - 4
IRCP_off
IRCP_off
IRCP_off
–
–
–
–
-0.9
-0.6
-0.45
24
–
–
–
–
A
A
A
DEVS.RCP = 1,
P_10.1.11
P_10.1.12
P_10.1.13
P_10.1.14
Tj = 25°C 1)
Reverse Current Comparator
Switch-off Current level CH 5 - 6
DEVS.RCP = 1,
Tj = 25°C 1)
Reverse Current Comparator
Switch-off Current level CH 7 - 10
DEVS.RCP = 1,
Tj = 25°C 1)
Reverse Current Comparator
switch on delay time
tRCP_on_
µs DEVS.RCP = 1,
Tj = 25°C 1)
delay
1) Parameter not subject to production test. Specified by design.
Data Sheet
36
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Protection Functions
ID
Leakage
(neighbour
channel)
RCP not active
RCP active
Reverse
Current
Comparator
Switch-off
Current level
Reverse Current
IRCP_off
ID
0
t
Reverse Current
Comparator
Switch-off
Current level
IRCP_off
Maximum
Rating
-
IDSD(low)
VD
VBatt
0
t
~ - 300mV
tRCP_on_delay
RCP active:
Regulation to
VD ~ - 300mV;
-ID through DMOS
RCP not active:
ID through Body
Diode of DMOS
RCP.vsd
Figure 22 Reverse Current Protection Comparator 6
Data Sheet
37
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Protection Functions
-40
-20
0
20
40
60
80
100
120
140
Tj / °C
-0.1
CH7-10
-0.3
-0.5
-0.7
-0.9
-1.1
-1.3
-1.5
CH1-6
IRCP_OFF_TC_12_ch.vsd
IRCP_off /A
Figure 23 Reverse Current Protection Comparator (typical behavior vs. junction temperature)
Data Sheet
38
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
16 bit SPI Interface
11
16 bit SPI Interface
11.1
Description 16 bit SPI Interface
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: S_SO, S_SI, S_CLK and S_CS.
Data is transferred by the lines S_SI and S_SO at the data rate given by S_CLK. The falling edge of S_CS
indicates the beginning of a data access. Data is sampled in on line S_SI at the falling edge of S_CLK and shifted
out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of S_CS. A modulo
8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. If in one transfer cycle
not a multiple of 8 bits have been counted, the data frame is ignored. The interface provides daisy chain
capability.
MSB 14
MSB 14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
LSB
LSB
S_SO
S_SI
S_CS
S_CLK
time
SPI.vsd
Figure 24 16 bit SPI Interface
The SPI protocol is described in Chapter “Control of the device”. Concerning Reset of the SPI, please refer to
the chapter “Reset”.
11.2
Timing Diagrams
t CS lead
t CSlag
t CStd
t
SCLKp
0.7V
dd
S_CS
S_CLK
S_SI
0.2V
dd
t
t
SCLKl
SCLKh
0.7V
dd
0.2V
dd
t
t SIh
SIsu
0.7V
dd
0.2V
dd
t
t SOv
t SOdis
SO(en)
0.7V
dd
S_SO
0.2V
dd
Timing SPI.vsd
Figure 25 SPI timing diagram
Data Sheet
39
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
16 bit SPI Interface
11.3
Electrical Characteristics 16 bit SPI Interface
Table 13
Electrical Characteristics: 16 bit SPI Interface
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
Input Characteristics (CS, SCLK, SI)
L level of pin
S_CS,
S_CLK,
S_SI,
-0.3
–
–
VCC* 0.2 V
–
–
–
P_11.3.1
VS_CSI
VS_CLKl
VS_SIl
H level of pin
S_CS,
S_CLK,
S_SI,
VCC* 0.4
VCC
V
P_11.3.2
P_11.3.3
VS_CSh
VS_CLKh
VS_SIh
Hysteresis Input Pins
VS_CShy 20
VS_CLKhy
100 300
mV
VS_SIhy
Input Pin pull-down Current
S_CLK, S_SI
IS_CLKh 20
IS_Slh
40
–
85
–
µA VIN = 5V
P_11.3.4
a)
b)
IS_CLKl
IS_Slh
IS_CSh
2.4
-4
µA VIN = 0.6V 1)
Input Pin pull-up Current
S_CS
–
–
µA VS_CS = 2V,
P_11.3.5
a)
b)
VCC = 5V
IS_CSl
-20
-40 -85
µA VS_CS = 0 V,
VCC = 5V
Output Characteristics (SO)
L level output voltage
VS_SOl
VS_SOh
0
–
–
0.4
V
–
IS_SO = -2 mA
IS_SO = 1.5 mA
P_11.3.6
P_11.3.7
H level output voltage
Vcc
-
Vcc
0.4 V
Output tristate leakage current
Timings
IS_SOoff -10
–
10
µA VS_SO = Vcc
P_11.3.8
Serial clock frequency
Serial clock period
Serial clock high time
Serial clock low time
fS_CLK
0
–
–
–
–
–
5
–
–
–
–
MHz CL = 50 pF 1)
P_11.3.9
1)
tS_CLK(P) 200
tSCLK(H) 50
tSCLK(L) 50
ns
P_11.3.10
P_11.3.11
P_11.3.12
P_11.3.13
1)
ns
1)
ns
1)
Enable lead time (falling CS to rising tCS(lead) 250
ns
SCLK)
1)
Enable lag time (falling SCLK to rising tCS(lag)
CS)
250
250
–
–
–
–
ns
P_11.3.14
P_11.3.15
1)
Transfer delay time (rising CS to
falling CS)
tCS(td)
ns
Data Sheet
40
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
16 bit SPI Interface
Table 13
Electrical Characteristics: 16 bit SPI Interface (cont’d)
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
1)
Data setup time (required time SI to tSI(su)
20
–
–
ns
P_11.3.16
falling SCLK)
1)
Data hold time (falling SCLK to SI)
tSI(h)
20
–
–
–
–
ns
P_11.3.17
P_11.3.18
Output enable time (falling CS to SO tSO(en)
valid)
200
ns CL = 50 pF 1)
ns CL = 50 pF 1)
ns CL = 50 pF 1)
Output disable time (rising CS to SO tSO(dis)
tri-state)
–
–
–
–
200
100
P_11.3.19
P_11.3.20
Output data valid time with
capacitive load
tSO(v)
tDidle
1)
Diagnosis Clear-to-Read Idle Time
16
12
–
–
–
–
µs
P_11.3.21
P_11.3.22
1)
Diagnosis Overcurrent-to-Clear Idle tOCidle
µs
Time
1) Not subject to production test, specified by design.
Data Sheet
41
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
12
Control of the device
This chapter describes the SPI-Interface signals, the protocol, registers and commands. Reading this chapter
allows the Software Engineer to control the device. The chapter contains also some information about
communication safety features of the protocol.
12.1
Internal Clock
The device contains an internal clock oscillator.
Table 14 Electrical Characteristics: Internal Clock
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Parallel Inputs
1)
internal clock oscillator frequency fint_osc
-
500
-
kHz
1) Parameter not subject to production test. Specified by design.
12.2
SPI Interface. Signals and Protocol
12.2.1
Description 16 bit SPI Interface Signals
S_CS - Chip Select:
The system micro controller selects the TLE8110ED by means of the S_CS pin. Whenever the pin is in low state,
data transfer can take place. When S_CS is in high state, any signals at the S_CLK and S_SI pins are ignored
and S_SO is forced into a high impedance state.
S_CS High to Low transition:
•
The information to be transferred loaded into the shift register (16-bit Protocol).
S_CS Low to High transition:
•
Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3...) of eight
S_CLK signals have been detected. (See Modulo-8 Counter: Chapter 12.2.4.2).
S_CLK - Serial Clock:
This input pin clocks the internal shift register. The serial input (S_SI) transfers data is shifted into register on
the falling edge of S_CLK while the serial output (S_SO) shifts the information out on the rising edge of the
serial clock. It is essential that the S_CLK pin is in low state whenever chip select CS makes any transition.
S_SI - Serial Input:
Serial input data bits are shifted in at this pin, the most significant bit first. The bit at the S_SI Pin is read on the
falling edge of S_CLK.
S_SO Serial Output:
Data is shifted out serially at this pin, the most significant bit first. S_SO is in high impedance state until the
S_CS pin goes to low state. The next bits will appear at the S_SO is in high impedance state until the S_CS goes
to low state. The next bits will appear at the S_SO pin following the rising edge of S_CLK.
Data Sheet
42
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
12.2.2
Daisy Chain
The SPI-Interface of TLE8110ED provides daisy chain capability, see Chapter 12.2.3.4 for more details. In this
configuration several devices are activated by the same S_CS signal. The S_SI line of one device is connected
with the S_SO line of another device (see Figure 26), which builds a chain. The ends of the chain are connected
with the output and input of the master device, S_SO and S_SI respectively. The master device provides the
master clock CLK, which is connected to the S_CLK line of each device in the chain. By each clock edge on
S_CLK, one bit is shifted into the S_SI. The bit shifted out can be seen at SO. After 16 S_CLK cycles, the data
transfer for one device has been finished. In single chip configuration, the S_CS line must go high to make the
device accept the transferred data. In daisy chain configuration the data shifted out at device 1 has been
shifted in to device 2. Example: When using three devices in daisy chain, three times 16 bits have to be shifted
through the devices. After that, the S_CS line must go high (see Figure 26).
SO device 3
SI device 3
SO device 2
SI device 2
SO device 1
SI device 1
SI
SO
CS
CLK
time
SPI_DasyChain2.emf
Figure 26 Principle example for Data Transfer in Daisy Chain Configuration
Note:
Due to the integrated modulo 8 counter, 8 bit and 16 bit devices can be used in one daisy chain.
12.2.3
SPI Protocol
The device contains two protocol styles which are applied dependent of the used commands. There is the
standard 16-bit protocol and the 2x8-bit protocol. Both protocols can appear also be mixed.
12.2.3.1 16-bit protocol
Each cycle where a serial data or command frame is sent to the S_SI of the SPI interface, a data frame is
returned at the same time by the S_SO. The content of the S_SO frame is dependent on the previous command
which has been sent to S_SI. Read Command (R/W = R) returns one cycle later the content of the address
register (see Figure 27).
R
ADR / DATA
W
ADR / DATA
Register
R
ADR / DATA
S_SO
dept. of
previous R/W
Short Diagnosis*
SPI_Protocol_Normal_Mode.vsd
* dependent on ADR; In case CMD or DCC is addressed, related content.
Figure 27 16-bit protocol
Data Sheet
43
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
16-bit protocol
S_SI Serial Input
15
14
13
12
12
11
11
10
10
9
9
8
8
7
7
6
5
4
3
2
2
1
1
0
0
W/R
ADDR
DATA/CMD
S_SO Serial Output
1)
Reset value: xxxx xxxx xxxx xxxxB
15
14
13
6
5
4
3
PAR
ADDR
DATA
1) after reset a Short Diagnosis and Device Status CMD_CSDS response is sent, see Chapter 12.3.1.2.
Bit description
Field
Bits
Type
Function
S_SI Serial Input
W/R
15
Write/Read
0
Write register: The register content of the addressed register
will be updated aꢀer CS low → high transition. Aꢀer sending a
WRITE command, the device returns data according the
addressed register,
1
Read register: The register content of the addressed register
will be sent in the next frame.
ADDR
[14:12]
ADDR - Address
Pointer to register for read and write command.
DATA/CMD [11:0]
DATA_CMD - Data / Command
Data written to or read from register selected by address ADDR.
S_SO Serial Output
PAR
15
PAR - Parity Bit
0
1
Even number of ‘1’ in data and address field,
Odd number of ‘1’ in data and address field.
ADDR
DATA
[14:12]
[11:0]
Address
Address which has been addressed.
Data
Content of Address or feedback data.
Note:
Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second
frame the output at SPI signal SO will contain the requested information. A new command can be
executed in the second frame.
Data Sheet
44
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
12.2.3.2 2x8-bit protocol
Each Cycle where a serial data or command frame is sent to the S_SI of the SPI interface, a data frame is
returned at the same time by the S_SO. The content of the S_SO frame is dependent of the previous command
which has been sent to S_SI and the content of the actual content of S_SI: The first Upper Byte send to S_SI
controls the content of the Lower Byte actual returned by S_SO. The Lower Byte send to S_SI controls the
Lower Byte in S_SO of the next frame (see Figure 28).
S_CS
S_SI
Upper
Byte
Lower
Byte
Upper
Byte
Lower
Byte
DMSx
OPSx
DO
S_SO
Upper
Byte
Lower
Byte
Upper
Byte
Lower
Byte
OPF
SPI_Protoco_lShort_Mode.vsd
Figure 28 2x8-bit protocol
2x8-bit protocol
S_SI Serial Input
15
14
13
12
11
10
9
9
8
8
7
7
6
5
4
3
2
2
1
1
0
0
Upper Byte
Lower Byte
S_SO Serial Output
15 14 13
1)
Reset value: xxxx xxxx xxxx xxxxB
12
11
10
6
5
4
3
Upper Byte
Lower Byte
1) after reset a Short Diagnosis and Device Status CMD_CSDS response is sent, see Chapter 12.3.1.2.
Bit description
Field
Bits
Type
Function
S_SI Serial Input
Upper Byte [15:8]
Upper Byte
Contains the command, which is performed after sending 8 bit to
S_SI. The action out of this command is affecting the Lower Byte of
S_SO of the actual communication frame.
Lower Byte [7:0]
Lower Byte
Containsthe command and data, which is performed at the end of
the actual communication frame. The action out of this command
is affection the Upper Byte of S_SO of next communication frame.
Data Sheet
45
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
Bit description
Field
Bits
Type
Function
S_SO Serial Output
Upper Byte [15:8]
Upper Byte
Contains the data according the command and data in the Lower
Byte of the previous communication frame.
Lower Byte [7:0]
Lower Byte
Contains the data according the command in the Upper Byte of the
actual communication frame.
Note:
Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second
frame the output at SPI signal SO will contain the requested information. A new command can be
executed in the second frame.
12.2.3.3 16- and 2x8-bit protocol mixed
The 16-bit and 2x8-bit protocols are mixed according the used commands (see Chapter 12.3.1). Special care
should be taken,changing from the 16-bit protocol to the 2x8-bit protocol. In this case, it is important to send
a NOP command to S_SI. Otherwise, by sending instead a Command, a collision between the S_SO data in the
following frame and the Lower Byte of the 2x8-bit protocol will happen (see Chapter 12.2.3.2).
Protocol Change from2x8-bit to16-bit
S_CS
S_SI
Upper
Byte
Lower
Byte
CMD
CMD
Data
S_SO
Upper
Byte
Lower
Byte
Upper
0
Byte
Protocol Change from16-bit to 2x8-bit
S_CS
S_SI
Upper
Byte
Lower
Byte
Upper
Byte
Lower
Byte
NOP
S_SO
Lower
Byte
Upper
Byte
Lower
Byte
Data
0
Critical Protocol Change from16-bit to2x8-bit
S_CS
2x8-bit protocol is
dominant
S_SI
Upper
Byte
Lower
Byte
Upper
Byte
Lower
Byte
CMD
S_SO
Lower
Byte
Upper
Byte
Lower
Byte
Data
Data...
collission
SPI_Protoco_l 16_2x8bit_mixed.vsd
Figure 29 16-bit protocol and 8bit protocol mixed
Data Sheet
46
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
12.2.3.4 Daisy-Chain and 2x8-bit protocol
when using the TLE8110ED in a daisy-chain connection with other devices (TLE8110ED and non) special care
has to be taken to avoid interference of 2x8-bit protocol with normal communication. Few simplifed rules
must be followed for a safe SPI communication in daisy-chain environment:
1. All TLE8110ED devices have to be routed at the beginning of the chain, other devices than TLE8110ED
afterward.
2. compactCONTROL commands (2x8-bit protocol) must not be addressed to TLE8110ED.
3. The SPI frame of the daisy-chain must be extended of additional 8-bit (all zeros 00H) at befinning of the
frame.
4. When a Read/Clear Diagnosis Register A command(DRA, DRACL) is addressed to TLE8110ED, a NOP
command must be sent to the next TLE8110ED on the chain.
5. When a Read/Clear Diagonosis Register A command (DRA, DRACL) is addressed to TLE8110ED, response of
the next device on the chain must be ignored in the next SPI cycle.
Details in Figure 30 and Figure 31.
Critical Communication with first 8-bit interpreted as compactCONTROL (2x8-bit protocol)
SPI daisy-chain word
S_CS
first 8-bit that could interfere with
compacCONTROL of device 1
S_SI
to dev.n
to dev.1
S_SO
from dev.n
from dev.1
lower-byte from dev.n affected by the
reaction of dev.1 to compactCONTROL
t
Safe Communication with first all zeros 8-bit extension
SPI daisy-chain word
S_CS
all zeros 8-bit extension
00H
S_SI
to dev.n
to dev.1
S_SO
from dev.n
from dev.1
last 8-bit to be ignored
t
Daisy-Chain and 2x8-bit protocol
Figure 30 Daisy-Chain and 2x8-bit protocol
Data Sheet
47
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
Critical Communication with dev.n+1 response altered by dev .n response to previous DRA /DRACL
SPI daisy-chain word
SPI daisy-chain word
S_CS
S_SI
x-command
DRA/DRACL
to dev.n
to dev.n+1
to dev.n+1
to dev.n
S_SO
from dev.n+1
from dev.n
from dev.n+1
from dev.n
response to x-command response to DRA-/CL
8-bit altered by dev.n response to DRA-/CL
t
Safe Communication with NOP command send to dev .n+1 and ignored response
SPI daisy-chain word SPI daisy-chain word
S_CS
S_SI
NOP
DRA/DRACL
to dev.n
to dev.n+1
to dev.n+1
to dev.n
S_SO
from dev.n+1
from dev.n
from dev.n+1
from dev.n
response to DRA-/CL
no response expected
ignored
t
DRA, DRACL to dev .n and NOP command to dev .n+1
Figure 31 DRA, DRACL to dev.n and NOP command to dev.n+1
12.2.4
safeCOMMUNICATION
The device contains some safety features, which are improving the protection of the application against mal-
function in case of disturbance of the communication between the Micro Controller and the Device:
12.2.4.1 Encoding of the commands
The Commands are encoded. In case other bit-patterns, then the defined once are received, the commands
are ignored and the communication error can be read out with the command CMD_RSDS (see
Chapter 12.3.1.2).
12.2.4.2 Modulo-8 Counter
The modulo is the integral remainder in integral division. In data communications, a modulo based approach
is used to ensure that user information in SPI protocols is in the correct order. The device has a receiver-side
counter, and a defined counter size. The modulo counter specifies the number of subsequent numbers
available. In case of TLE8110ED Modulo 8 counter specifies 8 serial numbers. The modulo 8 counter ensures
that data is taken only, when a multiple of 8 bit has been transferred. If in one transfer cycle not a multiple of
Data Sheet
48
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
8 bits have been counted, the data frame is ignored and a Communication Error is indicated in the CMD_RSDS
- Feedback (see Chapter 12.3.1.2).
12.3
Register and Command - Overview
This chapter describes the Registers and Commands. The commands allow to carry through some actions,
such as reading out or clearing the diagnosis or reading out the Input Pins.
Specially highlighted here should be the encoded CMD_DMSx/OPSx commands - compactCONTROL -, a highly
efficient command-set to set a part of the output pins and read out the diagnosis at the same time. Included
in this command set is the possibility to check, if the communication works well as also the possibility to read-
out some of the parallel Input Pins INx. Using this compact command set can reduce the workload of the
micro-controller during run-time significantly.
CMD_RSD is preformed and short diagnostics [SD] is returned after each Write Cycle to any of the writable
registers.
After start-up of the device, the registers are loaded with the default settings as described below in the register
descriptions. The Registers are cleared and set back to the default values, when a low signal is applied to the
pin RST or an under-voltage condition appears at the supply pin VCC what causes an under-voltage reset. If a
low signal at pin EN is applied or an under-voltage condition appears at pin VDD, the Registers are not cleared.
Table 15
Name
CMD
Command Overview
Type
W 1)
Addr.
000B
001B
010B
011B
100B
101B
110B
111B
Short Description
see:
Commands
Chapter 12.3.1
Chapter 12.3.2
Chapter 12.3.3
Chapter 12.3.6
-
DCC
W 1)
Diagnosis Registers and Compact Control
Output Control Register CHx
Device Settings
OUTx
DEVS
MSCS
ISAx
W/R
W/R
W/R
W/R
W/R
W/R
Reserved
Input or Serial Mode Register CHx Bank A
Input or Serial Mode Register CHx Bank B
Parallel Mode Control of CHx with CHy
Chapter 12.3.4
Chapter 12.3.4
Chapter 12.3.5
ISBx
PMx
1) if a read command is sent, the command is ignored and S_SO returns a frame with ’0’.
Table 16
Register Overview
Nam
e
Addr 11
.
10
9
8
7
6
5
4
3
2
1
0
def.
1)
CMD W 2) 000B
DCC W 2) 001B Command
0
1
1
1
Command
-
-
OUTx W/R 010B
1
1
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT C00H
10
9
8
7
6
5
4
3
2
1
DEVS W/R 011B RCP DBT2 DBT1 0
0
0
0
0
0
DCC DCC DCC 007H
10
9
18
MSCS W/R 100B Reserved
000H
AAAH
ISAx W/R 101B IS6
IS5
IS4
IS3
IS2
IS1
Data Sheet
49
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
Table 16
Register Overview
Nam
e
Addr 11
.
10
9
8
7
6
5
4
3
2
1
0
def.
1)
ISBx W/R 110B
PMx W/R 111B
0
0
0
0
0
0
0
0
IS10
PM
910 89
IS9
IS8
0
IS6
0AAH
000H
PM
PM
78
PM
56
PM
34
PM
23
PM
12
1) Default values after Reset.
2) if a read command is sent, the command is ignored and S_SO returns a frame with ’0’.
Data Sheet
50
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
IS1[1:0]:
AND IN/Serial-Mod0 = 11
IN-Mode = 10
Serial-Mode OUT1=1 = 01
Serial-Mode OUT1=0 = 00
DC18[0]:
Diagn. current off = 0
Diagn. Current on = 1
IS1[1:0]
OUT1
OUT2
11
IN1
IN2
IN3
IN4
10
0x
OUT1
IS2[1:0]
11
PM12=1
PM12=0
10
0x
OUT2
OUT3
PM23=1
PM23=0
OUT6
CH5
PM56=1
PM56=0
OUT7
OUT8
PM78=1
PM78=0
IS10[1:0]
OUT10
CH9
11
PM910=1
PM910=0
IN10
10
0x
OUT
10
Logic_Output_Control_CORE10.vsd
Figure 32 Logic Output Control Block Diagram TLE8110ED
Data Sheet
51
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
12.3.1
CMD - Commands
By using the Address Range CMD[14:12] = ’000’ commands can be send to the device. The feedback of the
commands is provided in the next SPI SO frame. Details about the Feedback on each command is described
in the Chapter 12.3.1.1.
It is possible to perform per each Communication Frame ONE command out of Group-A (see following
description of the commands) and ONE command out of Group-B at the same time. Performing more then one
Command of one Group is not possible. For the case, this happens, the commands are ignored.
Overview Commands
CMD Command Register
S_SI Serial Input
CMD
11
10
9
8
7
6
5
4
3
2
1
0
RSD
RSDS
RPC
RINx
CSDS
NOP
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
Command description
Field
Command Type
Function
Command Bits Group-B (Bits [7:4]). All other bit combinations are not valid. Command will be ignored
then.
NOP
0000
W
NOP - no operation
A frame with 0000H will be returned.
CMD_CSDS 0001
W
CMD_CSDS - Command: Clear Short Diagnosis and Device
Status
Clear the Device Status information.
Performing this Clear Command clears the Information in the Reset
and Communication Error Information as long as the incident is
not present anymore. If the incident is still present, the related Bits
remain setted. Performing this command does NOT clear the
Diagnosis Registers. The Diagnosis Information is cleared by the
Clear Diagnosis Commands (see Chapter 12.3.2).
SO returns a Frame with 0000H after performing CMD_CSDS or in
case this command is carried out together with a command out of
Group-A, the feedback is according the Group-A command.
Command Bits Group-A (Bits [3:0]). All other bit combinations are not valid. Command will be ignored
then.
CMD_NOP
CMD_RINx
CMD_RPC
0000
1000
0100
W
W
W
NOP - no operation
A frame with 0000H will be returned.
CMD_RINx - Command: Return Input Pin INx -Status
See Chapter 12.3.1.4.
CMD_PRC - Command: Return Pattern Check
See Chapter 12.3.1.3.
Data Sheet
52
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
Command description
Field
Command Type
Function
CMD_RSDS 0010
W
CMD_RSDS - Command: Return Short Diagnosis and Device
Status
See Chapter 12.3.1.2.
CMD_RSD
0001
W
CMD_RSD - Command: Return Short Diagnosis
See Chapter 12.3.1.1.
12.3.1.1 CMD_RSD - Command: Return Short Diagnosis
The Command CMD_RSD offers the possibility to read out the OR-operated “short”-Diagnosis within one SO
Feedback Frame. The data to be send is latched at the end of the command frame.
CMD_RSD
S_CS
S_SI
W
xxxx
xxxx
CMD_RSD
R/W
R/W
S_SO
dept. of
SD
xxxx
previous R/W
SPI_Protoco_l CMD_RSD.vsd
Figure 33 SPI Feedback on CMD_RSD
CMD_RSD
S_SO Serial Output
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PAR
0
0
0
0
0
SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1
Response description
Field
Bits
Type
Description
-
-
-
SD1-10 Short Diagnosis
0
1
Normal Operation,
Each SD-Bit contains the NAND-operated Diagnosis Error of
each related Channel. Details can be read in diagnosis
registers.
SD is returned after each Write Cycle to any of the writable
registers.
Data Sheet
53
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
12.3.1.2 CMD_RSDS - Command: Return Short Diagnosis and Device Status
The Command CMD_RSD offers the possibility to read out the OR-operated “short”-Diagnosis and the device
Status - such as Reset-Information and Communication Error - within one SO Feedback Frame. The data to be
send is latched at the end of the command frame.
CMD_RSDS
S_CS
S_SI
W
xxxx
xxxx
CMD_RSDS
R/W
R/W
S_SO
dept. of
SDS
xxxx
previous R/W
SPI_Protocol_CMD_RSDS.vsd
Figure 34 SPI Feedback on CMD_RSDS
Data Sheet
54
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
Behaviour of SDS 3 and SDS4 in relation to RST , EN, VDD, VCC and CMD .CSDS
SDS3
VCC
or...
RST
SDS3
VCC
0
1
0
SDS4
EN=1
CMD.CSDS
or...
RST
SDS4
VDD
0
0
1
1
0
0
CMD.CSDS
CMD.CSDS
SDS4
VCC
1
SDS4
EN=0
or...
RST
SDS4
VDD
0
0
0
0
0
0
CMD.CSDS
CMD.CSDS
SDS4
0
SDS4
EN=01
EN
SDS4
0
1*
CMD.CSDS
0
* During EN = 0, the device internal VDD supply is disabled in order to fulfill low
quiescent current requirements. After the transition from EN=0 to 1, the SDS4
will detect under voltage (it is set SDS4=1) until the clear command CMD.CSDS
it sent (SDS4=0).
SDS3_4_behaviour.vsd
Figure 35 Behaviour of SDS3, 4
Data Sheet
55
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
CMD_RSDS
S_SO Serial Output
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PAR
0
0
0
0
0
0
0
SDS8 SDS7 SDS6 SDS5 SDS4 SDS3 SDS2 SDS1
Response description
Field
Bits
[7:0]
0
Type
Description
-
-
-
-
SDS - Short Diagnosis and Device Status
SDS1 - Diagnosis Error in Channel 1 to 6
0
1
Normal Operation,
Diagnosis failure.
-
1
-
SDS2 - Diagnosis Error in Channel 7 to 10
0
1
Normal Operation,
Diagnosis failure.
-
-
-
2
3
4
-
-
-
SDS3 - Under Voltage on VCC (Digital Supply Voltage)
See Figure 35.
SDS4 - Under Voltage on VDD (Analogue Supply Voltage)
See Figure 35.
SDS5 - Modulo Error Counter
0
1
Normal Operation,
Diagnosis failure.
-
5
-
SDS6 - Previous Communication Error - Encoded Command
Ignored
0
1
Normal Operation,
Previous Communication Error - Encoded Command
ignored.
-
-
6
7
-
-
SDS7 - not used = ’0’
Always ‘0’.
SDS7 - not used = ’0’
Always ‘0’.
12.3.1.3 CMD_RPC - Command: Return Pattern Check
The Command CMD_RPC offers the possibility to get returned the previous Command to check if the
communication works well. The data to be send is latched at the end of the command frame.
Data Sheet
56
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
CMD_RPC
S_CS
S_SI
W
xxxx
xxxx
CMD_RPC
R/W
R/W
S_SO
dept. of
CMD_RPC
xxxx
previous R/W
SPI_Protocol_CMD_RPC.vsd
Figure 36 SPI Feedback on CMD_RPC
CMD_RPC
S_SO Serial Output
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PAR
= 0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
Response description
Field
Bits
Type
Description
CMD_RPC is returned
-
-
-
12.3.1.4 CMD_RINx - Command: Return Input Pin (INx) - Status
The Command CMD_RINx offers the possibility to read out the actual status of the Input Pins. This command
allows to check the correct communication on the INx Pins. The data to be send is latched at the end of the
command frame.
Data Sheet
57
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
CMD_RINx
S_CS
S_SI
W
xxxx
xxxx
CMD_RINx
R/W
R/W
S_SO
dept. of
INx
xxxx
previous R/W
SPI_Protocol_CMD_RINx.vsd
Figure 37 SPI Feedback on CMD_RINx
Data Sheet
58
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
OUT1
OUT2
Control Logic
IN1
IN2
OUTn
INx
Temporal INx Register
latched by CMD_PINx and
CS High-to-Low transition
Latch on CS
Transfer on CS to
SPI-SO-Register
CS
CMD_RINx
SI
RINx
SO
INx_readout.vsd
Figure 38 Read-out of INx Pins
CMD_RINx
S_SO Serial Output
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PAR
0
0
0
0
0
IN10 IN9
IN8
IN7
IN6
IN5
IN4
IN3
IN2
IN1
Data Sheet
59
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
Response description
Field
Bits
Type
Description
-
-
-
INx Input Pin Status
The Status of the INx Pins is read out at the moment of CS High-to-
Low transition. Details see Figure 38.
0
1
INx = Low corresponding OFF
INx = High corresponding ON
12.3.2
DCC - Diagnosis Registers and compactCONTROL
The DCC - Diagnosis and Compact Control Set allows to read out and clear the Diagnosis Registers.
Additionally this Command set offers the possibility to proceed with a compactCONTROL Mode using DMS -
Diagnosis Mode Set and OPS - Output Pin Set Commands. This compactCONTROL Mode offers the possibility
to Control the device with lowest work load on the micro controller side.
If any other pattern then the defined commands is recieved on S_SI, the command is ignored and rated as a
Communication Error. In this case, this incident is reported in SDS (Chapter 12.3.1.2).
If an Error in the Output Channels is detected by the diagnosis circuit, the result is latched in the diagnosis
registers related to each channel.
The Diagnosis Register is not deleted, when it is just read out. The Diagnosis Register byte can only be cleared
by using the appropriated command. In this case, the complete Register Bank is cleared.
When issuing a Diagnosis Register Clear command (DRxCL or DMSCL), the idle time tDidle needs to elapse, from
the CS low-to-high transition of the clear command, before the register content is effectively cleared
(Figure 39); This time has to be taken into account when trying to read the Diagnosis register content after a
clear, see Chapter 11.3 for tDidle defintion.
After an overcurrent entry is stored in the diagnosis register (OC), the idle time tOCidle needs to elapse before a
clear command can effectively clear the entry; if trying to clear the Diagnosis register after an OCT entry is read
(Figure 39), this time has to be taken into account starting from the CS high-to-low transition of the previous
read command, see (Chapter 11.3) for tOCidle defintion.
Data Sheet
60
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
Diagnosis Clear-to-Read idle time ( Didle)
t
tDidle
S_CS
S_SI
t
> tDidle
DRxCL/DMSCL
Clear Diagnosis
DRx
Read Diagnosis
Cleared diagnosis can be read
Diagnosis gets cleared
t
Diagnosis Overcurrent -to-Clear idle time (tOCidle
)
tOCidle
S_CS
t
>
tOCidle
S_SI
DRx
DRxCL/DMSCL
Clear Diagnosis
Read Diagnosis
OCT detected
Effective Diagnosis Clear
OCT can be cleared
t
Diagnosis Idle Times
Figure 39 Diagnosis idle times
DCC
Diagnosis Registers and Compact Control
S_SI Serial Input
DCC
11
10
9
8
7
6
5
4
3
2
1
0
DRA
DRB
DRACL
DRBCL
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMSCL/OPSx
DMS1/OPSx
DMS2/OPSx
DMS3/OPSx
DMSx/OPS1
DMSx/OPS2
DMSx/OPS3
DMSx/OPS4
DMSx/OPS5
DMSx/OPS6
DMSx/OPS7
DMSx/OPS8
OPSx
OPSx
OPSx
OPSx
DMSx
DMSx
DMSx
DMSx
DMSx
DMSx
DMSx
DMSx
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Data Sheet
61
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
Command description
Field
Bits
Type
Function
DCC_DRA
[11:0]
W
DRA - Diagnosis Register A (see Chapter 12.3.2.1)
Read out Diagnosis Register A. Return the contents in the next SPI
frame (see Chapter 12.3.2.2).
DCC_DRB
[11:0]
W
W
DRB - Diagnosis Register A (see Chapter 12.3.2.1)
Read out Diagnosis Register B. Return the contents in the next SPI
frame (see Chapter 12.3.2.2).
DCC_DRACL [11:0]
DCC_DRBCL [11:0]
DCC_DMSCL [11:8]
DRACL - Diagnosis Register A Clear
Clear the contents of the Diagnosis Register A. Return the content
present before the clear in the next SPI Frame. If the Diagnosis Error
Remains, the Information remains (see Chapter 12.3.2.2).
W
W
DRBCL - Diagnosis Register B Clear
Clear the contents of the Diagnosis Register B. Return the content
present before the clear in the next SPI Frame. If the Diagnosis Error
Remains, the Information remains (see Chapter 12.3.2.2).
DMSCL/OPSx - Diagnosis Mode Set, Clear / Output Pins Set
On sending this command, the diagnosis registers DRA, DRB as well
as the “virtual” Diagnosis Output Registers DO[7:0] (see
Chapter 12.3.2.3) are cleared. Output Pin Settings are done
according the content of OPSx.
Returns the contents of cleared DR2 on SO in the 2nd byte of the
actual communication frame and the Output Pin Feedback in
the 1st Byte of the next frame (see Chapter 12.3.2.3).
DCC_DMS1 [11:8]
DCC_DMS2 [11:8]
DCC_DMS3 [11:8]
W
W
W
DMS1/OPSx - Diagnosis Mode Set, Register1 / Output Pins Set
On sending this command, the diagnosis registers DR1 is selected.
Output Pin Settings are done according the content of OPSx.
Returns the contents of DR1 on SO in the 2nd byte of the actual
communication frame and the Output Pin Feedback in the 1st Byte
of the next frame (see Chapter 12.3.2.3).
DMS2/OPSx - Diagnosis Mode Set, Register2 / Output Pins Set
On sending this command, the diagnosis registers DR2 is selected.
Output Pin Settings are done according the content of OPSx.
Returns the contents of DR2 on SO in the 2nd byte of the actual
communication frame and the Output Pin Feedback in the 1st Byte
of the next frame (see Chapter 12.3.2.3).
DMS3/OPSx - Diagnosis Mode Set, Register3 / Output Pins Set
On sending this command, the diagnosis registers DR3 is selected.
Output Pin Settings are done according the content of OPSx.
Returns the contents of DR3 on SO in the 2nd byte of the actual
communication frame and the Output Pin Feedback in the 1st Byte
of the next frame (see Chapter 12.3.2.3).
Data Sheet
62
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
Command description
Field
Bits
Type
Function
DCC_DMSx/ [7:0]
OPSx
W
DMSx/OPS1 - Diagnosis Mode Set x/ Output Pins Set Command
1
On sending this command, the diagnosis register is selected
according DMSx. The Output Pins of Channel 7-10 are set according
the following definitions. The OPSx are commands, no register. The
commands are controlling the contents of ISA, ISB and OUTx.
OPS[7:0] - Output Pin Set:
0000 0001: CH7 input select, 1: parallel* / 0: Serial
0000 0010: CH8 input select, 1: parallel* / 0: Serial
0000 0100: CH9 input select, 1: parallel* / 0: Serial
0000 1000: CH10 input select, 1: parallel* / 0: Serial
0001 0000: CH7 output set, 1: ON / 0: OFF
0010 0000: CH8 output set, 1: ON / 0: OFF
0100 0000: CH9 output set, 1: ON / 0: OFF
1000 0000: CH10 output set, 1: ON / 0: OFF
(*parallel controlled by INx)
Sending OR operated combinations of above listed options (only
OPSx) are possible in order to control more then one channel at the
same time.
If parallel mode Mode is selected (in “input select”), the serial
settings (in “output select”) are ignored. In parallel Mode, the
selected Channels are controlled via INx Pins. The default setting of
ISB corresponds the command OPS[7:0] = xxxx 1111b. (parallel
mode, status of the Outputs according signal on INx).
Returns the contents the selected DRx register on SO in the 2nd
byte of the actual communication frame and the Output Pin
Feedback [OPF] in the 1st Byte of the next frame (see
Chapter 12.3.2.3).
12.3.2.1 DRx - Diagnosis Registers Contents
DRA[1:0]x / DRB[1:0]x
Diagnosis Register CHx Bank A and Bank B
Reset value 0000 0000 0000B = 000H
11
10
9
8
7
6
5
4
3
2
1
0
DRA[1]6 DRA[0]6 DRA[1]5 DRA[0]5 DRA[1]4 DRA[0]4 DRA[1]3 DRA[0]3 DRA[1]2 DRA[0]2 DRA[1]1 DRA[0]1
11
0
10
0
9
0
8
0
7
6
5
4
3
2
1
0
DRB[1]10 DRB[0]10 DRB[1]9 DRB[0]9 DRB[1]8 DRB[0]8 DRB[1]7 DRB[0]7
Data Sheet
63
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
Field
Bits
Type
Function
DRA[1:0]x / [1:0]
DRB[1:0}x
R
DRA[1:0]x / DRB[1:0]x
DRn[1]x/DRn[0]x = 11 no Error
DRn[1]x/DRn[0]x = 10 Over Load, Shorted Load, Over temperature
in ON-Mode
DRn[1]x/DRn[0]x = 01 Open Load in OFF-Mode
DRn[1]x/DRn[0]x = 00 Short to GND in OFF-Mode
default DRx[1:0] = 11B
A new error on the same channel will overwrite older information.
The diagnosis information which is returned by SO is latched when
CS makes a High-to-Low transistion of the frame which sends out
the register.
12.3.2.2 DRx - Return on DRx Commands
x_DRx
S_CS
S_SI
W
xxxx
xxxx
x_DRx
R/W
R/W
S_SO
dept. of
DRx
xxxx
previous R/W
SPI_Protocol_x_DRx.vsd
Figure 40 SPI Feedback on x_DRx commands
DRx
Return on DRx Commands
S_SO Serial Output
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DRx DRx DRx DRx DRx DRx DRx DRx DRx DRx DRx DRx
[1]x [0]x [1]x [0]x [1]x [0]x [1]x [0]x [1]x [0]x [1]x [0]x
PAR
0
0
1
Response description
Field
Bits
Type
Description
-
-
-
DRx contents
0
1
no diagnosis error
diagnosis error
Data Sheet
64
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
12.3.2.3 DMSx/OPSx - Diagnosis Mode Set / Output Pin Set Commands
Protocol
Each Cycle where a serial data or command frame is sent to the Serial Input [SI] of the SPI interface, a data
frame is returned immediately by the Serial Output [SO]. The content of the SO frame is dependent of the
previous command which has been sent to SI and the content of the actual content of SI: The first Byte send
by S_SI controls the content of the second byte actual returned by S_SO. The second Byte send by S_SI
controls the first byte in S_SO of the next frame (see Figure 41).
S_CS
S_SI
Upper
Byte
Lower
Byte
Upper
Byte
Lower
Byte
DMSx
OPSx
DO
S_SO
Upper
Byte
Lower
Byte
Upper
Byte
Lower
Byte
OPF
SPI_Protoco_l Short_Mode.vsd
Figure 41 Data Transfer in diagnosis and Compact Control
DMSx/OPSx
Diagnosis Mode Set/ Output Pin Set Commands
S_SI Serial Input
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Diagnosis Mode Set DMS [4:0]
-
Output Pin Set OPS[7:0]
Serial mode selected
Parallel or Serial mode
CH10: CH9: CH8: CH7:
CH10: CH9: CH8: CH7: 0 =
1:ON 1:ON 1:ON 1:ON serial serial serial serial
0:OFF 0:OFF 0:OFF 0:OFF 1 = 1 = 1 = 1 =
0 =
0 =
0 =
0
0
0
1
-
-
-
-
par. par. par. par.
Data Sheet
65
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
DMSx/OPSx
Diagnosis Mode Set/ Output Pin Set Commands
S_SO Serial Output
15
14
13
12
11
10
9
8
7
7
6
6
5
4
3
2
1
1
0
0
Output Pin Set Feedback OPF[7:0]
Diagnosis Output DO[7:0]
Diagnosis Output Registers
DO[7:0]
5
4
3
2
Diag Register-1
DR4[1] DR4[0] DR3[1] DR3[0] DR2[1] DR2[0] DR1[1] DR1[0]
Diag Register-2
DR1NA DR3NA
1
1
DR6[1] DR6[0] DR5[1] DR5[0]
DR10 DR10
Diag Register-3
[1]
[0] DR9[1] DR9[0] DR8[1] DR8[0] DR7[1] DR7[0]
Field
Bits
Type
Description
DO[7:0]
[7:0]
R
DO[7:0] - Diagnosis Output
Contents according settings of DMS[4:0].
Returned within the same frame as the pointer is send. DRx[1:0]
definitions: see Chapter 12.3.2.1.
DO[7:6]Diag [7:6]
Register-2
R
DO1NA: NAND-operated diagnosis of Diag Register-1
DO3NA: NAND-operated diagnosis of Diag Register-3
0
1
no diagnosis error is stored in the related Diag Register,
at least one diagnosis error is stored in the related Diag
Register.
Output Pin Feedback OPF[7:0]
15
14
13
12
11
10
9
8
OPF[7]
OPF[6]
OPF[5]
OPF[4]
OPF[3]
OPF[2]
OPF[1]
OPF[0]
Data Sheet
66
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
Field
Bits
Type
Description
OPF[7:0]
[15:8]
R
OPF[7:0] - Output Pin Feedback
Principally, OPF can return the previously send OPS word and the
IN 10:7 -pin settings, dependent serial/ parallel-setting of OPS:
•
If Serial Mode is selected by one or more OPS[3:0]-bits, the
related OPF[7:4]-bits are returning the settings of OPS[7:4],
send at the previous frame,
•
if Parallel Mode is selected by one or more OPS[3:0]-bits, the
related OPF[7:4]-bits are returning the condition available at
the related IN 10:7 Pins at the moment of S_CS high-to-low
transition.
A mix of both modes is possible and depends on the channel
related settings.
Data Sheet
67
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
12.3.3
OUTx - Output Control Register CHx
The Output Control Register OUTx consists of 10 Bits to control the Output Channel. Each Bit switches ON/OFF
the related Channel.
OUTx becomes only active when ISx[1:0] = 0x. For details refer to Chapter 12.3.4.
OUTx DATA
Output Control Register CHx
Reset value 1100 0000 0000B = C00H
11
10
9
8
7
6
5
4
3
2
1
0
1
1
OUT10 OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
Field
Bits
[9:0]
Type
Description
Data - OUTx[9:0]
OUTx[9:0]
R/W
OUTx = 0 According Channel is switched OFF,
OUTx = 1 According Channel is switched ON.
Default (all channels OFF) OUT[9:0] = 00 0000 0000B = 000H.
OUTx[11:10] [11:10]
R/W
Data - OUTx[11:10]
Bits are set to OUT[11:10] = 1.
Data Sheet
68
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
12.3.4
ISx - INPUT or Serial Mode Control Register, Bank A and Bank B
The INPUT or Serial Control Register [ISx[1:0] ] allows to define the way of controlling the Output Channels.
There are 4 setting options possible.
1. Standard Serial Control: The related Output Channel is set according the content of the OUTx Register.
(Chapter 12.3.3).
2. A further possibilty is the control by the Input Pins.
3. The settings of the Parallel Mode Register PMx[0] (see Chapter 12.3.5).
4. Additionally possible is the AND operation between the setting of the OUTx register and the PWM signal at
the INPUT Pin.
ISAx Command
INPUT or Serial Mode Control Register Bank A
Reset Value: 1010 1010 1010B = AAAH
11
10
9
8
7
6
5
4
3
2
1
0
IS6
IS5
IS4
IS3
IS2
IS1
Field
Bits
[11:0]
Type
Description
Command - ISx[1:0]
ISx[1:0]
R/W
0x: Serial Mode - The Channel is set ON/OFF by OUTx,
10: INPUT Mode - CHx ON/OFF according INx,
11: AND operate Mode INx with OUTx -> CHx ON if OUTx & INx = 1,
Default all channels ISx[1:0] = 10B.
ISBx Command
INPUT or Serial Mode Control Register Bank B
Reset Value: 0000 1010 1010B = 0AAH
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
IS10
IS9
IS8
IS7
Field
Bits
[7:0]
Type
Description
Command - ISx[1:0]
ISx[1:0]
R/W
0x: Serial Mode - The Channel is set ON/OFF by OUTx,
10: INPUT Mode - CHx ON/OFF according INx,
11: AND operate Mode INx with OUTx -> CHx ON if OUTx & INx = 1,
Default all channels ISx[1:0] = 10B.
Data Sheet
69
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
12.3.5
PMx - Parallel Mode Register CHx
The Parallel Mode Register PMx[1] allows to “inform” the device about externally parallel connected output
channels. If a PMx bit is set, the “lower” related Input Channel controls the indicated Output Channels to
achieve best possible matching and according to that highest efficiency of both channels. Additionally to that,
the CLAMPsafe feature allows high matching during clamping.
PMx Command
Parallel Mode Register CHx; Reset Value: 0000 0000 0000B= 000H
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
PM910 PM89
PM78
PM56
0
PM34
PM23
PM12
Field
PMx
PMx
Bits
Type
R/W
R/W
Description
[11:8]
[7:0]
0
PMx - Parallel Mode Bit
0
1
Direct Mode,
Parallel Mode of Channel 1 with x+1.
Default PMx[0] = 0.
Controlling Parallel Mode is possible between Channel 1 to 4, 5 to
6, 7 to 10. In between the groups, no parallel mode is supported but
possible.
In case Parallel Mode is chosen and a diagnosis error at only one of
the channels is detected, the according diagnosis bit is set. This
information mismatch can be caused by tolerance related
inbalance of the channels connected together in parallel mode.
The diagnosis bits should be or-operated by the Micro Controller
side.
Data Sheet
70
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Control of the device
12.3.6
DEVS - Device Settings
The Register allows additional Device settings. For details refer also to the Chapter “Electrical Characteristics”.
The Diagnosis Current Control register allow to select between different Diagnosis Modes. The Diagnosis
Currents can be switched off to avoid glowing of any connected LEDs.
DEVS Command
Device Settings
Reset Value: 0000 0000 0111B = 007H
11
10
9
8
7
6
5
4
3
2
1
0
RCP
DBT2
DBT1
0
0
0
0
0
0
DCC10
DCC9
DCC18
Field
Bits
Type
Description
RCP
11
R/W
RCP - Reverse Current Protection
0
1
disabled,
reverse current comp is enabled (valid for all Channels).
Default RPC = 0.
DBT[2:1]
[10:9]
R/W
DBT2,1 - Diagnosis Blind Time Channel 7 to 10
0,0 standard Filter Time of typ. 150μs,
1,0 standard Filter Time of typ. 150μs,
0,1 OFF-state diagnosis Blind Time of typ. 2.5ms,
1,1 OFF-state diagnosis Blind Time of typ. 5ms.
DEVS[7:5]
DEVS[4:3]
DCCx
[7:5]
[4:3]
[2:0]
R/W
R/W
R/W
not used. Set to 0.
0
DCCx - Diagnosis Current Control
DCC18 switching ON/OFF diagnosis current of CH1-8,
DCC9 switching ON/OFF diagnosis current of CH9,
DCC10 switching ON/OFF diagnosis current of CH10.
0
OFF-State Diagnosis (Detection of open load and short to
GND) of CHx is switched OFF. ON state diagnosis (over current
and over temperature detection) is still active. Diagnosis
Current is switched OFF.
1
OFF-State (Detection of open load and short to GND) and
ONState (over current and over temperature detection)
Diagnosis of CHx switched ON, Diagnosis Current is switched
ON.
Default DCC = 1.
Data Sheet
71
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Package Outlines
13
Package Outlines
Figure 42 PG-DSO-36-72 Exposed Pad
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a Green Product. Green Products are RoHS compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Floating Expose pad
The expose pad of TLE8110ED is floated. It is highly recommended to connect the expose pad to GND pins
externally.
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Dimensions in mm
Data Sheet
72
Rev. 1.1
2021-04-30
TLE8110ED
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
Revision History
14
Revision History
Table 17
Revision History
TLE8110ED
Revision History: 2021-04-30 , Rev. 1.1
•
•
•
P_4.3.2: Parameter Junction to ambient added
Rev. 1.1
P_8.2.2/P_8.2.6: Diagnosis current units updated (mA to µA)
Chapter 13, Package Outlines: Figure 42 updated
Rev. 1.0
Final Datasheet
Data Sheet
73
Rev. 1.1
2021-04-30
Trademarks
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Edition 2021-04-30
Published by
Infineon Technologies AG
81726 Munich, Germany
event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest
characteristics ("Beschaffenheitsgarantie").
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the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
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In addition, any information given in this document is
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Document reference
Z8F56166608
相关型号：
TLE8110EEXUMA2
Buffer/Inverter Based Peripheral Driver, 1.7A, PDSO36, GREEN, PLASTIC, DSO-36
INFINEON
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