IN74LV174D [INTEGRAL]
Hex D-type flip-flop with reset; positive edge-trigger; 六路D型触发器与复位;正边沿触发型号: | IN74LV174D |
厂家: | INTEGRAL CORP. |
描述: | Hex D-type flip-flop with reset; positive edge-trigger |
文件: | 总6页 (文件大小:54K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TECHNICAL DATA
IN74LV174
Hex D-type flip-flop with reset; positive edge-trigger
The 74LV174 is a low–voltage Si–gate CMOS device and is pin and
function compatible with the 74HC/HCT174.
The 74LV174 has six edge–triggered D–type flip–flops with individual D
inputs and Q outputs. The common clock (CP) and master reset (MR)
inputs load and reset (clear) all flip–flops simultaneously.
The register is fully edge–triggered. The state of each D input, one set–
up time prior to the LOW–to–HIGH clock transition, is transferred to the
corresponding output of the flip–flop.
A LOW level on the MR input forces all outputs LOW, independently of
clock or data inputs.
The device is useful for applications requiring true outputs only and
clock and master reset inputs that are common to all storage elements.
ORDERING INFORMATION
·
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
IN74LV174N Plastic
IN74LV174D SOIC
IZ74LV174 Chip
·
·
·
·
Supply voltage range: 1.2 to 5.5 V
Low input current: 1.0 mÀ; 0.1 mÀ at Ò = 25 °Ñ
Output current: 6 mA at Vcc = 3.0 V; 12 mA at Vcc = 4.5 V
High Noise Immunity Characteristic of CMOS Devices
TA = -40° to 125° C for all packages
PIN ASSIGNMENT
MR
Q0
1
2
3
4
5
6
7
8
16
V
CC
15 Q5
14 D5
13 D4
12 Q4
LOGIC DIAGRAM
D0
D1
Q1
D2
11
10 Q3
CP
D3
Q2
GND
9
FUNCTION TABLE
Inputs
CP
Outputs
CP
MR
L
Dn
X
H
L
Qn
X
L
MR
H
H
PIN 16=VCC
PIN 08 = GND
H
L
H
L
X
X
no change
no change
H
H= high level
L = low level
X = don’t care
INTEGRAL
1
IN74LV174
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +5.0
±20
Unit
V
VCC
DC supply voltage
Input diode current
Output diode current
1
IIK
*
mA
mA
mA
mA
mA
mW
2
IOK
*
±50
IO *3
Output source or sink current
VCC current
±25
ICC
±50
IGND
PD
GND current
±50
Power dissipation per package: *4
Plastic DIP
SO
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO
Package) from Case for 4 Seconds
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
*1 V < -0.5 V or V > VCC + 0.5 V
I
I
*2 VO < -0.5 V or VO > VCC + 0.5 V
*3 -0.5 V < VO < VCC + 0.5 V
*4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SO Package: : - 8 mW/°C from 70° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
1.2
0
Max
5.5
Unit
V
VCC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
IN
VCC
V
VOUT
TA
0
VCC
V
Operating Temperature, All Package Types
-40
+125
°C
tr, tf
Input Rise and Fall Time (Figure 1) 1.0 Â £VCC <2.0 Â
0
0
0
0
500
200
100
50
ns/V
2.0 Â £VCC <2.7 Â
2.7 Â £VCC <3.6 Â
3.6 Â £VCC £5.5 Â
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, V and VOUT should be constrained to the range GND£(V or
IN
IN
VOUT)£VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
INTEGRAL
2
IN74LV174
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Test
VCC
V
Guaranteed Limit
Symbol
Parameter
conditions
-40°C to 25°C
85°C
125°C
Unit
min
max
min
max
min
max
V
IH
HIGH level input
voltage
1.2
2.0
2.7
3.0
3.6
4.5
5.5
0.9
1.4
2.0
2.0
2.0
-
-
-
-
-
-
-
0.9
1.4
2.0
2.0
2.0
-
-
-
-
-
-
-
0.9
1.4
2.0
2.0
2.0
-
-
-
-
-
-
-
V
3.15
3.85
3.15
3.85
3.15
3.85
V
LOW level input
voltage
1.2
2.0
2.7
3.0
3.6
4.5
5.5
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
V
V
IL
1.35
1.65
1.35
1.65
1.35
1.65
VOH
HIGH level output V = V or V
IL
voltage
1.2
2.0
2.7
3.0
3.6
4.5
5.5
1.05
1.85
2.55
2.85
3.45
4.35
5.35
-
-
-
-
-
-
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
-
-
-
-
-
-
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
-
-
-
-
-
-
-
I
IH
IO = -100 mÀ
V = V or V
IL
3.0
2.48
-
2.34
-
2.20
-
V
V
V
I
IH
IO = -6 mÀ
V = V or V
IL
4.5
3.70
-
3.60
-
3.50
-
I
IH
IO = -12 mÀ
LOW level output V = V or V
IL
VOL
1.2
2.0
2.7
3.0
3.6
4.5
5.5
-
-
-
-
-
-
-
0.15
0.15
0.15
0.15
0.15
0.15
0.15
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
I
IH
voltage
IO = 100 mÀ
V = V or V
IL
3.0
-
0.33
-
0.40
-
0.50
V
V
I
IH
IO = 6 mÀ
V = V or V
IL
4.5
-
0.40
-
0.55
-
0.65
I
IH
IO = 12 mÀ
II
Input current
V = VCC or 0 V
5.5
5.5
-
-
±0.1
-
-
±1.0
-
-
±1.0
mÀ
mÀ
I
ICC
Supply current
V =VCC or 0 V
I
8.0
80
160
IO = 0 mÀ
ICC1
Additional
quiescent supply
V =VCC – 0.6 V
I
2.7
3.6
-
0.2
0.2
-
0.5
0.5
-
0.85
0.85
mA
INTEGRAL
3
IN74LV174
current per input
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, RL = 1 kW, tr=tf=2.5 ns)
Test
VCC
V
Guaranteed Limit
-40°C to 25°C 85°C
Symbol
Parameter
conditions
125°C
Unit
min
max
min
max
min max
tPHL, tPLH Propagation delay CP to V = 0 V or VCC
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
200
34
24
20
17
-
-
-
-
-
230
43
31
25
21
-
-
-
-
-
260
53
39
31
26
ns
I
Qn
Figure 1, 4
tPHL
Propagation delay MR to V = 0 V or VCC
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
160
34
24
20
17
-
-
-
-
-
190
43
31
25
21
-
-
-
-
-
220
53
39
31
26
ns
ns
ns
ns
ns
ns
I
Qn
Figure 2, 4
tW
Clock pulse width HIGH or V = 0 V or VCC
1.2
2.0
2.7
3.0
4.5
100
28
21
17
14
-
-
-
-
-
140
34
25
20
17
-
-
-
-
-
180
41
30
24
20
-
-
-
-
-
I
LOW
Figure 1, 4
tW
Master reset pulse width
LOW
V = 0 V or VCC
Figure 1, 4
1.2
2.0
2.7
3.0
4.5
100
28
21
17
14
-
-
-
-
-
140
34
25
20
17
-
-
-
-
-
180
41
30
24
20
-
-
-
-
-
I
tREM
tSU
th
Removal time MR to CP
Set-up time Dn to CP
Hold time Dn to CP
Input capacitance
V = 0 V or VCC
Figure 3, 4
1.2
2.0
2.7
3.0
4.5
40
19
13
11
9
-
-
-
-
-
60
22
16
13
11
-
-
-
-
-
80
26
19
15
13
-
-
-
-
-
I
V = 0 Â or VCC
1.2
2.0
2.7
3.0
4.5
50
5
5
5
5
-
-
-
-
-
50
5
5
5
5
-
-
-
-
-
50
5
5
5
5
-
-
-
-
-
I
Ðèñóí î ê 3, 4
V = 0 Â or VCC
1.2
2.0
2.7
3.0
4.5
50
5
5
5
5
-
-
-
-
-
50
5
5
5
5
-
-
-
-
-
50
5
5
5
5
-
-
-
-
-
I
Ðèñóí î ê 2, 4
CI
ÒA = 25°C
5.0
5.5
-
-
7.0
34
-
-
-
-
-
-
-
-
pF
pF
CPD
Power dissipation
V = 0 V or VCC
I
capacitance (per flip-flop)
TA = 25°C
fmax
Maximum clock pulse
frequency
V = 0 Â or VCC
Ðèñóí î ê 1
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
2.0
16
22
27
32
-
-
-
-
-
1.0
14
19
24
27
-
-
-
-
-
1.0 MHz
I
12
16
20
24
INTEGRAL
4
IN74LV174
tw
(2)
V1
t
t
r
f
(2)
(1)
V1
MR
Q
VM
90%
CP
(1 )
VM
GND
10%
GND
tPHL
t w
VOH
VOL
( 1)
VM
1/f
max
tPLH
tPHL
VOH
t rec
Q
(1 )
VM
(2)
V1
VOL
(1)
CP
VM
GND
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
TEST POINT
VALID
(2)
V
1
(1 )
OUTPUT
VM
DEVICE
UNDER
TEST
DATA
GND
t
t
h
su
*
R
L
(2)
C
L
V
1
( 1)
CP
VM
GND
* Includes all probe and jig capacitance
Figure 3. Switching Waveforms
(1)
Figure 4. Test Circuit
Note:
VM = 1.5 V at VCC = 2.7 V
VM = 0.5 ×VCC at VCC =1.2 V, 2.0 V, 3.0 V, 4.5 V
(2)
V = VCC at VCC =1.2 V, 2.0 V, 2.7 V, 4.5 V
1
V = 2.7 V at VCC = 3.0 V
1
INTEGRAL
5
IN74LV174
CHIP PAD DIAGRAM
10
14
11
15
13
12
09
08
16
01
02
03
04
05
Chip marking
LV174
06
07
Y
(0,0)
X
1.53 + 0.03
Location of marking (mm): left lower corner x=1.080, y=0.296
Chip thickness: 0.46 ± 0.02 mm.
PAD LOCATION
Location (left lower corner), mm
Pad No
Symbol
Pad size, mm
X
Y
0.295
0.127
0.127
0.127
0.127
0.127
0.127
0.741
1.079
1.247
1.247
1.247
1.247
1.247
1.247
0.633
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
MR
Q0
D0
D1
Q1
D2
Q2
GND
CP
Q3
D3
Q4
D4
D5
Q5
VCC
0.132
0.100 x0.100
0.100 x0.100
0.100 x0.100
0.100 x0.100
0.100 x0.100
0.100 x0.100
0.100 x0.100
0.100 x0.100
0.100 x0.100
0.100 x0.100
0.100 x0.100
0.100 x0.100
0.100 x0.100
0.100 x0.100
0.100 x0.100
0.100 x0.100
0.132
0.430
0.667
0.902
1.080
1.315
1.315
1.315
1.315
1.017
0.780
0.545
0.367
0.132
0.132
Note: Pad location is given as per metallization layer
INTEGRAL
6
相关型号:
©2020 ICPDF网 联系我们和版权申明