IN74LV240N_技术文档

TECHNICAL DATA

IN74LV240

OCTAL BUFFER/LINE DRIVE; 3-STATE

The IN74LV240 is a low-voltage Si-gate CMOS device and is pin and

function compatible with IN74HC/HCT240.

The IN74LV240 is an octal non-inverting buffer/line driver with 3-

state outputs. The 3-state outputs are controlled by the output enable

inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a

high impedance OFF-state.

N SUFFIX

PLASTIC DIP

20

1

DW SUFFIX

SO

The IN74LV240 is identical to the IN74LV244 but has inverting

outputs.

20

1

·

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 1.2 to 3.6 V

Low Input Current: 1.0 mA, 0.1 mÀ at Ò = 25 °Ñ

Output Current: 8 mA at V_CC= 3.0 V

ORDERING INFORMATION

IN74LV240N

IN74LV240DW

IZ74LV240

Plastic DIP

SOIC

chip

High Noise Immunity Characteristic of CMOS Devices

T_A= -40° to 125° C for all packages

LOGIC DIAGRAM

PIN ASSIGNMENT

2

18

16

14

12

9

1Y

1A

0

1

0

1OE

1

20

19

V_CC

2OE

4

1A

1A₀

2Y₃

2

1

3

18 1Y₀

17 2A₃

16 1Y₁

6

1Y

2Y

1A

2

3

0

1

2

3

0

1

1A₁

4

8

2Y₂

5

INVERTING

OUTPUTS

DATA

INPUTS

1A₂

6

15

2A₂

11

13

15

17

2A

2Y₁

7

14 1Y₂

13 2A₁

12 1Y₃

1A₃

8

7

2Y₀

9

5

2Y

2A

0

1

10

GND

11

2A₀

0

3

2A

1

1OE

2OE

FUNCTION TABLE

OUTPUT

ENABLES

19

Input

Output

nOE

nAn

L

nYn

H

L

H

L

PIN 20=V_CC

H

X

Z

PIN 10 = GND

H= high level

L = low level

X = don’t care

Z = high impedance

INTEGRAL

1

IN74LV240

MAXIMUM RATINGS^*

Symbol

Parameter

Value

-0.5 to +5.0

±20

Unit

V

V_CC

DC supply voltage

1

I_IK

*

DC Input diode current

DC Output diode current

mA

mW

2

I_OK

*

±50

I_O*³

DC Output source or sink current

DC V_CCcurrent

±35

I_CC

±70

I_GND

P_D

DC GND current

±70

Power dissipation per package: *⁴

Plastic DIP

SO

750

500

Tstg

T_L

Storage Temperature

-65 to +150

260

°C

Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO

Package) from Case for 4 Seconds

^*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

*¹V < -0.5 V or V > V_CC+ 0.5 V.

I

*²V_O< -0.5 V or V_O> V_CC+ 0.5 V.

*³-0.5 V < V_O< V_CC+ 0.5 V.

*⁴Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C

SO Package: : - 8 mW/°C from 70° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

1.2

0

Max

3.6

Unit

V

V_CC

DC Supply Voltage

Input Voltage

V

I

V_CC

V

V_O

T_A

Output Voltage

0

V_CC

V

Operating Temperature, All Package Types

Input Rise and Fall Time (Figure 1)

-40

+125

°C

ns

t_r, t_f

V_CC=1.2 V

V_CC=2.0 V

V_CC=3.0 V

V_CC=3.6 V

0

1000

700

500

400

This device contains protection circuitry to guard against damage due to high static voltages or electric

fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages

to this high-impedance circuit. For proper operation, V and V_OUTshould be constrained to the range GND£(V or

IN

V_OUT)£V_CC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V_CC). Unused

outputs must be left open.

INTEGRAL

2

IN74LV240

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Test

V_CC

V

Guaranteed Limit

Symbol

Parameter

conditions

25°C

-40°C to 85°C

125°C

Unit

min max min

max

min

max

V

IH

HIGH level input

voltage

1.2

2.0

3.0

3.6

0.9

1.4

2.1

2.5

-

0.9

1.4

2.1

2.5

-

0.9

1.4

2.1

2.5

-

V

LOW level input

voltage

1.2

2.0

3.0

3.6

-

0.3

0.6

0.9

1.1

-

0.3

0.6

0.9

1.1

-

0.3

0.6

0.9

1.1

V

IL

V_OH

HIGH level output V = V or V

IL

voltage

1.2

2.0

3.0

3.6

1.1

-

1.0

1.9

2.9

3.5

-

1.0

1.9

2.9

3.5

-

I

IH

I_O= -50 mÀ

1.92

2.92

3.52

V = V or V

IL

3.0

2.48

-

2.34

-

2.20

-

V

I

IH

I_O= -8 mÀ

LOW level output V = V or V

IL

V_OL

1.2

2.0

3.0

3.6

-

0.09

-

0.1

-

0.1

I

IH

voltage

I_O= 50 mÀ

V = V or V

IL

3.0

-

0.33

-

0.4

-

0.5

V

I

IH

I_O= 8 mÀ

V = V_CCor 0 V

I_I

Input current

*

-

±0.1

±0.5

-

±1.0

±5

-

±1.0

±10

mÀ

I

I_OZ

Three state leakage 3-state outputs

1.2

*

current

V (01,19) = V

I

IH

V_O=V_CCor 0 V

I_CC

Supply current

V =V_CCor 0 V

I

*

-

8.0

-

80

-

160

mÀ

I_O= 0 mÀ

* V_CC= 3.3 ± 0.3 V

INTEGRAL

3

IN74LV240

AC ELECTRICAL CHARACTERISTICS (C_L=50 pF, t_r=t_f=6.0 ns)

Test

V_CC

V

Guaranteed Limit

Symbol

Parameter

conditions

25°C

-40°C to

85°C

125°C

Unit

min max min

max

min

max

t_PHL,t_PLHPropagation delay , 1An V = 0 V or V_CC

1.2

2.0

*

-

100

24

15

-

125

30

19

-

150

36

23

ns

I

to 1Yn, 2An to 2Yn

Figure 1 and 3

t_PHZt_PLZPropagation delay, 1OE to V = 0 V or V_CC

1.2

2.0

*

-

140

30

20

-

175

35

24

-

210

41

28

I

1Yn, 2OE to 2Yn

Figure 2 and 4

t_PZHt_PZLPropagation delay, 1OE to V = 0 V or V_CC

1.2

2.0

*

-

140

32

20

-

175

40

25

-

210

48

30

I

1Yn, 2OE to 2Yn

Figure 2 and 4

t_THL,t_TLHOutput Transition Time,

Any Output

V = 0 V or V_CC

Figure 1 and 3

1.2

2.0

*

-

60

16

10

-

75

20

13

-

90

24

15

I

C_I

Input capacitance

3.0

-

7.0

50

-

7.0

-

7.0

-

pF

C_PD

Power dissipation

capacitance (per one

channel)

V = 0 V or V_CC

I

* V_CC= 3.3 ± 0.3 V

V_CC

t

f

r

50%

V_CC

1OE or 2OE

90%

50%

1A_nor 2A_n

GND

10%

t_PZL

t_PLZ

GND

t_PLH

t_PHL

V_CC

V_OL

50%

1Y_nor 2Y_n

90%

1Y_nor 2Y_n

50%

10%

t_PHZ

t_PZH

V_OH

GND

t_THL

t_TLH

Figure 1. Switching Waveforms

Figure 2. Switching Waveforms

TEST POINT

Connect to V when

CC

and t

PZL

DEVICE

UNDER

TEST

1 k

OUTPUT

testing t

OUTPUT

PLZ

DEVICE

UNDER

TEST

Connect to GND when

testing t and t

*

L

PHZ

PZH

C

L

* Includes all probe and jig capacitance

Figure 3. Test Circuit

Figure 4. Test Circuit

INTEGRAL

4

IN74LV240

CHIP PAD DIAGRAM

Chip marking

ÊÁLV240

13

18

17

19

16 15

14

12

11

20

10

09

01

02

05

06

04

07 08

03

Y

(0,0)

X

1.9 + 0.03

Location of marking (mm): left lower corner x=1.539, y=1.433.

Chip thickness: 0.46 ± 0.02 mm.

PAD LOCATION

Location (left lower corner), mm

Pad No

Symbol

Pad size, mm

X

Y

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

16

17

18

19

20

1OE

1A₀

0.115

0.55

0.108 x0.108

0.1075

0.3215

0.76

0.246

0.131

0.43

0.643

1.0855

1.266

1.4345

1.1385

0.949

2Y

3

1A₁

2Y

0.9285

1.2115

1.4615

1.674

1.685

1.674

1.6795

1.674

1.0525

0.7545

0.586

0.293

0.112

2

2A₂

2Y

1

2A₃

2Y

0

GND

2A₀

1Y

3

2A₁

1Y

2

2A₂

1Y

1

2A₃

1Y

0

2OE

V_CC

Note: Pad location is given as per metallization layer

INTEGRAL

5


型号：	IN74LV240N
厂家：	INTEGRAL CORP.
描述：	OCTAL BUFFER/LINE DRIVE; 3-STATE 八路缓冲器/线路驱动器; 3 -STATE 总线驱动器总线收发器
文件：	总5页 (文件大小：48K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IN74LV240N [INTEGRAL]

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