IZ74HC221AZ [INTEGRAL]
DUAL MONOSTABLE MULTIVIBRATOR; 双单稳多谐振荡器
| 型号： | IZ74HC221AZ |
| 厂家： | 
INTEGRAL CORP. |
| 描述： | DUAL MONOSTABLE MULTIVIBRATOR |
| 文件： | 总7页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IN74HC221A
DUAL MONOSTABLE MULTIVIBRATOR
The IN74HC221A is identical in pinout to the LS/ALS221. The
device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LS/ALSTTL outputs.
There are two trigger inputs, A INPUT (negative edge) and
B INPUT (positive edge). These inputs are valid for rising/falling
N SUFFIX
PLASTIC
16
signals
1
The device may also be triggered by using the RESET input
D SUFFIX
SOIC
(positive-edge) because of the Schmitt-trigger input; after
16
triggering the output maintains the MONOSTABLE state for the
ORDERING1INFORMATION
IN74HC221AN Plastic
IN74HC221AD SOIC
IZ74HC221AZ Chip
TA = -55° to 125° C for all
packages
time period determined by the external resistor REXT and
capacitor CEXT. Taking RESET low breaks this MONOSTABLE
STATE. If the next trigger pulse occurs during the
MONOSTABLE period it makes the MONOSTABLE period
longer.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 3.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
PIN ASSIGNMENT
LOGIC DIAGRAM
1A
1B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
1REXT/CEXT
1CEXT
DEXT
REXT
DEXT
REXT
1RESET
1Q
CEXT
CEXT
1Q
2Q
2Q
2CEXT
2RESET
2REXT/CEXT
GND
2B
2A
FUNCTION TABLE
Inputs
Outputs
Note
RESET
H
A
B
H
Q
Q
Output
Enable
Inhibit
Note
X
H
L
L
X
H
H
H
L *
L *
H *
H *
(1) CEXT, REXT, DEXT are external components.
(2) DEXT is a clamping diode.
Inhibit
Output
Enable
Output
Enable
Inhibit
The external capacitor is charged to VCC in the stand-by
state, i.e. no trigger. When the supply voltage is turned off
CX is discharged mainly through an internal parasitic
diode. If CX is sufficiently large and VCC decreases rapidy,
there will be some possibility of damaging the I.C. with a
surge current or latch-up. If the voltage supply filter
capacitor is large enough and VCC decrease slowly, the
surge current is automatically limited and damage the I.C.
is avoided. The maximum forward current of the parasitic
diode is approximately 20 mA.
L
H
X
X
L
L
H
X = don’t care
* - except for monostable period
1
IN74HC221A
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
Unit
V
VCC
VIN
VOUT
IIN
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
V
mA
, B,
A
RESET
±30
CEXT, REXT
IOUT
ICC
PD
DC Output Current, per Pin
mA
mA
mW
±25
DC Supply Current, VCC and GND Pins
±50
750
Power Dissipation in Still Air, Plastic DIP**
SOIC Package**
500
Tstg
TL
Storage Temperature
-65 to +150
°C
°C
Lead Temperature, 1 mm from Case for 10
Seconds
260
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
**Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
3.0 *
0
Max
6.0
Unit
V
DC Supply Voltage (Referenced to GND)
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to
GND)
VCC
V
TA
tr, tf
Operating Temperature, All Package Types
-55
+125
°C
ns
VCC =2.0 V
VCC =4.5 V
CC =6.0 V
0
0
0
-
1000
500
Input Rise and Fall Time -
RESET
(Figure 2)
V
400
No
A
or B
A
Limit
1000
1000
RX
CX
External Timing Resistor
External Timing Capacitor
VCC <4.5 V
CC ≥ 4.5 V
10
kΩ
µF
2.0
V
0
No
Limit
*
The IN74HC221 will function at 2.0 V but for optimum pulse width stability, VCC should be above
3.0 V.
This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and
V
OUT should be constrained to the range GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
VCC). Unused outputs must be left open.
2
IN74HC221A
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VCC
V
Guaranteed Limit
Unit
-55°C
≤85
°C
≤125
to
25 °C
0.3
°C
VIL
VIH
VOL
Maximum Low - VOUT ≤ 0.1 V or 2.0
0.3
0.9
0.3
0.9
1.2
1.5
3.15
4.2
0.1
0.1
0.1
0.4
V
V
V
Level Input Voltage VCC=0.1
IOUT ≤ 20 µA
V
4.5
6.0
0.9
1.2
1.2
Minimum High-Level VOUT ≤ 0.1 V or 2.0
1.5
1.5
Input Voltage
VCC=0.1
V
4.5
6.0
3.15
4.2
3.15
4.2
IOUT ≤ 20 µA
Maximum Low-Level VIN=VIH
or
VIL 2.0
4.5
0.1
0.1
Output Voltage
0.1
0.1
IOUT ≤ 20 µA
6.0
0.1
0.1
VIN=VIH
IOUT ≤ 4.0 mA
VIN=VIH or
IOUT ≤ 5.2 mA
or
VIL 4.5
0.26
0.33
VIL 6.0
0.26
0.33
0.40
VOH
Minimum
High- VIN=VIH or VIL 2.0
1.9
4.4
1.9
4.4
1.9
4.4
V
Level
Output
4.5
6.0
IOUT ≤ -20 µA
Voltage
5.9
5.9
5.9
VIN=VIH or VIL 4.5
IOUT ≤ -4.0 mA
3.98
3.84
3.70
VIN=VIH or VIL 6.0
IOUT ≤ -5.2 mA
5.48
-0.1
5.34
-1.0
5.2
IIL
Maximum
Level
Low- VIL=GND
6.0
-1.0
µA
Output VIH=VCC
High- VIL=GND
Current
Minimum
IIH
6.0
6.0
0.1
8.0
1.0
80
1.0
µA
µA
Level Input Current VIH=VCC
ICC
Maximum
VIL=GND
160
Quiescent Supply VIН=VCC
Current
(per
I
OUT=0 µA
Package) Standby
State
ICC1
Maximum Supply VIL=GND
2.0
4.5
6.0
0.08
1.0
0.11
1.3
0.13
1.6
mA
Current
Package)
State
(per VIH=VCC
Active
2.0
2.6
3.2
I
OUT=0
µA
VIN = 0.5 VCC
3
IN74HC221A
AC ELECTRICAL CHARACTERISTICS
Parameter
Test
VCC
V
Guaranteed Limit
Unit
ns
Symbol
Conditions
-55°C
≤85
°C
≤125
to
25°C
180
36
°C
Maximum
VIL=0
VIH=VCC
V
2.0
4.5
225
45
270
54
tPHL
A, B -
Q
Propagation
Delay
tLH=tHL=6 ns 6.0
31
38
46
CL=50
pF
2.0
4.5
6.0
2.0
4.5
6.0
180
36
225
45
270
54
- Q
RESET
CEXT=0
R
EXT=5 kΩ
31
38
46
195
39
245
49
295
59
-
RESET Q
33
42
50
Maximum
Propagation
Delay
A, B - Q
VIL=0
V
2.0
4.5
220
44
275
55
330
66
ns
ns
tPLH
VIH=VCC
tLH=tHL=6 ns 6.0
37
47
56
CL=50
pF
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
245
49
305
61
370
74
- Q
RESET
CEXT=0
R
EXT=5 kΩ
42
52
63
200
40
250
50
300
60
-
RESET Q
34
43
51
Maximum Output Transition VIL=0
Time, Any Output(Figures 2 VIH=VCC
V
75
95
110
22
tTLH, tTHL
16
20
and 3)
tLH=tHL=6 нс 6.0
14
17
20
CL=50 pF
-
Maximum
Input
10
20
10
20
10
20
pF
pF
CIN
, B,
A
RESET
CX, RX
Capacitance
Power
Dissipation
5.0
180*
CPD
Capacitance
(Per Multivibrator)
PD=CPDVCC2f+ICCVCC
Minimum Recovery Time, VIL=0
V
2.0
4.5
100
20
125
25
150
30
ns
ns
trec
Inactive
to
A
or
B
VIH=VCC
(Figure 2)
tLH=tHL=6 нс 6.0
17
21
26
CL=50 pF
Minimum
VIL=0
V
2.0
4.5
25
9
95
19
110
22
tw
A,
RESET
Pulse Width
VIH=VCC
tLH=tHL=6 ns 6.0
7
16
19
CL=50
pF
B
2.0
4.5
6.0
30
11
9
115
23
135
27
C
R
EXT=0
EXT=5 kΩ
20
23
Minimum
(Figure 4)
Pulse
Width СEXT =0 пФ 5.0
105*
ns
tWQ
R
EXT=5 kΩ
СEXT =1 nF 2.0
0.80*
0.75*
0.70*
80*
µs
4.5
R
EXT=10 kΩ
6.0
2.0
4.5
6.0
СEXT =1 µF
75*
R
EXT=10 kΩ
70*
* ТА=25±10°C
4
IN74HC221A
Figure 1. Switching Waveforms
RESET
Figure 2. Switching Waveforms
Figure 3. Test Circuit
5
IN74HC221A
TIMING DIAGRAM
REXT/CEXT
EXPANDED LOGIC DIAGRAM
REXT/CEXT
CEXT
6
IN74HC221A
CHIP PAD DIAGRAM IZ74HC221A
2.1
13
±
0.03
12
14
15
16
11
10
09
08
07
Chip marking
15HC221
1
(x=0.140, y=0.884)
02
03
04
05 06
(0,0)
Pad size 0.106 x 0.106 mm (Pad size is given as per passivation layer)
Thickness of chip 0,46±0,02 mm
PAD LOCATION
Pad No
Symbol
X
Y
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
1A
0.152
0.157
0.458
0.715
1.310
1.585
1.836
1.847
1.836
1.837
1.536
1.278
0.684
0.408
0.158
0.147
0.419
0.132
0.134
0.122
0.122
0.122
0.132
0.690
1.275
1.562
1.560
1.572
1.572
1.572
1.562
1.004
1B
1RESET
1Q
2Q
2CEXT
2REXT/CEXT
GND
2A
2B
2RESET
2Q
1Q
1CEXT
1REXT/CEXT
VCC
7
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