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DA28F016XS-20 [INTEL]

16-MBIT (1 MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY; 16兆位（ 1兆比特×16 ， 2兆×8 ）同步闪存
DA28F016XS-20
型号： DA28F016XS-20
厂家： INTEL    INTEL
描述：

16-MBIT (1 MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY
16兆位（ 1兆比特×16 ， 2兆×8 ）同步闪存

闪存 存储 内存集成电路 光电二极管
文件： 总54页 (文件大小：1262K)
中文：  中文翻译
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E
28F016XS  
16-MBIT (1 MBIT x 16, 2 MBIT x 8)  
SYNCHRONOUS FLASH MEMORY  
Effective Zero Wait-State Performance  
up to 33 MHz  
Synchronous Pipelined Reads  
Backwards-Compatible with 28F008SA  
Command-Set  
2 µA Typical Deep Power-Down  
SmartVoltage Technology  
1 mA Typical Active ICC Current in  
Static Mode  
User-Selectable 3.3V or 5V VCC  
User-Selectable 5V or 12V VPP  
16 Separately-Erasable/Lockable  
128-Kbyte Blocks  
0.33 MB/sec Write Transfer Rate  
Configurable x8 or x16 Operation  
1 Million Erase Cycles per Block  
56-Lead TSOP and SSOP Type I  
Package  
State-of-the-Art 0.6 µm ETOX™ IV Flash  
Technology  
Intel’s 28F016XS 16-Mbit flash memory is a revolutionary architecture which is the ideal choice for designing  
truly revolutionary high-performance products. Combining very high read performance with the intrinsic  
nonvolatility of flash memory, the 28F016XS eliminates the traditional redundant memory paradigm of  
shadowing code from a slow nonvolatile storage source to a faster execution memory, such as DRAM, for  
improved system performance. The innovative capabilities of the 28F016XS enable the design of direct-  
execute code and mass storage data/file flash memory systems.  
The 28F016XS is the highest performance high-density nonvolatile read/program flash memory solution  
available today. Its synchronous pipelined read interface, flexible VCC and VPP voltages, extended cycling,  
fast program and read performance, symmetrically-blocked architecture, and selective block locking provide a  
highly flexible memory component suitable for resident flash component arrays on the system board or  
SIMMs. The synchronous pipelined interface and x8/x16 architecture of the 28F016XS allow easy interface  
with minimal glue logic to a wide range of processors/buses, providing effective zero wait-state read  
performance up to 33 MHz. The 28F016XS’s dual read voltage allows the same component to operate at  
either 3.3V or 5.0V VCC. Programming voltage at 5V VPP minimizes external circuitry in minimal-chip, space  
critical designs, while the 12.0V VPP option maximizes program/erase performance. Its high read performance  
combined with flexible block locking enable both storage and execution of operating systems/application  
software and fast access to large data tables. The 28F016XS is manufactured on Intel’s 0.6 µm ETOX IV  
process technology.  
November 1996  
Order Number: 290532-004  
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or  
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of  
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to  
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or  
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life  
saving, or life sustaining applications.  
Intel may make changes to specifications and product descriptions at any time, without notice.  
The 28F016XS may contain design defects or errors known as errata. Current characterized errata are available upon request.  
*Third-party brands and names are the property of their respective owners.  
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.  
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be  
obtained from:  
Intel Corporation  
P.O. Box 7641  
Mt. Prospect, IL 60056-7641  
or call 1-800-879-4683  
COPYRIGHT © INTEL CORPORATION, 1996  
CG-041493  
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28F016XS FLASH MEMORY  
CONTENTS  
PAGE  
PAGE  
1.0 INTRODUCTION............................................7  
5.0 ELECTRICAL SPECIFICATIONS .................24  
5.1 Absolute Maximum Ratings .......................24  
5.2 Capacitance...............................................24  
1.1 Product Overview ........................................7  
2.0 DEVICE PINOUT........................................... 10  
5.3 Transient Input/Output Reference  
2.1 Lead Descriptions...................................... 12  
Waveforms...............................................26  
5.4 DC Characteristics (VCC = 3.3V) ................27  
5.5 DC Characteristics (VCC = 5.0V) ................30  
5.6 Timing Nomenclature.................................33  
3.0 MEMORY MAPS........................................... 14  
3.1 Extended Status Register Memory Map..... 15  
4.0 BUS OPERATIONS, COMMANDS AND  
STATUS REGISTER DEFINITIONS............. 16  
5.7 AC Characteristics—Read Only  
Operations ................................................34  
4.1 Bus Operations for Word-Wide Mode  
5.8 AC Characteristics for WE#—Controlled  
Write Operations.......................................40  
(BYTE# = VIH)........................................... 16  
4.2 Bus Operations for Byte-Wide Mode  
5.9 AC Characteristics for CE #—Controlled  
X
(BYTE# = VIL) ........................................... 17  
Write Operations.......................................44  
5.10 Power-Up and Reset Timings ..................48  
5.11 Erase and Program Performance.............49  
4.3 28F008SA—Compatible Mode Command  
Bus Definitions.......................................... 18  
4.4 28F016XS—Enhanced Command Bus  
Definitions................................................. 19  
6.0 MECHANICAL SPECIFICATIONS................51  
4.5 Compatible Status Register ....................... 20  
4.6 Global Status Register............................... 21  
4.7 Block Status Register ................................ 22  
4.8 Device Configuration Code ........................ 23  
4.9 SFI Configuration Table............................. 23  
APPENDIX A: Device Nomenclature and  
Ordering Information..................................53  
APPENDIX B: Additional Information...............54  
3
28F016XS FLASH MEMORY  
Number  
E
REVISION HISTORY  
Description  
-001  
-002  
Original Version  
Removed support of the following features:  
•
•
•
•
•
All page buffer operations (read, write, programming, Upload Device Information)  
Command queuing  
Software Sleep and Abort  
Erase all Unlocked Blocks and Two-Byte Write  
RY/BY# Configuration as part of the Device Configuration command  
Changed definition of “NC.” Removed “No internal connection to die” from description.  
Added “xx” to Upper Byte of Command (Data) Definition in Sections 4.3 and 4.4.  
Modified parameters “V” and “I” of Section 5.1 to apply to “NC” pins.  
Increased IPPR (VPP Read Current) for VPP > VCC to 200 µA at VCC = 3.3V/5.0V.  
Changed VCC = 5.0V DC Characteristics (Section 5.5) marked with Note 1 to indicate  
that these currents are specified for a CMOS rise/fall time (10% to 90%) of <5 ns  
and a TTL rise/fall time of <10 ns.  
Corrected tPHCH (RP# High to CLK) to be a “Min” specification at VCC = 3.3V/5.0V.  
Corrected the graphical representation of tWHCH and tEHCH in Figures 15 and 16.  
Increased Typical “Byte/Word Program Times” (tWHRH1A/tWHRH1B) for VPP = 5.0V (Sec.  
5.13): tWHRH1A from 16.5 µs to 29.0 µs and tWHRH1B from 24.0 µs to 35.0 µs at VCC  
3.3V  
=
tWHRH1A from 11.0 µs to 20.0 µs and tWHRH1B from 16.0 µs to 25.0 µs at VCC = 5.0V.  
Increased Typical “Block Program Times” (tWHRH2/ tWHRH3) for VPP = 5.0V (Section 5.13):  
tWHRH2 from 2.2 sec to 3.8 sec and tWHRH3 from 1.6 sec to 2.4 sec at VCC = 3.3V  
tWHRH2 from 1.6 sec to 2.8 sec and tWHRH3 from 1.2 sec to 1.7 sec at VCC = 5.0V.  
Changed “Time from Erase Suspend Command to WSM Ready” spec name to “Erase  
Suspend Latency Time to Read;” Modified typical values and Added Min/Max values  
at VCC =3.3/5.0V and VPP =5.0/12.0V (Section 5.13).  
Minor cosmetic changes throughout document.  
Added 3/5# pin to Pinout Configuration (Figure 2), Product Overview (Section 1.1) and  
Lead Descriptions (Section 2.1)  
-003  
Modified Block Diagram (Figure 1): Removed Address Counter; Added 3/5# pin  
Added 3/5# pin to Test Conditions of ICCS Specifications  
Added 3/5# pin (Y) to Timing Nomenclature (Section 5.6)  
Removed Note 7 of Section 5.7  
Modified Device Configuration Code: Incorporated RY/BY# Configuration (Level Mode  
support ONLY)  
Modified Power-Up and Reset Timings (Section 5.10) to include 3/5# pin: Removed t5VPH  
and t3VPH specifications; Added tPLYL, tPLYH, tYLPH, and tYHPH specifications  
Added SSOP pinout (Figure 2) and Mechanical Specifications  
Corrected TSOP Mechanical Specification A1 from 0.50 mm to 0.050 mm (Section 6.0)  
Minor cosmetic changes throughout document.  
4
E
28F016XS FLASH MEMORY  
REVISION HISTORY (Continued)  
Number  
Description  
Require all VCC Tolerences to be within 5% of Operational Voltage  
IPPES Is Pushed to 200 µA from 50 Max  
ICCD Is Pushed to 10 µA from 5 Max  
Updated tAVAV at 3.3V  
-004  
Updated tELEH at 3.3V and 5.0V  
5
28F016XS FLASH MEMORY  
E
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6
E
28F016XS FLASH MEMORY  
The implementation of a new architecture, with  
many enhanced features, will improve the device  
operating characteristics and result in greater  
product reliability and ease-of-use as compared to  
other flash memories. Significant features of the  
28F016XS as compared to previous asynchronous  
flash memories include:  
1.0  
INTRODUCTION  
The documentation of the Intel 28F016XS Flash  
memory device includes this datasheet, a detailed  
user’s manual, a number of application notes and  
design tools, all of which are referenced in  
Appendix B.  
•
•
Synchronous Pipelined Read Interface  
The datasheet is intended to give an overview of  
the chip feature-set and of the operating AC/DC  
specifications. The 16-Mbit Flash Product Family  
User’s Manual provides complete descriptions of  
the user modes, system interface examples and  
detailed descriptions of all principles of operation. It  
also contains the full list of software algorithm  
flowcharts, and a brief section on compatibility with  
the Intel 28F008SA.  
Significantly Improved Read and Program  
Performance  
•
SmartVoltage Technology  
Selectable 3.3V or 5.0 VCC  
Selectable 5.0V or 12.0 VPP  
Block Program/Erase Protection  
•
The 28F016XS’s synchronous pipelined interface  
dramatically raises read performance far beyond  
previously attainable levels. Addresses are  
synchronously latched and data is read from a  
Significant 28F016XS feature revisions occurred  
between datasheet revisions 290532-001 and  
290532-002. These revisions center around  
removal of the following features:  
28F016XS bank every 30 ns (5V VCC  
, SFI  
•
All page buffer operations (read, write,  
programming, Upload Device Information)  
Configuration = 2). This capability translates to zero  
wait-state reads at clock rates up to 33 MHz at 5V  
V
CC, after an initial address pipeline fill delay and  
•
•
•
•
Command queuing  
assuming even and odd banks within the flash  
memory are alternately accessed. Data is latched  
and driven valid 20 ns (tCHQV) after a rising CLK  
edge. The 28F016XS is capable of operating up to  
Software Sleep and Abort  
Erase all Unlocked Blocks and Two-Byte Write  
RY/BY# Configuration options  
50 MHz (5V  
VCC); its programmable SFI  
Configuration enables system design flexibility,  
optimizing the 28F016XS to a specific system clock  
frequency. See Section 4.9, SFI Configuration  
Table, for specific SFI Configurations for given  
operating frequencies.  
In addition,  
a
significant 28F016XS change  
occurred between datasheet revisions 290532-002  
and 290532-003. This change centers around the  
addition of  
a 3/5# pin to the device’s pinout  
configuration. Figures 2 and 3 show the 3/5# pin  
assignment for the TSOP and SSOP Type  
packages.  
I
The SFI Configuration optimizes the 28F016XS for  
a wide range of system operating frequencies. The  
default SFI Configuration is 4, which allows system  
boot from the 28F016XS at any frequency up to  
50 MHz at 5V VCC. After initiating an access, data  
is latched and begins driving on the data outputs  
Intel recommends that all customers obtain the  
latest revisions of 28F016XS documentation.  
after  
a CLK count corresponding to the SFI  
1.1  
Product Overview  
Configuration has elapsed. The 28F016XS will hold  
data valid until CE# or OE# is deactivated or a CLK  
count corresponding to the SFI Configuration for a  
subsequent access has elapsed.  
The 28F016XS is a high-performance, 16-Mbit  
(16,777,216-bit) block erasable nonvolatile random  
access memory organized as either 1 Mword x 16  
or 2 Mbyte x 8, subdivided into even and odd  
banks. Address A1 makes the bank selection. The  
28F016XS includes sixteen 128-Kbyte (131,072  
byte) blocks or sixteen 64-Kword (65,536 word)  
blocks. Chip memory maps for x8 and x16 modes  
are shown in Figures 4 and 5.  
The CLK and ADV# inputs, new to the 28F016XS in  
comparison to previous flash memories, control  
address latching and device synchronization during  
read operations. The CLK input controls the device  
latencies, times out the SFI Configuration counter  
and synchronizes data outputs. ADV# indicates the  
presence of a valid address on the 28F016XS  
7
28F016XS FLASH MEMORY  
E
address inputs. During read operations, addresses  
are latched and accesses are initiated on a rising  
CLK edge in conjunction with ADV# low. Both CLK  
and ADV# are ignored by the 28F016XS during  
command/data write sequences.  
Block Erase Cycles by providing wear-leveling  
algorithms and graceful block retirement. These  
techniques have already been employed in many  
flash file systems and hard disk drive designs.  
All operations are started by a sequence of Write  
commands to the device. Three Status Registers  
(described in detail later in this datasheet) and a  
RY/BY# output pin provide information on the  
progress of the requested operation.  
The  
28F016XS  
incorporates  
SmartVoltage  
technology, providing VCC operation at both 3.3V  
and 5.0V and program and erase capability at  
VPP = 12.0V or 5.0V. Operating at VCC = 3.3V, the  
28F016XS consumes less than one half the power  
consumption at 5.0V VCC, while 5.0V VCC provides  
highest read performance capability. VPP operation  
at 5.0V eliminates the need for a separate 12.0V  
converter, while the VPP = 12.0V option maximizes  
program/erase performance. In addition to the  
flexible program and erase voltages, the dedicated  
The following Status Registers are used to provide  
device and WSM operation information to the user:  
•
A Compatible Status Register (CSR) which is  
100% compatible with the 28F008SA FlashFile  
memory Status Register. The CSR, when used  
a straightforward upgrade  
capability to the 28F016XS from a 28F008SA-  
based design.  
VPP gives complete code protection with VPP  
VPPLK  
≤
alone, provides  
.
A 3/5# input pin configures the device’s internal  
circuitry for optimal 3.3V or 5.0V read/program  
operation.  
•
•
A Global Status Register (GSR) which also  
informs the system of overall Write State  
Machine (WSM) status.  
A Command User Interface (CUI) serves as the  
system interface between the microprocessor or  
microcontroller and the internal memory operation.  
16 Block Status Registers (BSRs) which  
provide block-specific status information such  
as the block lock-bit status.  
Internal Algorithm Automation allows program and  
block erase operations to be executed using a Two-  
Write command sequence to the CUI in the same  
way as the 28F008SA 8-Mbit FlashFile™ memory.  
The GSR and BSR memory maps for Byte-Wide  
and Word-Wide modes are shown in Figures 5  
and 6.  
Software locking of memory blocks is an added  
feature of the 28F016XS as compared to the  
28F008SA. The 28F016XS provides selectable  
block locking to protect code or data such as direct-  
executable operating systems or application code.  
Each block has an associated nonvolatile lock-bit  
which determines the lock status of the block. In  
addition, the 28F016XS has a master Write Protect  
pin (WP#) which prevents any modifications to  
memory blocks whose lock-bits are set.  
The 28F016XS incorporates an open drain RY/BY#  
output pin. This feature allows the user to OR-tie  
many RY/BY# pins together in a multiple memory  
configuration such as a Resident Flash Array.  
The 28F016XS also incorporates a dual chip-  
enable function with two input pins, CE0# and CE1#.  
These pins have exactly the same functionality as  
the regular chip-enable pin, CE#, on the 28F008SA.  
For minimum chip designs, CE1# may be tied to  
ground and system logic may use CE0# as the chip  
enable input. The 28F016XS uses the logical  
combination of these two signals to enable or  
disable the entire chip. Both CE0# and CE1# must  
be active low to enable the device. If either one  
becomes inactive, the chip will be disabled. This  
feature, along with the open drain RY/BY# pin,  
allows the system designer to reduce the number of  
control pins used in a large array of 16-Mbit  
devices.  
Writing of memory data is performed in either byte  
or word increments, typically within 6 µs at 12.0V  
VPP  
, which is a 33% improvement over the  
28F008SA. A block erase operation erases one of  
the 16 blocks in typically 1.2 sec, independent of  
the other blocks.  
Each block can be written and erased a minimum of  
100,000 cycles. Systems can achieve one million  
8
E
28F016XS FLASH MEMORY  
DQ  
DQ  
8-15  
0-7  
Output  
Buffer  
Output  
Buffer  
Input  
Buffer  
Input  
Buffer  
3/5#  
I/O Logic  
BYTE#  
Data  
Register  
ID  
Register  
CLK  
ADV#  
CSR  
CE  
#
#
0
ESRs  
CE  
1
OE#  
WE#  
WP#  
RP#  
Data  
Comparator  
Input  
Buffer  
Y
Y Gating/Sensing  
Even Bank  
Decoder  
X
Decoder  
RY/BY#  
Address  
Register  
V
PP  
Program/Erase  
Voltage Switch  
3/5#  
V
CC  
X
Decoder  
GND  
Odd Bank  
Y
Y Gating/Sensing  
Decoder  
0532_01  
Figure 1. 28F016XS Block Diagram  
Architectural Evolution Includes Synchronous Pipelined Read Interface,  
SmartVoltage Technology, and Extended Status Registers  
9
4/15/97 9:41 AM 9053204.DOC  
INTEL CONFIDENTIAL  
(until publication date)  
28F016XS FLASH MEMORY  
E
The BYTE# pin allows either x8 or x16  
read/programs to the 28F016XS. BYTE# at logic  
low selects 8-bit mode with address A0 selecting  
between low byte and high byte. On the other hand,  
BYTE# at logic high enables 16-bit operation with  
address A1 becoming the lowest order address and  
address A0 is not used (don’t care). A device block  
diagram is shown in Figure 1.  
28F016XS. In the deep power-down state, the  
WSM is reset (any current operation will abort) and  
the CSR, GSR and BSR registers are cleared.  
A CMOS standby mode of operation is enabled  
when either CE0# or CE1# transitions high and RP#  
stays high with all input control pins at CMOS  
levels. In this mode, the device typically draws an  
I
CC standby current of 70 µA at 5V VCC.  
The 28F016XS incorporates an Automatic Power  
Saving (APS) feature, which substantially reduces  
the active current when the device is in static mode  
of operation (addresses not switching). In APS  
mode, the typical ICC current is 1 mA at 5.0V (3 mA  
at 3.3V).  
The 28F016XS is available in 56-Lead, 1.2 mm  
thick, 14 mm x 20 mm TSOP and 1.8 mm thick, 16  
mm x 23.7 mm SSOP Type I packages. The form  
factor and pinout of these two packages allow for  
very high board layout densities.  
A deep power-down mode of operation is invoked  
when the RP# (called PWD# on the 28F008SA) pin  
transitions low. This mode brings the device power  
consumption to less than 2.0 µA, typically, and  
provides additional write protection by acting as a  
device reset pin during power transitions. A reset  
time of 300 ns (5V VCC) is required from RP#  
switching high before latching an address into the  
2.0 DEVICE PINOUT  
The 28F016XS is pinout compatible with the  
28F016SA/SV 16-Mbit FlashFile memory com-  
ponents, providing a performance upgrade path to  
the 28F016XS. The 28F016XS 56-Lead TSOP and  
SSOP pinout configurations are shown in Figures 2  
and 3.  
28F016SA/SV  
28F016SA/SV  
56  
1
2
3
4
5
6
7
3/5#  
CE1#  
WP#  
WE#  
OE#  
RY/BY#  
DQ15  
DQ7  
DQ14  
DQ6  
GND  
DQ13  
DQ5  
WP#  
WE#  
OE#  
RY/BY#  
DQ15  
DQ7  
DQ14  
DQ6  
GND  
DQ13  
DQ5  
DQ12  
DQ4  
VCC  
GND  
DQ11  
DQ3  
DQ10  
DQ2  
VCC  
3/5#  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
CE #  
1
NC  
A20  
A19  
A18  
A17  
A16  
VCC  
A15  
A14  
A13  
A12  
CE0#  
VPP  
RP#  
A11  
A10  
A9  
A8  
GND  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
NC  
A20  
A19  
A18  
A17  
A16  
VCC  
A15  
A14  
A13  
A12  
CE0 #  
VPP  
RP#  
A11  
A10  
A9  
A8  
GND  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
E28F016XS  
56-LEAD TSOP PINOUT  
DQ12  
DQ4  
VCC  
GND  
DQ11  
DQ3  
DQ10  
DQ 2  
VCC  
DQ 9  
DQ 1  
DQ 8  
DQ 0  
A0  
14 mm x 20 mm  
TOP VIEW  
DQ9  
DQ1  
DQ8  
DQ0  
A0  
BYTE#  
NC  
26  
27  
28  
BYTE#  
ADV#  
CLK  
30  
29  
NC  
0532_02  
Figure 2. 28F016XS 56-Lead TSOP Pinout Configuration Shows Compatibility with  
the 28F016SA/SV, Allowing for Easy Performance Upgrades from Existing 16-Mbit Designs  
10  
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28F016XS FLASH MEMORY  
28F016SA/SV  
28F016SA/SV  
CE0#  
A12  
CE0#  
A12  
1
2
3
4
56  
VPP  
VPP  
55  
54  
RP#  
A11  
RP#  
A11  
A13  
A13  
A14  
53  
52  
51  
50  
A10  
A9  
A1  
A2  
A10  
A9  
A1  
A2  
A14  
A15  
A15  
3/5#  
5
6
3/5#  
CE1#  
NC  
A20  
CE1#  
NC  
A20  
7
8
9
49  
48  
47  
46  
A3  
A4  
A5  
A6  
A3  
A4  
A5  
A6  
A19  
A18  
A19  
A18  
10  
11  
12  
13  
14  
15  
DA28F016XS  
56-LEAD SSOP  
STANDARD PINOUT  
A17  
A16  
VCC  
A17  
A16  
VCC  
45  
A7  
A7  
44  
43  
42  
GND  
A8  
GND  
A8  
16 mm x 23.7 mm  
TOP VIEW  
GND  
DQ6  
VCC  
VCC  
DQ9  
DQ1  
DQ8  
DQ0  
A0  
GND  
DQ6  
41  
40  
39  
DQ9  
DQ1  
DQ8  
16  
17  
18  
19  
DQ14  
DQ7  
DQ14  
DQ7  
DQ15  
DQ15  
38  
37  
36  
DQ0  
A0  
RY/BY#  
OE#  
RY/BY#  
OE#  
20  
21  
22  
23  
BYTE#  
BYTE#  
WE#  
WP#  
DQ13  
WE#  
35  
34  
ADV#  
CLK  
NC  
NC  
WP#  
DQ13  
24  
25  
26  
27  
28  
33  
32  
31  
30  
29  
DQ2  
DQ10  
DQ2  
DQ10  
DQ3  
DQ5  
DQ12  
DQ4  
VCC  
DQ5  
DQ12  
DQ4  
VCC  
DQ3  
DQ11  
GND  
DQ11  
GND  
XS_SSOP  
Figure 3. 28F016XS 56-Lead SSOP Pinout Configuration Shows Compatibility with the 28F016SA/SV,  
Allowing for Easy Performance Upgrades from Existing 16-Mbit Designs  
11  
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INTEL CONFIDENTIAL  
(until publication date)  
28F016XS FLASH MEMORY  
E
2.1  
A0  
Lead Descriptions  
Symbol  
Type  
Name and Function  
INPUT  
BYTE-SELECT ADDRESS: Selects between high and low byte when device is  
in x8 mode. This address is latched in x8 data programs and ignored in x16  
mode (i.e., the A0 input buffer is turned off when BYTE# is high).  
A1  
INPUT  
BANK-SELECT ADDRESS: Selects an even or odd bank in a selected block.  
A 128-Kbyte block is subdivided into an even and odd bank. A1 = 0 selects the  
even bank and A1 = 1 selects the odd bank, in both byte-wide mode and word-  
wide mode device configurations.  
A2–A16  
INPUT  
WORD-SELECT ADDRESSES: Select a word within one 128-Kbyte block.  
Address A1 and A7–16 select 1 of 2048 rows, and A2–6 select 16 of 512  
columns. These addresses are latched during both data reads and programs.  
A17–A20  
INPUT  
INPUT/  
BLOCK-SELECT ADDRESSES: Select 1 of 16 erase blocks. These  
addresses are latched during data programs, erase and lock-block operations.  
DQ0–DQ7  
LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.  
OUTPUT Outputs array, identifier or status data in the appropriate read mode. Floated  
when the chip is de-selected or the outputs are disabled.  
DQ8–DQ15  
INPUT/  
HIGH-BYTE DATA BUS: Inputs data during x16 data program operations.  
OUTPUT Outputs array or identifier data in the appropriate read mode; not used for  
Status Register reads. Outputs floated when the chip is de-selected, the  
outputs are disabled (OE# = VIH) or BYTE# is driven active.  
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,  
decoders and sense amplifiers. With either CE0# or CE1# high, the device is  
de-selected and power consumption reduces to standby levels upon  
completion of any current data program or erase operations. Both CE0# and  
CE1# must be low to select the device.  
CE0#, CE1#  
INPUT  
All timing specifications are the same for both signals. Device Selection occurs  
with the latter falling edge of CE0# or CE1#. The first rising edge of CE0# or  
CE1# disables the device.  
RESET/POWER-DOWN: RP# low places the device in a deep power-down  
state. All circuits that consume static power, even those circuits enabled in  
standby mode, are turned off. When returning from deep power-down, a  
recovery time of tPHCH is required to allow these circuits to power-up.  
When RP# goes low, the current WSM operation is terminated, and the device  
is reset. All Status Registers return to ready, clearing all status flags. Exit from  
deep power-down places the device in read array mode.  
RP#  
INPUT  
OUTPUT ENABLE: Drives device data through the output buffers when low.  
The outputs float to tri-state off when OE# is high. CE # overrides OE#, and  
x
OE# overrides WE#.  
OE#  
WE#  
INPUT  
INPUT  
WRITE ENABLE: Controls access to the CUI, Data Register and Address  
Latch. WE# is active low, and latches both address and data (command or  
array) on its rising edge.  
12  
E
28F016XS FLASH MEMORY  
2.1  
Lead Descriptions (Continued)  
Symbol  
CLK  
Type  
Name and Function  
INPUT  
CLOCK: Provides the fundamental timing and internal operating frequency.  
CLK latches input addresses in conjunction with ADV#, times out the desired  
output SFI Configuration as a function of the CLK period, and synchronizes  
device outputs. CLK can be slowed or stopped with no loss of data or  
synchronization. CLK is ignored during program operations.  
ADV#  
INPUT  
ADDRESS VALID: Indicates that a valid address is present on the address  
inputs. ADV# low at the rising edge of CLK latches the address on the address  
inputs into the flash memory and initiates a read access to the even or odd  
bank depending on the state of A1. ADV# is ignored during program operations.  
RY/BY#  
OPEN  
DRAIN  
READY/BUSY: Indicates status of the internal WSM. When low, it indicates  
that the WSM is busy performing an operation. RY/BY# high indicates that the  
OUTPUT WSM is ready for new operations, erase is suspended, or the device is in deep  
power-down mode. This output is always active (i.e., not floated to tri-state off  
when OE# or CE0#, CE1# are high).  
WP#  
INPUT  
WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile lock-bit  
for each block. When WP# is low, those locked blocks as reflected by the  
Block-Lock Status bits (BSR.6), are protected from inadvertent data programs  
or erases. When WP# is high, all blocks can be written or erased regardless of  
the state of the lock-bits. The WP# input buffer is disabled when RP#  
transitions low (deep power-down mode).  
BYTE ENABLE: BYTE# low places device in x8 mode. All data is then input or  
output on DQ0–7, and DQ8–15 float. Address A0 selects between the high and  
low byte. BYTE# high places the device in x16 mode, and turns off the A0 input  
buffer. Address A1 then becomes the lowest order address.  
BYTE#  
3/5#  
INPUT  
INPUT  
3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V  
operation. 3/5# low configures internal circuits for 5.0V operation.  
NOTE:  
Reading the array with 3/5# high in a 5.0V system could damage the device.  
Reference the power-up and reset timings (Section 5.10) for 3/5# switching  
delay to valid data.  
VPP  
SUPPLY PROGRAM/ERASE POWER SUPPLY (12.0V ± 0.6V, 5.0V ± 0.5V) :  
For erasing memory array blocks or writing words/bytes into the flash array.  
VPP = 5.0V ± 0.5V eliminates the need for a 12.0V converter, while the 12.0V ±  
0.6V option maximizes program/erase performance.  
Successful completion of program and erase attempts is inhibited with VPP at  
or below 1.5V. Program and erase attempts with VPP between 1.5V and 4.5V,  
between 5.5V and 11.4V, and above 12.6V produce spurious results and  
should not be attempted.  
DEVICE POWER SUPPLY (3.3V ± 5%, 5.0V ± 5%):  
VCC  
SUPPLY  
To switch 3.3V to 5.0V (or vice versa), first ramp VCC down to GND, and then  
power to the new VCC voltage. Do not leave any power pins floating.  
13  
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INTEL CONFIDENTIAL  
(until publication date)  
28F016XS FLASH MEMORY  
2.1 Lead Descriptions (Continued)  
E
Symbol  
GND  
Type  
Name and Function  
GROUND FOR ALL INTERNAL CIRCUITRY:  
Do not leave any ground pins floating.  
SUPPLY  
NO CONNECT:  
NC  
Lead may be driven or left floating.  
3.0 MEMORY MAPS  
x8 Mode  
x16 Mode  
A20-1  
A20-0  
1FFFFF  
FFFFF  
128-Kbyte Block 15  
128-Kbyte Block 14  
128-Kbyte Block 13  
128-Kbyte Block 12  
128-Kbyte Block 11  
64-Kword Block 15  
1E0000  
1DFFFF  
F0000  
EFFFF  
64-Kword Block  
64-Kword Block  
64-Kword Block  
64-Kword Block  
64-Kword Block  
14  
13  
12  
11  
10  
E0000  
DFFFF  
1C0000  
1BFFFF  
1A0000  
19FFFF  
D0000  
CFFFF  
180000  
17FFFF  
C0000  
BFFFF  
160000  
15FFFF  
B0000  
AFFFF  
128-Kbyte Block  
128-Kbyte Block  
128-Kbyte Block  
128-Kbyte Block  
10  
9
140000  
13FFFF  
A0000  
9FFFF  
64-Kword Block 9  
64-Kword Block 8  
64-Kword Block 7  
120000  
11FFFF  
90000  
8FFFF  
8
100000  
0FFFFF  
80000  
7FFFF  
7
0E0000  
0DFFFF  
70000  
6FFFF  
6
128-Kbyte Block  
128-Kbyte Block  
6
64-Kword Block  
0C0000  
0BFFFF  
60000  
5FFFF  
5
64-Kword Block 5  
64-Kword Block 4  
64-Kword Block 3  
64-Kword Block 2  
64-Kword Block 1  
0A0000  
09FFFF  
50000  
4FFFF  
128-Kbyte Block 4  
080000  
07FFFF  
40000  
3FFFF  
3
2
1
0
128-Kbyte Block  
128-Kbyte Block  
128-Kbyte Block  
128-Kbyte Block  
060000  
05FFFF  
30000  
2FFFF  
040000  
03FFFF  
20000  
1FFFF  
020000  
01FFFF  
10000  
0FFFF  
0
64-Kword Block  
000000  
00000  
0532_03  
0532_04  
Figure 4. 28F016XS Memory Map  
(Byte-Wide Mode)  
Figure 5. 28F016XS Memory Map  
(Word-Wide Mode)  
14  
E
28F016XS FLASH MEMORY  
3.1  
Extended Status Register Memory Map  
x8 Mode  
x16 Mode  
A 20-1  
A20-0  
FFFFFH  
1FFFFFH  
RESERVED  
RESERVED  
F0003H  
F0002H  
1E0006H  
1E0005H  
1E0004H  
1E0003H  
RESERVED  
GSR  
RESERVED  
GSR  
RESERVED  
RESERVED  
BSR 15  
BSR 15  
F0001H  
F0000H  
1E0002H  
1E0001H  
1E0000H  
RESERVED  
RESERVED  
RESERVED  
RESERVED  
.
.
.
.
.
.
0FFFFH  
01FFFFH  
000006H  
RESERVED  
RESERVED  
00003H  
00002H  
RESERVED  
GSR  
RESERVED  
GSR  
000005H  
000004H  
RESERVED  
BSR 0  
RESERVED  
BSR 0  
000003H  
000002H  
00001H  
00000H  
RESERVED  
RESERVED  
RESERVED  
RESERVED  
000001H  
000000H  
0532_05  
0532_06  
Figure 6. Extended Status Register Memory  
Map (Byte-Wide Mode)  
Figure 7. Extended Status Register Memory  
Map (Word-Wide Mode)  
15  
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INTEL CONFIDENTIAL  
(until publication date)  
28F016XS FLASH MEMORY  
4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS  
4.1 Bus Operations for Word-Wide Mode (BYTE# = V )  
E
IH  
Mode  
Notes  
RP# CE0–1  
#
OE#  
WE# ADV#  
CLK  
A1  
DQ0–15 RY/BY#  
Latch Read  
Address  
1,9,10  
VIH  
VIL  
X
VIH  
VIL  
↑
X
X
X
X
X
Inhibit  
1,9  
VIH  
VIL  
X
VIH  
VIH  
↑
X
Latching  
Read Address  
Read  
1,2,7,9  
1,6,7,9  
VIH  
VIH  
VIL  
VIL  
VIL  
VIH  
VIH  
VIH  
X
X
↑
X
X
DOUT  
X
X
Output  
X
High Z  
Disable  
Standby  
1,6,7,9  
1,3  
VIH  
VIL  
VIL  
X
X
X
X
X
X
X
X
X
X
X
High Z  
High Z  
X
Deep  
VOH  
Power-Down  
Manufacturer  
ID  
1,4,9  
VIH  
VIL  
VIL  
VIH  
X
↑
VIL  
0089H  
VOH  
Device ID  
1,4,8,9  
1,5,6,9  
VIH  
VIH  
VIL  
VIL  
VIL  
VIH  
VIH  
VIL  
X
X
↑
VIH  
X
66A8H  
DIN  
VOH  
X
Write  
X
NOTES:  
1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH, or High Z or DOUT for data  
pins depending on whether or not OE# is active.  
2. RY/BY# output is open drain. When the WSM is ready, Erase is suspended, or the device is in deep power-down mode,  
RY/BY# will be at VOH if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM operation  
is in progress.  
3. RP# at GND ± 0.2V ensures the lowest deep power-down current.  
4.  
A0 and A1 at VIL provide device manufacturer codes in x8 and x16 modes respectively. A and A1 at VIH provide device ID  
0
codes in x8 and x16 modes respectively. All other addresses are set to zero.  
5. Commands for erase, data program, or lock-block operations can only be completed successfully when VPP = VPPH1 or  
PP = VPPH2  
V
.
6. While the WSM is running, RY/BY# stays at VOL until all operations are complete. RY/BY# goes to VOH when the WSM is  
not busy or in erase suspend mode.  
7. RY/BY# may be at VOL while the WSM is busy performing various operations (for example, a Status Register read during a  
write operation).  
8. The 28F016XS shares an identical device identifier with the 28F016XD.  
9. CE0–1# at VIL is defined as both CE0# and CE1# low, and CE0–1# at VIH is defined as either CE0# or CE1# high.  
10. Addresses are latched on the rising edge of CLK in conjunction with ADV# low. Address A1 = 0 selects the even bank and  
A
1 = 1 selects the odd bank, in both byte-wide mode and word-wide mode device configurations.  
16  
E
28F016XS FLASH MEMORY  
4.2  
Bus Operations for Byte-Wide Mode (BYTE# = V )  
IL  
Mode  
Notes  
RP# CE0–1  
#
OE#  
WE# ADV#  
CLK  
A0  
DQ0–7 RY/BY#  
Latch Read  
Address  
1,9,10  
VIH  
VIL  
X
VIH  
VIL  
↑
X
X
X
Inhibit  
1,9  
VIH  
VIL  
X
VIH  
VIH  
↑
X
X
X
Latching  
Read Address  
Read  
1,2,7,9  
1,6,7,9  
VIH  
VIH  
VIL  
VIL  
VIL  
VIH  
VIH  
VIH  
X
X
↑
X
X
DOUT  
X
X
Output  
X
High Z  
Disable  
Standby  
1,6,7,9  
1,3  
VIH  
VIL  
VIH  
X
X
X
X
X
X
X
X
X
X
X
High Z  
High Z  
X
Deep  
VOH  
Power-Down  
Manufacturer  
ID  
1,4,9  
VIH  
VIL  
VIL  
VIH  
X
↑
VIL  
89H  
VOH  
Device ID  
1,4,8,9  
1,5,6,9  
VIH  
VIH  
VIL  
VIL  
VIL  
VIH  
VIH  
VIL  
X
X
↑
VIH  
X
A8H  
DIN  
VOH  
X
Write  
X
NOTES:  
1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH, or High Z or DOUT for data  
pins depending on whether or not OE# is active.  
2. RY/BY# output is open drain. When the WSM is ready, Erase is suspended, or the device is in deep power-down mode,  
RY/BY# will be at VOH if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM operation  
is in progress.  
3. RP# at GND ± 0.2V ensures the lowest deep power-down current.  
4.  
A0 and A1 at VIL provide device manufacturer codes in x8 and x16 modes respectively. A and A1 at VIH provide device ID  
0
codes in x8 and x16 modes respectively. All other addresses are set to zero.  
5. Commands for erase, data program, or lock-block operations can only be completed successfully when VPP = VPPH1 or  
PP = VPPH2  
V
.
6. While the WSM is running, RY/BY# stays at VOL until all operations are complete. RY/BY# goes to VOH when the WSM is  
not busy or in erase suspend mode.  
7. RY/BY# may be at VOL while the WSM is busy performing various operations (for example, a Status Register read during a  
program operation).  
8. The 28F016XS shares an identical device identifier with the 28F016XD.  
9. CE0–1# at VIL is defined as both CE0# and CE1# low, and CE0–1# at VIH is defined as either CE0# or CE1# high.  
10. Addresses are latched on the rising edge of CLK in conjunction with ADV# low. Address A = 0 selects the even bank and  
1
A
1 = 1 selects the odd bank, in both byte-wide mode and word-wide mode device configurations.  
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INTEL CONFIDENTIAL  
(until publication date)  
28F016XS FLASH MEMORY  
4.3 28F008SA—Compatible Mode Command Bus Definitions  
E
First Bus Cycle  
Second Bus Cycle  
Command  
Read Array  
Notes  
Oper  
Addr  
X
Data(4)  
Oper  
Read  
Read  
Read  
Addr  
AA  
IA  
Data(4)  
AD  
Write  
Write  
Write  
Write  
Write  
Write  
Write  
Write  
xxFFH  
xx90H  
xx70H  
xx50H  
xx40H  
xx10H  
xx20H  
xxB0H  
Intelligent Identifier  
1
2
3
X
ID  
Read Compatible Status Register  
Clear Status Register  
Program  
X
X
CSRD  
X
X
Write  
Write  
Write  
Write  
PA  
PA  
BA  
X
PD  
PD  
Alternate Program  
X
Block Erase/Confirm  
Erase Suspend/Resume  
X
xxD0H  
xxD0H  
X
ADDRESS  
DATA  
AA = Array Address  
AD = Array Data  
BA = Block Address  
IA = Identifier Address  
PA = Program Address  
X = Don’t Care  
CSRD = CSR Data  
ID = Identifier Data  
PD = Program Data  
NOTES:  
1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes.  
2. The CSR is automatically available after device enters data program, erase, or suspend operations.  
3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5, BSR.4 and BSR.2 bits. See Status Register  
definitions.  
4. The upper byte of the data bus (D8–15) during command writes is a “Don’t Care” in x16 operation of the device.  
18  
E
28F016XS FLASH MEMORY  
Second Bus Cycle  
4.4  
28F016XS—Enhanced Command Bus Definitions  
First Bus Cycle  
Command  
Notes  
Oper  
Addr  
Data(4)  
Oper  
Addr  
Data(4)  
Read Extended Status Register  
1
Write  
X
xx71H  
Read  
RA  
GSRD  
BSRD  
Lock Block/Confirm  
Write  
Write  
Write  
X
X
X
xx77H  
xx97H  
xx96H  
Write  
Write  
Write  
BA  
X
xxD0H  
xxD0H  
DCCD  
Upload Status Bits/Confirm  
Device Configuration  
2
3
X
ADDRESS  
DATA  
BA = Block Address  
RA = Extended Register Address  
PA = Program Address  
X = Don’t Care  
AD = Array Data  
BSRD = BSR Data  
GSRD = GSR Data  
DCCD = Device Configuration Code Data  
NOTES:  
1. RA can be the GSR address or any BSR address. See Figures 5 and 6 for Extended Status Register memory maps.  
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the  
actual lock-bit status.  
3. This command sets the SFI Configuration allowing the device to be optimized for the specific sytem operating frequency.  
4. The upper byte of the Data bus (D8–15) during command writes is a “Don’t Care” in x16 operation of the device.  
19  
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INTEL CONFIDENTIAL  
(until publication date)  
28F016XS FLASH MEMORY  
4.5 Compatible Status Register  
E
WSMS  
7
ESS  
6
ES  
5
DWS  
4
VPPS  
3
R
2
R
1
R
0
NOTES:  
CSR.7 = WRITE STATE MACHINE STATUS  
RY/BY# output or WSMS bit must be checked to  
determine completion of an operation (erase,  
erase suspend, or data program) before the  
appropriate Status bit (ESS, ES or DWS) is  
checked for success.  
1 = Ready  
0 = Busy  
CSR.6 = ERASE-SUSPEND STATUS  
1 = Erase Suspended  
0 = Erase In Progress/Completed  
CSR.5 = ERASE STATUS  
1 = Error In Block Erasure  
0 = Successful Block Erase  
If DWS and ES are set to “1” during an erase  
attempt, an improper command sequence was  
entered. Clear the CSR and attempt the  
operation again.  
CSR.4 = DATA WRITE STATUS  
1 = Error in Data Program  
0 = Data Program Successful  
CSR.3 = VPP STATUS  
1 = VPP Error Detect, Operation Abort  
0 = VPP OK  
The VPPS bit, unlike an A/D converter, does not  
provide continuous indication of VPP level. The  
WSM interrogates VPP’s level only after the Data  
Program or Erase command sequences have  
been entered, and informs the system if VPP has  
not been switched on. VPPS is not guaranteed to  
report accurate feedback between VPPLK(max)  
and VPPH1(min), between VPPH1(max) and  
V
PPH2(min), and above VPPH2(max).  
CSR.2–0 = RESERVED FOR FUTURE ENHANCEMENTS  
These bits are reserved for future use; mask them out when polling the CSR.  
20  
E
28F016XS FLASH MEMORY  
4.6  
Global Status Register  
WSMS  
7
OSS  
6
DOS  
5
R
4
R
3
R
2
R
1
R
0
NOTES:  
GSR.7 = WRITE STATE MACHINE STATUS  
RY/BY# output or WSMS bit must be checked to  
determine completion of an operation (block lock,  
suspend, Upload Status Bits, erase or data  
program) before the appropriate Status bit (OSS  
or DOS) is checked for success.  
1 = Ready  
0 = Busy  
GSR.6 = OPERATION SUSPEND STATUS  
1 = Operation Suspended  
0 = Operation in Progress/Completed  
GSR.5 = DEVICE OPERATION STATUS  
1 = Operation Unsuccessful  
0 = Operation Successful or Currently  
Running  
GSR.4–0 = RESERVED FOR FUTURE ENHANCEMENTS  
These bits are reserved for future use; mask them out when polling the GSR.  
21  
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INTEL CONFIDENTIAL  
(until publication date)  
28F016XS FLASH MEMORY  
4.7 Block Status Register  
E
BS  
7
BLS  
6
BOS  
5
R
4
R
3
VPPS  
2
VPPL  
1
R
0
NOTES:  
BSR.7 = BLOCK STATUS  
1 = Ready  
RY/BY# output or BS bit must be checked to  
determine completion of an operation (block lock,  
suspend, erase or data program) before the  
appropriate Status bits (BOS, BLS) is checked  
for success.  
0 = Busy  
BSR.6 = BLOCK LOCK STATUS  
1 = Block Unlocked for Program/Erase  
0 = Block Locked for Program/Erase  
BSR.5 = BLOCK OPERATION STATUS  
1 = Operation Unsuccessful  
0 = Operation Successful or  
Currently Running  
BSR.2 = VPP STATUS  
1 = VPP Error Detect, Operation Abort  
0 = VPP OK  
BSR.1 = VPP LEVEL  
BSR.1 is not guaranteed to report accurate  
feedback between the VPPH1 and VPPH2 voltage  
ranges. Programs and erases with VPP between  
1 = VPP Detected at 5.0V ± 10%  
0 = VPP Detected at 12.0V ± 5%  
V
V
V
PPLK(max) and VPPH1 (min), between  
PPH1(max) and VPPH2(min), and above  
PPH2(max) produce spurious results and should  
not be attempted.  
BSR.4,3,0 = RESERVED FOR FUTURE ENHANCEMENTS  
These bits are reserved for future use; mask them out when polling the BSRs.  
22  
E
28F016XS FLASH MEMORY  
4.8  
Device Configuration Code  
R
7
R
6
SFI2  
5
SFI1  
4
SFI0  
3
R
2
R
1
RB  
0
NOTES:  
DCC.5–DCC.3 = SFI CONFIGURATION  
(SFI2-SFI0)  
Default SFI Configuration on power-up or return  
from deep power-down mode is 4, allowing  
system boot from the 28F016XS at any  
001 = SFI Configuration 1  
010 = SFI Configuration 2  
011 = SFI Configuration 3  
100 = SFI Configuration 4  
(Default)  
frequency up to the device's maximum  
frequency. Undocumented combinations of  
SFI2-SFI0 are reserved by Intel Corporation for  
future implementations and should not be used.  
DCC.0 = RY/BY# CONFIGURATION  
(RB)  
Undocumented combinations of RB are reserved  
by Intel Corporation for future implementations  
and should not be used.  
1 = Level Mode (Default)  
DCC.7–DCC.6, DCC.2–DCC.1 = RESERVED FOR FUTURE ENHANCEMENTS  
These bits are reserved for future use. Set these bits to “0” when modifying the Device Configuration  
Code.  
4.9 SFI Configuration Table  
SFI  
28F016XS-15  
Frequency (MHz)  
28F016XS-20  
Frequency (MHz)  
28F016XS-25  
Frequency (MHz)  
Configuration  
Notes  
4
3
2
1
1
50 (and below)  
50 (and below)  
33 (and below)  
16.7 (and below)  
50 (and below)  
37.5 (and below)  
25 (and below)  
12.5 (and below)  
40 (and below)  
30 (and below)  
20 (and below)  
10 (and below)  
NOTE:  
1. Default SFI Configuration after power-up or return from deep power-down mode via RP#low.  
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(until publication date)  
28F016XS FLASH MEMORY  
E
5.0 ELECTRICAL SPECIFICATIONS  
NOTICE: This is  
a
production datasheet. The  
specifications are subject to change without notice. Verify  
with your local Intel Sales office that you have the latest  
datasheet before finalizing a design.  
5.1  
Absolute Maximum Ratings*  
Temperature Under Bias ....................0°C to +80°C  
*WARNING: Stressing the device beyond the “Absolute  
Maximum Ratings” may cause permanent damage.  
These are stress ratings only. Operation beyond the  
“Operating Conditions” is not recommended and  
extended exposure beyond the "Operating Conditions"  
may affect device reliability.  
Storage Temperature ...................–65°C to +125°C  
VCC = 3.3V ± 5% Systems  
Symbol  
TA  
Parameter  
Notes Min Max Units  
Test Conditions  
Operating Temperature, Commercial  
VCC with Respect to GND  
1
0
70  
°C Ambient Temperature  
VCC  
VPP  
V
2
–0.2  
7.0  
V
V
V
V
PP Supply Voltage with Respect to GND  
2,3  
2,5  
–0.2 14.0  
VCC  
Voltage on any Pin (except VCC,VPP) with  
Respect to GND  
–0.5  
+ 0.5  
± 30  
100  
I
Current into any Non-Supply Pin  
Output Short Circuit Current  
5
4
mA  
mA  
IOUT  
VCC = 5.0V ± 5% Systems  
Symbol  
Parameter  
Notes Min Max Units  
Test Conditions  
TA  
Operating Temperature, Commercial  
VCC with Respect to GND  
1
0
70  
°C Ambient Temperature  
VCC  
VPP  
V
2
–0.2  
7.0  
V
V
V
VPP Supply Voltage with Respect to GND  
2,3  
2,5  
–0.2 14.0  
Voltage on any Pin (except VCC,VPP) with  
Respect to GND  
–2.0  
7.0  
I
Current into any Non-Supply Pin  
Output Short Circuit Current  
5
4
± 30  
mA  
mA  
IOUT  
100  
NOTES:  
1. Operating temperature is for commercial product defined by this specification.  
2. Minimum DC voltage is –0.5V on input/output pins. During transitions, this level may undershoot to–2.0V for periods  
<20 ns. Maximum DC voltage on input/output pins is VCC +0.5V which may overshoot to VCC +2.0V for periods <20 ns.  
3. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns.  
4. Output shorted for no more than one second. No more than one output shorted at a time.  
5. This specification also applies to pins marked “NC.”  
24  
E
28F016XS FLASH MEMORY  
5.2  
Capacitance  
For a 3.3V ± 5% System:  
Symbol  
Parameter  
Notes  
Typ  
Max  
Units  
Test Conditions  
CIN  
Capacitance Looking into an  
Address/Control Pin  
1
6
8
pF  
TA = +25°C, f = 1.0 MHz  
COUT  
Capacitance Looking into an  
Output Pin  
1
8
12  
50  
pF  
pF  
TA = +25°C, f = 1.0 MHz  
CLOAD  
Load Capacitance Driven by  
Outputs for Timing Specifications  
1, 2  
For the 28F016XS-20  
and 28F016XS-25  
For 5.0V ± 5% System:  
Symbol  
Parameter  
Notes  
Typ  
Max  
Units  
Test Conditions  
CIN  
Capacitance Looking into an  
Address/Control Pin  
1
6
8
pF  
TA = +25°C, f = 1.0 MHz  
COUT  
CLOAD  
Capacitance Looking into an  
Output Pin  
1
8
12  
100  
30  
pF  
pF  
pF  
TA = +25°C, f = 1.0 MHz  
For the 28F016XS-20  
For the 28F016XS-15  
Load Capacitance Driven by  
Outputs for Timing Specifications  
1, 2  
NOTE:  
1. Sampled, not 100% tested. Guaranteed by design.  
2. To obtain iBIS models for the 28F016XS, please contact your local Intel/Distribution Sales Office.  
25  
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INTEL CONFIDENTIAL  
(until publication date)  
28F016XS FLASH MEMORY  
5.3 Transient Input/Output Reference Waveforms  
E
2.4  
2.0  
0.8  
2.0  
0.8  
INPUT  
OUTPUT  
TEST POINTS  
0.45  
0532_07  
AC test inputs are driven at VOH (2.4 VTTL) for a Logic “1” and VOL (0.45 VTTL) for a Logic “0.” Input timing begins at V  
IH  
(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.  
Figure 8. Transient Input/Output Reference Waveform (VCC = 5.0V ± 5%)  
for Standard Testing Configuration(1)  
3.0  
OUTPUT  
INPUT  
1.5  
TEST POINTS  
1.5  
0.0  
0532_08  
AC test inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0.” Input timing begins, and output timing ends, at 1.5V.  
Input rise and fall times (10% to 90%) <10 ns.  
Figure 9. Transient Input/Output Reference Waveform (VCC = 3.3V ± 5%)  
High Speed Reference Waveform(2) (VCC = 5.0V ± 5%)  
NOTES:  
1. Testing characteristics for 28F016XS-20 at 5V VCC  
.
2. Testing characteristics for 28F016XS-15 at 5V VCC and 28F016XS-20/28F016XS-25 at 3.3V VCC  
.
26  
E
28F016XS FLASH MEMORY  
5.4  
DC Characteristics  
VCC = 3.3V ± 5%, TA = 0°C to +70°C  
3/5# = Pin Set High for 3.3V Operations  
Symbol  
Parameter  
Notes  
Min  
Typ  
Max  
Units  
Test Conditions  
ILI  
Input Load Current  
1
± 1  
µA  
VCC = VCC Max  
V
IN = VCC or GND  
VCC = VCC Max  
OUT = VCC or GND  
ILO  
Output Leakage  
Current  
1
± 10  
µA  
µA  
V
ICCS  
VCC Standby  
Current  
1,5  
70  
1
130  
VCC = VCC Max  
CE0#, CE1#, RP# = VCC  
0.2V  
BYTE#, WP#, 3/5# = VCC  
0.2V or GND ± 0.2V  
VCC = VCC Max  
±
±
4
mA  
CE0#, CE1#, RP# = VIH  
BYTE#, WP#, 3/5# = VIH or  
VIL  
ICCD  
VCC Deep  
Power-Down  
Current  
1
2
5
µA  
RP# = GND ± 0.2V  
BYTE# = VCC ± 0.2V or  
GND ± 0.2V  
1
ICCR  
VCC Word/Byte  
Read Current  
1,4,5  
65  
85  
mA  
VCC = VCC Max  
CMOS: CE0# ,CE1# = GND  
± 0.2V, BYTE# = GND ±  
0.2V or VCC ± 0.2V,  
Inputs = GND ± 0.2V or  
VCC ± 0.2V  
4-Location Access  
Sequence: 3-1-1-1  
(clocks)  
f = 25 MHz, IOUT = 0 mA  
2
ICCR  
VCC Word/Byte  
Read Current  
1,4,  
5,6  
60  
75  
mA  
VCC = VCC Max  
CMOS: CE0#, CE1# = GND  
± 0.2V, BYTE# = GND ±  
0.2V or VCC ± 0.2V,  
Inputs = GND ± 0.2V or  
VCC ± 0.2V  
4-Location Access  
Sequence: 3-1-1-1  
(clocks)  
f = 16 MHz, IOUT = 0 mA  
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(until publication date)  
28F016XS FLASH MEMORY  
E
5.4  
DC Characteristics (Continued)  
VCC = 3.3V ± 5%, TA = 0°C to +70°C  
3/5# = Pin Set High for 3.3V Operations  
Symbol  
Parameter  
Notes  
Min  
Typ  
Max  
Units  
Test Conditions  
VPP = 12.0V ± 5%  
ICCW  
VCC Program  
Current  
1,6  
8
12  
mA  
Program in Progress  
VPP = 5.0V ± 10%  
8
6
17  
12  
mA  
mA  
Program in Progress  
VPP = 12.0V ± 5%  
ICCE  
VCC Block Erase  
Current  
1,6  
Block Erase in Progress  
9
3
17  
6
mA  
mA  
µA  
VPP = 5.0V ± 10%  
Block Erase in Progress  
ICCES  
VCC Erase  
1,2  
1
CE0#, CE1# = VIH  
Suspend Current  
Block Erase Suspended  
IPPS  
IPPR  
IPPD  
VPP Standby/Read  
Current  
± 1  
± 10  
VPP ≤ VCC  
30  
200  
5
µA  
µA  
VPP > VCC  
VPP Deep Power-  
Down Current  
1
0.2  
RP# = GND ± 0.2V  
IPPW  
VPP Program  
Current  
1,6  
10  
15  
mA  
VPP = 12.0V ± 5%  
Program in Progress  
Program in Progress  
VPP = 12.0V ± 5%  
15  
4
25  
10  
mA  
mA  
IPPE  
VPP Erase Current  
1,6  
Block Erase in Progress  
VPP = 5.0V ± 10%  
14  
30  
20  
mA  
µA  
Block Erase in Progress  
VPP = VPPH1 or VPPH2  
Block Erase Suspended  
IPPES  
VPP Erase  
1
200  
Suspend Current  
VIL  
VIH  
Input Low Voltage  
Input High Voltage  
6
6
–0.3  
2.0  
0.8  
V
V
VCC  
+0.3  
0.4  
VOL  
Output Low  
Voltage  
6
6
V
V
V
VCC = VCC Min  
I
OL = 4 mA  
VOH  
1
2
Output High  
Voltage  
2.4  
VCC = VCC Min  
IOH = –2.0 mA  
VOH  
VCC  
VCC = VCC Min  
–0.2  
IOH = –100 µA  
28  
E
28F016XS FLASH MEMORY  
5.4  
DC Characteristics (Continued)  
VCC = 3.3V ± 5%, TA = 0°C to +70°C  
3/5# = Pin Set High for 3.3V Operations  
Symbol  
Parameter  
Notes  
Min  
Typ  
Max  
Units  
Test Conditions  
VPPLK  
VPP  
3,6  
0.0  
1.5  
V
Erase/Program  
Lock Voltage  
VPPH1  
VPPH2  
VLKO  
VPP during  
3
3
4.5  
5.0  
5.5  
V
V
V
Program/Erase  
Operations  
VPP during  
11.4 12.0 12.6  
Program/Erase  
Operations  
VCC  
2.0  
Erase/Program  
Lock Voltage  
NOTES:  
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3V, VPP = 12.0V or 5.0V, T = +25°C. These  
currents are valid for all product versions (package and speeds).  
2.  
I
I
CCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of  
CCES and ICCR  
.
3. Block erases, programs and lock block operations are inhibited when VPP ≤ VPPLK and not guaranteed in the ranges  
between VPPLK(max) and VPPH1(min), between VPPH1 (max) and VPPH2(min) and above VPPH2(max).  
4. Automatic Power Savings (APS) reduces ICCR to 3 mA typical in static operation.  
5. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH  
.
6. Sampled, but not 100% tested. Guaranteed by design.  
29  
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INTEL CONFIDENTIAL  
(until publication date)  
28F016XS FLASH MEMORY  
5.5 DC Characteristics  
VCC = 5.0V ± 5%, TA = 0°C to +70°C  
3/5# = Pin Set Low for 5.0V Operations  
E
Parameter  
Notes  
Min  
Typ  
Max  
Units  
Test Conditions  
Symbol  
ILI  
Input Load Current  
1
± 1  
µA  
V
V
CC = VCC Max  
IN = VCC or GND  
ILO  
Output Leakage  
Current  
1
± 10  
130  
µA  
µA  
V
V
CC = VCC Max  
OUT = VCC or GND  
ICCS  
VCC Standby  
Current  
1,5  
70  
2
V
CC = VCC Max  
CE0#, CE1#, RP# = VCC  
0.2V  
BYTE#, WP#, 3/5# = VCC  
0.2V or GND ± 0.2V  
±
±
4
mA  
V
CC = VCC Max  
CE0#, CE1#, RP# = VIH  
BYTE#, WP#, 3/5#  
VIL  
V
IH or  
=
ICCD  
VCC Deep Power-  
Down Current  
1
2
5
µA  
RP# = GND ± 0.2V  
BYTE# = VCC ± 0.2V or  
GND ± 0.2V  
1
ICCR  
VCC Read Current  
1,4,5  
120  
175  
mA  
VCC = VCC Max  
CMOS: CE0# ,CE1# = GND  
± 0.2V, BYTE# = GND ±  
0.2V or VCC ± 0.2V,  
Inputs = GND ± 0.2V or  
VCC ± 0.2V  
4-Location Access  
Sequence: 3-1-1-1  
(clocks)  
f = 33 MHz, IOUT = 0 mA  
2
ICCR  
VCC Read Current  
1,4,  
5,6  
105  
150  
mA  
VCC = VCC Max  
CMOS: CE0#, CE1# = GND  
± 0.2V, BYTE# = GND ±  
0.2V, or VCC ± 0.2V,  
Inputs = GND ± 0.2V or  
VCC ± 0.2V  
4-Location Access  
Sequence: 3-1-1-1  
(clocks)  
f = 20 MHz, IOUT = 0 mA  
30  
E
28F016XS FLASH MEMORY  
5.5  
DC Characteristics (Continued)  
VCC = 5.0V ± 5%, TA = 0°C to +70°C  
3/5# = Pin Set Low for 5.0V Operations  
Parameter  
Notes  
Min  
Typ  
Max  
Units  
Test Conditions  
Symbol  
ICCW  
VCC Program  
1,6  
25  
35  
mA  
VPP = 12.0V ± 5%  
Current  
Program in Progress  
VPP = 5.0V ± 10%  
25  
18  
20  
5
40  
25  
mA  
mA  
mA  
mA  
µA  
Program in Progress  
VPP = 12.0V ± 5%  
ICCE  
VCC Erase  
1,6  
Suspend Current  
Block Erase in Progress  
VPP = 5.0V ± 10%  
30  
Block Erase in Progress  
ICCES  
VCC Block Erase  
Current  
1,2  
1
10  
CE0#, CE1# = VIH  
Block Erase Suspended  
IPPS  
IPPR  
IPPD  
VPP Standby/Read  
Current  
± 1  
± 10  
V
V
PP ≤ VCC  
30  
200  
5
µA  
µA  
PP > VCC  
VPP Deep Power-  
Down Current  
1
0.2  
RP# = GND ± 0.2V  
IPPW  
VPP Program  
Current  
1,6  
7
12  
22  
mA  
mA  
mA  
mA  
µA  
VPP  
Program in Progress  
VPP ± 10%  
Program in Progress  
VPP ± 5%  
Block Erase in Progress  
VPP ± 10%  
=
± 5%  
12.0V  
17  
5
=
5.0V  
IPPE  
VPP Block Erase  
Current  
1,6  
10  
=
12.0V  
16  
30  
20  
=
5.0V  
Block Erase in Progress  
VPP = VPPH1 or VPPH2  
IPPES  
VPP Erase  
1
200  
Suspend Current  
Block Erase Suspended  
VIL  
VIH  
Input Low Voltage  
Input High Voltage  
6
6
–0.5  
2.0  
0.8  
V
V
VCC  
+0.5  
0.45  
VOL  
Output Low  
Voltage  
6
6
V
V
V
CC = VCC Min  
OL = 5.8 mA  
VCC = VCC Min  
OH = –2.5 mA  
CC = VCC Min  
OH = –100 µA  
I
VOH  
1
2
Output High  
Voltage  
0.85  
VCC  
I
VOH  
VCC  
V
–0.4  
I
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(until publication date)  
28F016XS FLASH MEMORY  
E
5.5  
DC Characteristics (Continued)  
VCC  
=
± 5%, TA = 0°C to +70°C  
5.0V  
3/5# = Pin Set Low for  
Operations  
5.0V  
Parameter  
Notes  
Min  
Typ  
Max  
Units  
Test Conditions  
Symbol  
VPPLK  
VPP  
3,6  
0.0  
1.5  
V
Program/Erase  
Lock Voltage  
VPPH1  
VPPH2  
VLKO  
VPP during  
4.5  
5.0  
5.5  
V
V
V
Program/Erase  
Operations  
VPP during  
11.4 12.0 12.6  
Program/Erase  
Operations  
VCC  
2.0  
Program/Erase  
Lock Voltage  
NOTES:  
1. All currents are in RMS unless otherwise noted. Typical values at VCC  
=
, V = 12.0V or  
, T = +25°C. These  
5.0V  
5.0V  
PP  
currents are valid for all product versions (package and speeds) and are specified for a CMOS rise/fall time (10% to 90%) of  
<5 ns and a TTL rise/fall time of <10 ns.  
2.  
I
I
CCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of  
CCES and ICCR.  
3. Block erases, programs and lock block operations are inhibited when VPP ≤ VPPLK and not guaranteed in the ranges  
between VPPLK(max) and VPPH1(min), between VPPH1 (max) and VPPH2(min) and above VPPH2(max).  
4. Automatic Power Saving (APS) reduces ICCR to 1 mA typical in static operation.  
5. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH  
.
6. Sampled, but not 100% tested. Guaranteed by design.  
32  
E
28F016XS FLASH MEMORY  
5.6  
Timing Nomenclature  
All 3.3V system timings are measured from where signals cross 1.5V.  
For 5.0V systems, use the standard JEDEC cross point definitions (standard testing) or from where signals  
cross 1.5V (high speed testing).  
Each timing parameter consists of five characters. Some common examples are defined below:  
t
ELCH time(t) from CE# (E) going low (L) to CLK (C) going high (H)  
tAVCH time(t) from address (A) valid (V) to CLK (C) going high (H)  
tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X)  
Pin Characters  
Address Inputs  
Pin States  
A
C
H
L
High  
Low  
CLK (Clock)  
D
Data Inputs  
V
X
Z
L
Valid  
Q
E
Data Outputs  
Driven, but Not Necessarily Valid  
High Impedance  
CE# (Chip Enable)  
BYTE# (Byte Enable)  
OE# (Output Enable)  
WE# (Write Enable)  
RP# (Deep Power-Down Pin)  
RY/BY# (Ready Busy)  
ADV# (Address Valid)  
3/5# Pin  
F
Latched  
G
W
P
R
V
Y
5V  
3V  
VCC at 4.5V Minimum  
VCC at 3.0V Minimum  
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28F016XS FLASH MEMORY  
E
(1)  
5.7  
AC Characteristics—Read Only Operations  
VCC = 3.3V ± 5%, TA = 0°C to +70°C  
Versions(3)  
28F016XS-20  
28F016XS-25  
Symbol  
fCLK  
Parameter  
CLK Frequency  
Notes  
Min  
Max  
Min  
Max  
Units  
MHz  
ns  
50  
40  
tCLK  
CLK Period  
20  
6
25  
8.5  
8.5  
tCH  
CLK High Time  
ns  
tCL  
CLK Low Time  
6
ns  
tCLCH  
tCHCL  
tELCH  
tVLCH  
tAVCH  
tCHAX  
tCHVH  
tGLCH  
tCHQV  
tPHCH  
tCHQX  
tELQX  
tEHQZ  
tGLQX  
tGHQZ  
tOH  
CLK Rise Time  
4
4
4
4
ns  
CLK Fall Time  
ns  
CEX# Setup to CLK  
ADV# Setup to CLK  
Address Valid to CLK  
Address Hold from CLK  
ADV# Hold from CLK  
OE# Setup to CLK  
CLK to Data Delay  
RP# High to CLK  
6
25  
20  
20  
0
35  
25  
25  
0
ns  
ns  
ns  
ns  
0
0
ns  
20  
25  
ns  
30  
35  
ns  
480  
6
480  
6
ns  
Output Hold from CLK  
CEX# to Output Low Z  
CEX# High to Output High Z  
OE# to Output Low Z  
OE# High to Output High Z  
2
2,6  
2,6  
2
ns  
0
0
ns  
30  
30  
30  
30  
ns  
0
0
0
0
ns  
2
ns  
Output Hold from CEX# or OE#  
Change, Whichever Occurs First  
6
ns  
34  
E
28F016XS FLASH MEMORY  
(1)  
5.7  
AC Characteristics—Read Only Operations (Continued)  
VCC = 5.0V ± 5%, TA = 0°C to +70°C  
Versions(3)  
28F016XS-15(4)  
28F016XS-20(5)  
Symbol  
Parameter  
Notes  
Min  
Max  
Min  
Max  
Units  
MHz  
ns  
fCLK  
CLK Frequency  
66  
50  
tCLK  
CLK Period  
15  
3.5  
3.5  
20  
6
tCH  
CLK High Time  
ns  
tCL  
CLK Low Time  
6
ns  
tCLCH  
tCHCL  
tELCH  
tVLCH  
tAVCH  
tCHAX  
tCHVH  
tGLCH  
tCHQV  
tPHCH  
tCHQX  
tELQX  
tEHQZ  
tGLQX  
tGHQZ  
tOH  
CLK Rise Time  
4
4
4
4
ns  
CLK Fall Time  
ns  
CEX# Setup to CLK  
ADV# Setup to CLK  
Address Valid to CLK  
Address Hold from CLK  
ADV# Hold from CLK  
OE# Setup to CLK  
CLK to Data Delay  
RP# High to CLK  
6
25  
15  
15  
0
30  
20  
20  
0
ns  
ns  
ns  
ns  
0
0
ns  
15  
20  
ns  
20  
30  
ns  
300  
5
300  
5
ns  
Output Hold from CLK  
CEX# to Output Low Z  
CEX# High to Output High Z  
OE# to Output Low Z  
OE# High to Output High Z  
2
2,6  
2,6  
2
ns  
0
0
ns  
30  
30  
30  
30  
ns  
0
0
0
0
ns  
2
ns  
Output Hold from CEX# or OE#  
Change, Whichever Occurs First  
6
ns  
NOTES:  
1. See AC Input/Output Reference Waveforms for timing measurements.  
2. Sampled, not 100% tested. Guaranteed by design.  
3. Device speeds are defined as:  
15 ns at V = 5.0V equivalent to 20 ns at V = 3.3V  
CC  
CC  
20 ns at V  
= 5.0V equivalent to 25 ns at V = 3.3V  
CC  
CC  
4. See the high speed AC Input/Output Reference Waveforms.  
5. See the standard AC Input/Output Reference Waveforms.  
6. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.  
35  
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INTEL CONFIDENTIAL  
(until publication date)  
28F016XS FLASH MEMORY  
E
t CH  
t CL  
t CHCL  
t CLCH  
t CLK  
0532_09  
Figure 10. CLK Waveform  
CLK  
ADDR  
t
CHAX  
A
1
1 CLK Periods  
t
AVCH  
ADV#  
t
t
EHQZ  
VLCH  
t
CHVH  
CEx#  
t
GHQZ  
t
ELCH  
t
ELQX  
OE#  
t
t
GLCH  
GLQX  
t
OH  
Even  
Odd  
Even  
Odd  
DATA  
t
t
CHQV  
CHQX  
0532_10  
NOTE:  
1. The 28F016XS can sustain an optimized burst access throughout the 28F016XS array assuming alternating bank  
accesses; the length of the burst access is dictated by the control CPU or bus architecture.  
Figure 11. Read Timing Waveform(1)  
(SFI Configuration = 1, Alternate-Bank Accesses)  
36  
E
28F016XS FLASH MEMORY  
CLK  
ADDR  
t
CHAX  
A
1
2 CLK Periods  
t
AVCH  
ADV#  
CEx#  
t
t
EHQZ  
VLCH  
t
CHVH  
t
GHQZ  
t
ELCH  
t
ELQX  
OE#  
t
t
GLCH  
GLQX  
t
OH  
Even  
Odd  
Even  
Odd  
DATA  
t
t
CHQV  
CHQX  
0532_11  
NOTE:  
1. The 28F016XS can sustain an optimized burst access throughout the 28F016XS array assuming alternating bank  
accesses; the length of the burst access is dictated by the control CPU or bus architecture.  
Figure 12. Read Timing Waveform(1)  
(SFI Configuration = 2, Alternate-Bank Accesses)  
37  
4/15/97 9:41 AM 9053204.DOC  
INTEL CONFIDENTIAL  
(until publication date)  
28F016XS FLASH MEMORY  
E
CLK  
ADDR  
t
CHAX  
A
1
3 CLK Periods  
t
AVCH  
ADV#  
t
EHQZ  
t
VLCH  
t
CHVH  
CEx#  
t
GHQZ  
t
ELCH  
t
ELQX  
OE#  
t
t
GLCH  
t
OH  
Note 2  
Note 2  
Even  
GLQX  
Odd  
Even  
Odd  
DATA  
t
t
CHQV  
CHQX  
0532_12  
NOTES:  
1. The 28F016XS can sustain an optimized burst access throughout the 28F016XS array assuming alternating bank  
accesses; the length of the burst access is dictated by the control CPU or bus architecture.  
2. Depending on the actual operation frequency, a consecutive alternating bank access can be initiated one clock period  
earlier. See AP-398 Designing with the 28F016XS for further information.  
Figure 13. Read Timing Waveform(1)  
(SFI Configuration = 3, Alternate-Bank Accesses)  
38  
E
28F016XS FLASH MEMORY  
CLK  
ADDR  
t
CHAX  
A
1
4 CLK Periods  
t
AVCH  
ADV#  
t
EHQZ  
t
VLCH  
t
CHVH  
CEx#  
t
GHQZ  
t
ELCH  
t
ELQX  
OE#  
t
GLCH  
Even  
t
OH  
Odd  
Even  
Odd  
t
GLQX  
DATA  
t
t
t
CHQV  
PHCH  
CHQX  
RP#  
0532_13  
NOTE:  
1. The 28F016XS can sustain an optimized burst access throughout the 28F016XS array assuming alternating bank  
accesses; the length of the burst access is dictated by the control CPU or bus architecture.  
Figure 14. Read Timing Waveform(1)  
(SFI Configuration = 4, Alternating Bank Accesses)  
39  
4/15/97 9:41 AM 9053204.DOC  
INTEL CONFIDENTIAL  
(until publication date)  
28F016XS FLASH MEMORY  
E
(1)  
5.8  
AC Characteristics for WE#—Controlled Write Operations  
VCC = 3.3V ± 5%, TA = 0°C to +70°C  
Versions  
28F016XS-20  
28F016XS-25  
Symbol  
tAVAV  
Parameter  
Notes  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
Write Cycle Time  
75  
75  
ns  
tVPWH1,2  
VPP Setup to WE# Going  
High  
3
100  
100  
ns  
tPHEL  
tELWL  
tAVWH  
tDVWH  
RP# Setup to CEX# Going  
Low  
3,7  
3,7  
2,6  
2,6  
480  
0
480  
0
ns  
ns  
ns  
ns  
CEX# Setup to WE# Going  
Low  
Address Setup to WE#  
Going High  
60  
60  
60  
60  
Data Setup to WE# Going  
High  
tWLWH  
tWHDX  
tWHAX  
WE# Pulse Width  
60  
5
60  
5
ns  
ns  
ns  
Data Hold from WE# High  
2
2
Address Hold from WE#  
High  
5
5
tWHEH  
tWHWL  
tGHWL  
CEX# hold from WE# High  
WE# Pulse Width High  
3,7  
5
15  
0
5
15  
0
ns  
ns  
ns  
Read Recovery before  
Write  
3
3
3
tWHRL  
tRHPL  
WE# High to RY/BY#  
Going Low  
100  
100  
ns  
ns  
RP# Hold from Valid  
Status Register (CSR,  
GSR, BSR) data and  
RY/BY# High  
0
0
tPHWL  
RP# High Recovery to  
WE# Going Low  
3
3
480  
20  
0
480  
20  
0
ns  
ns  
µs  
tWHCH  
Write Recovery before  
Read  
tQVVL1,2  
VPP Hold from Valid Status  
Register (CSR, GSR, BSR)  
Data and RY/BY# High  
tWHQV  
1
2
Duration of Program  
Operation  
3,4,  
5,8  
5
9
TBD  
20  
5
9
TBD  
20  
µs  
tWHQV  
Duration of Block Erase  
Operation  
3,4  
0.6  
1.6  
0.6  
1.6  
sec  
40  
E
28F016XS FLASH MEMORY  
(1)  
5.8  
AC Characteristics for WE#—Controlled Write Operations (Continued)  
VCC = 5.0V ± 5%, TA = 0°C to +70°C  
Versions  
28F016XS-15  
28F016XS-20  
Symbol  
Parameter  
Notes  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
ns  
tAVAV  
Write Cycle Time  
65  
65  
tVPWH1,2  
VPP Setup to WE# Going  
High  
3
100  
100  
ns  
tPHEL  
tELWL  
tAVWH  
tDVWH  
RP# Setup to CEX# Going  
Low  
3,7  
3,7  
2,6  
2,6  
300  
0
300  
0
ns  
ns  
ns  
ns  
CEX# Setup to WE# Going  
Low  
Address Setup to WE#  
Going High  
50  
50  
50  
50  
Data Setup to WE# Going  
High  
tWLWH  
tWHDX  
tWHAX  
WE# Pulse Width  
50  
0
50  
0
ns  
ns  
ns  
Data Hold from WE# High  
2
2
Address Hold from WE#  
High  
5
5
tWHEH  
tWHWL  
tGHWL  
CEX# hold from WE# High  
WE# Pulse Width High  
3,7  
5
15  
0
5
15  
0
ns  
ns  
ns  
Read Recovery before  
Write  
3
3
3
tWHRL  
tRHPL  
WE# High to RY/BY#  
Going Low  
100  
100  
ns  
ns  
RP# Hold from Valid  
Status Register (CSR,  
GSR, BSR) data and  
RY/BY# High  
0
0
tPHWL  
RP# High Recovery to  
WE# Going Low  
3
3
300  
20  
0
300  
20  
0
ns  
ns  
µs  
tWHCH  
Write Recovery before  
Read  
tQVVL1,2  
VPP Hold from Valid Status  
Register (CSR, GSR, BSR)  
Data and RY/BY# High  
tWHQV  
1
2
Duration of Program  
Operation  
3,4,  
5,8  
4.5  
0.6  
6
TBD  
20  
4.5  
0.6  
6
TBD  
20  
µs  
tWHQV  
Duration of Block Erase  
Operation  
3,4  
1.2  
1.2  
sec  
41  
4/15/97 9:41 AM 9053204.DOC  
INTEL CONFIDENTIAL  
(until publication date)  
28F016XS FLASH MEMORY  
E
NOTES:  
1. Read timings during program and erase are the same as for normal read.  
2. Refer to command definition tables for valid address and data values.  
3. Sampled, but not 100% tested. Guaranteed by design.  
4. Program/erase durations are measured to valid Status Register (CSR) Data.  
5. Program operations are typically performed with 1 Programming Pulse.  
6. Address and Data are latched on the rising edge of WE# for all command program operations.  
7. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.  
8. Please contact Intel’s Application Hotline or your local sales office for current TBD information.  
42  
E
28F016XS FLASH MEMORY  
CLK  
NOTE 6  
WRITE VALID ADDRESS  
& DATA (DATA-WRITE) OR  
ERASE CONFIRM COMMAND  
WRITE READ EXTENDED  
REGISTER COMMAND  
READ EXTENDED  
STATUS REGISTER DATA  
DEEP  
POWER-DOWN  
WRITE DATA-WRITE OR  
ERASE SETUP COMMAND  
AUTOMATED DATA-WRITE  
OR ERASE DELAY  
V
IH  
ADDRESSES (A)  
V
A
A=RA  
IN  
NOTE 1  
IL  
t
t
t
READ COMPATIBLE  
STATUS REGISTER DATA  
AVAV  
WHAX  
WHAX  
t
AVWH  
V
NOTE 3  
IH  
ADDRESSES (A)  
A
IN  
V
NOTE 2  
IL  
t
t
AVAV  
AVWH  
ADV#  
NOTE 6  
V
V
IH  
IL  
CEx # (E)  
NOTE 4  
t
t
ELWL  
WHEH  
t
WHCH  
V
V
IH  
IL  
OE# (G)  
t
t
t
WHWL  
WHQV1,2  
GHWL  
V
V
IH  
IL  
WE# (W)  
t
t
WLWH  
DVWH  
t
WHDX  
V
V
IH  
IL  
HIGH Z  
t
DATA (D/Q)  
D
D
D
D
D
IN  
IN  
IN  
IN  
OUT  
PHWL  
t
WHRL  
V
OH  
OL  
RY/BY# (R)  
V
t
RHPL  
V
IH  
IL  
NOTE 5  
RP# (P)  
V
t
t
QVVL2  
VPWH2  
V
V
PPH2  
PPH1  
V
(V)  
PP  
NOTE 7  
t
V
V
VPWH1  
t
PPLK  
IL  
QVVL1  
NOTE 8  
0532_14  
NOTES:  
1. This address string depicts data program/erase cycles with corresponding verification via ESRD.  
2. This address string depicts data program/erase cycles with corresponding verification via CSRD.  
3. This cycle is invalid when using CSRD for verification during data program/erase operations.  
4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.  
5. RP# low transition is only to show tRHPL; not valid for above read and program cycles.  
6. Data program/erase cycles are asynchronous; CLK and ADV# are ignored.  
7. VPP voltage during data program/erase operations valid at both 12.0V and  
.
5.0V  
8. VPP voltage equal to or below VPPLK provides complete flash memory array protection.  
Figure 15. AC Waveforms for WE#—Command Write Operations,  
Illustrating a Two Command Write Sequence Followed by an Extended Status Register Read  
43  
4/15/97 9:41 AM 9053204.DOC  
INTEL CONFIDENTIAL  
(until publication date)  
28F016XS FLASH MEMORY  
E
(1)  
5.9  
AC Characteristics for CE #—Controlled Write Operations  
X
VCC = 3.3V ± 5%, TA = 0°C to +70°C  
Versions  
28F016XS-20  
28F016XS-25  
Symbol  
Parameter  
Notes  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
tAVAV  
Write Cycle Time  
80  
75  
ns  
tVPEH1,2 VPP Setup to CEX# Going  
High  
3,7  
3
100  
100  
ns  
tPHWL  
tWLEL  
tAVEH  
tDVEH  
RP# Setup to WE# Going  
Low  
480  
0
480  
0
ns  
ns  
ns  
ns  
WE# Setup to CEX# Going  
Low  
3,7  
Address Setup to CEX#  
Going High  
2,6,7  
2,6,7  
60  
60  
60  
60  
Data Setup to CEX# Going  
High  
tELEH  
tEHDX  
tEHAX  
CEX# Pulse Width  
7
65  
10  
10  
60  
10  
10  
ns  
ns  
ns  
Data Hold from CEX# High  
2,7  
2,7  
Address Hold from CEX#  
High  
tEHWH  
tEHEL  
tGHEL  
WE hold from CEX# High  
CEX# Pulse Width High  
3,7  
7
5
15  
0
5
15  
0
ns  
ns  
ns  
Read Recovery before  
Write  
3
tEHRL  
tRHPL  
CEX# High to RY/BY#  
Going Low  
3,7  
3
100  
100  
ns  
ns  
RP# Hold from Valid Status  
Register (CSR, GSR, BSR)  
Data and RY/BY# High  
0
0
tPHEL  
RP# High Recovery to  
CEX# Going Low  
3,7  
3
480  
20  
0
480  
20  
0
ns  
ns  
µs  
tEHCH  
Write Recovery before  
Read  
tQVVL1,2  
VPP Hold from Valid Status  
Register (CSR, GSR, BSR)  
Data and RY/BY# High  
tEHQV  
1
2
Duration of Program  
Operation  
3,4,5,8  
3,4  
5
9
TBD  
20  
5
9
TBD  
20  
µs  
tEHQV  
Duration of Block Erase  
Operation  
0.6  
1.6  
0.6  
1.6  
sec  
44  
E
28F016XS FLASH MEMORY  
(1)  
5.9  
AC Characteristics for CE #—Controlled Write Operations (Continued)  
X
VCC = 5.0V ± 5%, TA = 0°C to +70°C  
Versions  
28F016XS-15  
28F016XS-20  
Symbol  
Parameter  
Notes  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
ns  
tAVAV  
Write Cycle Time  
60  
60  
tVPEH1,2 VPP Setup to CEX# Going  
High  
3,7  
3
100  
100  
ns  
tPHWL  
tWLEL  
tAVEH  
tDVEH  
RP# Setup to WE# Going  
Low  
300  
0
300  
0
ns  
ns  
ns  
ns  
WE# Setup to CEX# Going  
Low  
3,7  
Address Setup to CEX#  
Going High  
2,6,7  
2,6,7  
45  
45  
45  
45  
Data Setup to CEX# Going  
High  
tELEH  
tEHDX  
tEHAX  
CEX# Pulse Width  
7
50  
0
50  
0
ns  
ns  
ns  
Data Hold from CEX# High  
2,7  
2,7  
Address Hold from CEX#  
High  
5
5
tEHWH  
tEHEL  
tGHEL  
WE hold from CEX# High  
CEX# Pulse Width High  
3,7  
7
5
15  
0
5
15  
0
ns  
ns  
ns  
Read Recovery before  
Write  
3
tEHRL  
tRHPL  
CEX# High to RY/BY#  
Going Low  
3,7  
3
100  
100  
ns  
ns  
RP# Hold from Valid Status  
Register (CSR, GSR, BSR)  
Data and RY/BY# High  
0
0
tPHEL  
RP# High Recovery to  
CEX# Going Low  
3,7  
3
300  
20  
0
300  
20  
0
ns  
ns  
µs  
tEHCH  
Write Recovery before  
Read  
tQVVL1,2  
VPP Hold from Valid Status  
Register (CSR, GSR, BSR)  
Data and RY/BY# High  
tEHQV  
1
2
Duration of Program  
Operation  
3,4,5,8  
3,4  
4.5  
0.6  
6
TBD  
20  
4.5  
0.6  
6
TBD  
20  
µs  
tEHQV  
Duration of Block Erase  
Operation  
1.2  
1.2  
sec  
45  
4/15/97 9:41 AM 9053204.DOC  
INTEL CONFIDENTIAL  
(until publication date)  
28F016XS FLASH MEMORY  
E
NOTES:  
1. Read timings during write and erase are the same as for normal read.  
2. Refer to command definition tables for valid address and datavalues.  
3. Sampled, but not 100% tested. Guaranteed by design.  
4. Program/erase durations are measured to valid Status Register (CSR) Data.  
5. Program operations are typically performed with 1 Programming Pulse.  
6. Address and Data are latched on the rising edge of WE# for all command write operations.  
7. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.  
8. Please contact Intel’s Application Hotline or your local sales office for current TBD information.  
46  
E
28F016XS FLASH MEMORY  
CLK  
NOTE 6  
WRITE VALID ADDRESS  
& DATA (DATA-WRITE) OR  
ERASE CONFIRM COMMAND  
WRITE READ EXTENDED  
REGISTER COMMAND  
DEEP  
POWER-DOWN  
WRITE DATA-WRITE OR  
ERASE SETUP COMMAND  
AUTOMATED DATA-WRITE  
OR ERASE DELAY  
READ EXTENDED  
STATUS REGISTER DATA  
V
IH  
ADDRESSES (A)  
V
A
A=RA  
IN  
NOTE 1  
IL  
t
t
AVAV  
EHAX  
EHAX  
READ COMPATIBLE  
STATUS REGISTER DATA  
t
AVEH  
V
NOTE 3  
IH  
ADDRESSES (A)  
V
A
IN  
NOTE 2  
IL  
t
t
t
AVAV  
AVEH  
ADV#  
NOTE 6  
V
V
IH  
IL  
WE# (W)  
t
t
WLEL  
EHWH  
t
EHCH  
V
V
IH  
IL  
OE# (G)  
t
t
t
EHEL  
EHQV1,2  
GHEL  
V
V
IH  
IL  
CEx#(E)  
NOTE 4  
t
t
ELEH  
DVEH  
t
EHDX  
V
V
IH  
IL  
HIGH Z  
t
DATA (D/Q)  
D
D
D
D
D
IN  
IN  
IN  
IN  
OUT  
PHEL  
t
EHRL  
V
OH  
OL  
RY/BY# (R)  
V
t
RHPL  
V
IH  
IL  
NOTE 5  
RP# (P)  
V
t
t
QVVL2  
VPEH2  
V
PPH1  
PPH2  
V
V
V
V
(V)  
PP  
t
NOTE 7  
VPEH1  
t
PPLK  
IL  
QVVL1  
NOTE 8  
0532_15  
NOTES:  
1. This address string depicts data program/erase cycles with corresponding verification via ESRD.  
2. This address string depicts data program/erase cycles with corresponding verification via CSRD.  
3. This cycle is invalid when using CSRD for verification during data program/erase operations.  
4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.  
5. RP# low transition is only to show tRHPL; not valid for above read and program cycles.  
6. Data program/erase cycles are asynchronous; CLK and ADV# are ignored.  
7. VPP voltage during data program/erase operations valid at both 12.0V and  
.
5.0V  
8. VPP voltage equal to or below VPPLK provides complete flash memory array protection.  
Figure 16. AC Waveforms for CEX#—Controlled Write Operations,  
Illustrating a Two Command Write Sequence Followed by an Extended Status Register Read  
47  
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(until publication date)  
28F016XS FLASH MEMORY  
E
5.10 Power-Up and Reset Timings  
V
POWER-UP  
CC  
RP#  
(P)  
tYHPH  
tYLPH  
3/5#  
(Y)  
5.0V  
tPLYL  
4.5V  
3.3V  
V
CC  
0V  
(3V,5V)  
tPL5V  
0532_18  
NOTE:  
For read timings following reset see Section 5.7.  
Figure 17. VCC Power-Up and RP# Reset Waveforms  
Symbol  
Parameter  
RP# Low to 3/5# Low (High)  
Notes  
Min  
Max  
Unit  
tPLYL  
tPLYH  
tYLPH  
tYHPH  
tPL5V  
tPL3V  
0
µs  
3/5# Low (High) to RP# High  
0
0
µs  
µs  
RP# Low to VCC at 4.5V (Minimum)  
2
RP# Low to VCC at 3V (Min) or 3.6V (Max)  
NOTES:  
1. The tYLPH and/or tYHPH times must be strictly followed to guarantee all other read and program specifications for the  
28F016XS.  
2. The power supply may start to switch concurrently with RP# going low.  
48  
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28F016XS FLASH MEMORY  
(3,4)  
5.11 Erase and Program Performance  
VCC = 3.3V ± 5%, VPP  
=
± 5%, TA = 0°C to +70°C  
5.0V  
Symbol  
Parameter  
Notes  
2,5  
Min  
Typ(1)  
29  
Max  
TBD  
TBD  
TBD  
Units  
µs  
Test Conditions  
TBD  
TBD  
TBD  
tWHRH1A Byte Program Time  
tWHRH1B Word Program Time  
2,5  
35  
µs  
tWHRH  
2
Block Program Time  
Block Program Time  
Block Erase Time  
2,5  
3.8  
sec  
Byte Program  
Mode  
TBD  
tWHRH  
3
2,5  
2,5  
2.4  
TBD  
sec  
Word Program  
Mode  
TBD  
1.0  
2.8  
12  
TBD  
75  
sec  
µs  
Erase Suspend  
Latency Time to Read  
V
CC = 3.3V ± 5%, VPP = 12.0V ± 0.6V, TA = 0°C to +70°C  
Symbol  
Parameter  
Program Time  
Notes  
Min  
Typ(1)  
Max  
TBD  
4.2  
Units  
Test Conditions  
tWHRH  
1
2
2,5  
5
9
µs  
tWHRH  
Block Program Time  
Block Program Time  
Block Erase Time  
2,5  
2,5  
2
TBD  
1.2  
sec  
Byte Program  
Mode  
tWHRH  
3
TBD  
0.6  
2.0  
sec  
Word Program  
Mode  
0.6  
1.0  
1.6  
9
20  
55  
sec  
µs  
Erase Suspend  
Latency Time to Read  
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(until publication date)  
28F016XS FLASH MEMORY  
E
(3,4)  
5.11 Erase and Program Performance  
(Continued)  
VCC  
=
± 5%, V  
=
± 5%, TA = 0°C to +70°C  
5.0V  
5.0V  
PP  
Symbol  
Parameter  
Notes  
2,5  
Min  
Typ(1)  
20  
Max  
Units  
µs  
Test Conditions  
tWHRH1A Byte Program Time  
tWHRH1B Word Program Time  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
2,5  
25  
µs  
tWHRH  
2
Block Program Time  
Block Program Time  
Block Erase Time  
2,5  
2.8  
sec  
Byte Program  
Mode  
tWHRH  
3
2,5  
2,5  
TBD  
1.7  
sec  
Word Program  
Mode  
TBD  
TBD  
1.0  
2.0  
9
sec  
µs  
TBD  
55  
Erase Suspend  
Latency Time to Read  
VCC  
=
± 5%, VPP = 12.0V ± 0.6V, TA = 0°C to +70°C  
5.0V  
Symbol  
Parameter  
Program Time  
Notes  
Min  
Typ(1)  
Max  
TBD  
4.2  
Units  
Test Conditions  
tWHRH  
1
2
2,5  
4.5  
6
µs  
tWHRH  
Block Program Time  
Block Program Time  
Block Erase Time  
2,5  
2,5  
2
TBD  
0.8  
sec  
Byte Program  
Mode  
tWHRH  
3
TBD  
0.4  
2.0  
sec  
Word Program  
Mode  
0.6  
1.0  
1.2  
7
20  
40  
sec  
µs  
Erase Suspend  
Latency Time to Read  
NOTES:  
1. +25°C, and nominal voltages.  
2. Excludes system-level overhead.  
3. These performance numbers are valid for all speed versions.  
4. Sampled, but not 100% tested. Guaranteed by design.  
5. Please contact Intel’s Application Hotline or your local sales office for current TBD information.  
50  
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28F016XS FLASH MEMORY  
6.0 MECHANICAL SPECIFICATIONS  
048928.eps  
Figure 18. Mechanical Specifications of the 28F016XS 56-Lead TSOP Type I Package  
Family: Thin Small Out-Line Package  
Symbol  
Millimeters  
Nominal  
Notes  
Minimum  
Maximum  
A
1.20  
A
A
0.050  
0.965  
0.100  
0.115  
18.20  
13.80  
1
2
0.995  
0.150  
0.125  
18.40  
14.00  
0.50  
1.025  
0.200  
0.135  
18.60  
14.20  
b
c
D
1
E
e
D
L
19.80  
0.500  
20.00  
0.600  
56  
20.20  
0.700  
N
0°  
3°  
5°  
Y
Z
0.100  
0.350  
0.150  
0.250  
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INTEL CONFIDENTIAL  
(until publication date)  
28F016XS FLASH MEMORY  
E
a
He  
E
R1  
A2  
b
R2  
L
1
Detail A  
D
A
e
B
Y
C
A1  
1
See Detail A  
0528_20  
Figure 19. Mechanical Specifications of the 28F016SV 56-Lead SSOP Type I Package  
Family: Shrink Small Out-Line Package  
Symbol  
Millimeters  
Nominal  
1.80  
Notes  
Minimum  
Maximum  
1.90  
A
A1  
A2  
B
0.47  
1.18  
0.52  
0.57  
1.28  
1.38  
0.25  
0.30  
0.40  
C
0.13  
0.15  
0.20  
D
23.40  
13.10  
23.70  
13.30  
0.80  
24.00  
13.50  
E
e1  
He  
N
15.70  
0.45  
16.00  
56  
16.30  
L1  
Y
0.50  
0.55  
0.10  
4°  
a
2°  
3°  
3°  
4°  
b
5°  
R1  
R2  
0.15  
0.15  
0.20  
0.20  
0.25  
0.25  
52  
E
28F016XS FLASH MEMORY  
APPENDIX A  
DEVICE NOMENCLATURE AND ORDERING  
INFORMATION  
Product line designator for all Intel Flash products  
-
5
DA28F01 6XS 1  
Package  
DA = SSOP  
Period of Maximum CLK  
Input Frequency (ns)  
E = TSOP  
Device Density  
016 = 16 Mbit  
Device Type  
S = Synchronous Pipelined  
Interface  
Product Family  
X = Fast Flash  
0532_20  
Valid Combinations  
Option  
Order Code  
VCC = 3.3V ± 5%,  
VCC = 5.0V ± 5%,  
100 pF load  
VCC = 5.0V ± 5%,  
50 pF load,  
30 pF load  
1.5V I/O Levels(1)  
TTL I/O Levels(1)  
1.5V I/O Levels(1)  
1
2
3
E28F016XS15  
E28F016XS20  
DA28F016XS15  
DA28F016XS20  
28F016XS-20  
28F016XS-25  
28F016XS-20  
28F016XS-25  
28F016XS-15  
28F016XS-20  
28F016XS-20  
28F016XS-15  
4
NOTE:  
1. See Section 5.3 for Transient Input/Output Reference Waveforms.  
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(until publication date)  
28F016XS FLASH MEMORY  
E
APPENDIX B  
ADDITIONAL INFORMATION  
(1,2)  
Order Number  
297372  
Document/Tool  
16-Mbit Flash Product Family User’s Manual  
AP-398 Designing with the 28F016XS  
292147  
292146  
AP-600 Performance Benefits and Power/Energy Savings of 28F016XS-  
Based System Designs  
292163  
292165  
297500  
297504  
294016  
AP-610 Flash Memory In-System Code and Data Update Techniques  
AB-62 Compiled Code Optimizations for Flash Memories  
Interfacing the 28F016XS to the i960 Microprocessor Family  
Interfacing the 28F016XS to the Intel486™ Microprocessor Family  
ER-33 ETOX™ Flash Memory Technology—Insight to Intel’s Fourth  
Generation Process Innovation  
297508  
FLASHBuilder Utility  
Contact Intel/Distribution  
Sales Office  
28F016XS Benchmark Utility  
Contact Intel/Distribution  
Sales Office  
Flash Cycling Utility  
Contact Intel/Distribution  
Sales Office  
28F016XS iBIS Model  
Contact Intel/Distribution  
Sales Office  
28F016XS VHDL Model  
Contact Intel/Distribution  
Sales Office  
28F016XS TimingDesigner* Library Files  
28F016XS Orcad/Viewlogic Schematic Symbols  
Contact Intel/Distribution  
Sales Office  
NOTE:  
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should  
contact their local Intel or distribution sales office.  
2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.  
54  

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