DA28F320J5-120_技术文档

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY

32 AND 64 MBIT

28F320J5 and 28F640J5

High-Density Symmetrically-Blocked

Architecture

64 128-Kbyte Erase Blocks (64 M)

Cross-Compatible Command Support

Intel Basic Command Set

Common Flash Interface

32 128-Kbyte Erase Blocks (32 M)

Scaleable Command Set

5 V V_CCOperation

2.7 V I/O Capable

32-Byte Write Buffer

6 µs per Byte Effective

Programming Time

Configurable x8 or x16 I/O

640,000 Total Erase Cycles (64 M)

320,000 Total Erase Cycles (32 M)

10,000 Erase Cycles per Block

120 ns Read Access Time (32 M)

150 ns Read Access Time (64 M)

Enhanced Data Protection Features

Absolute Protection with

V_PEN= GND

Automation Suspend Options

Block Erase Suspend to Read

Block Erase Suspend to Program

Flexible Block Locking

Block Erase/Program Lockout

during Power Transitions

System Performance Enhancements

STS Status Output

Industry-Standard Packaging

µBGA* Package, SSOP and TSOP

Packages (32 M)

Intel StrataFlash™ Memory Flash

Technology

Capitalizing on two-bit-per-cell technology, Intel StrataFlash™ memory products provide 2X the bits in 1X the

space. Offered in 64-Mbit (8-Mbyte) and 32-Mbit (4-Mbyte) densities, Intel StrataFlash memory devices are

the first to bring reliable, two-bit-per-cell storage technology to the flash market.

Intel StrataFlash memory benefits include: more density in less space, lowest cost-per-bit NOR devices,

support for code and data storage, and easy migration to future devices.

Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash

memory devices take advantage of 400 million units of manufacturing experience since 1988. As a result,

Intel StrataFlash components are ideal for code or data applications where high density and low cost are

required. Examples include networking, telecommunications, audio recording, and digital imaging.

By applying FlashFile™ memory family pinouts, Intel StrataFlash memory components allow easy design

migrations from existing 28F016SA/SV, 28F032SA, and Word-Wide FlashFile memory devices (28F160S5

and 28F320S5).

Intel StrataFlash memory components deliver a new generation of forward-compatible software support. By

using the Common Flash Interface (CFI) and the Scaleable Command Set (SCS), customers can take

advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices.

Manufactured on Intel’s 0.4 micron ETOX™ V process technology, Intel StrataFlash memory provides the

highest levels of quality and reliability.

January 1998

Order Number: 290606-004

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of

Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to

sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or

infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life

saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

The 28F320J5 and 28F640J4 may contain design defects or errors known as errata. Current characterized errata are available

on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation

P.O. Box 5937

Denver, CO 80217-9808

or call 1-800-548-4725

or visit Intel’s website at http://www.intel.com

CG-041493

*Third-party brands and names are the property of their respective owners.

2

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

CONTENTS

PAGE

1.0 PRODUCT OVERVIEW...................................5

5.0 DESIGN CONSIDERATIONS........................40

5.1 Three-Line Output Control..........................40

2.0 PRINCIPLES OF OPERATION .....................11

5.2 STS and Block Erase, Program, and Lock-

Bit Configuration Polling ............................40

2.1 Data Protection ..........................................12

5.3 Power Supply Decoupling ..........................40

5.4 V_CC, V_PEN, RP# Transitions........................40

5.5 Power-Up/Down Protection ........................41

5.6 Power Dissipation.......................................41

3.0 BUS OPERATION.........................................12

3.1 Read ..........................................................13

3.2 Output Disable ...........................................13

3.3 Standby......................................................13

3.4 Reset/Power-Down ....................................13

3.5 Read Query................................................14

3.6 Read Identifier Codes.................................14

3.7 Write ..........................................................14

6.0 ELECTRICAL SPECIFICATIONS..................42

6.1 Absolute Maximum Ratings........................42

6.2 Operating Conditions..................................42

6.3 Capacitance ...............................................42

6.4 DC Characteristics .....................................43

4.0 COMMAND DEFINITIONS ............................14

4.1 Read Array Command................................18

4.2 Read Query Mode Command.....................18

4.2.1 Query Structure Output .......................18

4.2.2 Query Structure Overview ...................20

4.2.3 Block Status Register ..........................21

4.2.4 CFI Query Identification String.............22

4.2.5 System Interface Information...............23

4.2.6 Device Geometry Definition.................24

6.5 AC Characteristics— Read-Only

Operations.................................................45

6.6 AC Characteristics— Write Operations.......48

6.7 Block Erase, Program, and Lock-Bit

Configuration Performance........................51

7.0 ORDERING INFORMATION.........................52

8.0 ADDITIONAL INFORMATION......................53

4.2.7 Primary-Vendor Specific Extended

Query Table .......................................25

4.3 Read Identifier Codes Command ...............26

4.4 Read Status Register Command................27

4.5 Clear Status Register Command................27

4.6 Block Erase Command ..............................27

4.7 Block Erase Suspend Command................27

4.8 Write to Buffer Command...........................28

4.9 Byte/Word Program Commands.................28

4.10 Configuration Command...........................29

4.11 Set Block and Master Lock-Bit

Commands................................................29

4.12 Clear Block Lock-Bits Command..............30

3

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

FIGURES

TABLES

Figure 1. Intel StrataFlash™ Memory Block

Table 1. Lead Descriptions.................................7

Table 2. Chip Enable Truth Table.....................13

Table 3. Bus Operations...................................15

Diagram..............................................6

Figure 2. µBGA* Package (64-Mbit and 32-Mbit)9

Figure 3. TSOP Lead Configuration (32-Mbit)..10

Table 4. Intel StrataFlash™ Memory Command

Set Definitions ...................................16

Figure 4. SSOP Lead Configuration (64-Mbit

and 32-Mbit) .....................................11

Table 5. Summary of Query Structure Output as

a Function of Device and Mode .........19

Figure 5. Memory Map.....................................12

Figure 6. Device Identifier Code Memory Map .14

Figure 7. Write to Buffer Flowchart...................34

Figure 8. Byte/Word Program Flowchart ..........35

Figure 9. Block Erase Flowchart ......................36

Table 6. Example of Query Structure Output of

a x16- and x8-Capable Device...........19

Table 7. Query Structure..................................20

Table 8. Block Status Register .........................21

Table 9. CFI Identification ................................22

Table 10. System Interface Information............23

Table 11. Device Geometry Definition..............24

Figure 10. Block Erase Suspend/Resume

Flowchart..........................................37

Figure 11. Set Block Lock-Bit Flowchart...........38

Figure 12. Clear Block Lock-Bit Flowchart........39

Table 12. Primary Vendor-Specific Extended

Query.................................................25

Figure 13. Transient Input/Output Reference

Waveform for V_CCQ= 5.0 V ± 10%

Table 13. Identifier Codes ................................26

Table 14. Write Protection Alternatives ............30

Table 15. Configuration Coding Definitions.......31

Table 16. Status Register Definitions ...............32

Table 17. eXtended Status Register Definitions33

(Standard Testing Configuration)......45

Figure 14. Transient Input/Output Reference

Waveform for V_CCQ= 2.7 V−3.6V.....45

Figure 15. Transient Equivalent Testing Load

Circuit...............................................45

Figure 16. AC Waveform for Read Operations.47

Figure 17. AC Waveform for Write Operations .49

Figure 18. AC Waveform for Reset Operation..50

REVISION HISTORY

Date of

Revision

Version

Description

09/01/97

09/17/97

12/01/97

-001

-002

-003

Original Version

Modifications made to cover sheet

V_CC/GND Pins Converted to No Connects specification change added

I

_CCS, I_CCD, I_CCW, and I_CCEspecification change added

Order Codes specification change added

1/31/98

-004

The µBGA* chip-scale package in Figure 2 was changed to a 52-ball

package and appropriate documentation added. The 64-Mb µBGA

package dimensions were changed in Figure 2. Changed Figure 4 to

read SSOP instead of TSOP.

4

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

Individual block locking uses a combination of bits,

1.0 PRODUCT OVERVIEW

block lock-bits and a master lock-bit, to lock and

unlock blocks. Block lock-bits gate block erase

and program operations while the master lock-bit

gates block lock-bit modification. Three lock-bit

configuration operations set and clear lock-bits

(Set Block Lock-Bit, Set Master Lock-Bit, and

Clear Block Lock-Bits commands).

The Intel StrataFlash™ memory family contains

high-density memories organized as 8 Mbytes or

4 Mwords (64-Mbit) and 4 Mbytes or 2 Mwords

(32-Mbit). These devices can be accessed as 8- or

16-bit words. The 64-Mbit device is organized as

sixty-four 128-Kbyte (131,072 bytes) erase blocks

while the 32-Mbits device contains thirty-two 128-

Kbyte erase blocks. Blocks are selectively and

individually lockable and unlockable in-system.

See the memory map in Figure 5.

The status register indicates when the WSM’s

block erase, program, or lock-bit configuration

operation is finished.

The STS (STATUS) output gives an additional

indicator of WSM activity by providing both a

hardware signal of status (versus software polling)

and status masking (interrupt masking for

background block erase, for example). Status

indication using STS minimizes both CPU

overhead and system power consumption. When

configured in level mode (default mode), it acts as

a RY/BY# pin. When low, STS indicates that the

WSM is performing a block erase, program, or

lock-bit configuration. STS-high indicates that the

WSM is ready for a new command, block erase is

suspended (and programming is inactive), or the

device is in reset/power-down mode. Additionally,

the configuration command allows the STS pin to

be configured to pulse on completion of

programming and/or block erases.

A Common Flash Interface (CFI) permits software

algorithms to be used for entire families of

devices. This allows device-independent, JEDEC

ID-independent, and forward- and backward-

compatible software support for the specified flash

device families. Flash vendors can standardize

their existing interfaces for long-term compatibility.

Scaleable Command Set (SCS) allows a single,

simple software driver in all host systems to work

with all SCS-compliant flash memory devices,

independent of system-level packaging (e.g.,

memory card, SIMM, or direct-to-board place-

ment). Additionally, SCS provides the highest

system/device data transfer rates and minimizes

device and system-level implementation costs.

A Command User Interface (CUI) serves as the

interface between the system processor and

internal operation of the device. A valid command

sequence written to the CUI initiates device

automation. An internal Write State Machine

(WSM) automatically executes the algorithms and

timings necessary for block erase, program, and

lock-bit configuration operations.

Three CE pins are used to enable and disable the

device. A unique CE logic design (see Table 2,

Chip Enable Truth Table) reduces decoder logic

typically required for multi-chip designs. External

logic is not required when designing a single chip,

a dual chip, or a 4-chip miniature card or SIMM

module.

The BYTE# pin allows either x8 or x16 read/writes

to the device. BYTE# at logic low selects 8-bit

mode; address A₀selects between the low byte

and high byte. BYTE# at logic high enables 16-bit

operation; address A₁becomes the lowest order

address and address A₀is not used (don’t care). A

device block diagram is shown in Figure 1.

A block erase operation erases one of the device’s

128-Kbyte blocks typically within one second—

independent of other blocks. Each block can be

independently erased 10,000 times. Block erase

suspend mode allows system software to suspend

block erase to read or program data from any

other block.

When the device is disabled (see Table 2, Chip

Enable Truth Table) and the RP# pin is at V_CC, the

standby mode is enabled. When the RP# pin is at

GND, a further power-down mode is enabled

which minimizes power consumption and provides

Each device incorporates

a Write Buffer of

32 bytes (16 words) to allow optimum

programming performance. By using the Write

Buffer, data is programmed in buffer increments.

This feature can improve system program

performance by up to 20 times over non Write

Buffer writes.

write protection during reset. A reset time (t_PHQV

)

is required from RP# switching high until outputs

5

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

are valid. Likewise, the device has a wake time

(t_PHWL) from RP#-high until writes to the CUI are

recognized. With RP# at GND, the WSM is reset

and the status register is cleared.

available in 56-lead SSOP (Shrink Small Outline

Package) and µBGA* package (micro Ball Grid

Array). The 32-Mbit is available in 56-lead TSOP

(Thin Small Outline Package), 56-lead SSOP, and

56-bump µBGA packages. Figures 2, 3, and 4

show the pinouts.

The Intel StrataFlash memory devices are

available in several package types. The 64-Mbit is

DQ₀- DQ₁₅

V_CCQ

Output Buffer

Input Buffer

V_CC

Query

I/O Logic

BYTE#

CE₀

CE₁

CE₂

WE#

OE#

RP#

Identifier

Register

CE

Logic

Command

User

Interface

Status

Register

Multiplexer

Data

Comparator

Y-Decoder

X-Decoder

Y-Gating

STS

32-Mbit: A - A₂₁

64-Mbit: A₀⁰_-A₂₂

Input Buffer

Write State

Machine

V_PEN

Program/Erase

Voltage Switch

32-Mbit: Thirty-two

64-Mbit: Sixty-four

128-Kbyte Blocks

Address

Latch

V_CC

GND

Address

Counter

0606_01

Figure 1. Intel StrataFlash™ Memory Block Diagram

6

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

Table 1. Lead Descriptions

Name and Function

Symbol

Type

A₀

INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when the device

is in x8 mode. This address is latched during a x8 program cycle. Not used in

x16 mode (i.e., the A₀input buffer is turned off when BYTE# is high).

A₁–A₂₂

INPUT ADDRESS INPUTS: Inputs for addresses during read and program operations.

Addresses are internally latched during a program cycle.

32-Mbit: A₀–A₂₁

64-Mbit: A₀–A₂₂

DQ₀–DQ₇

INPUT/ LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and

OUTPUT inputs commands during Command User Interface (CUI) writes. Outputs array,

query, identifier, or status data in the appropriate read mode. Floated when the

chip is de-selected or the outputs are disabled. Outputs DQ₆–DQ₀are also

floated when the Write State Machine (WSM) is busy. Check SR.7 (Status

Register bit 7) to determine WSM status.

DQ₈–DQ₁₅

INPUT/ HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming

OUTPUT operations. Outputs array, query, or identifier data in the appropriate read mode;

not used for Status Register reads. Floated when the chip is de-selected, the

outputs are disabled, or the WSM is busy.

CE₀,

CE₁,

CE₂

INPUT CHIP ENABLES: Activates the device’s control logic, input buffers, decoders,

and sense amplifiers. When the device is de-selected (see Table 2, Chip Enable

Truth Table), power reduces to standby levels.

All timing specifications are the same for these three signals. Device selection

occurs with the first edge of CE₀, CE₁, or CE₂that enables the device. Device

deselection occurs with the first edge of CE₀, CE₁, or CE₂that disables the

device (see Table 2, Chip Enable Truth Table).

RP#

INPUT RESET/ POWER-DOWN: Resets internal automation and puts the device in

power-down mode. RP#-high enables normal operation. Exit from reset sets the

device to read array mode. When driven low, RP# inhibits write operations which

provides data protection during power transitions.

RP# at V_HHenables master lock-bit setting and block lock-bits configuration

when the master lock-bit is set. RP# = V_HHoverrides block lock-bits thereby

enabling block erase and programming operations to locked memory blocks. Do

not permanently connect RP# to V_HH

.

OE#

WE#

INPUT OUTPUT ENABLE: Activates the device’s outputs through the data buffers

during a read cycle. OE# is active low.

INPUT WRITE ENABLE: Controls writes to the Command User Interface, the Write

Buffer, and array blocks. WE# is active low. Addresses and data are latched on

the rising edge of the WE# pulse.

STS

OPEN

STATUS: Indicates the status of the internal state machine. When configured in

DRAIN level mode (default mode), it acts as a RY/BY# pin. When configured in one of

OUTPUT its pulse modes, it can pulse to indicate program and/or erase completion. For

alternate configurations of the STATUS pin, see the Configurations command.

Tie STS to V_CCQwith a pull-up resistor.

7

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

Table 1. Lead Descriptions (Continued)

Symbol

BYTE#

Type

Name and Function

INPUT BYTE ENABLE: BYTE# low places the device in x8 mode. All data is then input

or output on DQ₀–DQ₇, while DQ₈–DQ₁₅float. Address A₀selects between the

high and low byte. BYTE# high places the device in x16 mode, and turns off the

A₀input buffer. Address A₁then becomes the lowest order address.

V_PEN

INPUT ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks,

programming data, or configuring lock-bits.

With V_PEN≤ V_PENLK, memory contents cannot be altered.

V_CC

SUPPLY DEVICE POWER SUPPLY: With V_CC≤ V_LKO, all write attempts to the flash

memory are inhibited.

V_CCQ

OUTPUT OUTPUT BUFFER POWER SUPPLY: This voltage controls the device’s output

BUFFER voltages. To obtain output voltages compatible with system data bus voltages,

SUPPLY connect V_CCQto the system supply voltage.

GND

NC

SUPPLY GROUND: Do not float any ground pins.

NO CONNECT: Lead is not internally connected; it may be driven or floated.

8

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

8

7

6

5

4

3

1

2

3

4

5

6

2

1

7

8

A

GND

A₁₀

A₉

A₈

A₃

V_PEN

CE₀

A₁₂

A₁₃

A₁₄

A₁₅

A₁₆

A₁₈

V_CC

A₁₄

A₁₅

A₁₆

A₁₈

CE₀

A₁₂

A₁₃

V_PEN

A₁₀

A₉

GND

A₇

B

C

A₄

A₅

A₂

A₇

A₁₁

A₁₇

A₁₉

A₂₀

A₂₂

A₁₉

A₂₀

A₂₂

A₁₇

A₁₁

A₄

A₅

A₂

C

A₆

RP#

A₂₁

RP# A₈

A₆

D

A₁

CE₁

A₃

A₁

E

F

E

F

CE₂

A₀

BYTE#

DQ₁

DQ₇

DQ₆

WE#

OE#

STS

WE#

OE#

STS

DQ₇

DQ₆

DQ₁₃

DQ₅

BYTE#

DQ₁

CE₂

A₀

G

H

I

G

H

I

DQ₈

DQ₉

DQ₃

DQ₁₁

GND

DQ₁₂

DQ₄

DQ₁₅

DQ₁₄

DQ₁₂

DQ₄

DQ₃

DQ₈

DQ₉

DQ₀

DQ₂

DQ₁₃DQ₁₄

DQ₁₁

DQ₂

DQ₀

V_CC

DQ₁₀

V_CCQ

DQ₅

GND⁽¹⁾

V_CCQ

GND DQ₁₀

V_CC

(1)

Bottom View - Ball Side Up

Top View

64-Mbit Intel StrataFlash™ Memory: 7.67 mm x 16.37 mm^(2,4)

32-Mbit Intel StrataFlash Memory: 7.67 mm x 9.79 mm^(2,3,4)

NOTES:

1. V_CC(Ball I7) and GND (Ball I2) have been removed. Future generations of Intel StrataFlash memory may make use of

these missing ball locations.

2. The tolerances above indicate projected production accuracy. This product is in the design phase. The package body

width and length are subject to change dependent on final die size. Actual die size could shift these values by ± 0.1 mm

for the 64 Mbit and ± 0.2 mm for the 32 Mbit.

3. Address A₂₂is not included in 28F320J5.

4. Figures are not drawn to scale.

Figure 2. µBGA* Package (64 Mbit and 32 Mbit)

9

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

28F016SV

28F016SA

28F160S5

28F032SA 28F320J5

28F320J5 28F032SA

28F160S5

28F016SA

3/5#

CE₁#

NC

3/5#

NC

1

NC

CE₁#

NC

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

1

2

3

4

5

6

7

NC

WP#

WE#

OE#

WP#

WE#

OE#

WP#

WE#

OE#

CE #

CE

1

WE#

OE#

STS

DQ

CE₂#

A₂₁

A₂₀

A₁₉

A₁₈

A₁₇

A₁₆

V_CC

A₁₅

A₁₄

A₁₃

A₁₂

CE₀

RY/BY# STS

A²⁰

A20

A¹⁹

A₁₈

RY/BY#

DQ

A₁₉

DQ₁₅

DQ₇

DQ

DQ₁₅

DQ₇

DQ

DQ¹₇⁵

DQ₁₄

18

DQ¹₇⁵

DQ₁₄

DQ₆

A

A¹⁷

17

16

DQ¹₆⁴

GND

DQ₁₃

DQ₅

DQ₁₂

DQ₄

DQ¹₆⁴

GND

DQ₁₃

DQ₅

A

8

9

DQ

GND

A16

V_CC

A₁₅

6

GND

V_CC

A₁₅

A₁₄

A₁₃

V_CC

A₁₅

A₁₄

A₁₃

10

11

12

13

14

15

16

17

18

19

20

21

22

23

DQ₁₃

DQ₅

DQ₁₂

DQ₄

Intel StrataFlash™ Memory

56-LEAD TSOP

DQ

12

DQ₄

A₁₄

5

A₁₃

DQ₁₂

DQ₄

A₁₂

STANDARD PINOUT

V_CCQ

GND

DQ₁₁

DQ₃

DQ₁₀

DQ₂

V_CC

DQ₉

DQ₁

DQ₈

DQ₀

CE₀#

V_CC

V

RP#

V

RP#

V

RP#

GND

V_PEN

RP#

PP

DQ

DQ₁₁

DQ₃

DQ₁₀

DQ₂

V_CC

A

DQ¹₃¹

DQ

DQ¹₃¹

DQ

14 mm x 20 mm

TOP VIEW

A₁₁

A₁₀

A₉

A₁₁

A₁₀

A₉

A₁₁

A₁₀

A₉

11

A₁₀

A₉

DQ¹₂⁰

V_CC

DQ¹₂⁰

V_CC

A

8

A

8

A₈

DQ ₉

DQ ₁

DQ ₈

DQ ₀

DQ ₉

DQ ₁

DQ ₈

DQ ₀

DQ ₉

DQ ₁

DQ ₈

DQ ₀

GND

A₇

A₆

A₅

A₄

A₇

A₆

A₅

A₄

A₇

A₆

A₅

A₄

A₇

A₆

A₅

A₄

A₃

A₂

A₁

24

25

26

27

28

A₀

A

A₀

0

BYTE#

A

3

A

3

BYTE# BYTE# BYTE#

3

30

29

NC

A

A₂

A₁

2

CE₂

A₁

Highlights pinout changes.

0606_03

NOTE:

V_CC(Pin 37) and GND (Pin 48) are not internally connected. For future device revisions, it is recommended that these pins be

connected to their respected power supplies (i.e., Pin 37 = V_CCand Pin 48 = GND).

Figure 3. TSOP Lead Configuration (32 Mbit)

10

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

0606_04

NOTE:

V_CC(Pin 42) and GND (Pin 15) are not internally connected. For future device revisions, it is recommended that these pins be

connected to their respected power supplies (i.e., Pin 42 = V_CCand Pin 15 = GND).

Figure 4. SSOP Lead Configuration (64 Mbit and 32 Mbit)

After initial device power-up or return from

reset/power-down mode (see Bus Operations), the

2.0 PRINCIPLES OF OPERATION

device defaults to read array mode. Manipulation of

external memory control pins allows array read,

standby, and output disable operations.

The Intel StrataFlash memory devices include an

on-chip WSM to manage block erase, program, and

lock-bit configuration functions. It allows for 100%

TTL-level control inputs, fixed power supplies

Read array, status register, query, and identifier

codes can be accessed through the CUI (Command

User Interface) independent of the V_PENvoltage.

during

block

erasure,

program,

lock-bit

configuration, and minimal processor overhead with

RAM-like interface timings.

11

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

V_PENHon V_PENenables successful block erasure,

programming, and lock-bit configuration. All

functions associated with altering memory

2.1

Data Protection

Depending on the application, the system designer

may choose to make the V_PENswitchable (available

only when memory block erases, programs, or lock-

bit configurations are required) or hardwired to

contents—block

erase,

program,

lock-bit

configuration—are accessed via the CUI and

verified through the status register.

V

_PENH. The device accommodates either design

Commands are written using standard micro-

processor write timings. The CUI contents serve as

input to the WSM, which controls the block erase,

program, and lock-bit configuration. The internal

algorithms are regulated by the WSM, including

pulse repetition, internal verification, and margining

of data. Addresses and data are internally latched

during program cycles.

practice and encourages optimization of the

processor-memory interface.

When V_PEN≤ V_PENLK, memory contents cannot be

altered. The CUI’s two-step block erase, byte/word

program, and lock-bit configuration command

sequences provide protection from unwanted

operations even when V_PENHis applied to V_PEN. All

program functions are disabled when V_CCis below

the write lockout voltage V_LKOor when RP# is V_IL.

The device’s block locking capability provides

additional protection from inadvertent code or data

alteration by gating erase and program operations.

Interface software that initiates and polls progress

of block erase, program, and lock-bit configuration

can be stored in any block. This code is copied to

and executed from system RAM during flash

memory updates. After successful completion,

reads are again possible via the Read Array

command. Block erase suspend allows system

software to suspend a block erase to read or

program data from/to any other block.

3.0 BUS OPERATION

The local CPU reads and writes flash memory

in-system. All bus cycles to or from the flash

memory conform to standard microprocessor bus

cycles.

A [22-0]: 64-Mbit

A [21-0]: 32-Mbit

7FFFFF

A [22-1]: 64-Mbit

A [21-1]: 32-Mbit

3FFFFF

128-Kbyte Block

64-Word Block

63

31

63

31

7E0000

3F0000

3FFFFF

3E0000

1FFFFF

1F0000

03FFFF

01FFFF

128-Kbyte Block

64-Word Block

1

0

1

0

020000

01FFFF

010000

00FFFF

000000

Byte-Wide (x8) Mode

Word Wide (x16) Mode

0606_05

Figure 5. Memory Map

12

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

3.3 Standby

Table 2. Chip Enable Truth Table^(1,2)

CE₂

V_IL

V_IH

CE₁

V_IL

V_IH

V_IL

V_IH

CE₀

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

DEVICE

Enabled

Disabled

Enabled

Disabled

CE₀, CE₁, and CE₂can disable the device (see

Table 2, Chip Enable Truth Table) and place it in

standby mode which substantially reduces device

power consumption. DQ₀–DQ₁₅outputs are placed

in a high-impedance state independent of OE#. If

deselected during block erase, program, or lock-bit

configuration, the WSM continues functioning, and

consuming active power until the operation

completes.

3.4

Reset/Power-Down

RP# at V_ILinitiates the reset/power-down mode.

In read modes, RP#-low deselects the memory,

places output drivers in a high-impedance state,

and turns off numerous internal circuits. RP# must

be held low for a minimum of t_PLPH. Time t_PHQVis

required after return from reset mode until initial

memory access outputs are valid. After this wake-

up interval, normal operation is restored. The CUI is

reset to read array mode and status register is set

to 80H.

NOTE:

1. See Application Note AP-647 Intel StrataFlash™

Memory Design Guide for typical CE configurations.

2. For single-chip applications CE₂and CE₁can be

strapped to GND.

3.1

Read

Information can be read from any block, query,

identifier codes, or status register independent of

During block erase, program, or lock-bit

configuration modes, RP#-low will abort the

operation. In default mode, STS transitions low and

remains low for a maximum time of t_PLPH+ t_PHRH

until the reset operation is complete. Memory

contents being altered are no longer valid; the data

may be partially corrupted after a program or

partially altered after an erase or lock-bit

configuration. Time t_PHWLis required after RP#

goes to logic-high (V_IH) before another command

can be written.

the V_PENvoltage. RP# can be at either V_IHor V_HH

.

Upon initial device power-up or after exit from

reset/power-down mode, the device automatically

resets to read array mode. Otherwise, write the

appropriate read mode command (Read Array,

Read Query, Read Identifier Codes, or Read Status

Register) to the CUI. Six control pins dictate the

data flow in and out of the component: CE₀, CE₁,

CE₂, OE#, WE#, and RP#. The device must be

enabled (see Table 2, Chip Enable Truth Table),

and OE# must be driven active to obtain data at the

outputs. CE₀, CE₁, and CE₂are the device

selection controls and, when enabled (see Table 2,

Chip Enable Truth Table), select the memory

device. OE# is the data output (DQ₀–DQ₁₅) control

and, when active, drives the selected memory data

As with any automated device, it is important to

assert RP# during system reset. When the system

comes out of reset, it expects to read from the flash

memory. Automated flash memories provide status

information when accessed during block erase,

program, or lock-bit configuration modes. If a CPU

reset occurs with no flash memory reset, proper

initialization may not occur because the flash

memory may be providing status information

instead of array data. Intel’s flash memories allow

proper initialization following a system reset through

the use of the RP# input. In this application, RP# is

controlled by the same RESET# signal that resets

the system CPU.

onto the I/O bus. WE# must be at V_IH

.

3.2

Output Disable

With OE# at a logic-high level (V_IH), the device

outputs are disabled. Output pins DQ₀–DQ₁₅are

placed in a high-impedance state.

13

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

V_PENadditionally enables block erase, program,

and lock-bit configuration operations.

3.5

Read Query

The read query operation outputs block status

information, CFI (Common Flash Interface) ID

string, system interface information, device

geometry information, and Intel-specific extended

query information.

Device operations are selected by writing specific

commands into the CUI. Table 4 defines these

commands.

Word

Address

A[22-1]: 64 Mbit

A[21-1]: 32 Mbit

3.6

Read Identifier Codes

3FFFFF

Block 63

The read identifier codes operation outputs the

manufacturer code, device code, block lock

configuration codes for each block, and the master

lock configuration code (see Figure 6). Using the

manufacturer and device codes, the system CPU

can automatically match the device with its proper

algorithms. The block lock and master lock

configuration codes identify locked and unlocked

blocks and master lock-bit setting.

Reserved for Future

Implementation

3F0003

3F0002

Block 63 Lock Configuration

Reserved for Future

Implementation

3F0000

3EFFFF

(Blocks 32 through 62)

Block 31

Reserved for Future

Implementation

3.7

Write

Writing commands to the CUI enables reading of

device data, query, identifier codes, inspection and

1F0003

1F0002

Block 31 Lock Configuration

clearing of the status register, and, when V_PEN

V_PENHblock erasure, program, and lock-bit

configuration.

=

Reserved for Future

Implementation

,

1F0000

1EFFFF

(Blocks 2 through 30)

The Block Erase command requires appropriate

command data and an address within the block to

be erased. The Byte/Word Program command

requires the command and address of the location

to be written. Set Master and Block Lock-Bit

commands require the command and address

within the device (Master Lock) or block within the

device (Block Lock) to be locked. The Clear Block

Lock-Bits command requires the command and

address within the device.

01FFFF

Block 1

Reserved for Future

Implementation

010003

010002

Block 1 Lock Configuration

Reserved for Future

Implementation

010000

00FFFF

Block 0

Reserved for Future

Implementation

The CUI does not occupy an addressable memory

location. It is written when the device is enabled

and WE# is active. The address and data needed to

execute a command are latched on the rising edge

of WE# or the first edge of CE₀, CE₁, or CE₂that

disables the device (see Table 2, Chip Enable Truth

Table). Standard microprocessor write timings are

used.

000004

000003

Master Lock Configuration

Block 0 Lock Configuration

Device Code

000002

000001

000000

Manufacturer Code

0606_06

NOTE:

4.0 COMMAND DEFINITIONS

A₀is not used in either x8 or x16 modes when obtaining

these identifier codes. Data is always given on the low byte

in x16 mode (upper byte contains 00h).

When the V_PENvoltage

≤ V_PENLK, only read

operations from the status register, query, identifier

codes, or blocks are enabled. Placing V_PENHon

Figure 6. Device Identifier Code Memory Map

14

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

Table 3. Bus Operations

(10)

Mode

Notes RP# CE_0,1,2

OE#⁽¹¹⁾WE#⁽¹¹⁾Address V_PEN

DQ⁽⁸⁾

STS

(default

mode)

Read Array

1,2,3 V_IHor Enabled

V_HH

V_IL

V_IH

X

V_IH

X

D_OUT

High Z⁽⁹⁾

Output

Disable

V_IHor Enabled

V_HH

High Z

Note 4

X

Standby

V_IHor Disabled

V_HH

X

Reset/Power-

Down Mode

V_IL

X

High Z⁽⁹⁾

Read

V

_IHor Enabled

V_IL

V_IH

See

Identifier

Codes

V_HH

Figure 6

Read Query

V_IHor Enabled

V_HH

V_IL

V_IH

See

Table 7

X

Note 5

D_OUT

High Z⁽⁹⁾

Read Status

(WSM off)

V_IHor Enabled

V_HH

X

Read Status

(WSM on)

V_IHor Enabled

V_HH

X

V_PENH

DQ₇= D_OUT

DQ_15–8= High Z

DQ_6–0= High Z

Write

3,6,7 V_IHor Enabled

V_HH

V_IH

V_IL

X

D_IN

X

NOTES:

1. Refer to DC Characteristics. When V_PEN≤ V_PENLK, memory contents can be read, but not altered.

2. X can be V_ILor V_IHfor control and address pins, and V_PENLKor V_PENHfor V_PEN. See DC Characteristics for V_PENLKand

_PENHvoltages.

V

3. In default mode, STS is V_OLwhen the WSM is executing internal block erase, program, or lock-bit configuration algorithms.

It is V_OHwhen the WSM is not busy, in block erase suspend mode (with programming inactive), or reset/power-down

mode.

4. See Read Identifier Codes Command section for read identifier code data.

5. See Read Query Mode Command section for read query data.

6. Command writes involving block erase, program, or lock-bit configuration are reliably executed when V_PEN= V_PENHand

V

_CCis within specification. Block erase, program, or lock-bit configuration with V_IH< RP# < V_HHproduce spurious results

and should not be attempted.

7. Refer to Table 4 for valid D_INduring a write operation.

8. DQ refers to DQ₀–DQ₇if BYTE# is low and DQ₀–DQ₁₅if BYTE# is high.

9. High Z will be V_OHwith an external pull-up resistor.

10. See Table 2 for valid CE configurations.

11. OE# and WE# should never be enabled simultaneously.

15

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

Table 4. Intel StrataFlash™ Memory Command Set Definitions⁽¹⁴⁾

Command

Scaleable Bus Notes

or Basic Cycles

Command Req'd.

Set⁽¹⁵⁾

First Bus Cycle

Second Bus Cycle

Oper⁽¹⁾Addr⁽²⁾Data^(3,4)Oper⁽¹⁾Addr⁽²⁾Data^(3,4)

Read Array

SCS/BCS

1

Write

X

FFH

90H

Read Identifier

Codes

≥2

5

6

Read

IA

ID

Read Query

SCS

≥ 2

Write

X

98H

70H

Read

QA

X

QD

Read Status

Register

SCS/BCS

2

SRD

Clear Status

Register

SCS/BCS

1

Write

X

50H

E8H

Write to Buffer

SCS/BCS

> 2

2

7,8,9

Write

BA

X

Write

BA

PA

N

Word/Byte

Program

10,11

40H

or

PD

10H

Block Erase

SCS/BCS

2

1

9,10

Write

X

20H

B0H

Write

BA

D0H

Block Erase

Suspend

Block Erase

Resume

SCS/BCS

1

10

Write

X

D0H

Configuration

SCS

2

Write

X

B8H

60H

Write

X

BA

X

CC

01H

D0H

Set Block Lock-Bit

12

13

Clear Block Lock-

Bits

Set Master Lock-

Bit

2

12,13

Write

X

60H

Write

X

F1H

16

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

NOTES:

1. Bus operations are defined in Table 3.

2. X = Any valid address within the device.

BA = Address within the block.

IA = Identifier Code Address: see Figure 6 and Table 13.

QA = Query database Address.

PA = Address of memory location to be programmed.

3. ID = Data read from Identifier Codes.

QD = Data read from Query database.

SRD = Data read from status register. See Table 16 for a description of the status register bits.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.

CC = Configuration Code.

4. The upper byte of the data bus (DQ₈–DQ₁₅) during command writes is a “Don’t Care” in x16 operation.

5. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock

codes. See Read Identifier Codes Command section for read identifier code data.

6. If the WSM is running, only DQ₇is valid; DQ₁₅–DQ₈and DQ₆–DQ₀float, which places them in a high-impedance state.

7. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.

8. The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument. Count ranges

on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N = 000FH. The third and

consecutive bus cycles, as determined by N, are for writing data into the Write Buffer. The Confirm command (D0H) is

expected after exactly N + 1 write cycles; any other command at that point in the sequence aborts the write to buffer

operation. Please see Figure 7, Write to Buffer Flowchart, for additional information.

9. The write buffer or erase operation does not begin until a Confirm command (D0h) is issued.

10. If the block is locked, RP# must be at V_HHto enable block erase or program operations. Attempts to issue a block erase or

program to a locked block while RP# is V_IHwill fail.

11. Either 40H or 10H are recognized by the WSM as the byte/word program setup.

12. If the master lock-bit is set, RP# must be at V_HHto set a block lock-bit. RP# must be at V_HHto set the master lock-bit. If the

master lock-bit is not set, a block lock-bit can be set while RP# is V .

IH

13. If the master lock-bit is set, RP# must be at V_HHto clear block lock-bits. The clear block lock-bits operation simultaneously

clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is V .

IH

14. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.

15. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The

Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.

17

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

4.2.1 QUERY STRUCTURE OUTPUT

4.1

Read Array Command

The Query “database,” described later, allows

system software to gain critical information for

controlling the flash component. This section

describes the device’s CFI-compliant interface that

allows the host system to access Query data.

Upon initial device power-up and after exit from

reset/power-down mode, the device defaults to read

array mode. This operation is also initiated by

writing the Read Array command. The device

remains enabled for reads until another command

is written. Once the internal WSM has started a

block erase, program, or lock-bit configuration, the

device will not recognize the Read Array command

until the WSM completes its operation unless the

WSM is suspended via an Erase Suspend

command. The Read Array command functions

independently of the V_PENvoltage and RP# can be

Query data are always presented on the lowest-

order data outputs DQ₀–DQ₇only. The Query table

device starting address is a 10h word address.

The first two bytes of the Query structure, “Q” and

”R” in ASCII, appear on the low byte at word

addresses 10h and 11h. This CFI-compliant device

outputs 00H data on upper bytes. Thus, the device

outputs ASCII “Q” in the low byte DQ₀–DQ₇and

V

_IHor V_HH

.

00h in the high byte DQ₈–DQ₁₅

.

4.2

Read Query Mode Command

Since the device is x8/x16 capable, the x8 data is

still presented in word-relative (16-bit) addresses.

However, the “fill data” (00h) is not the same as

driven by the upper bytes in the x16 mode. As in

x16 mode, the byte address (A₀or A₁depending on

pinout) is ignored for Query output so that the “odd

byte address” (A₀or A₁high) repeats the “even byte

address” data (A₀or A₁low). Therefore, in x8 mode

using byte addressing, the device will output the

sequence “Q,” “Q,” “R,” “R,” “Y,” “Y,” and so on,

beginning at byte-relative address 20h (which is

equivalent to word offset 10h in x16 mode).

This section defines the data structure or

“database” returned by the SCS (Scaleable

Command Set) Query command. System software

should parse this structure to gain critical

information to enable programming, block erases,

and otherwise control the flash component. The

SCS Query is part of an overall specification for

multiple command set and control interface

descriptions called Common Flash Interface, or

CFI. The Query can only be accessed when the

WSM is off or the device is suspended.

In Query addresses where two or more bytes of

information are located, the least significant data

byte is presented on the lower address, and the

most significant data byte is presented on the

higher address.

18

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

Table 5. Summary of Query Structure Output as a Function of Device and Mode

Device

type/

Query start

location

Query data with

Query

start

address

in bytes

Query data with

byte addressing

maximum device

mode

in maximum

device

bus width addressing

“x” = ASCII equivalent

bus width

addresses

x16 device/

x16 mode

10h

10h: 0051h

11h: 0052h

12h: 0059h

“Q”

“R”

“Y”

20h

20h: 51h

21h: 00h

22h: 52h

“Q”

null

“R”

x16 device/

x8 mode

N/A⁽¹⁾

20h: 51h

21h: 51h

22h: 52h

“Q”

“R”

NOTE:

1. The system must drive the lowest order addresses to access all the device’s array data when the device is configured in x8

mode. Therefore, word addressing where these lower addresses not toggled by the system is“Not Applicable” for x8-

configured devices.

Table 6. Example of Query Structure Output of a x16- and x8-Capable Device

Device

Address

Word Addressing:

Query Data

Byte

Address

Byte Addressing:

Query Data

A₁₆–A₁

D₁₅–D₀

A₇–A₀

D₇–D₀

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

...

0051h

“Q”

“R”

“Y”

PrVendor

ID #

PrVendor

TblAdr

AltVendor

ID #

20h

21h

22h

23h

24h

25h

26h

27h

28h

...

51h

52h

59h

P_ID_LO

P_ID_HI

...

“Q”

“R”

“Y”

PrVendor

ID #

“

0052h

0059h

P_ID_LO

P_ID_HI

P_LO

P_HI

A_ID_LO

A_ID_HI

...

19

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

4.2.2 QUERY STRUCTURE OVERVIEW

E

The Query command causes the flash component to display the Common Flash Interface (CFI) Query

structure or “database.” The structure sub-sections and address locations are summarized below. See AP-

646 Common Flash Interface (CFI) and Command Sets (order number 292204) for a full description of CFI.

The following sections describe the Query structure sub-sections in detail.

Table 7. Query Structure

Offset

00h

Sub-Section Name

Description

Manufacturer Code

01h

Device Code

(BA+2)h⁽²⁾

04–0Fh

10h

Block Status Register

Block-Specific Information

Reserved

Reserved for Vendor-Specific Information

Command Set ID and Vendor Data Offset

Device Timing and Voltage Information

Flash Device Layout

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

P⁽³⁾

Primary Vendor-Specific Extended

Query table

Vendor-Defined Additional Information

Specific to the Primary Vendor Algorithm

NOTES:

1. Refer to Query Data Output section of Device Hardware interface for the detailed definition of offset address as a function

of device word width and mode.

2. BA = The beginning location of a Block Address (i.e., 2000h is the beginning location of block 2 when the block size is

128 KB).

3. The Primary Vendor-Specific Extended Query table (P) address may change among SCS-compliant devices. Software

should retrieve this address from address 15 to guarantee compatibility with future SCS-compliant devices.

20

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

4.2.3

BLOCK STATUS REGISTER

The Block Status Register indicates whether a given block is locked and can be accessed for program/erase

operations. On SCS devices that do not implement block locking, BSR.0 will indicate functional block status

on partially functional devices. The Block Status Register is accessed from word address 02h within each

block.

Table 8. Block Status Register

Offset

Length

(bytes)

Description

Intel StrataFlash™

Memory

x16 device/mode

(BA +2)h¹

01h

Block Status Register

BSR.0 = Block Lock or Non-Functional Status

BA+2: 0000h or

0001h

BA+2 (bit 0): 0 or 1

(Optional)

1 = Locked or Non-Functional

0 = Unlocked

BSR.1 = Block Erase or Non-Functional

Status⁽²⁾(Optional)

BA+2 (bit 1): 0

(The device does

not support Block

Erase Status)

1 = Last erase operation did

not complete successfully or Non-

Functional

0 = Last erase operation

completed successfully or Functional

BSR 2–7 Reserved for future use

BA+2 (bits 2–7): 0

NOTES:

1. BA = The beginning location of a Block Address (i.e., 2000h is the beginning location of block 2).

2. Block Erase Status is an optional part of the SCS definition and is not incorporated on this device.

21

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

4.2.4 CFI QUERY IDENTIFICATION STRING

E

The Identification String provides verification that the component supports the Common Flash Interface

specification. Additionally, it indicates which version of the spec and which vendor-specified command set(s)

is(are) supported.

Table 9. CFI Identification

Offset

Length

(bytes)

Description

Intel StrataFlash™

Memory

10h

03h

Query-unique ASCII string “QRY“

10:

11:

12:

0051h

0052h

0059h

13h

02h

Primary Vendor Command Set and

Control Interface ID Code

13:

14:

0001h

0000h

16-bit ID code for vendor-specified algorithms

15h

17h

02h

Address for Primary Algorithm Extended Query table

Offset value = P = 31h

15:

16:

0031h

0000h

Alternate Vendor Command Set and

Control Interface ID Code

17:

18:

0000h

second vendor-specified algorithm supported

Note: 0000h means none exists

19h

02h

Address for Secondary Algorithm Extended Query table

Note: 0000h means none exists

19:

1A:

0000h

22

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

4.2.5

SYSTEM INTERFACE INFORMATION

The following device information can optimize system interface software.

Table 10. System Interface Information

Offset

Length

(bytes)

Description

Intel

StrataFlash™

Memory

1Bh

01h

V_CCLogic Supply Minimum

Program/Erase voltage

1B:

0045h

0055h

0000h

bits 7–4

bits 3–0

BCD volts

BCD 100 mv

1Ch

1Dh

1Eh

V_CCLogic Supply Maximum

Program/Erase voltage

1C:

1D:

1E:

bits 7–4

bits 3–0

BCD volts

BCD 100 mv

V_PP[Programming] Supply

Minimum Program/Erase voltage

bits 7–4

bits 3–0

HEX volts

BCD 100 mv

V_PP[Programming] Supply

Maximum Program/Erase voltage

bits 7–4

bits 3–0

HEX volts

BCD 100 mv

1Fh

20h

21h

22h

23h

24h

25h

26h

01h

Typical time-out per single byte/word

program, 2^Nµs

1F:

20:

21:

22:

23:

24:

25:

26:

0007h

000Ah

0000h

0004h

0000h

Typical time-out for max. buffer write,

2^Nµs

Typical time-out per individual block

erase, 2^Nms

Typical time-out for full chip erase,

2^Nms (0000h = not supported)

Maximum time-out for byte/word program,

2^Ntimes typical

Maximum time-out for buffer write,

2^Ntimes typical

Maximum time-out per individual

block erase, 2^Ntimes typical

Maximum time-out for chip erase,

2^Ntimes typical (00h = not supported)

23

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

4.2.6 DEVICE GEOMETRY DEFINITION

This field provides critical details of the flash device geometry.

E

Table 11. Device Geometry Definition

Description

Offset

Length

(bytes)

Intel

StrataFlash™

Memory

27h

01h

Device Size = 2^Nin number of bytes.

27:

0017h

(64-Mbit)

0016h

(32-Mbit)

28h

02h

Flash Device Interface description

28:

29:

0002h

0000h

value

meaning

0000h

0002h

x8 asynchronous

x8/x16 asynchronous

2Ah

2Ch

02h

01h

Maximum number of bytes in write buffer = 2^N

2A:

2B:

0005h

0000h

Number of Erase Block Regions within device:

bits 7–0 = x = # of Erase Block Regions

Erase Block Region Information

2C:

0001h

2Dh

04h

y: 64 Blocks

(64-Mbit)

2D:

2E:

bits 15–0 = y, where y+1 = Number of Erase Blocks

of identical size within region

003Fh

0000h

bits 31–16 = z, where the Erase Block(s) within this

Region are (z) times 256 bytes

y: 32 Blocks

(32-Mbit)

2D:

2E:

001Fh

0000h

z: (128 KB size)

2F:

30:

0000h

0002h

24

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

4.2.7

PRIMARY-VENDOR SPECIFIC EXTENDED QUERY TABLE

Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query table

specifies this and other similar information.

Table 12. Primary Vendor-Specific Extended Query

Offset⁽¹⁾

Length

(bytes)

Description

Intel

StrataFlash™

Memory

(P)h

03h

Primary extended Query table unique ASCII string “PRI”

31:

32:

33:

0050h

0052h

0049h

(P +3)h

(P +4)h

(P +5)h

01h

04h

Major version number, ASCII

34:

35:

0031

Minor version number, ASCII

Optional Feature and Command Support

36:

37:

38:

39:

000Ah

0000h

bit 0

bit 1

bit 2

bit 3

bit 4

Chip Erase Supported

Suspend Erase Supported

Suspend Program Supported (1=yes, 0=no)

Lock/Unlock Supported

Queued Erase Supported

(1=yes, 0=no)

bits 5–31 Reserved for future use; undefined bits

are “0”

(P +9)h

01h

Supported functions after Suspend

3A:

0001h

Read Array, Status, and Query are always supported

during suspended Erase. This field defines other

operations supported.

bit 0

Program supported after Erase Suspend

(1=yes, 0=no)

bits 1–7 Reserved for future use; undefined bits

are “0”

(P +A)h

02h

Block Status Register Mask

3B:

3C:

0001h

0000h

Defines which bits in the Block Status Register section of

Query are implemented.

bit 0

bit 1

Block Status Register Lock Bit [BSR.0] active

(1=yes, 0=no)

Block Status Register Valid Bit [BSR.1] active

(1=yes, 0=no)

bits 2–15 Reserved for future use; undefined bits

are “0”

NOTE:

1. The Primary Vendor-Specific Extended Query table (P) address may change among SCS-compliant devices. Software

should retrieve this address from address 15 to guarantee compatibility with future SCS-compliant devices.

25

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

Table 12. Primary Vendor-Specific Extended Query (Continued)

Offset⁽¹⁾

Length

(bytes)

Description

Intel

StrataFlash™

Memory

(P +C)h

01h

V_CCOptimum Program/Erase voltage (highest

performance)

3D:

3E:

0050h

bits 7–4

BCD value in volts

bits 3–0

BCD value in 100 millivolts

(P +D)h

(P +E)h

01h

V_PP[Programming] Optimum Program/Erase voltage

0000h

bits 7–4

bits 3–0

HEX value in volts

BCD value in 100 millivolts

Note: This value is 0000h; no V_PPpin is present

Reserved for future use

reserved

NOTE:

1. The Primary Vendor-Specific Extended Query table (P) address may change among SCS-compliant devices. Software

should retrieve this address from address 15 to guarantee compatibility with future SCS-compliant devices.

Table 13. Identifier Codes⁽¹⁾

4.3

Read Identifier Codes

Command

Code

Address⁽¹⁾

Data

Manufacture Code

Device Code 32-Mbit

64-Mbit

00000

00001

(00) 89

(00) 14

(00) 15

The identifier code operation is initiated by writing

the Read Identifier Codes command. Following the

command write, read cycles from addresses shown

in Figure 6 retrieve the manufacturer, device, block

lock configuration and master lock configuration

codes (see Table 13 for identifier code values). To

terminate the operation, write another valid

command. Like the Read Array command, the

Read Identifier Codes command functions

independently of the V_PENvoltage and RP# can be

V_IHor V_HH. This command is valid only when the

WSM is off or the device is suspended. Following

the Read Identifier Codes command, the following

information can be read:

00001

Block Lock Configuration

• Block Is Unlocked

• Block Is Locked

X0002⁽²⁾

DQ₀= 0

DQ₀= 1

DQ_1–7

• Reserved for Future Use

Master Lock Configuration

• Device Is Unlocked

• Device Is Locked

• Reserved for Future Use

NOTE:

00003

DQ₀= 0

DQ₀= 1

DQ_1–7

1.

A₀is not used in either x8 or x16 modes when obtaining

the identifier codes. The lowest order address line is A .

1

Data is always presented on the low byte in x16 mode

(upper byte contains 00h).

2. X selects the specific block’s lock configuration code.

See Figure 6 for the device identifier code memory

map.

26

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

4.4

Read Status Register

Command

4.6

Block Erase Command

Erase is executed one block at a time and initiated

by a two-cycle command. A block erase setup is

first written, followed by an block erase confirm.

This command sequence requires an appropriate

address within the block to be erased (erase

changes all block data to FFH). Block

preconditioning, erase, and verify are handled

internally by the WSM (invisible to the system).

After the two-cycle block erase sequence is written,

the device automatically outputs status register

data when read (see Figure 9). The CPU can detect

block erase completion by analyzing the output of

the STS pin or status register bit SR.7. Toggle OE#,

CE₀, CE₁, or CE₂to update the status register.

The status register may be read to determine when

a block erase, program, or lock-bit configuration is

complete and whether the operation completed

successfully. It may be read at any time by writing

the Read Status Register command. After writing

this command, all subsequent read operations

output data from the status register until another

valid command is written. The status register

contents are latched on the falling edge of OE# or

the first edge of CE₀, CE₁, or CE₂that enables the

device (see Table 2, Chip Enable Truth Table). OE#

must toggle to V_IHor the device must be disabled

(see Table 2, Chip Enable Truth Table) before

further reads to update the status register latch.

The Read Status Register command functions

independently of the V_PENvoltage. RP# can be V_IH

When the block erase is complete, status register

bit SR.5 should be checked. If a block erase error is

detected, the status register should be cleared

before system software attempts corrective actions.

The CUI remains in read status register mode until

a new command is issued.

or V_HH

.

During a program, block erase, set lock-bit, or clear

lock-bit command sequence, only SR.7 is valid until

the Write State Machine completes or suspends the

operation. Device I/O pins DQ₀–DQ₆and DQ₈–

DQ₁₅are placed in a high-impedance state. When

the operation completes or suspends (check Status

Register bit 7), all contents of the Status Register

are valid when read.

This two-step command sequence of set-up

followed by execution ensures that block contents

are not accidentally erased. An invalid Block Erase

command sequence will result in both status

register bits SR.4 and SR.5 being set to “1.” Also,

reliable block erasure can only occur when

V_CCis valid and V_PEN= V_PENH. If block erase is

attempted while V_PEN≤ V_PENLK, SR.3 and SR.5 will

be set to “1.” Successful block erase requires that

the corresponding block lock-bit be cleared or, if

set, that RP# = V_HH. If block erase is attempted

when the corresponding block lock-bit is set and

RP# = V_IH, SR.1 and SR.5 will be set to “1.” Block

erase operations with V_IH< RP# < V_HHproduce

spurious results and should not be attempted.

4.5

Clear Status Register

Command

Status register bits SR.5, SR.4, SR.3, and SR.1 are

set to “1”s by the WSM and can only be reset by

the Clear Status Register command. These bits

indicate various failure conditions (see Table 16).

By allowing system software to reset these bits,

several operations (such as cumulatively erasing or

locking multiple blocks or writing several bytes in

sequence) may be performed. The status register

may be polled to determine if an error occurred

during the sequence.

4.7

Block Erase Suspend

Command

The Block Erase Suspend command allows

block-erase interruption to read or program data in

another block of memory. Once the block erase

process starts, writing the Block Erase Suspend

command requests that the WSM suspend the

block erase sequence at a predetermined point in

the algorithm. The device outputs status register

data when read after the Block Erase Suspend

command is written. Polling status register bit SR.7

then SR.6 can determine when the block erase

operation has been suspended (both will be set to

“1”). In default mode, STS will also transition to

To clear the status register, the Clear Status

Register command (50H) is written. It functions

independently of the applied V_PENvoltage. RP# can

be V_IHor V_HH. The Clear Status Register Command

is only valid when the WSM is off or the device is

suspended.

27

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

V_OH. Specification t_WHRHdefines the block erase

suspend latency.

Internally, this device programs many flash cells in

parallel. Because of this parallel programming,

maximum programming performance and lower

power are obtained by aligning the start address at

the beginning of

(i.e., A₄–A₀of the start address = 0).

At this point, a Read Array command can be written

to read data from blocks other than that which is

suspended. A program command sequence can

also be issued during erase suspend to program

data in other blocks. During a program operation

with block erase suspended, status register bit

SR.7 will return to “0” and the STS output (in default

a

write buffer boundary

After the final buffer data is given, a Write Confirm

command is issued. This initiates the WSM (Write

State Machine) to begin copying the buffer data to

the flash array. If a command other than Write

Confirm is written to the device, an “Invalid

Command/Sequence” error will be generated and

Status Register bits SR.5 and SR.4 will be set to a

“1.” For additional buffer writes, issue another Write

to Buffer setup command and check XSR.7.

mode) will transition to V_OL

.

The only other valid commands while block erase is

suspended are Read Query, Read Status Register,

Clear Status Register, Configure, and Block Erase

Resume. After a Block Erase Resume command is

written to the flash memory, the WSM will continue

the block erase process. Status register bits SR.6

and SR.7 will automatically clear and STS (in

default mode) will return to V_OL. After the Erase

Resume command is written, the device

automatically outputs status register data when

read (see Figure 10). V_PENmust remain at V_PENH

(the same V_PENlevel used for block erase) while

block erase is suspended. RP# must also remain at

V_IHor V_HH(the same RP# level used for block

erase). Block erase cannot resume until program

operations initiated during block erase suspend

have completed.

If an error occurs while writing, the device will stop

writing, and Status Register bit SR.4 will be set to a

“1” to indicate a program failure. The internal WSM

verify only detects errors for “1”s that do not

successfully program to “0”s. If a program error is

detected, the status register should be cleared. Any

time SR.4 and/or SR.5 is set (e.g., a media failure

occurs during a program or an erase), the device

will not accept any more Write to Buffer commands.

Additionally, if the user attempts to program past an

erase block boundary with

a Write to Buffer

command, the device will abort the Write to Buffer

operation. This will generate an "Invalid Command/

Sequence" error and Status Register bits SR.5 and

SR.4 will be set to a “1.”

4.8

Write to Buffer Command

Reliable buffered writes can only occur when

To program the flash device, a Write to Buffer

command sequence is initiated. A variable number

of bytes, up to the buffer size, can be loaded into

the buffer and written to the flash device. First, the

Write to Buffer setup command is issued along with

the Block Address (see Figure 7, Write to Buffer

Flowchart). At this point, the eXtended Status

Register (XSR, see Table 17) information is loaded

and XSR.7 reverts to "buffer available" status. If

XSR.7 = 0, the write buffer is not available. To retry,

continue monitoring XSR.7 by issuing the Write to

Buffer setup command with the Block Address until

XSR.7 = 1. When XSR.7 transitions to a “1,” the

buffer is ready for loading.

V

_PEN= V_PENH. If a buffered write is attempted while

V_PEN≤ V_PENLK, Status Register bits SR.4 and SR.3

will be set to “1.” Buffered write attempts with

invalid V_CCand V_PENvoltages produce spurious

results and should not be attempted. Finally,

successful programming requires that the

corresponding Block Lock-Bit be reset or, if set, that

RP# = V_HH. If a buffered write is attempted when

the corresponding Block Lock-Bit is set and RP# =

V_IH, SR.1 and SR.4 will be set to “1.” Buffered write

operations with V_IH< RP# < V_HHproduce spurious

results and should not be attempted.

Now a word/byte count is given to the part with the

Block Address. On the next write, a device start

address is given along with the write buffer data.

Subsequent writes provide additional device

addresses and data, depending on the count. All

subsequent addresses must lie within the start

address plus the count.

4.9

Byte/Word Program Commands

Byte/Word program is executed by a two-cycle

command sequence. Byte/Word program setup

(standard 40H or alternate 10H) is written followed

by a second write that specifies the address and

data (latched on the rising edge of WE#). The WSM

28

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

then takes over, controlling the program and

program verify algorithms internally. After the

program sequence is written, the device

automatically outputs status register data when

read (see Figure 8). The CPU can detect the

completion of the program event by analyzing the

STS pin or status register bit SR.7.

An invalid configuration code will result in both

status register bits SR.4 and SR.5 being set to “1.”

When configured in one of the pulse modes, the

STS pin pulses low with a typical pulse width of

250 ns.

4.11 Set Block and Master Lock-Bit

Commands

When program is complete, status register bit SR.4

should be checked. If a program error is detected,

the status register should be cleared. The internal

WSM verify only detects errors for “1”s that do not

successfully program to “0”s. The CUI remains in

read status register mode until it receives another

command.

A flexible block locking and unlocking scheme is

enabled via a combination of block lock-bits and a

master lock-bit. The block lock-bits gate program

and erase operations while the master lock-bit

gates block-lock bit modification. With the master

lock-bit not set, individual block lock-bits can be set

using the Set Block Lock-Bit command. The Set

Master Lock-Bit command, in conjunction with

RP# = V_HH, sets the master lock-bit. After the

master lock-bit is set, subsequent setting of block

lock-bits requires both the Set Block Lock-Bit

command and V_HHon the RP# pin. These

commands are invalid while the WSM is running or

Reliable byte/word programs can only occur when

V_CCand V_PENare valid. If a byte/word program is

attempted while V_PEN≤ V_PENLK, status register bits

SR.4 and SR.3 will be set to “1.” Successful

byte/word programs require that the corresponding

block lock-bit be cleared or, if set, that RP# = V_HH

.

If a byte/word program is attempted when the

corresponding block lock-bit is set and RP# = V_IH,

SR.1 and SR.4 will be set to “1.” Byte/Word

program operations with V_IH< RP# < V_HHproduce

spurious results and should not be attempted.

the device is suspended. See Table 14 for

summary of hardware and software write protection

options.

a

Set block lock-bit and master lock-bit commands

are executed by a two-cycle sequence. The set

block or master lock-bit setup along with

appropriate block or device address is written

followed by either the set block lock-bit confirm (and

an address within the block to be locked) or the set

master lock-bit confirm (and any device address).

The WSM then controls the set lock-bit algorithm.

After the sequence is written, the device

automatically outputs status register data when

read (see Figure 11). The CPU can detect the

completion of the set lock-bit event by analyzing the

STS pin output or status register bit SR.7.

4.10 Configuration Command

The Status (STS) pin can be configured to different

states using the Configuration command. Once the

STS pin has been configured, it remains in that

configuration until another configuration command

is issued or RP# is asserted low. Initially, the STS

pin defaults to RY/BY# operation where RY/BY#

low indicates that the state machine is busy.

RY/BY# high indicates that the state machine is

ready for a new operation or suspended. Table 15

displays the possible STS configurations.

When the set lock-bit operation is complete, status

register bit SR.4 should be checked. If an error is

detected, the status register should be cleared. The

CUI will remain in read status register mode until a

new command is issued.

To reconfigure the Status (STS) pin to other modes,

the Configuration command is given followed by the

desired configuration code. The three alternate

configurations are all pulse mode for use as a

system interrupt as described below. For these

configurations, bit

interrupt pulse, and bit

0

controls Erase Complete

controls Program

This two-step sequence of set-up followed by

execution ensures that lock-bits are not accidentally

set. An invalid Set Block or Master Lock-Bit

command will result in status register bits SR.4 and

SR.5 being set to “1.” Also, reliable operations

occur only when V_CCand V_PENare valid. With V_PEN

≤ V_PENLK, lock-bit contents are protected against

alteration.

1

Complete interrupt pulse. Supplying the 00h

configuration code with the Configuration command

resets the STS pin to the default RY/BY# level

mode. The possible configurations and their usage

are described in Table 15. The Configuration

command may only be given when the device is not

busy or suspended. Check SR.7 for device status.

29

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

A successful set block lock-bit operation requires

that the master lock-bit be zero or, if the master

lock-bit is set, that RP# = V_HH. If it is attempted with

the master lock-bit set and RP# = V_IH, SR.1 and

SR.4 will be set to “1” and the operation will fail. Set

block lock-bit operations while V_IH< RP# < V_HH

produce spurious results and should not be

can detect completion of the clear block lock-bits

event by analyzing the STS pin output or status

register bit SR.7.

When the operation is complete, status register bit

SR.5 should be checked. If a clear block lock-bit

error is detected, the status register should be

cleared. The CUI will remain in read status register

mode until another command is issued.

attempted.

A

successful set master lock-bit

operation requires that RP# = V_HH. If it is attempted

with RP# = V_IH, SR.1 and SR.4 will be set to “1”

and the operation will fail. Set master lock-bit

operations with V_IH< RP# < V_HHproduce spurious

results and should not be attempted.

This two-step sequence of set-up followed by

execution ensures that block lock-bits are not

accidentally cleared. An invalid Clear Block

Lock-Bits command sequence will result in status

register bits SR.4 and SR.5 being set to “1.” Also, a

reliable clear block lock-bits operation can only

occur when V_CCand V_PENare valid. If a clear block

4.12 Clear Block Lock-Bits

Command

lock-bits operation is attempted while V_PEN

≤

V

_PENLK, SR.3 and SR.5 will be set to “1.” A

All set block lock-bits are cleared in parallel via the

Clear Block Lock-Bits command. With the master

lock-bit not set, block lock-bits can be cleared using

only the Clear Block Lock-Bits command. If the

master lock-bit is set, clearing block lock-bits

requires both the Clear Block Lock-Bits command

and V_HHon the RP# pin. This command is invalid

while the WSM is running or the device is

successful clear block lock-bits operation requires

that the master lock-bit is not set or, if the master

lock-bit is set, that RP# = V_HH. If it is attempted with

the master lock-bit set and RP# = V_IH, SR.1 and

SR.5 will be set to “1” and the operation will fail. A

clear block lock-bits operation with V_IH< RP# < V_HH

produce spurious results and should not be

attempted.

suspended. See Table 14 for

a summary of

hardware and software write protection options.

If a clear block lock-bits operation is aborted due to

V

_PENor V_CCtransitioning out of valid range or RP#

Clear block lock-bits command is executed by a

two-cycle sequence. A clear block lock-bits setup is

first written. The device automatically outputs status

register data when read (see Figure 12). The CPU

active transition, block lock-bit values are left in an

undetermined state. A repeat of clear block lock-

bits is required to initialize block lock-bit contents to

known values. Once the master lock-bit is set, it

cannot be cleared.

Table 14. Write Protection Alternatives

Block

Master

RP#

Operation

Lock-Bit Lock-Bit

Effect

Block Erase or

Program

0

V_IHor V_HHBlock Erase and Program Enabled

X

1

V_IH

Block is Locked. Block Erase and Program Disabled

V_HH

Block Lock-Bit Override. Block Erase and Program

Enabled

Set or Clear Block

Lock-Bit

0

1

X

V_IHor V_HHSet or Clear Block Lock-Bit Enabled

V_IH

Master Lock-Bit Is Set. Set or Clear Block Lock-Bit

Disabled

V_HH

Master Lock-Bit Override. Set or Clear Block Lock-Bit

Enabled

Set Master

Lock-Bit

X

V_IH

Set Master Lock-Bit Disabled

Set Master Lock-Bit Enabled

V_HH

30

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

Table 15. Configuration Coding Definitions

Pulse On

Program

Pulse On

Erase

Reserved

Complete⁽¹⁾Complete⁽¹⁾

bits 7–2

bit 1

DQ –DQ are reserved for future use.

bit 0

DQ –DQ

=

Reserved

STS Pin Configuration Codes

7

2

7

2

DQ –DQ

default (DQ –DQ = 00) RY/BY#, level mode

1 0

1

0

— used to control HOLD to a memory controller to

prevent accessing a flash memory subsystem while

any flash device's WSM is busy.

00 = default, level mode RY/BY#

(device ready) indication

01 = pulse on Erase complete

10 = pulse on Program complete

configuration 01

— used to generate a system interrupt pulse when

any flash device in an array has completed a Block

ER INT, pulse mode

11 = pulse on Erase or Program Complete Erase or sequence of Queued Block Erases. Helpful

for reformatting blocks after file system free space

Configuration Codes 01b, 10b, and 11b are all pulse

reclamation or “cleanup”

mode such that the STS pin pulses low then high

when the operation indicated by the given

configuration is completed.

configuration 10

PR INT, pulse mode

— used to generate a system interrupt pulse when

any flash device in an array has complete a Program

operation. Provides highest performance for servicing

continuous buffer write operations.

Configuration Command Sequences for STS pin

configuration (masking bits DQ –DQ to 00h) are

7

2

as follows:

configuration 11

ER/PR INT, pulse mode

Default RY/BY# level mode:

ER INT (Erase Interrupt):

Pulse-on-Erase Complete

PR INT (Program Interrupt):

B8h, 00h

B8h, 01h

— used to generate system interrupts to trigger

servicing of flash arrays when either erase or

program operations are completed when a common

interrupt service routine is desired.

B8h, 02h

Pulse-on-Program Complete

ER/PR INT (Erase or Program Interrupt): B8h, 03h

Pulse-on-Erase or Program Complete

NOTE:

1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.

31

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

Table 16. Status Register Definitions

WSMS

bit 7

ESS

bit 6

ECLBS

bit 5

PSLBS

bit 4

VPENS

bit 3

R

DPS

bit 1

R

bit 2

bit 0

High Z

When

Busy?

Status Register Bits

SR.7 = WRITE STATE MACHINE STATUS

NOTES:

No

Yes

Check STS or SR.7 to determine block

erase, program, or lock-bit configuration

completion. SR.6–SR.0 are not driven while

SR.7 = “0.”

1

0

= Ready

= Busy

SR.6 = ERASE SUSPEND STATUS

1

0

= Block Erase Suspended

= Block Erase in Progress/Completed

If both SR.5 and SR.4 are “1”s after a block

erase or lock-bit configuration attempt, an

improper command sequence was entered.

SR.5 = ERASE AND CLEAR LOCK-BITS

STATUS

SR.3 does not provide a continuous

1

0

= Error in Block Erasure or Clear Lock-Bits

programming voltage level indication. The

= Successful Block Erase or Clear Lock-Bits WSM interrogates and indicates the

programming voltage level only after Block

Yes

SR.4 = PROGRAM AND SET LOCK-BIT STATUS

Erase, Program, Set Block/Master Lock-Bit,

or Clear Block Lock-Bits command

sequences.

1

= Error in Programming or Set Master/Block

Lock-Bit

0

= Successful Programming or Set

Master/Block Lock Bit

SR.1 does not provide a continuous

indication of master and block lock-bit

values. The WSM interrogates the master

lock-bit, block lock-bit, and RP# only after

Block Erase, Program, or Lock-Bit

configuration command sequences. It

informs the system, depending on the

attempted operation, if the block lock-bit is

set, master lock-bit is set, and/or RP# is not

SR.3 = PROGRAMMING VOLTAGE STATUS

1

= Low Programming Voltage Detected,

Operation Aborted

0

= Programming Voltage OK

Yes

SR.2 = RESERVED FOR FUTURE

ENHANCEMENTS

SR.1 = DEVICE PROTECT STATUS

V

_HH. Read the block lock and master lock

1

= Master Lock-Bit, Block Lock-Bit and/or

RP# Lock Detected, Operation Abort

= Unlock

configuration codes using the Read

Identifier Codes command to determine

master and block lock-bit status.

0

Yes

SR.0 = RESERVED FOR FUTURE

ENHANCEMENTS

SR.2 and SR.0 are reserved for future use

and should be masked when polling the

status register.

32

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

Table 17. eXtended Status Register Definitions

Reserved

WBS

bit 7

bits 6–0

High Z

When

Busy?

Status Register Bits

NOTES:

No

XSR.7 = WRITE BUFFER STATUS

1 = Write buffer available

After a Buffer-Write command, XSR.7 = 1

indicates that a Write Buffer is available.

0 = Write buffer not available

SR.6–SR.0 are reserved for future use and

should be masked when polling the status

register.

Yes

XSR.6–XSR.0

=

RESERVED FOR FUTURE

ENHANCEMENTS

33

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

Bus

Operation

Start

Command

Comments

Set Time-Out

Write to

Buffer

Data = E8H

Block Address

Write

Read

Issue Write Command

E8H, Block Address

No

XSR. 7 = Valid

Addr = X

Check XSR. 7

Read Extended

Status Register

Standby

1 = Write Buffer Available

0 = Write Buffer Not Available

Data = N = Word/Byte Count

N = 0 Corresponds to Count = 1

Addr = Block Address

Write

(Note 1, 2)

0

Write

Buffer Time-Out?

XSR.7 =

1

Write

(Note 3, 4)

Data = Write Buffer Data

Addr = Device Start Address

Write Word or Byte

Count, Block Address

Write

(Note 5, 6)

Data = Write Buffer Data

Addr = Device Address

Buffer Write

to Flash

Confirm

Data = D0H

Addr = X

Write Buffer Data,

Start Address

Write

Read

Status Register Data with the

Device Enabled, OE# Low

Updates SR

X = 0

Yes

Addr = X

Check SR.7

1 = WSM Ready

0 = WSM Busy

Check

X = N?

Standby

No

Yes

1. Byte or word count values on DQ₀-DQ ₇are loaded into the

count register. Count ranges on this device for byte mode are

= 00H to 1FH and for word mode are N = 0000H to 000FH.

2. The device now outputs the status register when read (XSR is

no longer available).

N

Abort Buffer Write

Command?

Yes

Write to Another

Block Address

3. Write Buffer contents will be programmed at the device start

address or destination flash address.

4. Align the start address on a Write Buffer boundary for

maximum programming performance (i.e., A₄- A ₀of the start

address = 0).

Yes

No

Write Next Buffer Data,

Device Address

Buffer Write to

Flash Aborted

5. The device aborts the Write to Buffer command if the current

address is outside of the original block address.

6. The status register indicates an "improper command

sequence" if the Write to Buffer command is aborted. Follow this

with a Clear Status Register command.

X = X + 1

Buffer Write to Flash

Confirm D0H

Full status check can be done after all erase and write sequences

complete. Write FFH after the last operation to reset the device to

read array mode.

Another Buffer

Write?

Issue Read

Status Command

No

Read Status Register

0

SR.7 =

1

Full Status

Check if Desired

Buffer Write to

Flash Complete

0606_07

Figure 7. Write to Buffer Flowchart

34

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

Start

Bus

Operation

Command

Comments

Setup Byte/

Data = 40H

Write 40H,

Address

Write

Word Program Addr = Location to Be Programmed

Byte/Word

Program

Data = Data to Be Programmed

Addr = Location to Be Programmed

Write

Read

Write Data and

Address

Status Register Data

Check SR.7

1 = WSM Ready

0 = WSM Busy

Read Status

Register

Standby

Repeat for subsequent programming operations.

0

SR.7 =

1

SR full status check can be done after each program operation, or

after a sequence of programming operations.

Write FFH after the last program operation to place device in read

array mode.

Full Status

Check if Desired

Byte/Word

Program Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Command

Comments

Check SR.3

1 = Programming to Voltage Error

Detect

Read Status

Register Data

(See Above)

Standby

1

Check SR.1

SR.3 =

SR.1 =

SR.4 =

Voltage Range Error

1 = Device Protect Detect

RP# = V_IH, Block Lock-Bit Is Set

Only required for systems

implemeting lock-bit configuration.

Standby

0

1

Check SR.4

1 = Programming Error

Device Protect Error

Programming Error

SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register

command in cases where multiple locations are programmed before

full status is checked.

If an error is detected, clear the status register before attempting retry

or other error recovery.

Byte/Word

Program

Successful

0606_08

Figure 8. Byte/Word Program Flowchart

35

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

Bus

Start

Command

Comments

Operation

Data = 28H or 20H

Addr = Block Address

Write

Read

Erase Block

Device Supports

Queuing

XSR.7 = Valid

Addr = X

Check XSR.7

Yes

Standby

Write

1 = Erase Queue Avail.

0 = No Erase Queue Avail.

Set Time-Out

Data = 28H

Addr = Block Address

Erase Block

Issue Block Queue Erase

Command 28H, Block

Address

SR.7 = Valid; SR.6 - 0 = X

With the device enabled,

OE# low updates SR

Addr = X

Read

No

Read Extended Status

Register

Check XSR.7

Standby

1 = Erase Queue Avail.

0 = No Erase Queue Avail.

Is Queue

Available?

XSR.7=

Erase

Confirm

Data = D0H

Addr = X

No

Erase Block

Time-Out?

0=No

Write (Note 1)

Status register data

With the device enabled,

OE# low updates SR

Addr = X

1=Yes

Read

Another

Block

Erase?

Check SR.7

1 = WSM Ready

0 = WSM Busy

Standby

Yes

1. The Erase Confirm byte must follow Erase Setup when

the Erase Queue status (XSR.7) = 0.

Yes

Issue Erase Command 28H

Block Address

1=No

Full status check can be done after all erase and write

sequences complete. Write FFH after the last operation to

reset the device to read array mode.

Read Extended

Status Register

No

Issue Single Block Erase

Command 20H, Block

Address

Is Queue Full?

XSR.7=

0=Yes

Write Confirm D0H

Block Address

Write Confirm D0H

Block Address

Another

Block

Erase?

Issue Read

Status Command

No

Read

Status Register

No

Suspend

Erase Loop

0

Yes

SR.7 =

1

Suspend Erase

Full Status

Check if Desired

Erase Flash

Block(s) Complete

0606_09

Figure 9. Block Erase Flowchart

36

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

Bus

Operation

Start

Command

Comments

Data = B0H

Write

Erase Suspend

Addr = X

Write B0H

Status Register Data

Addr = X

Read

Check SR.7

Standby

1 - WSM Ready

0 = WSM Busy

Read Status Register

Check SR.6

Standby

Write

1 = Block Erase Suspended

0 = Block Erase Completed

0

SR.7 =

1

Data = D0H

Addr = X

Erase Resume

SR.6 =

Block Erase Completed

1

Read

Program

Read or Program?

Read Array

Data

Program

Loop

No

Done?

Yes

Write D0H

Write FFH

Block Erase Resumed

Read Array Data

0606_10

Figure 10. Block Erase Suspend/Resume Flowchart

37

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

Start

Bus

Operation

Command

Comments

Data = 60H

Addr =Block Address (Block),

Device Address (Master)

Set Block/Master

Lock-Bit Setup

Write 60H,

Block/Device Address

Write

Data = 01H (Block)

Set Block or Master

Lock-Bit Confirm

F1H (Master)

Addr = Block Address (Block),

Device Address (Master)

Write 01H/F1H,

Block/Device Address

Write

Read

Status Register Data

Read Status Register

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

0

SR.7 =

1

Repeat for subsequent lock-bit operations.

Full status check can be done after each lock-bit set operation or after

a sequence of lock-bit set operations

Full Status

Check if Desired

Write FFH after the last lock-bit set operation to place device in read

array mode.

Set Lock-Bit Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Command

Comments

Check SR.3

Read Status Register

Data (See Above)

Standby

1 = Programming Voltage Error

Detect

1

SR.3 =

Voltage Range Error

Check SR.1

1 = Device Protect RP# = V

IH

Standby

(Set Master Lock-Bit Operation)

RP# = V_IH, Master Lock-Bit Is Set

(set Block Lock-Bit Operation)

0

SR. 1 =

0

1

Device Protect Error

Check SR.4, 5

Both 1 = Command Sequence

Error

Standby

Command Sequence

Error

Check SR.4

1 = Set Lock-Bit Error

SR.4,5 =

0

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status

Register command, in cases where multiple lock-bits are set before full

status is checked.

SR.4 =

0

Set Lock-Bit Error

If an error is detected, clear the status register before attempting retry

or other error recovery.

Set Lock-Bit

Successful

0606_11

Figure 11. Set Block Lock-Bit Flowchart

38

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

Start

Bus

Operation

Command

Comments

Data = 60H

Clear Block

Lock-Bits Setup

Write

Write 60H

Write D0H

Addr = X

Clear Block or

Lock-Bits Confirm Addr = X

Data = D0H

Write

Read

Status Register Data

Check SR.7

1 = WSM Ready

0 = WSM Busy

Read Status Register

Standby

Write FFH after the clear lock-bits operation to place device in read

array mode.

0

SR.7 =

1

Full Status

Check if Desired

Clear Block Lock-Bits

Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Command

Comments

Check SR.3

Read Status Register

Data (See Above)

Standby

1 = Programming Voltage Error

Detect

1

SR.3 =

Voltage Range Error

Check SR.1

Standby

1 = Device Protect RP# = V ,

IH

Master Lock-Bit Is Set

0

SR. 1 =

0

1

Check SR.4, 5

Both 1 = Command Sequence

Error

Standby

Device Protect Error

Check SR.5

1 = Clear Block Lock-Bits Error

Command Sequence

Error

SR.4,5 =

0

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status

Register command.

If an error is detected, clear the status register before attempting retry

or other error recovery.

Clear Block Lock-Bits

Error

SR.5 =

0

Clear Block Lock-Bits

Successful

0606_12

Figure 12. Clear Block Lock-Bit Flowchart

39

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

5.0 DESIGN CONSIDERATIONS 5.3 Power Supply Decoupling

5.1 Three-Line Output Control

E

Flash memory power switching characteristics

require careful device decoupling. System

designers are interested in three supply current

issues; standby current levels, active current levels

and transient peaks produced by falling and rising

edges of CE₀, CE₁, CE₂, and OE#. Transient

current magnitudes depend on the device outputs’

capacitive and inductive loading. Two-line control

and proper decoupling capacitor selection will

suppress transient voltage peaks. Since Intel

StrataFlash memory devices draw their power from

three V_CCpins (these devices do not include a V_PP

pin), it is recommended that systems without

separate power and ground planes attach a 0.1 µF

ceramic capacitor between each of the device’s

three V_CCpins (this includes V_CCQ) and ground.

These high-frequency, low-inductance capacitors

should be placed as close as possible to package

leads on each StrataFlash device. Each device

should have a 0.1 µF ceramic capacitor connected

between its V_CCand GND. These high-frequency,

low inductance capacitors should be placed as

close as possible to package leads. Additionally, for

every eight devices, a 4.7 µF electrolytic capacitor

should be placed between V_CCand GND at the

array’s power supply connection. The bulk capacitor

will overcome voltage slumps caused by PC board

trace inductance.

The device will often be used in large memory

arrays. Intel provides five control inputs (CE₀, CE₁,

CE₂, OE#, and RP#) to accommodate multiple

memory connections. This control provides for:

a. Lowest possible memory power dissipation.

b. Complete assurance that data bus

contention will not occur.

To use these control inputs efficiently, an address

decoder should enable the device (see Table 2,

Chip Enable Truth Table) while OE# should be

connected to all memory devices and the system’s

READ# control line. This assures that only selected

memory devices have active outputs while de-

selected memory devices are in standby mode.

RP# should be connected to the system

POWERGOOD signal to prevent unintended writes

during system power transitions. POWERGOOD

should also toggle during system reset.

5.2

STS and Block Erase, Program,

and Lock-Bit Configuration

Polling

5.4

V

, V

, RP# Transitions

STS is an open drain output that should be

connected to V_CCQby a pull-up resistor to provide a

hardware method of detecting block erase,

program, and lock-bit configuration completion. In

default mode, it transitions low after block erase,

program, or lock-bit configuration commands and

returns to High Z when the WSM has finished

executing the internal algorithm. For alternate

configurations of the STS pin, see the Configuration

command.

CC PEN

Block erase, program, and lock-bit configuration are

not guaranteed if V_PENor V_CCfalls outside of the

specified operating ranges, or RP# ≠ V_IHor V_HH. If

RP# transitions to V_ILduring block erase, program,

or lock-bit configuration, STS (in default mode) will

remain low for a maximum time of t_PLPH+ t_PHRH

until the reset operation is complete. Then, the

operation will abort and the device will enter

reset/power-down mode. The aborted operation

may leave data partially corrupted after

programming, or partially altered after an erase or

lock-bit configuration. Therefore, block erase and

lock-bit configuration commands must be repeated

after normal operation is restored. Device power-off

or RP# = V_ILclears the status register.

STS can be connected to an interrupt input of the

system CPU or controller. It is active at all times.

STS, in default mode, is also High Z when the

device is in block erase suspend (with programming

inactive) or in reset/power-down mode.

40

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

The CUI latches commands issued by system

software and is not altered by V_PEN, CE₀, CE₁, or

CE₂transitions, or WSM actions. Its state is read

array mode upon power-up, after exit from

reset/power-down mode, or after V_CCtransitions

below V_LKO. V_CCmust be kept at or above V_PEN

during V_CCtransitions.

A system designer must guard against spurious

writes for V_CCvoltages above V_LKOwhen V_PENis

active. Since WE# must be low and the device

enabled (see Table 2, Chip Enable Truth Table) for

a command write, driving WE# to V_IHor disabling

the device will inhibit writes. The CUI’s two-step

command sequence architecture provides added

protection against data alteration.

After block erase, program, or lock-bit configuration,

even after V_PENtransitions down to V_PENLK, the CUI

must be placed in read array mode via the Read

Array command if subsequent access to the

memory array is desired. V_PENmust be kept at or

below V_CCduring V_PENtransitions.

Keeping V_PENbelow V_PENLKprevents inadvertent

data alteration. In-system block lock and unlock

capability protects the device against inadvertent

programming. The device is disabled while RP# =

V

_ILregardless of its control inputs.

5.5

Power-Up/Down Protection

5.6

Power Dissipation

The device is designed to offer protection against

accidental block erasure, programming, or lock-bit

configuration during power transitions. Internal

circuitry resets the CUI to read array mode at

power-up.

When designing portable systems, designers must

consider battery power consumption not only during

device operation, but also for data retention during

system idle time. Flash memory’s nonvolatility

increases usable battery life because data is

retained when system power is removed.

41

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

6.0 ELECTRICAL SPECIFICATIONS

NOTICE: This datasheet contains information on products

in the sampling and initial production phases of

development. The specifications are subject to change

without notice. Verify with your local Intel Sales office that

you have the latest datasheet before finalizing a design.

6.1

Absolute Maximum Ratings*

Commercial Operating Temperature

During Read, Block Erase, Program,

*WARNING: Stressing the device beyond the “Absolute

Maximum Ratings” may cause permanent damage. These

are stress ratings only. Operation beyond the “Operating

Conditions” is not recommended and extended exposure

beyond the “Operating Conditions” may affect device

reliability.

and Lock-Bit Configuration .....0 °C to +70 °C⁽¹⁾

Temperature under Bias........ –10 °C to +80 °C

Storage Temperature................. –65 °C to +125 °C

Voltage On Any Pin (except RP#)

............................................ –2.0 V to +7.0 V⁽²⁾

RP# Voltage with Respect to

GND during Lock-Bit

Configuration Operations–2.0 V to +14.0 V^(2,3,4)

Output Short Circuit Current.....................100 mA⁽⁵⁾

NOTES:

1. Operating temperature is for commercial product defined by this specification.

2. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and –0.2 V on V_CCand

V

_PENpins. During transitions, this level may undershoot to–2.0 V for periods <20 ns. Maximum DC voltage on input/output

pins, V_CC, and V_PENis V_CC+0.5 V which, during transitions, may overshoot to V_CC+2.0 V for periods <20 ns.

3. Maximum DC voltage on RP# may overshoot to +14.0 V for periods <20 ns.

4. RP# voltage is normally at V_ILor V_IH. Connection to supply of V_HHis allowed for a maximum cumulative period of 80 hours.

5. Output shorted for no more than one second. No more than one output shorted at a time.

6.2

Operating Conditions

Temperature and V_CCOperating Conditions

Symbol

Parameter

Notes Min

Max

+70

Unit

°C

V

Test Condition

T_A

Operating Temperature

0

Ambient Temperature

V_CC

V_CC1Supply Voltage (5 V ± 10%)

V_CCQ1Supply Voltage (5 V ± 10%)

V_CCQ2Supply Voltage (2. 7V−3.6 V)

4.50

2.70

5.50

3.60

V_CCQ1

V_CCQ2

V

(1)

6.3

Capacitance

T_A= +25 °C, f = 1 MHz

Symbol

Parameter

Typ

6

Max

Unit

Condition

V_IN= 0.0 V

V_OUT= 0.0 V

C_IN

Input Capacitance

Output Capacitance

8

pF

C_OUT

NOTE:

8

12

1. Sampled, not 100% tested.

42

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

6.4

DC Characteristics

Sym

Parameter

Notes Typ

Max

Unit

Test Conditions

I_LI

Input and V_PENLoad

Current

1

±1

µA V_CC= V_CCMax

V_IN= V_CCor GND

I_LO

Output Leakage

Current

1

±10

150

900

650

400

µA V_CC= V_CCMax

V_IN= V_CCor GND

I_CCS

V_CCStandby Current

1,3,5

80

µA CMOS Inputs, V_CC= V_CCMax,

CE₀= CE₁= CE₂= RP# = V_CCQ1± 0.2 V

450

325

210

µA CMOS Inputs, RP# = V_CC= V_CCMax,

CE₀= CE₁= CE₂= V_CCQ2Min

µA CMOS Inputs, RP# = V_CC= V_CCMax,

CE₂= GND, CE₀= CE₁= V_CCQ2Min

µA CMOS Inputs, RP# = V_CC= V_CCMax,

CE₁= CE₂= GND, CE₀= V_CCQ2Min or

CE₀= CE₂= GND, CE₁= V_CCQ2Min

mA TTL Inputs, V_CC= V_CCMax,

0.71

80

2

CE₀= CE₁= CE₂= RP# = V_IH

I_CCD

I_CCR

V_CCPower-Down

Current

125

55

µA RP# = GND ± 0.2V

I_OUT(STS) = 0 mA

V_CCRead Current

1,5,6

35

mA CMOS Inputs, V_CC= V_CCQ=V_CCMax

Device is enabled (see Table 2, Chip Enable

Truth Table)

f = 5 MHz

I_OUT= 0 mA

45

65

mA TTL Inputs ,V_CC= V_CCMax

Device is enabled (see Table 2, Chip Enable

Truth Table)

f = 5 MHz

I_OUT= 0 mA

I_CCWV_CCProgram or Set

Lock-Bit Current

1,6,7

35

40

35

60

70

mA CMOS Inputs, V_PEN= V_CC

mA TTL Inputs, V_PEN= V_CC

mA CMOS Inputs, V_PEN= V_CC

I_CCE

V_CCBlock Erase or

Clear Block Lock-Bits

Current

40

80

10

mA TTL Inputs, V_PEN= V_CC

I_CCESV_CCBlock Erase

Suspend Current

1,2

mA Device is disabled (see Table 2, Chip Enable

Truth Table)

43

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

6.4 DC Characteristics (Continued)

E

Sym

Parameter

Input Low Voltage

Input High Voltage

Notes Min

Max

Unit

V

Test Conditions

V_IL

7

–0.5

2.0

0.8

V_IH

7

V_CC

+ 0.5

0.45

V

V_OL

Output Low Voltage

3,7

V

V_CCQ= V_CCQ1Min

I_OL= 5.8 mA

0.4

V_CCQ= V_CCQ2Min

I_OL= 2 mA

3,7

2.4

V_OH1Output High Voltage

(TTL)

V

_CCQ= V_CCQ1Min or V_CCQ= V_CCQ2Min

I_OH= –2.5 mA (V_CCQ1

–2 mA (V_CCQ2

_CCQ= V_CCQ1Min or V_CCQ= V_CCQ2Min

)

0.85

V

V_OH2Output High Voltage

(CMOS)

V

V_CCQ

I_OH= –2.5 mA

V_CCQ

–0.4

V_CCQ= V_CCQ1Min or V_CCQ= V_CCQ2Min

I_OH= –100 µA

4,7,11 3.6

V_PENLKV_PENLockout during

Normal Operations

4,11

V_PENHV_PENduring Block

Erase, Program, or

4.5

5.5

Lock-Bit Operations

8

3.25

11.4

V

V_LKOV_CCLockout Voltage

9,10

12.6

Set master lock-bit

Override lock-bit

V_HH

RP# Unlock Voltage

NOTES:

1.

All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds).

Contact Intel’s Application Support Hotline or your local sales office for information about typical specifications.

2.

I_CCESis specified with the device de-selected. If the device is read or written while in erase suspend mode, the device’s

current draw is I_CCRor I_CCW

.

3.

4.

Includes STS.

Block erases, programming, and lock-bit configurations are inhibited when V_PEN≤ V_PENLK, and not guaranteed in the

range between V_PENLK(max) and V_PENH(min), and above V_PENH(max).

5.

6.

7.

8.

CMOS inputs are either V_CC± 0.2 V or GND ± 0.2 V. TTL inputs are either V_ILor V_IH

Add 5 mA for V_CCQ= V_CCQ2min.

.

Sampled, not 100% tested.

Block erases, programming, and lock-bit configurations are inhibited when V_CC< V_LKO, and not guaranteed in the range

between V_LKO(max) and V_CC(min), and above V_CC(max).

9.

Master lock-bit set operations are inhibited when RP# = V . Block lock-bit configuration operations are inhibited when the

IH

master lock-bit is set and RP# = V_IH. Block erases and programming are inhibited when the corresponding block-lock bit

is set and RP# = V_IH. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be

attempted with V_IH< RP# < V_HH

.

10. RP# connection to a V_HHsupply is allowed for a maximum cumulative period of 80 hours.

11. Tie V_PENto V_CC(4.5 V–5.5 V).

44

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

2.4

2.0

0.8

2.0

Output

0.8

Input

Test Points

0.45

AC test inputs are driven at V_OH(2.4 V_TTL) for a Logic "1" and V_OL(0.45 V_TTL) for a Logic "0." Input timing begins at V

IH

(2.0 V_TTL) and V_IL(0.8 V_TTL). Output timing ends at V_IHand V_IL. Input rise and fall times (10% to 90%) <10 ns.

Figure 13. Transient Input/Output Reference Waveform for VCCQ = 5.0 V ± 10%

(Standard Testing Configuration)

2.7

Input

1.35

Test Points

1.35 Output

0.0

AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35 V

(50% of V_CCQ). Input rise and fall times (10% to 90%) <10 ns.

Figure 14. Transient Input/Output Reference Waveform for VCCQ = 2.7 V−3.6 V

Test Configuration Capacitance Loading Value

1.3V

Test Configuration

V_CCQ= 5.0V ± 10%

V_CCQ= 2.7V−3.6V

C_L(pF)

100

1N914

50

R_L= 3.3 k

Ω

Device

Under Test

Out

C_L

NOTE:

C_LIncludes Jig Capacitance

Figure 15. Transient Equivalent Testing

Load Circuit

45

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

Min

120

150

(1)

6.5

AC Characteristics— Read-Only Operations

Versions

5 V ± 10% V_CCQ

2.7 V—3.6V V_CCQ

Notes

–120/–150⁽⁴⁾

(All units in ns unless otherwise noted)

–L120/–L150⁽⁴⁾

#

Sym

Parameter

Min

120

150

Max

R1 t_AVAVRead/Write Cycle Time

R2 t_AVQVAddress to Output Delay

R3 t_ELQVCEX to Output Delay

32 Mbit

64 Mbit

32 Mbit

120

150

120

150

50

120

150

120

150

50

64 Mbit

32 Mbit

64 Mbit

2

R4 t_GLQVOE# to Output Delay

R5 t_PHQVRP# High to Output Delay

32 Mbit

64 Mbit

180

210

180

210

R6 t_ELQXCEX to Output in Low Z

R7 t_GLQXOE# to Output in Low Z

R8 t_EHQZCEX High to Output in High Z

R9 t_GHQZOE# High to Output in High Z

3

0

55

15

55

15

R10 t_OH

Output Hold from Address, CEX, or OE#

Change, Whichever Occurs First

0

R11 t_ELFLCEX Low to BYTE# High or Low

t_ELFH

3

10

R12 t_FLQVBYTE# to Output Delay

t_FHQV

1000

R13 t_FLQZBYTE# to Output in High Z

3

NOTES:

CE_Xlow is defined as the first edge of CE , CE , or CE that enables the device. CE_Xhigh is defined at the first edge of CE ,

0

1

2

0

CE , or CE that disables the device (see Table 2, Chip Enable Truth Table).

1

2

1. See Figure 16, AC Waveform for Read Operations for the maximum allowable input slew rate.

2. OE# may be delayed up to t_ELQV-t_GLQVafter the first edge of CE , CE , or CE that enables the device (see Table 2, Chip

0

1

2

Enable Truth Table) without impact on t_ELQV

.

3. Sampled, not 100% tested.

4. See Figures 13–15, Transient Input/Output Reference Waveform for V_CCQ= 5.0 V ±10%, Transient Input/Output

Reference Waveform for V_CCQ= 2.7 V –3.6 V, and Transient Equivalent Testing Load Circuit for testing characteristics.

46

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

0606_16

NOTES:

CE_Xlow is defined as the first edge of CE , CE , or CE that enables the device. CE_Xhigh is defined at the first edge of CE ,

0

1

2

0

CE , or CE that disables the device (see Table 2, Chip Enable Truth Table).

1

2

Figure 16. AC Waveform for Read Operations

47

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

Unit

(1,2)

6.6

AC Characteristics— Write Operations

Valid for All

Speeds

Versions

#

Sym

t_{PHWL ( PHEL)}

Parameter

Notes

Min

Max

W1

t

RP# High Recovery to WE# (CE_X) Going

Low

3

1

µs

W2

W3

W4

W5

W6

W7

W8

W9

t_ELWL(t_WLEL

t_WP

t_{DVWH ( DVEH)}

t_{AVWH ( AVEH)}

t_{WHEH ( EHWH)}

t_{WHDX ( EHDX)}

t_{WHAX ( EHAX)}

t_WPH

)

CE_X(WE#) Low to WE# (CE_X) Going Low

Write Pulse Width

8

4

0

70

50

10

0

ns

t

Data Setup to WE# (CE_X) Going High

Address Setup to WE# (CE_X) Going High

CE_X(WE#) Hold from WE# (CE_X) High

Data Hold from WE# (CE_X) High

Address Hold from WE# (CE_X) High

Write Pulse Width High

t

0

9

30

0

W10 t_{PHHWH ( PHHEH)}

W11 t_{VPWH ( VPEH)}

W12 t_{WHGL ( EHGL)}

W13 t_{WHRL ( EHRL)}

t

RP# V_HHSetup to WE# (CE_X) Going High

V_PENSetup to WE# (CE_X) Going High

Write Recovery before Read

3

t

0

t

6

35

t

WE# (CE_X) High to STS Going Low

5

90

W14 t_QVPH

RP# V_HHHold from Valid SRD, STS Going

High

3,5,7

0

W15 t_QVVL

V_PENHold from Valid SRD, STS Going High

3,5,7

ns

NOTES:

CE_Xlow is defined as the first edge of CE , CE , or CE that enables the device. CE_Xhigh is defined at the first edge of CE ,

0

1

2

0

CE , or CE that disables the device (see Table 2, Chip Enable Truth Table).

1

2

1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during

read-only operations. Refer to AC Characteristics–Read-Only Operations.

2. A write operation can be initiated and terminated with either CE_Xor WE#.

3. Sampled, not 100% tested.

4. Refer to Table 4 for valid A_INand D_INfor block erase, program, or lock-bit configuration.

5. STS timings are based on STS configured in its RY/BY# default mode.

6. For array access, t_AVQVis required in addition to t_WHGLfor any accesses after a write.

7.

V

_PENshould be held at V_PENH(and if necessary RP# should be held at V_HH) until determination of block erase, program, or

lock-bit configuration success (SR.1/3/4/5 = 0).

8. Write pulse width (t_WP) is defined from CE_Xor WE# going low (whichever goes low first) to CE_Xor WE# going high

(whichever goes high first). Hence, t_WP= t_WLWH= t_ELEH= t_WLEH= t_ELWH. If CE_Xis driven low 10 ns before WE# going low,

WE# pulse width requirement decreases to t_WP- 10 ns.

9. Write pulse width high (t_WPH) is defined from CE_Xor WE# going high (whichever goes high first) to CE_Xor WE# going low

(whichever goes low first). Hence, t_WPH= t_WHWL= t_EHEL= t_WHEL= t_EHWL

.

48

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

0606_17

NOTES:

CE_Xlow is defined as the first edge of CE , CE , or CE that enables the device. CE_Xhigh is defined at the first edge of CE ,

0

1

2

0

CE , or CE that disables the device (see Table 2, Chip Enable Truth Table).

1

2

STS is shown in its default mode (RY/BY#).

1. power-up and standby.

V

CC

2. Write block erase, write buffer, or program setup.

3. Write block erase or write buffer confirm, or valid address and data.

4. Automated erase delay.

5. Read status register or query data.

6. Write Read Array command.

Figure 17. AC Waveform for Write Operations

49

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

V

IH

STS (R)

V_IL

P2

V_IH

RP# (P)

V_IL

P1

0606_18

NOTES:

STS is shown in its default mode (RY/BY#).

Figure 18. AC Waveform for Reset Operation

Reset Specifications⁽¹⁾

#

Sym.

Parameter

Notes Min Max Unit

P1

t_PLPH

RP# Pulse Low Time

(If RP# is tied to V_CC, this specification is not applicable)

2

35

µs

P2

t_PHRHRP# High to Reset during Block Erase, Program, or

Lock-Bit Configuration

3

100

ns

NOTES:

1. These specifications are valid for all product versions (packages and speeds).

2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum

required RP# Pulse Low Time is 100 ns.

3. A reset time, t_PHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.

50

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

(3,4)

6.7

Block Erase, Program, and Lock-Bit Configuration Performance

#

Sym

Parameter

Notes

Min

Typ⁽¹⁾

Max

Unit

W16 t_WHQV1

t_EHQV1

Write Buffer Byte Program Time

2,5

TBD

6

TBD

µs

W16 t_WHQV2

t_EHQV2

Write Buffer Word Program Time

2,5

2

TBD

12

120

0.8

1.0

12

TBD

35

µs

W16 t_WHQV3

t_EHQV3

Byte Program Time (Using

Word/Byte Program Command)

Block Program Time (Using Write

to Buffer Command)

2

sec

µs

W16 t_WHQV4

t_EHQV4

Block Erase Time

2

W16 t_WHQV5

t_EHQV5

Set Lock-Bit Time

2

W16 t_WHQV6

t_EHQV6

Clear Block Lock-Bits Time

2

1.5

25

sec

µs

W16 t_WHRH

t_EHRH

Erase Suspend Latency Time to

Read

NOTES:

1. Typical values measured at T_A= +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to

change based on device characterization.

2. Excludes system-level overhead.

3. These performance numbers are valid for all speedversions.

4. Sampled but not 100% tested.

5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.

51

ADVANCE INFORMATION

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

7.0 ORDERING INFORMATION

G 2 8 F 6 4 0 J 5 - 1 5 0

Package

Access Speed (ns)

(120, 150)

G = 56-Ball µBGA* CSP

E = 56-Lead TSOP

DA = 56-Lead SSOP

Product line designator

for all Intel Flash products

Voltage (V_CC/V_PEN

5 = 5V/5V

)

Device Density

640 = x8/x16 (64 Mbit)

320 = x8/x16 (32 Mbit)

Product Family

J = Intel StrataFlash^TMmemory,

2 bits-per-cell

Valid Operational

Conditions

Order Code by Density

5 V V_CC

32 Mbit

64 Mbit

2.7 V – 3.6

V V_CCQ

5 V ± 10%

V_CCQ

DA28F320J5-120

G28F320J5-120

E28F320J5-120

DA28F640J5-150

G28F640J5-150

Yes

52

ADVANCE INFORMATION

E

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

(1,2)

8.0 ADDITIONAL INFORMATION

Order Number

Document

210830

292123

292203

292204

292205

1997 Flash Memory Databook

AP-374 Flash Memory Write Protection Techniques

AP-644 Intel StrataFlash™ Memory Migration Guide

AP-646 Common Flash Interface (CFI) and Command Sets

AP-647 Intel StrataFlash™ Memory Design Guide

NOTE:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should

contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools.

53

ADVANCE INFORMATION


型号：	DA28F320J5-120
厂家：	INTEL
描述：	StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT 的StrataFlash存储器技术32和64 MBIT 存储
文件：	总53页 (文件大小：638K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DA28F320J5-120 [INTEL]

相关型号：

DA28F320J5A-120

DA28F320S5-110

DA28F320S5-90

DA28F640J5-150

DA28F640J5A-150

DA2B010V11

DA2DF62

DA2J001

DA2J101

DA2J10100L

DA2J104

DA2J10400L