DA28F160S5-100_技术文档

ADVANCE INFORMATION

E

WORD-WIDE

FlashFile™ MEMORY FAMILY

28F160S5, 28F320S5

Includes Extended Temperature Specifications

Two 32-Byte Write Buffers

Cross-Compatible Command Support

Intel Standard Command Set

2 µs per Byte Effective

Programming Time

Common Flash Interface (CFI)

Scaleable Command Set (SCS)

Operating Voltage

5V V_CC

100,000 Block Erase Cycles

5V V_PP

Enhanced Data Protection Features

Absolute Protection with V_PP= GND

Flexible Block Locking

70 ns Read Access Time (16 Mbit)

90 ns Read Access Time (32 Mbit)

Block Erase/Program Lockout

during Power Transitions

High-Density Symmetrically-Blocked

Architecture

32 64-Kbyte Erase Blocks (16 Mbit)

64 64-Kbyte Erase Blocks (32 Mbit)

Configurable x8 or x16 I/O

Automation Suspend Options

Program Suspend to Read

System Performance Enhancements

STS Status Output

Block Erase Suspend to Program

Block Erase Suspend to Read

Industry-Standard Packaging

SSOP and TSOP (16 Mbit)

SSOP (32 Mbit)

ETOX™ V Nonvolatile Flash

Technology

Intel’s Word-Wide FlashFile™ memory family provides high-density, low-cost, nonvolatile, read/write storage

solutions for a wide range of applications. The word-wide memories are available at various densities in the

same package type. Their symmetrically-blocked architecture, voltage, and extended cycling provide highly

flexible components suitable for resident flash arrays, SIMMs, and memory cards. Enhanced suspend

capabilities provide an ideal solution for code or data storage applications. For secure code storage

applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM,

the word-wide memories offer three levels of protection: absolute protection with V_PPat GND, selective block

locking, and program/erase lockout during power transitions. These alternatives give designers ultimate

control of their code security needs.

This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. It comes in the

industry-standard 56-lead SSOP. In addition, the 16-Mb device is available in the industry-standard 56-lead

TSOP package.

June 1997

Order Number: 290609-001

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of

Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to

sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or

infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life

saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

The 28F160S5 and 28F320S5 may contain design defects or errors known as errata. Current characterized errata are available

on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation

P.O. Box 7641

Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

or visit Intel’s website at http:\\www.intel.com

CG-041493

*Third-party brands and names are the property of their respective owners.

E

28F160S5, 28F320S5

CONTENTS

PAGE

4.8 Write to Buffer Command...........................26

4.9 Byte/Word Write Command........................26

4.10 STS Configuration Command...................27

4.11 Block Erase Suspend Command..............27

4.12 Program Suspend Command ...................27

4.13 Set Block Lock-Bit Commands .................28

4.14 Clear Block Lock-Bits Command..............28

1.0 INTRODUCTION .............................................5

1.1 New Features...............................................5

1.2 Product Overview.........................................5

1.3 Pinout and Pin Description...........................6

2.0 PRINCIPLES OF OPERATION .......................9

2.1 Data Protection ..........................................10

3.0 BUS OPERATION.........................................11

3.1 Read ..........................................................11

3.2 Output Disable ...........................................11

3.3 Standby......................................................11

3.4 Deep Power-Down.....................................11

3.5 Read Query Operation ...............................11

3.6 Read Identifier Codes Operation................12

3.7 Write ..........................................................12

5.0 DESIGN CONSIDERATIONS........................38

5.1 Three-Line Output Control..........................38

5.2. STS and WSM Polling...............................38

5.3 Power Supply Decoupling ..........................38

5.4 V_PPTrace on Printed Circuit Boards...........38

5.5 V_CC, V_PP, RP# Transitions..........................38

5.6 Power-Up/Down Protection ........................38

6.0 ELECTRICAL SPECIFICATIONS..................39

6.1 Absolute Maximum Ratings........................39

6.2 Operating Conditions..................................39

6.2.1 Capacitance.........................................40

6.2.2 AC Input/Output Test Conditions .........40

6.2.3 DC Characteristics...............................41

4.0 COMMAND DEFINITIONS ............................12

4.1 Read Array Command................................16

4.2 Read Query Mode Command.....................16

4.2.1 Query Structure Output .......................16

4.2.2 Query Structure Overview ...................18

4.2.3 Block Status Register ..........................19

4.2.4 CFI Query Identification String.............20

4.2.5 System Interface Information..............21

4.2.6 Device Geometry Definition.................22

4.2.7 Intel-Specific Extended Query Table ...23

4.3 Read Identifier Codes Command ...............24

4.4 Read Status Register Command................24

4.5 Clear Status Register Command................25

4.6 Block Erase Command ..............................25

4.7 Full Chip Erase Command .........................25

6.2.4 AC Characteristics - Read-Only

Operations..........................................43

6.2.5 AC Characteristics - Write Operations .45

6.2.6 Reset Operations.................................47

6.2.7 Erase, Program, and Lock-Bit

Configuration Performance.................48

APPENDIX A: Device Nomenclature and

Ordering Information ..................................49

APPENDIX B: Additional Information...............50

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ADVANCE INFORMATION

28F160S5, 28F320S5

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REVISION HISTORY

Number

Description

-001

Original version

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ADVANCE INFORMATION

E

28F160S5, 28F320S5

Specifically designed for 5V systems, the

28F160S5 and 28F320S5 support read and write

operation with V_CCequal to V_PP. Coupled with this

capability, high programming performance is

achieved through small, highly-optimized write

buffer operations. Additionally, the dedicated V_PP

1.0 INTRODUCTION

This datasheet contains Word-Wide FlashFile™

memory (28F160S5, 28F320S5) specifications.

Section

1 provides a flash memory overview.

Sections 2, 3, 4, and 5 describe the memory

organization and functionality. Section 6 covers

electrical specifications for extended temperature

product offerings.

pin gives complete data protection when V_PP

V_PPLK

≤

.

A Common Flash Interface (CFI) permits OEM-

specified software algorithms to be used for entire

families of devices. This allows device-independent,

JEDEC ID-independent, and forward- and

backward-compatible software support for the

specified flash device families. Flash vendors can

standardize their existing interfaces for long-term

compatibility.

1.1

New Features

The Word-Wide FlashFile memory family maintains

basic compatibility with Intel’s 28F016SA and

28F016SV. Key enhancements include:

•

Common Flash Interface (CFI) Support

Scaleable Command Set (SCS) Support

S5 Technology

Scaleable Command Set (SCS) allows a single,

simple software driver in all host systems to work

with all SCS-compliant flash memory devices,

independent of system-level packaging (e.g.,

memory card, SIMM, or direct-to-board placement).

Enhanced Suspend Capabilities

Additionally,

SCS

provides

the

highest

They share a compatible Status Register, basic

software commands, and pinout. These similarities

enable a clean migration from the 28F016SA or

28F016SV. When upgrading, it is important to note

the following differences:

system/device data transfer rates and minimizes

device and system-level implementation costs.

A Command User Interface (CUI) serves as the

interface between the system processor and

internal device operation.

A

valid command

sequence written to the CUI initiates device

automation. An internal Write State Machine (WSM)

automatically executes the algorithms and timings

necessary for block erase, program, and lock-bit

configuration operations.

•

Because of new feature and density options,

the devices have different device identifier

codes. This allows for software optimization.

•

New software commands.

To take advantage of the 5V technology on the

A block erase operation erases one of the device’s

64-Kbyte blocks typically within t_WHQV2/EHQV2

independent of other blocks. Each block can be

independently erased 100,000 times. Block erase

suspend allows system software to suspend block

erase to read or write data from any other block.

28F160S5

connection to V_CC

28F320S5 FlashFile memories do not support a

12V V_PPoption.

and

28F320S5,

allow

V_PP

.

The 28F160S5 and

1.2

Product Overview

Data is programmed in byte, word or page

increments. Program suspend mode enables the

system to read data or execute code from any other

flash memory array location.

The Word-Wide FlashFile memory family provides

density upgrades with pinout compatibility for the

16- and 32-Mbit densities. They are high-

performance memories arranged as 1 Mword and

2 Mwords of 16 bits or 2 Mbyte and 4 Mbyte of

8 bits. This data is grouped in thirty-two and sixty-

four 64-Kbyte blocks that can be erased, locked,

and unlocked in-system. Figure 1 shows the block

The device incorporates two Write Buffers of 32

bytes (16 words) to allow optimum-performance

data programming. This feature can improve

system program performance by up to eight times

over non-buffer programming.

diagram, and Figure

organization.

4 illustrates the memory

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ADVANCE INFORMATION

28F160S5, 28F320S5

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Individual block locking uses a combination of block

lock-bits to lock and unlock blocks. Block lock-bits

gate block erase, full chip erase, program and write

to buffer operations. Lock-bit configuration

operations (Set Block Lock-Bit and Clear Block

Lock-Bits commands) set and clear lock-bits.

The BYTE# pin allows either x8 or x16 read/writes

to the device. BYTE# at logic low selects 8-bit

mode with address A₀selecting between the low

byte and high byte. BYTE# at logic high enables

16-bit operation with address A₁becoming the

lowest order address. Address A₀is not used in 16-

bit mode.

The Status Register and the STS pin in RY/BY#

mode indicate whether or not the device is busy

When one of the CE_X# pins (CE₀#, CE₁#) and RP#

pins are at V_CC, the component enters a CMOS

standby mode. Driving RP# to GND enables a deep

power-down mode which significantly reduces

power consumption, provides write protection,

resets the device, and clears the Status Register. A

reset time (t_PHQV) is required from RP# switching

high until outputs are valid. Likewise, the device

has a wake time (t_PHEL) from RP#-high until writes

to the CUI are recognized.

executing an operation or ready for

a new

command. Polling the Status Register, system

software retrieves WSM feedback. STS in RY/BY#

mode gives an additional indicator of WSM activity

by providing a hardware status signal. Like the

Status Register, RY/BY#-low indicates that the

WSM is performing a block erase, program, or lock-

bit operation. RY/BY#-high indicates that the WSM

is ready for a new command, block erase is

suspended (and program is inactive), program is

suspended, or the device is in deep power-down

mode.

1.3

Pinout and Pin Description

The Automatic Power Savings (APS) feature

substantially reduces active current when the

device is in static mode (addresses not switching).

The 16-Mbit device is available in the 56-lead

TSOP and 56-lead SSOP. The 32- Mb device is

available in the 56-lead SSOP. The pinouts are

shown in Figures 2 and 3.

DQ₀- DQ₁₅

Output Buffer

Input Buffer

V_CC

Query

I/O Logic

BYTE#

CE#

WE#

OE#

RP#

WP#

Identifier

Register

Command

User

Interface

Status

Register

Multiplexer

Data

Comparator

Y-Decoder

X-Decoder

Y-Gating

STS

16-Mbit: A - A₂₀

32-Mbit: A₀⁰_-A₂₁

Input Buffer

Write State

Machine

V_PP

Program/Erase

Voltage Switch

16-Mbit: Thirty-two

32-Mbit: Sixty-four

64-Kbyte Blocks

Address

Latch

V_CC

GND

Address

Counter

0608_01

Figure 1. 28F320S5 and 28F160S5 Block Diagram

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ADVANCE INFORMATION

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28F160S5, 28F320S5

Table 1. Pin Descriptions

Name and Function

Sym

Type

A₀–A₂₁

INPUT ADDRESS INPUTS: Address inputs for read and write operations are internally

latched during a write cycle. A₀selects high or low byte when operating in x8 mode.

In x16 mode, A₀is not used; input buffer is off.

16-Mbit → A₀–A₂₀32-Mbit → A₀–A₂₁

DQ₀–

INPUT/ DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles;

DQ₁₅

OUTPUT outputs data during memory array, Status Register, query and identifier code read

cycles. Data pins float to high-impedance when the chip is deselected or outputs

are disabled. Data is internally latched during a write cycle.

CE₀#,

CE₁#

INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and

sense amplifiers. With CE₀# or CE₁# high, the device is deselected and power

consumption reduces to standby levels. Both CE₀# and CE₁# must be low to select

the device. Device selection occurs with the latter falling edge of CE₀# or CE₁#. The

first rising edge of CE₀# or CE₁# disables the device.

RP#

INPUT RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations

which provides data protection during system power transitions, puts the device in

deep power-down mode, and resets internal automation. RP#-high enables normal

operation. Exit from deep power-down sets the device to read array mode.

OE#

WE#

INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.

INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data

are latched on the rising edge of the WE# pulse.

STS

OPEN

STATUS: Indicates the status of the internal state machine. When configured in

DRAIN level mode (default), it acts as a RY/BY# pin. For this and alternate configurations

OUTPUT of the STATUS pin, see the Configuration command. Tie STS to V_CCwith a pull-up

resistor.

WP#

INPUT WRITE PROTECT: Master control for block locking. When V_IL, locked blocks

cannot be erased or programmed, and block lock-bits cannot be set or cleared.

BYTE#

V_PP

INPUT BYTE ENABLE: Configures x8 mode (low) or x16 mode (high).

SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:

Necessary voltage to perform block erase, program, and lock-bit configuration

operations. Do not float any power pins.

V_CC

GND

NC

SUPPLY DEVICE POWER SUPPLY: Do not float any power pins.

SUPPLY GROUND: Do not float any ground pins.

NO CONNECT: Lead is not internally connected; it may be driven or floated.

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ADVANCE INFORMATION

28F160S5, 28F320S5

E

28F016SA 28F160S3

28F160S3 28F016SA

28F160S5

28F016SV

28F160S5

28F016SV

3/5#

NC

CE₁#

NC

A₂₀

A₁₉

A₁₈

A₁₇

A₁₆

V_CC

A₁₅

A₁₄

A₁₃

A₁₂

CE₀#

V_PP

RP#

A₁₁

A₁₀

A₉

A₈

GND

A₇

A₆

A₅

A₄

A₃

A₂

A₁

WP#

WE#

OE#

STS

DQ₁₅

DQ₇

DQ₁₄

DQ₆

GND

DQ₁₃

DQ₅

DQ₁₂

DQ₄

V_CC

WP#

WE#

OE#

1

2

3

4

5

6

7

8

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

CE₁#

NC

A₂₀

A₁₉

A₁₈

A₁₇

A₁₆

V_CC

A₁₅

A₁₄

A₁₃

A₁₂

CE₀#

V_PP

RP#

A₁₁

A₁₀

A₉

A₈

GND

A₇

A₆

A₅

A₄

A₃

A₂

A₁

RY/BY#

DQ₁₅

DQ₇

DQ₁₄

DQ₆

GND

DQ₁₃

DQ₅

DQ₁₂

DQ₄

V_CC

9

56-LEAD TSOP

STANDARD PINOUT

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

14 mm x 20 mm

TOP VIEW

GND

DQ₁₁

DQ₃

DQ₁₀

DQ₂

V_CC

GND

DQ₁₁

DQ₃

DQ₁₀

DQ₂

V_CC

DQ₉

DQ₁

DQ₈

DQ₀

A₀

DQ₉

DQ₁

DQ₈

DQ₀

A₀

BYTE# BYTE#

NC

Highlights pinout changes.

Figure 2. 28F160S5 TSOP 56-Lead Pinout

0608_02

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ADVANCE INFORMATION

E

28F160S5, 28F320S5

Figure 3. 28F320S5 and 28F160S5 SSOP 56-Lead Pinout

After initial device power-up or return from deep

power-down mode (see Bus Operations), the

device defaults to read array mode. Manipulation

of external memory control pins allow array read,

standby, and output disable operations.

2.0 PRINCIPLES OF OPERATION

The Word-Wide FlashFile memories include an

on-chip Write State Machine (WSM) to manage

block erase, program, and lock-bit configuration

functions. It allows for: 100% TTL-level control

inputs, fixed power supplies during block erasure,

programming, lock-bit configuration, and minimal

processor overhead with RAM-like interface

timings.

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ADVANCE INFORMATION

28F160S5, 28F320S5

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Read Array, Status Register, query, and identifier

codes can be accessed through the CUI

independent of the V_PPvoltage. Proper

programming voltage on V_PPenables successful

via the Read Array command. Block erase

suspend allows system software to suspend a

block erase to read or write data from any other

block. Program suspend allows system software

to suspend a program to read data from any

other flash memory array location.

block

erasure,

program,

and

lock-bit

configuration. All functions associated with

altering memory contents—block erase, program,

lock-bit configuration, status, and identifier

codes—are accessed via the CUI and verified

through the Status Register.

2.1

Data Protection

Depending on the application, the system

designer may choose to make the V_PPpower

supply switchable or hardwired to V_PPH. The

device supports either design practice, and

encourages optimization of the processor-

memory interface.

Commands are written using standard micro-

processor write timings. The CUI contents serve

as input to the WSM that controls the block

erase, programming, and lock-bit configuration.

The internal algorithms are regulated by the

WSM, including pulse repetition, internal

verification, and margining of data. Addresses

and data are internally latched during write

cycles. Writing the appropriate command outputs

array data, identifier codes, or Status Register

data.

When V_PP≤ V_PPLK, memory contents cannot be

altered. When high voltage is applied to V_PP, the

two-step block erase, program, or lock-bit

configuration command sequences provide

protection from unwanted operations. All write

functions are disabled when V_CCvoltage is below

the write lockout voltage V_LKOor when RP# is at

V_IL. The device’s block locking capability

provides additional protection from inadvertent

code or data alteration.

Interface software that initiates and polls

progress of block erase, programming, and lock-

bit configuration can be stored in any block. This

code is copied to and executed from system

RAM during flash memory updates. After

successful completion, reads are again possible

0608_05

Figure 4. Memory Map

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ADVANCE INFORMATION

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28F160S5, 28F320S5

Deep Power-Down

3.0 BUS OPERATION

3.4

The local CPU reads and writes flash memory in-

system. All bus cycles to or from the flash

memory conform to standard microprocessor bus

cycles.

RP# at V_ILinitiates the deep power-down mode.

In read mode, RP#-low deselects the memory,

places output drivers in a high-impedance state,

and turns off all internal circuits. RP# must be

held low for time t_PLPH. Time t_PHQVis required

after return from power-down until initial memory

access outputs are valid. After this wake-up

interval, normal operation is restored. The CUI

resets to read array mode, and the Status

Register is set to 80H.

3.1

Read

Block information, query information, identifier

codes and Status Registers can be read

independent of the V_PPvoltage.

During block erase, programming, or lock-bit

configuration modes, RP#-low will abort the

operation. STS in RY/BY# mode remains low

until the reset operation is complete. Memory

contents being altered are no longer valid; the

The first task is to place the device into the

desired read mode by writing the appropriate

read-mode command (Read Array, Query, Read

Identifier Codes, or Read Status Register) to the

CUI. Upon initial device power-up or after exit

from deep power-down mode, the device

automatically resets to read array mode. Control

pins dictate the data flow in and out of the

component. CE₀#, CE₁# and OE# must be driven

active to obtain data at the outputs. CE₀# and

CE₁# are the device selection controls, and,

when both are active, enable the selected

memory device. OE# is the data output (DQ₀–

DQ₁₅) control: When active it drives the selected

memory data onto the I/O bus. WE# must be at

data may be partially

corrupted after

programming or partially altered after an erase or

lock-bit configuration. Time t_PHWLis required after

RP# goes to logic-high (V_IH) before another

command can be written.

It is important in any automated system to assert

RP# during system reset. When the system

comes out of reset, it expects to read from the

flash memory. Automated flash memories

provide status information when accessed during

V

_IHand RP# must be at V_IH. Figure 16 illustrates

block

erase,

programming,

or

lock-bit

a read cycle.

configuration modes. If a CPU reset occurs with

no flash memory reset, proper CPU initialization

may not occur because the flash memory may be

providing status information instead of array data.

Intel’s Flash memories allow proper CPU

initialization following a system reset through the

use of the RP# input. In this application, RP# is

controlled by the same RESET# signal that

resets the system CPU.

3.2

Output Disable

With OE# at a logic-high level (V_IH), the device

outputs are disabled. Output pins DQ₀–DQ₁₅are

placed in a high-impedance state.

3.3

Standby

3.5

Read Query Operation

CE₀# or CE₁# at a logic-high level (V_IH) places

the device in standby mode, substantially

reducing device power consumption. DQ₀–DQ₁₅

(or DQ₀– DQ₇in x8 mode) outputs are placed in

a high-impedance state independent of OE#. If

deselected during block erase, programming, or

lock-bit configuration, the device continues

functioning and consuming active power until the

operation completes.

The read query operation outputs block status,

Common Flash Interface (CFI) ID string, system

interface, device geometry, and Intel-specific

extended query information.

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28F160S5, 28F320S5

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3.6

Read Identifier Codes

Operation

3.7

Write

Writing commands to the CUI enables reading of

device data, query, identifier codes, inspection

and clearing of the Status Register. Additionally,

when V_PP= V_PPH, block erasure, programming,

and lock-bit configuration can also be performed.

The read-identifier codes operation outputs the

manufacturer code, device code, and block lock

configuration codes for each block configuration

(see Figure 5). Using the manufacturer and

device codes, the system software can

automatically match the device with its proper

algorithms. The block-lock configuration codes

identify each block’s lock-bit setting.

The Block Erase command requires appropriate

command data and an address within the block

to be erased. The Byte/Word Write command

requires the command and address of the

location to be written. Set Block Lock-Bit

commands require the command and address

within the block to be locked. The Clear Block

Lock-Bits command requires the command and

an address within the device.

The CUI does not occupy an addressable

memory location. It is written when WE#, CE₀#,

and CE₁# are active and OE# = V_IH. The address

and data needed to execute a command are

latched on the rising edge of WE# or CE_X#

(CE₀#, CE₁#), whichever goes high first.

Standard microprocessor write timings are used.

Figure 17 illustrates a write operation.

4.0 COMMAND DEFINITIONS

V_PPvoltage ≤ V_PPLKenables read operations

from the Status Register, identifier codes, or

memory blocks. Placing V_PPHon V_PPenables

successful block erase, programming, and lock-

bit configuration operations.

Device operations are selected by writing specific

commands into the CUI. Table 2 and Table 3

define these commands.

0608_06

Figure 5. Device Identifier Code Memory Map

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28F160S5, 28F320S5

Table 2. Bus Operations

Mode

Read

Notes RP# CE₀# CE₁# OE#⁽¹¹⁾WE#⁽¹¹⁾Address

V_PP

X

DQ⁽⁸⁾

D_OUT

STS⁽³⁾

1,2

V_IH

V_IL

V_IH

X

V_IL

V_IH

V_IL

V_IH

X

V_IL

V_IH

X

V_IH

X

Output Disable

Standby

X

High Z

X

Reset/Power-

Down Mode

10

4

V_IL

V_IH

X

High Z High Z⁽⁹⁾

D_OUTHigh Z⁽⁹⁾

Read Identifier

Codes

V_IL

V_IH

See

Figure 5

Read Query

5

V_IH

V_IL

V_IH

V_IL

See Table 6

X

Write

3,6,7

V_PPH

D_IN

X

NOTES:

1. Refer to Table 19. When V_PP≤ V_PPLK, memory contents can be read, but not altered.

2. X can be V_ILor V_IHfor control and address input pins and V_PPLKor V_PPHfor V_PP. See Table 19, for V_PPLKand V_PPH

voltages.

3. STS in RY/BY# mode (default) is V_OLwhen the WSM is executing internal block erase, programming, or lock-bit

configuration algorithms. It is V_OHwhen the WSM is not busy, in block erase suspend mode (with programming inactive),

program suspend mode, or deep power-down mode.

4. See Section 4.3 for read identifier code data.

5. See Section 4.2 for read query data.

6. Command writes involving block erase, write, or lock-bit configuration are reliably executed when V_PP= V_PPHand

V

_CC= V_CC1/2(see Section 6.2).

7. Refer to Table 3 for valid D_INduring a write operation.

8. DQ refers to DQ_0–7if BYTE# is low and DQ_0–15if BYTE# is high.

9. High Z will be V_OHwith an external pull-up resistor.

10. RP# at GND ± 0.2V ensures the lowest deep power-down current.

11. OE# = V_ILand WE# = V_ILconcurrently is an undefined state and should not be attempted.

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Table 3. Word-Wide FlashFile™ Memory Command Set Definitions⁽¹³⁾

Command

Scaleable Bus

or Basic Cycles

Command Req'd

Set⁽¹⁴⁾

Notes

First Bus Cycle

Second Bus Cycle

Oper⁽¹⁾Addr⁽²⁾Data^(3,4)Oper⁽¹⁾Addr⁽²⁾Data^(3,4)

Read Array

SCS/BCS

SCS

1

≥2

≥ 2

2

Write

X

FFH

90H

98H

70H

50H

E8H

Read Identifier Codes

Read Query

5

Read

IA

QA

X

ID

X

QD

Read Status Register

Clear Status Register

Write to Buffer

SCS/BCS

SCS

X

SRD

1

X

> 2 8, 9, 10 Write

BA

X

Write

BA

PA

N

Word/Byte Program

SCS/BCS

2

6,7

Write

40H

or

PD

10H

Block Erase

SCS/BCS

2

1

6,10

6

Write

X

20H

B0H

Write

BA

D0H

Block Erase, Word/Byte SCS/BCS

Program Suspend

Block Erase, Word/Byte SCS/BCS

Program Resume

1

6

Write

X

D0H

STS pin Configuration

Set Block Lock-Bit

Clear Block Lock-Bits

Full Chip Erase

SCS

2

Write

X

B8H

60H

30H

Write

X

BA

X

CC

11

12

10

01H

D0H

X

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NOTES:

1. Bus operations are defined in.Table 2.

2. X = Any valid address within the device.

BA = Address within the block being erased or locked.

IA = Identifier Code Address: see Table 12.

QA = Query database Address.

PA = Address of memory location to be programmed.

3. ID = Data read from Identifier Codes.

QD = Data read from Query database.

SRD = Data read from Status Register. See Table 15 for a description of the Status Register bits.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.

CC = Configuration Code. (See Table 14.)

4. The upper byte of the data bus (DQ_8–15) during command writes is a “Don’t Care” in x16 operation.

5. Following the Read Identifier Codes command, read operations access manufacturer, device, and block-lock codes. See

Section 4.3 for read identifier code data.

6. If a block is locked (i.e., the block’s lock-bit is set to 0), WP# must be at V_IHin order to perform block erase, program and

suspend operations. Attempts to issue a block erase, program and suspend operation to a locked block while WP# is V

IL

will fail.

7. Either 40H or 10H are recognized by the WSM as the byte/word program setup.

8. After the Write to Buffer command is issued, check the XSR to make sure a Write Buffer is available.

9. N = byte/word count argument such that the number of bytes/words to be written to the input buffer = N + 1. N = 0 is 1

byte/word length, and so on. Write to Buffer is a multi-cycle operation, where a byte/word count of N + 1 is written to the

correct memory address (WA) with the proper data (WD). The Confirm command (D0h) is expected after exactly N + 1 write

cycles; any other command at that point in the sequence aborts the buffered write. Writing a byte/word count outside the

buffer boundary causes unexpected results and should be avoided.

10. The write to buffer, block erase, or full chip erase operation does not begin until a Confirm command (D0h) is issued.

Confirm also reactivates suspended operations.

11. A block lock-bit can be set only while WP# is V .

IH

12. WP# must be at V_IHto clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits.

13. Commands other than those shown above are reserved for future use and should not be used.

14. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The

Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.

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4.1

Read Array Command

Query data are always presented on the lowest-

order data outputs (DQ_0-7) only. The numerical

offset value is the address relative to the maximum

bus width supported by the device. On this device,

the Query table device starting address is a 10h

word address, since the maximum bus width is x16.

Upon initial device power-up and after exit from

deep power-down mode, the device defaults to read

array mode. This operation is also initiated by

writing the Read Array command. The device

remains enabled for reads until another command

is written. Once the internal WSM has started block

erase, program, or lock-bit configuration, the device

will not recognize the Read Array command until

the WSM completes its operation—unless the WSM

is suspended via an Erase-Suspend or Program-

Suspend command. The Read Array command

functions independently of the V_PPvoltage.

For this word-wide (x16) device, the first two bytes

of the Query structure, “Q” and ”R” in ASCII, appear

on the low byte at word addresses 10h and 11h.

This CFI-compliant device outputs 00H data on

upper bytes. Thus, the device outputs ASCII “Q” in

the low byte (DQ_0-7) and 00h in the high byte

(DQ_8-15).

Since the device is x8/x16 capable, the x8 data is

still presented in word-relative (16-bit) addresses.

However, the “fill data” (00h) is not the same as

driven by the upper bytes in the x16 mode. As in

x16 mode, the byte address (A₀) is ignored for

Query output so that the “odd byte address” (A₀

high) repeats the “even byte address” data (A₀low).

Therefore, in x8 mode using byte addressing, the

device will output the sequence “Q”, “Q”, “R”, “R”,

“Y”, “Y”, and so on, beginning at byte-relative

address 20h (which is equivalent to word offset 10h

in x16 mode).

4.2

Read Query Mode Command

This section defines the data structure or

“database” returned by the Common Flash Interface

(CFI) Query command. System software should

parse this structure to gain critical information such

as block size, density, x8/x16, and electrical

specifications. Once this information has been

obtained, the software will know which command

sets to use to enable flash writes, block erases, and

otherwise control the flash component. The Query

is part of an overall specification for multiple

command set and control interface descriptions

called Common Flash Interface, or CFI.

At Query addresses containing two or more bytes

of information, the least significant data byte is

presented at the lower address, and the most

significant data byte is presented at the higher

address.

4.2.1

QUERY STRUCTURE OUTPUT

The Query “database” allows system software to

gain critical information for controlling the flash

component. This section describes the device’s

CFI-compliant interface that allows the host system

to access Query data.

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Table 4. Summary of Query Structure Output as a Function of Device and Mode

Device Type/Mode

Word Addressing

Location Query Data

Byte Addressing

Location

Query Data

Hex, ASCII

x16 device/

x16 mode

10h

11h

12h

0051h “Q”

0052h “R”

0059h “Y”

20h

21h

22h

51h

00h

52h

“Q”

null

“R”

x16 device/

x8 mode

N/A⁽¹⁾

N/A

20h

21h

22h

51h

52h

“Q”

“R”

NOTE:

1. The system must drive the lowest order addresses to access all the device’s array data when the device is configured in x8

mode. Therefore, word addressing where lower addresses are not toggled by the system is“Not Applicable” for x8-

configured devices.

Table 5. Example of Query Structure Output of a x16- and x8-Capable Device

Device

Address

Word Addressing:

Query Data

Byte

Address

Byte Addressing:

Query Data

A₁₆–A₁

D₁₅–D₀

A₇–A₀

D₇–D₀

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

...

0051h “Q”

0052h “R”

0059h “Y”

P_ID_LOPrVendor

P_ID_HIID #

20h

21h

22h

23h

24h

25h

26h

27h

28h

...

51h

52h

59h

“Q”

“R”

“Y”

P_LO

P_HI

PrVendor

TblAdr

P_ID_LOPrVendor

P_ID_LOID #

P_ID_HI

...

A_ID_LOAltVendor

A_ID_HIID #

...

“

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4.2.2

QUERY STRUCTURE OVERVIEW

The Query command causes the flash component

to display the Common Flash Interface (CFI) Query

structure or “database.” The structure sub-sections

and address locations are summarized in Table 8.

The following sections describe the Query structure

sub-sections in detail.

Table 6. Query Structure⁽¹⁾

Sub-Section Name

Offset

00h

Description

Manufacturer Code

01h

Device Code

(BA+2)h⁽²⁾

04-0Fh

10h

Block Status Register

Block-specific information

Reserved

Reserved for vendor-specific information

Command set ID and vendor data offset

Device timing & voltage information

Flash device layout

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

P⁽³⁾

Primary Intel-specific Extended Query

table

Vendor-defined additional information

specific to the Primary Vendor Algorithm

NOTES:

1. Refer to Section 4.2.1 and Table 4 for the detailed definition of offset address as a function of device word width and mode.

2. BA = The beginning location of a Block Address (i.e., 08000h is the beginning location of block 1 when the block size is

32 Kword).

3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.

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4.2.3

BLOCK STATUS REGISTER

Block Erase Status (BSR.1) allows system software

to determine the success of the last block erase

operation. BSR.1 can be used just after power-up to

verify that the V_CCsupply was not accidentally

removed during an erase operation. This bit is only

reset by issuing another erase operation to the

block. The Block Status Register is accessed from

word address 02h within each block.

The Block Status Register indicates whether an

erase operation completed successfully or whether

a given block is locked or can be accessed for flash

program/erase operations.

Table 7. Block Status Register

Description

Offset

Length

(bytes)

28F32/160S5

x16 Device/Mode

(BA+2)h⁽¹⁾

01h

Block Status Register

BA+2: 0000h or

0001h

BSR.0 = Block Lock Status

1 = Locked

BA+2 (bit 0): 0 or 1

0 = Unlocked

BSR.1 = Block Erase Status

BA+2 (bit 1): 0 or 1

1 = Last erase operation did not complete

successfully

0 = Last erase operation completed successfully

BSR 2-7 Reserved for future use

BA+2 (bits 2-7): 0

NOTE:

1. BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1 in word mode.)

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4.2.4

CFI QUERY IDENTIFICATION STRING

The Identification String provides verification that

the component supports the Common Flash

Interface specification. Additionally, it indicates

which version of the spec and which vendor-

specified command set(s) is (are) supported.

Table 8. CFI Identification

Description

Offset

10h

Length

(Bytes)

28F32/160S5

03h

Query-Unique ASCII string “QRY“

10:

0051h

0052h

0059h

11:

12:

13h

15h

17h

02h

Primary Vendor Command Set and Control Interface ID Code

16-bit ID Code for Vendor-Specified Algorithms

13:

14:

0001h

0000h

Address for Primary Algorithm Extended Query Table

Offset value = P = 31h

15:

16:

0031h

0000h

Alternate Vendor Command Set and Control Interface ID Code

Second Vendor-Specified Algorithm Supported

Note: 0000h means none exists

17:

18:

0000h

19h

02h

Address for Secondary Algorithm Extended Query Table

Note: 0000h means none exists

19:

1A:

0000h

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4.2.5

SYSTEM INTERFACE INFORMATION

The following device information can be useful in

optimizing system interface software.

Table 9. System Interface Information

Offset

Length

(bytes)

Description

28F32/160S5

1Bh

01h

V_CCLogic Supply Minimum Program/Erase Voltage

bits 7–4 BCD volts

1B:

1C:

1D:

0030h

0055h

0030h

bits 3–0 BCD 100 mv

1Ch

1Dh

V_CCLogic Supply Maximum Program/Erase Voltage

bits 7–4 BCD volts

bits 3–0 BCD 100 mv

V_PP[Programming] Supply Minimum Program/Erase

Voltage

bits 7–4 HEX volts

bits 3–0 BCD 100 mv

1Eh

01h

V_PP[Programming] Supply Maximum Program/Erase

1E:

0055h

Voltage

bits 7–4 HEX volts

bits 3–0 BCD 100 mv

1Fh

01h

Typical Time-Out per Single Byte/Word Program, 2^Nµ-

sec

1F:

0003h

20h

21h

22h

23h

01h

Typical Time-Out for Max. Buffer Write, 2^Nµ-sec

Typical Time-Out per Individual Block Erase, 2^Nm-sec

Typical Time-Out for Full Chip Erase, 2^Nm-sec

20:

21:

22:

23:

0006h

000Ah

000Fh

TBD

Maximum Time-Out for Byte/Word Program,

2^NTimes Typical

24h

25h

01h

Maximum Time-Out for Buffer Write, 2^NTimes Typical

24:

25:

TBD

Maximum Time-Out per Individual Block Erase,

2^NTimes Typical

26h

01h

Maximum Time-Out for Chip Erase, 2^NTimes Typical

26:

TBD

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4.2.6

DEVICE GEOMETRY DEFINITION

This field provides critical details of the flash device

geometry.

Table 10. Device Geometry Definition

Offset

27h

Length

(bytes)

Description

28F32/160S5

01h

Device Size = 2^Nin Number of Bytes

27:

0015h

(16 Mbit)

0016h

(32 Mbit)

28h

02h

Flash Device Interface Description

28:

29:

0002h

0000h

value

meaning

0002h

x8/x16 asynchronous

2Ah

2Ch

02h

01h

Maximum Number of Bytes in Write Buffer = 2^N

2A:

2B:

0005h

0000h

Number of Erase Block Regions within Device:

bits 7–0 = x = # of Erase Block Regions

Erase Block Region Information

2C:

0001h

2Dh

04h

y:

32 Blocks

(16 Mbit)

001Fh

bits 15–0 = y, Where y+1 = Number of Erase Blocks of

Identical Size within Region

2D:

2E:

0000h

bits 31–16 = z, Where the Erase Block(s) within This

Region are (z) × 256 Bytes

y:

64 Blocks

(32 Mbit)

003Fh

2D:

2E:

0000h

z:

2F:

30:

(64-KB)

0000h

0001h

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4.2.7

INTEL-SPECIFIC EXTENDED QUERY

TABLE

Certain flash features and commands are optional.

The Intel-Specific Extended Query table specifies

this and other similar types of information.

Table 11. Primary-Vendor Specific Extended Query

Description

Offset⁽¹⁾

Length

(bytes)

Data

(P)h

03h

Primary Extended Query Table

Unique ASCII String “PRI“

31:

32:

33:

0050h

0052h

0049h

(P+3)h

(P+4)h

(P+5)h

01h

04h

Major Version Number, ASCII

Minor Version Number, ASCII

Optional Feature & Command Support

34:

35:

0031h

0030h

36:

37:

38:

39:

000Fh

0000h

bit 0 Chip Erase Supported

bit 1 Suspend Erase Supported

bit 2 Suspend Program Supported (1=yes, 0=no)

(1=yes, 0=no)

bit 3 Lock/Unlock Supported

bit 4 Queued Erase Supported

(1=yes, 0=no)

bits 5–31 Reserved for future use; undefined bits

are “0”

(P+9)h

01h

Supported Functions after Suspend

3A:

0001h

Read Array, Status, and Query are always supported

during suspended Erase or Program operation. This field

defines other operations supported.

bit 0 Program Supported after Erase Suspend

(1=yes, 0=no)

bits 1-7 Reserved for future use; undefined bits are “0”

(P+A)h

02h

Block Status Register Mask

3B:

3C:

0003h

0000h

Defines which bits in the Block Status Register section of

Query are implemented.

bit 0 Block Status Register Lock-Bit [BSR.0] active

(1=yes, 0=no)

bit 1 Block Erase Status Bit [BSR.1] active

(1=yes, 0=no)

bits 2-15 Reserved for future use; undefined bits

are “0”

NOTES:

1. The variable P is a pointer which is defined at offset 15h inTable 8.

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Table 11. Primary-Vendor Specific Extended Query (Continued)

Offset

Length

(bytes)

Description

Data

(P+C)h

01h

V_CCLogic Supply Optimum Program/Erase voltage

(highest performance)

3D:

3E:

0050h

bits 7–4

bits 3–0

BCD value in volts

BCD value in 100 mv

(P+D)h

(P+E)h

01h

VPP [Programming] Supply Optimum Program/Erase

0050h

voltage

bits 7–4

bits 3–0

HEX value in volts

BCD value in 100 mv

reserved Reserved for future use

4.3

Read Identifier Codes

Command

Table 12. Identifier Codes

Code

Address⁽²⁾Data

The identifier code operation is initiated by writing

the Read Identifier Codes command. Following the

command write, read cycles from addresses shown

in Figure 5 retrieve the manufacturer, device, block

lock configuration, and block erase status codes

(see Table 12 for identifier code values). To

terminate the operation, write another valid

command. Like the Read Array command, the

Read Identifier Codes command functions

independently of the V_PPvoltage. Following the

Read Identifier Codes command, the information in

Table 12 can be read.

Manufacturer Code

Device Code

000000

000001

X0002⁽¹⁾

B0

D0

D4

16 Mbit

32 Mbit

Block Lock Configuration

• Block is Unlocked

DQ₀= 0

DQ₀= 1

DQ_2-7

• Block is Locked

• Reserved for Future Use

Block Erase Status

x0002⁽¹⁾

• Last erase completed

DQ₁= 0

DQ₁= 1

DQ_2-7

successfully

• Last erase did not

complete successfully

4.4

Read Status Register

Command

• Reserved for Future Use

NOTES:

The Status Register may be read to determine

when programming, block erasure, or lock-bit

configuration is complete and whether the operation

completed successfully. It may be read at any time

by writing the Read Status Register command.

After writing this command, all subsequent read

operations output data from the Status Register

until another valid command is written. The Status

Register contents are latched on the falling edge of

OE#, CE₀#, or CE₁# whichever occurs last. OE# or

CE_X# must toggle to V_IHto update the Status

Register latch. The Read Status Register command

functions independently of the V_PPvoltage.

1. X selects the specific block lock configuration code.

See Figure 5 for the device identifier code memory

map.

2. A₀should be ignored in this address. The lowest order

address line is A₁in both word and byte mode.

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Following a program, block erase, set block lock-bit,

or clear block lock-bits command sequence, only

SR.7 is valid until the Write State Machine

completes or suspends the operation. Device I/O

pins DQ_0-6and DQ_8-15are invalid. When the

operation completes or suspends (SR.7 = 1), all

contents of the Status Register are valid when read.

analyzing STS in level RY/BY# mode or Status

Register bit SR.7. Toggle OE#, CE₀#, or CE₁# to

update the Status Register.

When the block erase is complete, Status Register

bit SR.5 should be checked. If a block erase error is

detected, the Status Register should be cleared

before system software attempts corrective actions.

The CUI remains in read Status Register mode until

a new command is issued.

The eXtended Status Register (XSR) may be read

to determine Write Buffer availability (see Table 16).

The XSR may be read at any time by writing the

Write to Buffer command. After writing this

command, all subsequent read operations output

data from the XSR, until another valid command is

written. The contents of the XSR are latched on the

falling edge of OE# or CE_X# whichever occurs last

in the read cycle. Write to buffer command must be

re-issued to update the XSR latch.

This two-step command sequence of set-up

followed by execution ensures that block contents

are not accidentally erased. An invalid Block Erase

command sequence will result in both Status

Register bits SR.4 and SR.5 being set to “1.” Also,

reliable block erasure can only occur when

V_CC= V_CC1/2and V_PP= V_PPH. In the absence of

these voltages, block contents are protected

against erasure. If block erase is attempted while

V_PP≤ V_PPLK, SR.3 and SR.5 will be set to “1.”

Successful block erase requires that the

corresponding block lock-bit be cleared, or WP# =

V_IH. If block erase is attempted when the

corresponding block lock-bit is set and WP# = V_IL,

the block erase will fail and SR.1 and SR.5 will be

set to “1.”

4.5

Clear Status Register

Command

Status Register bits SR.5, SR.4, SR.3, and SR.1

are set to “1”s by the WSM and can only be reset

by the Clear Status Register command. These bits

indicate various failure conditions (see Table 15).

By allowing system software to reset these bits,

several operations (such as cumulatively erasing or

locking multiple blocks or programming several

bytes/words in sequence) may be performed. The

Status Register may be polled to determine if an

error occurred during the sequence.

4.7

Full Chip Erase Command

The Full Chip Erase command followed by

a

Confirm command erases all unlocked blocks. After

the Confirm command is written, the device erases

all unlocked blocks from block 0 to block 31 (or 63)

sequentially. Block preconditioning, erase, and

verify are handled internally by the WSM. After the

Full Chip Erase command sequence is written to

the CUI, the device automatically outputs the Status

Register data when read. The CPU can detect full

chip erase completion by polling the STS pin in

level RY/BY# mode or Status Register bit SR.7.

To clear the Status Register, the Clear Status

Register command is written. It functions

independently of the applied V_PPvoltage. This

command is not functional during block erase or

program suspend modes.

4.6

Block Erase Command

When the full chip erase is complete, Status

Register bit SR.5 should be checked to see if the

operation completed successfully. If an erase error

occurred, the Status Register should be cleared

before issuing the next command. The CUI remains

in read Status Register mode until a new command

is issued. If an error is detected while erasing a

block during a full chip erase operation, the WSM

skips the remaining cells in that block and proceeds

to erase the next block. Reading the block valid

status code by issuing the Read Identifier Codes

command or Query command informs the user of

which block(s) failed to erase.

Block Erase is executed one block at a time and

initiated by a two-cycle command. A Block Erase

Setup command is written first, followed by a

Confirm command. This command sequence

requires appropriate sequencing and an address

within the block to be erased (erase changes all

block data to FFH). Block preconditioning, erase,

and verify are handled internally by the WSM

(invisible to the system). After the two-cycle block

erase sequence is written, the device automatically

outputs Status Register data when read (see Figure

9). The CPU can detect block erase completion by

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This two-step command sequence of setup followed

by execution ensures that block contents are not

accidentally erased. An invalid Full Chip Erase

command sequence will result in both Status

Register bits SR.4 and SR.5 being set to 1. Also,

reliable full chip erasure can only occur when

If an error occurs while writing, the device will stop

programming, and Status Register bit SR.4 will be

set to a “1” to indicate a program failure. Any time a

media failure occurs during a program or an erase

(SR.4 or SR.5 is set), the device will not accept any

more Write to Buffer commands. Additionally, if the

user attempts to write past an erase block boundary

with a Write to Buffer command, the device will

abort programming. This will generate an “Invalid

Command/Sequence” error and Status Register bits

SR.5 and SR.4 will be set to “1.” To clear SR.4

V

_CC= V_CC1/2and V_PP= V_PPH. In the absence these

voltages, block contents are protected against

erasure. If full chip erase is attempted while V_PP

_PPLK, SR.3 and SR.5 will be set to 1. When WP# =

≤

V

V_IL, only unlocked blocks are erased. Full chip

erase cannot be suspended.

and/or SR.5, issue

command.

a Clear Status Register

Reliable buffered programming can only occur

when V_CC= V_CC1/2and V_PP= V_PPH. If programming

is attempted while V_PP≤ V_PPLK, Status Register bits

SR.4 and SR.5 will be set to “1.” Programming

attempts with invalid V_CCand V_PPvoltages produce

spurious results and should not be attempted.

Finally, successful programming requires that the

corresponding Block Lock-Bit be cleared, or WP# =

V_IH. If a buffered write is attempted when the

corresponding Block Lock-Bit is set and WP# = V_IL,

SR.1 and SR.4 will be set to “1.”

4.8

Write to Buffer Command

To program the flash device via the write buffers, a

Write to Buffer command sequence is initiated. A

variable number of bytes or words, up to the buffer

size, can be written into the buffer and programmed

to the flash device. First, the Write to Buffer setup

command is issued along with the Block Address.

At this point, the eXtended Status Register

information is loaded and XSR.7 reverts to the

“buffer available” status. If XSR.7 = 0, no write

buffer is available. To retry, continue monitoring

XSR.7 by issuing the Write to Buffer setup

command with the Block Address until XSR.7 = 1.

When XSR.7 transitions to a “1,” the buffer is ready

for loading.

4.9

Byte/Word Program Command

Byte/Word programming is executed by a two-cycle

command sequence. Byte/Word Program setup

(standard 40H or alternate 10H) is written, followed

by a second write that specifies the address and

data (latched on the rising edge of WE#). The WSM

then takes over, controlling the program and verify

algorithms internally. After the write sequence is

written, the device automatically outputs Status

Register data when read. The CPU can detect the

completion of the program event by analyzing STS

in level RY/BY# mode or Status Register bit SR.7.

Now a Word/Byte count is issued at an address

within the block. On the next write, a device start

address is given along with the write buffer data.

For maximum programming performance and lower

power, align the start address at the beginning of a

Write Buffer boundary. Subsequent writes must

supply additional device addresses and data,

depending on the count. All subsequent addresses

must lie within the start address plus the count.

After the final buffer data is given, a Write Confirm

command is issued. This initiates the WSM to begin

copying the buffer data to the flash memory. If a

command other than Write Confirm is written to the

device, an “Invalid Command/Sequence” error will

be generated and Status Register bits SR.5 and

SR.4 will be set to “1.” For additional buffer writes,

issue another Write to Buffer setup command and

check XSR.7. The write buffers can be loaded while

the WSM is busy as long as XSR.7 indicates that a

buffer is available. Refer to Figure 6 for the Write to

Buffer flowchart.

When programming is complete, Status Register bit

SR.4 should be checked. If a programming error is

detected, the Status Register should be cleared.

The internal WSM verify only detects errors for “1”s

that do not successfully program to “0”s. The CUI

remains in read Status Register mode until it

receives another command. Refer to Figure 7 for

the Word/Byte Program flowchart.

Also, Reliable byte/word programming can only

occur when V_CC= V_CC1/2and V_PP= V_PPH. In the

absence of this high voltage, contents are protected

against programming. If a byte/word program is

26

ADVANCE INFORMATION

E

28F160S5, 28F320S5

attempted while V_PP≤ V_PPLK, Status Register bits

SR.4 and SR.3 will be set to “1.” Successful

also be set to “1”, indicating that the device is in the

erase suspend mode. STS in level RY/BY# mode

will also transition to V_OH. Specification t_WHRH2

defines the block erase suspend latency.

byte/word

programming

requires

that

the

a

corresponding block lock-bit be cleared. If

byte/word program is attempted when the

corresponding block lock-bit is set and WP# = V_IL,

SR.1 and SR.4 will be set to “1.”

At this point, a Read Array command can be written

to read data from blocks other than that which is

suspended. A Program command sequence can

also be issued during erase suspend to program

data in other blocks. Using the Program Suspend

command (see Section 4.12), a program operation

can also be suspended. During a program operation

with block erase suspended, Status Register bit

SR.7 will return to “0” and STS in RY/BY# mode will

transition to V_OL. However, SR.6 will remain “1” to

indicate block erase suspend status.

4.10 STS Configuration Command

The Status (STS) pin can be configured to different

states using the STS pin Configuration command.

Once the STS pin has been configured, it remains

in that configuration until another configuration

command is issued or RP# is low. Initially, the STS

pin defaults to level RY/BY# operation where STS

low indicates that the state machine is busy. STS

high indicates that the state machine is ready for a

new operation or suspended.

The only other valid commands while block erase is

suspended are Read Status Register and Block

Erase Resume. After

a Block Erase Resume

command is written to the flash memory, the WSM

will continue the block erase process. Status

register bits SR.6 and SR.7 will automatically clear

and STS in RY/BY# mode will return to V_OL. After

the Erase Resume command is written, the device

automatically outputs Status Register data when

read (see Figure 10). V_PPmust remain at V_PPHand

V_CCmust remain at V_CC1/2(the same V_PPand V_CC

levels used for block erase) while block erase is

suspended. RP# must also remain at V_IH(the same

RP# level used for block erase). Block erase cannot

resume until program operations initiated during

block erase suspend have completed.

To reconfigure the Status (STS) pin to other modes,

the STS pin Configuration command is issued

followed by the desired configuration code. The

three alternate configurations are all pulse mode for

use as a system interrupt as described in Table 14.

For these configurations, bit

0 controls Erase

Complete interrupt pulse, and bit 1 controls Write

Complete interrupt pulse. When the device is

configured in one of the pulse modes, the STS pin

pulses low with a typical pulse width of 250 ns.

Supplying the 00h configuration code with the

Configuration command resets the STS pin to the

default RY/BY# level mode. Refer to Table 14 for

configuration coding definitions. The Configuration

command may only be given when the device is not

busy or suspended. Check SR.7 for device status.

An invalid configuration code will result in both

Status Register bits SR.4 and SR.5 being set to “1.”

4.12 Program Suspend Command

The Program Suspend command allows program

interruption to read data in other flash memory

locations. Once the programming process starts,

writing the Program Suspend command requests

that the WSM suspend the program sequence at a

predetermined point in the algorithm. The device

continues to output Status Register data when read

after the Program Suspend command is written.

Polling Status Register bits SR.7 can determine

when the programming operation has been

suspended. When SR.7 = 1, SR.2 should also be

set to “1”, indicating that the device is in the

program suspend mode. STS in level RY/BY#

mode will also transition to V_OH. Specification

4.11 Block Erase Suspend

Command

The Block Erase Suspend command allows

block-erase interruption to read or program data in

another block of memory. Once the block erase

process starts, writing the Block Erase Suspend

command requests that the WSM suspend the

block erase sequence at a predetermined point in

the algorithm. The device outputs Status Register

data when read after the Block Erase Suspend

command is written. Polling Status Register bits

SR.7 can determine when the block erase operation

has been suspended. When SR.7 = 1, SR.6 should

t

_WHRH1defines the program suspend latency.

At this point, a Read Array command can be written

to read data from locations other than that which is

27

ADVANCE INFORMATION

28F160S5, 28F320S5

E

suspended. The only other valid commands while

programming is suspended are Read Status

Register and Program Resume. After a Program

Resume command is written, the WSM will

continue the programming process. Status Register

bits SR.2 and SR.7 will automatically clear and STS

in RY/BY# mode will return to V_OL. After the

Program Resume command is written, the device

automatically outputs Status Register data when

read. V_PPmust remain at V_PPHand V_CCmust

remain at V_CC1/2(the same V_PPandV_CClevels used

for programming) while in program suspend mode.

RP# must also remain at V_IH(the same RP# level

used for programming). Refer to Figure 8 for the

Program Suspend/Resume flowchart.

A successful set block lock-bit operation requires

that WP# = V_IH. If it is attempted with WP# = V_IL,

the operation will fail and SR.1 and SR.4 will be set

to “1.” See Table 13 for write protection alternatives.

Refer to Figure 11 for the Set Block Lock-Bit

flowchart.

4.14 Clear Block Lock-Bits

Command

All set block lock-bits are cleared in parallel via the

Clear Block Lock-Bits command. This command is

valid only when WP# = V_IH.

The clear block lock-bits operation is initiated using

a two-cycle command sequence. A Clear Block

Lock-Bits setup command is written followed by a

Confirm command. Then, the device automatically

outputs Status Register data when read (see Figure

12). The CPU can detect completion of the clear

block lock-bits event by analyzing STS in level

RY/BY# mode or Status Register bit SR.7.

4.13 Set Block Lock-Bit Command

A flexible block locking and unlocking scheme is

enabled via a combination of block lock-bits. The

block lock-bits gate program and erase operations.

With WP# = V_IH, individual block lock-bits can be

set using the Set Block Lock-Bit command.

Set block lock-bit is initiated using a two-cycle

command sequence. The Set Block Lock-Bit setup

along with appropriate block or device address is

written followed by the Set Block Lock-Bit Confirm

and an address within the block to be locked. The

WSM then controls the set lock-bit algorithm. After

the sequence is written, the device automatically

outputs Status Register data when read. The CPU

can detect the completion of the set lock-bit event

by analyzing STS in level RY/BY# mode or Status

Register bit SR.7.

This two-step sequence of set-up followed by

execution ensures that block lock-bits are not

accidentally cleared. An invalid Clear Block

Lock-Bits command sequence will result in Status

Register bits SR.4 and SR.5 being set to “1.” Also,

a reliable clear block lock-bits operation can only

occur when V_CC= V_CC1/2and V_PP= V_PPH. If a clear

block lock-bits operation is attempted while V_PP

_PPLK, SR.3 and SR.5 will be set to “1.” In the

absence of these voltages, the block lock-bits

contents are protected against alteration.

≤

V

A

successful clear block lock-bits operation requires

that WP# = V_IH.

When the set lock-bit operation is complete, Status

Register bit SR.4 should be checked. If an error is

detected, the Status Register should be cleared.

The CUI will remain in read Status Register mode

until a new command is issued.

If a clear block lock-bits operation is aborted due to

V

_PPor V_CCtransitioning out of valid range or RP# or

WP# active transition, block lock-bit values are left

in an undetermined state. A repeat of clear block

lock-bits is required to initialize block lock-bit

contents to known values.

This two-step sequence of setup followed by

execution ensures that lock-bits are not accidentally

set. An invalid Set Block Lock-Bit command will

result in Status Register bits SR.4 and SR.5 being

set to “1.” Also, reliable operations occur only when

When the operation is complete, Status Register bit

SR.5 should be checked. If a clear block lock-bit

error is detected, the Status Register should be

cleared. The CUI will remain in read Status Register

mode until another command is issued.

V

_CC= V_CC1/2and V_PP= V_PPH. In the absence these

voltages, lock-bit contents are protected against

alteration.

28

ADVANCE INFORMATION

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28F160S5, 28F320S5

Table 13. Write Protection Alternatives

Block

Lock-

Bit

Operation

WP#

Effect

Program and

0

1

V_ILor V_IH

V_IL

Block erase and programming enabled

Block Erase

Block is locked. Block erase and programming disabled

Block Lock-Bit override. Block erase and programming enabled

All unlocked blocks are erased

V_IH

Full Chip Erase

0,1

X

V_IL

V_IH

Block Lock-Bit override. All blocks are erased

Set or clear block lock-bit disabled

Set or Clear

X

V_IL

Block Lock-Bit

V_IH

Set or clear block lock-bit enabled

Table 14. Configuration Coding Definitions

Reserved

Pulse on

Write

Pulse on

Erase

Complete

bits 7–2

bit 1

bit 0

DQ7–DQ2 = Reserved

DQ7–DQ2 are reserved for future use.

DQ1/DQ0 = STS Pin Configuration Codes

default (DQ1/DQ0 = 00) RY/BY#, level mode

-----used to control HOLD to a memory controller to

prevent accessing a flash memory subsystem while

any flash device's WSM is busy.

00 = default, level mode RY/BY#

(device ready) indication

01 = pulse on Erase complete

configuration 01

ER INT, pulse mode⁽¹⁾

10 = pulse on Flash Program complete

11 = pulse on Erase or Program Complete

-----used to generate a system interrupt pulse when

any flash device in an array has completed a block

erase or sequence of queued block erases. Helpful

for reformatting blocks after file system free space

reclamation or ‘cleanup’

Configuration Codes 01b, 10b, and 11b are all pulse

mode such that the STS pin pulses low then high

when the operation indicated by the given

configuration is completed.

configuration 10

PR INT, pulse mode⁽¹⁾

-----used to generate a system interrupt pulse when

any flash device in an array has complete a

program operation. Provides highest performance

for servicing continuous buffer write operations.

Configuration Command Sequences for STS pin

configuration (masking bits D7–D2 to 00h) are as

follows:

Default RY/BY# level mode

ER INT (Erase Interrupt):

Pulse-on-Erase Complete

PR INT (Program Interrupt):

Pulse-on-Flash-Program Complete

B8h, 00h

B8h, 01h

configuration

ER/PR INT, pulse mode⁽¹⁾

-----used to generate system interrupts to trigger

servicing of flash arrays when either erase or flash

program operations are completed when a common

interrupt service routine is desired.

B8h, 02h

ER/PR INT (Erase or Program Interrupt): B8h, 03h

Pulse-on-Erase or Program Complete

NOTE:

1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.

29

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Table 15. Status Register Definition

WSMS

7

ESS

6

ECLBS

5

BWSLBS

4

VPPS

3

BWSS

2

DPS

1

R

0

NOTES:

SR.7 = WRITE STATE MACHINE STATUS

Check STS in RY/BY# mode or SR.7 to determine

block erase, programming, or lock-bit configuration

completion. SR.6-0 are invalid while SR.7 = “0.”

1 = Ready

0 = Busy

SR.6 = ERASE SUSPEND STATUS

1 = Block erase suspended

0 = Block erase in progress/completed

SR.5 = ERASE AND CLEAR LOCK-BITS STATUS If both SR.5 and SR.4 are “1”s after a block erase

1 = Error in block erasure or clear lock-bits

0 = Successful block erase or clear lock-bits

or lock-bit configuration attempt, an improper

command sequence was entered.

SR.4 = PROGRAM AND SET LOCK-BIT

STATUS

1 = Error in program or block lock-bit

0 = Successful program or set block lock-bit

SR.3 = V_PPSTATUS

1 = V_PPlow detect, operation abort

0 = V_PPOK

SR.3 does not provide a continuous indication of

V

_PPlevel. The WSM interrogates and indicates the

_PPlevel only after a block erase, program, or lock-

bit configuration operation. SR.3 reports accurate

feedback only when V_PP= V_PPH

.

SR.2 = PROGRAM SUSPEND STATUS

1 = Program suspended

0 = Program in progress/completed

SR.1 = DEVICE PROTECT STATUS

1 = Block Lock-Bit and/or

RP# lock detected, operation abort

0 = Unlock

SR.1 does not provide a continuous indication of

block lock-bit values. The WSM interrogates the

block lock-bit, and WP# only after a block erase,

program, or lock-bit configuration operation. It

informs the system, depending on the attempted

operation, if the block lock-bit is set.

SR.0 = RESERVED FOR FUTURE

ENHANCEMENTS

SR.0 is reserved for future use and should be

masked when polling the Status Register.

Table 16. Extended Status Register Definition

WBS

7

R

6

R

1

R

0

5

4

3

2

NOTES:

XSR.7 = WRITE BUFFER STATUS

1 = Write to buffer available

After a Write to buffer command, XSR.7 indicates

that another Write to buffer command is possible.

0 = Write to buffer not available

XSR.6 = RESERVED FOR FUTURE

ENHANCEMENTS

SR.6–0 are reserved for future use and should be

masked when polling the status register

30

ADVANCE INFORMATION

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28F160S5, 28F320S5

Bus

Operation

Write

Command

Comments

Start

Write to

Buffer

Data = E8h

Addr = Block Address

XSR.7=valid

Addr = X

Set Time-Out

Read

Issue Write Command

E8H, Block Address

No

Standby

Check XSR.7

1 = Write buffer available

0 = Write buffer not available

Data = N = word/byte count

N = 0 corresponds to count = 1

Addr = Block Address

Data = write buffer data

Addr = device start address

Data = write buffer data

Addr = device address

Data = D0h

Read Extended

Status Register

Write

(Note 1, 2)

Write

(Note 3, 4)

Write

(Note 5, 6)

Write

Write Buffer

Time-Out?

0

XSR.7 =

1

Buffer

Write Word or Byte

Count, Block Address

write to flash Addr = X

confirm

Read

Status Register data

Write Buffer Data,

Start Address

CE# & OE# low updates SR

Addr = X

Check SR.7

Standby

1 = WSM ready

0 = WSM busy

X = 0

1. Byte- or word-count values on DQ

the Count register.

2. The device now outputs the Status Register when

read (XSR is no longer available).

3. Write Buffer contents will be programmed at the

device start address or destination flash address.

4. Align the start address on a Write Buffer boundary for

maximum programming performance.

are loaded into

0-7

Yes

X = N

No

Yes

5. The device aborts the Write to Buffer command if the

current address is outside of the original block

address.

6. The Status Register indicates an “improper command

sequence” if the Write to Buffer command is aborted.

Follow this with a Clear Status Register command.

Abort Buffer

Write

Command?

Write to Another

Block Address

Yes

Buffer Write to

Flash Aborted

Yes

No

Write Next Buffer Data,

Device Address

Full status check can be done after all Erase and

Write sequences complete. Write FFh after the last

operation to reset the device to Read Array mode.

X = X + 1

Buffer Write to Flash

Confirm D0H

Another

Buffer

Write?

Issue Read

Status Command

No

Read

Status Register

No

Suspend

Write Loop

Yes

Suspend

Write?

0

SR.7 =

1

Full Status

Check if Desired

Buffer Write to

Flash Complete

0608_07

Figure 6. Write to Buffer Flowchart

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E

0608_08

Figure 7. Single Byte/Word Program Flowchart

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28F160S5, 28F320S5

0608_09

Figure 8. Program Suspend/Resume Flowchart

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ADVANCE INFORMATION

28F160S5, 28F320S5

E

Bus

Operation

Write

Command

Comments

Start

Erase Block Data = 28h or 20h

Addr = Block Address

Device

Supports

Queuing

Read

XSR.7=valid

Addr = X

Check XSR.7

Standby

Yes

1 = Erase queue available

0 = No Erase queue available

Erase Block Data = 28H

Addr = Block Address

SR.7=valid; SR.6-0=X

With the device enabled,

OE# low updates SR

Addr = X

Set Time-Out

Write

Read

Issue Block Queue

Erase Command 28H,

Block Address

No

Read Extended Status

Register

Standby

Check XSR.7

1 = Erase queue available

0 = No Erase queue available

Write

(Note 1)

Read

Erase

Confirm

Data = D0H

Addr = X

Status Register data

With the device enabled,

OE# low updates SR

Addr = X

Is Queue

Available?

XSR.7=

Erase Block

Time-Out?

0=No

No

1=Yes

Standby

Check SR.7

1 = WSM ready

0 = WSM busy

Another

Block

Yes

Erase?

1. The Erase Confirm byte must follow Erase Setup when

the Erase Queue status (XSR.7)=0.

Yes

Full status check can be done after all Erase and Write

sequences complete. Write FFh after the last

operation to reset the device to Read Array mode.

Issue Erase Command

28H Block Address

1=No

Read Extended

Status Register

No

Is Queue

Full?

XSR.7=

Issue Single Block

Erase Command 20H,

Block Address

0=Yes

Write Confirm D0H

Block Address

Write Confirm D0H

Block Address

Another

Block

Erase?

Issue Read

Status Command

No

Read

Status Register

No

Suspend

Erase Loop

Suspend

Erase

0

Yes

SR.7 =

1

Full Status

Check if Desired

Erase Flash

Block(s) Complete

0609_10

Figure 9. Block Erase Flowchart

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ADVANCE INFORMATION

E

28F160S5, 28F320S5

Start

Bus

Operation

Command

Comments

Write

Read

Erase

Suspend

Data = B0H

Addr = X

Write B0H

Status Register Data

Addr = X

Read

Status Register

Check SR.7

1 = WSM Ready

0 = WSM Busy

Standby

0

SR.7 =

1

Check SR.6

1 = Block Erase Suspended

0 = Block Erase Completed

Erase

Resume

Data = D0H

Addr = X

Write

SR.6 =

1

Block Erase Completed

Read

Write

Read or

Write?

Write

Loop

Read Array

Data

No

Done?

Yes

Write D0H

Write FFH

Block Erase Resumed

Read Array Data

Figure 10. Block Erase Suspend/Resume Flowchart

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ADVANCE INFORMATION

28F160S5, 28F320S5

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Start

Bus

Operation

Command

Comments

Set

Data = 60H

Addr = Block Address (Block),

Device Address (Master)

Write 60H,

Block/Device Address

Write

Block/Master

Lock-Bit Setup

Data = 01H (Block),

Set

F1H (Master)

Write 01H/F1H,

Block/Device Address

Block or Master

Lock-Bit Confirm

Addr = Block Address (Block),

Device Address (Master)

Read

Status Register Data

Read

Status Register

Check SR.7

1 = WSM Ready

0 = WSM Busy

Standby

0

SR.7 =

Repeat for subsequent lock-bit set operations.

Full status check can be done after each lock-bit set operation

or after a sequence of lock-bit set operations.

Write FFH after the last lock-bit set operation to place device in

read array mode.

1

Full Status

Check if Desired

Set Lock-Bit

Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Read Status Register

Data (See Above)

Command

Comments

Check SR.3

1 = Programming Voltage Error

Detect

Standby

1

SR.3 =

0

Voltage Range Error

Check SR.1

1 = Device Protect Detect

RST# = V

(Set Master Lock-Bit Operation)

IH

Standby

1

RST# = V , Master Lock-Bit Is Set

IH

(Set Block Lock-Bit Operation)

Device Protect Error

SR.1 =

0

Check SR.4,5

Both 1 = Command Sequence Error

Standby

1

Command Sequence

Error

SR.4,5 =

0

Check SR.4

1 = Set Lock-Bit Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status

Register command in cases where multiple lock-bits are set

before full status is checked.

If error is detected, clear the Status Register before attempting retry

or other error recovery.

1

SR.4 =

0

Set Lock-Bit Error

Set Lock-Bit Successful

Figure 11. Set Block Lock-Bit Flowchart

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ADVANCE INFORMATION

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28F160S5, 28F320S5

Start

Bus

Operation

Command

Comments

Data = 60H

Addr = X

Clear Block

Lock-Bits Setup

Write

Write 60H

Data = D0H

Addr = X

Clear Block

Lock-Bits Confirm

Write D0H

Read

Status Register Data

Read Status

Register

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

0

SR.7 =

1

Write FFH after the Clear Block Lock-Bits operation to place device

to read array mode.

Full Status

Check if Desired

Clear Block Lock-Bits

Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Read Status Register

Data (See Above)

Command

Comments

Check SR.3

1 = Programming Voltage Error

Detect

Standby

1

SR.3 =

0

Voltage Range Error

Device Protect Error

Check SR.1

1 = Device Protect Detect

Standby

IH

RST# = V , Master Lock-Bit Is Set

1

Check SR.4,5

Both 1 = Command Sequence Error

SR.1=

0

Standby

Check SR.5

1 = Clear Block Lock-Bits Error

Command Sequence

Error

SR.4,5 =

0

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status

Register command.

If error is detected, clear the Status Register before attempting

retry or other error recovery.

1

Clear Block Lock-Bits

Error

SR.5 =

0

Clear Block Lock-Bits

Successful

Figure 12. Clear Block Lock-Bits Flowchart

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28F160S5, 28F320S5

E

Additionally, for every eight devices, a 4.7 µF

electrolytic capacitor should be placed at the array’s

power supply connection between V_CCand GND.

The bulk capacitor will overcome voltage slumps

caused by PC board trace inductance.

5.0 DESIGN CONSIDERATIONS

5.1

Three-Line Output Control

Intel provides three control inputs to accommodate

multiple memory connections: CE_X# (CE₀#, CE₁#),

OE#, and RP#. Three-line control provides for:

5.4

V

Trace on Printed Circuit

PP

Boards

a. Lowest possible memory power dissipation;

b. Data bus contention avoidance.

Updating target-system resident flash memories

requires that the printed circuit board designer pay

attention to V_PPpower supply traces. The V_PPpin

supplies the memory cell current for programming

and block erasing. Use similar trace widths and

layout considerations given to the V_CCpower bus.

Adequate V_PPsupply traces and decoupling will

decrease V_PPvoltage spikes and overshoots.

To use these control inputs efficiently, an address

decoder should enable CEx# while OE# should be

connected to all memory devices and the system’s

READ# control line. This assures that only selected

memory devices have active outputs, while de-

selected memory devices are in standby mode.

RP# should be connected to the system

POWERGOOD signal to prevent unintended writes

during system power transitions. POWERGOOD

should also toggle during system reset.

5.5

V

, V , RP# Transitions

CC PP

Block erase, program, and lock-bit configuration are

not guaranteed if RP# ≠ V_IH,or if V_PPor V_CCfall

outside of a valid voltage range (V_CC1/2and V_PPH).

If V_PPerror is detected, Status Register bit SR.3

and SR.4 or SR.5 are set to “1.” If RP# transitions

to V_ILduring block erase, program, or lock-bit

configuration, STS in level RY/BY# mode will

remain low until the reset operation is complete.

Then, the operation will abort and the device will

enter deep power-down. Because the aborted

operation may leave data partially altered, the

command sequence must be repeated after normal

operation is restored.

5.2

STS and WSM Polling

STS is an open drain output that should be

connected to V_CCby a pull-up resistor to provide a

hardware form of detecting block erase, program,

and lock-bit configuration completion. In default

mode, it transitions low during execution of these

commands and returns to V_OHwhen the WSM has

finished executing the internal algorithm. For

alternate STS pin configurations, see Section 4.10.

STS can be connected to an interrupt input of the

system CPU or controller. It is active at all times.

STS, in default mode, is also V_OHwhen the device

is in block erase suspend (with programming

inactive) or in reset/power-down mode.

5.6

Power-Up/Down Protection

The device offers protection against accidental

block erase, programming, or lock-bit configuration

during power transitions.

5.3

Power Supply Decoupling

Flash memory power switching characteristics

require careful device decoupling. Standby current

levels, active current levels and transient peaks

produced by falling and rising edges of CE_X# and

OE# are areas of interest. Two-line control and

proper decoupling capacitor selection will suppress

transient voltage peaks. Each device should have a

0.1 µF ceramic capacitor connected between its

V_CCand GND and V_PPand GND. These high-

frequency, low-inductance capacitors should be

placed as close as possible to package leads.

A system designer must guard against spurious

writes for V_CCvoltages above V_LKOwhen V_PPis

active. Since both WE# and CE_X# must be low for a

command write, driving either input signal to V_IHwill

inhibit writes. The CUI’s two-step command

sequence architecture provides an added level of

protection against data alteration.

In-system block lock and unlock renders additional

protection during power-up by prohibiting block

erase and program operations. RP# = V_ILdisables

the device regardless of its control inputs states.

38

ADVANCE INFORMATION

E

28F160S5, 28F320S5

6.0 ELECTRICAL SPECIFICATIONS

NOTICE: This datasheet contains information on products

in the design phase of development. Do not finalize a

design with this information. Revised information will be

published when the product is available. Verify with your

local Intel Sales office that you have the latest datasheet

before finalizing a design

6.1

Absolute Maximum Ratings

Temperature under Bias ................ –40°C to +85°C

Storage Temperature................... –65°C to +125°C

Voltage On Any Pin

*WARNING: Stressing the device beyond the “Absolute

Maximum Ratings” may cause permanent damage. These

are stress ratings only. Operation beyond the “Operating

Conditions” is not recommended and extended exposure

beyond the “Operating Conditions” may affect device

reliability.

(except V_CCand V_PP

)

.................................... –0.5V to + V_CC+0.5V⁽¹⁾

V_CCSupply Voltage ............ –0.2V to + V_CC+0.5V⁽¹⁾

V_PPUpdate Voltage during

NOTES:

Block Erase, Flash Write, and

1. All specified voltages are with respect to GND. Minimum

Lock-Bit Configuration ........... –0.2V to +7.0V⁽²⁾

DC voltage is –0.5V on input/output pins and –0.2V on

Output Short Circuit Current.....................100 mA⁽³⁾

V

_CCand V_PPpins. During transitions, this level may

undershoot to –2.0V for periods <20 ns. Maximum DC

voltage on input/output pins and V_CCis V_CC+0.5V

which, during transitions, may overshoot to V_CC+2.0V

for periods <20 ns.

2. Maximum DC voltage on V_PPmay overshoot to +7.0V

for periods <20 ns.

3. Output shorted for no more than one second. No more

than one output shorted at a time.

4. Operating temperature is for extended product defined

by this specification.

6.2

Operating Conditions

Table 17. Temperature and V_CCOperating Conditions ⁽¹⁾

Symbol

Parameter

Notes

Min

-40

Max

+85

Unit

°C

V

Test Condition

T_A

Operating Temperature

Ambient Temperature

V_CC1

V_CCSupply Voltage (5V ± 5%)

V_CCSupply Voltage (5V ± 10%)

4.75

4.50

5.25

5.50

V_CC2

V

NOTES:

1. Device operations in the V_CCvoltage ranges not covered in the table produce spurious results and should not be

attempted.

39

ADVANCE INFORMATION

28F160S5, 28F320S5

6.2.1 CAPACITANCE

E

Table 18. Capacitance⁽¹⁾, T_A= +25°C, f = 1 MHz

Symbol

Parameter

Typ

6

Max

8

Unit

pF

Condition

V_IN= 0.0V

C_IN

Input Capacitance

Output Capacitance

C_OUT

8

12

pF

V_OUT= 0.0V

NOTE:

1. Sampled, not 100% tested.

6.2.2

AC INPUT/OUTPUT TEST CONDITIONS

3.0

OUTPUT

INPUT

1.5

TEST POINTS

1.5

0.0

AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V.

Input rise and fall times (10% to 90%) <10 ns.

Figure 13. Transient Input/Output Reference Waveform for V_CC= 5.0V ± 5%

(High Speed Testing Configuration)

2.4

2.0

0.8

2.0

0.8

INPUT

OUTPUT

TEST POINTS

0.45

AC test inputs are driven at V_OH(2.4 V_TTL) for a Logic "1" and V (0.45 V_TTL) for a Logic "0." Input timing begins at V

IH

(2.0 V_TTL) and V_IL(0.8 V_TTL). Output timing ends at V_IHand V_IL. ^OIn^Lput rise and fall times (10% to 90%) <10 ns.

Figure 14. Transient Input/Output Reference Waveform for V_CC= 5.0V ± 10%

(Standard Testing Configuration)

1.3V

Test Configuration Capacitance Loading Value

Test Configuration

V_CC= 5.0V ± 5%

V_CC= 5.0V ± 10%

C_L(pF)

1N914

30

R_L= 3.3 k

Ω

100

DEVICE

UNDER

TEST

OUT

C_L

C_LIncludes Jig

Capacitance

Figure 15. Transient Equivalent Testing

Load Circuit

40

ADVANCE INFORMATION

E

28F160S5, 28F320S5

Conditions

6.2.3

DC CHARACTERISTICS

Table 19. DC Characteristics, T_A= –40^oC to +85^oC

Sym

Parameter

Input Load Current

Notes Typ

Max

Unit

I_LI

1

±1

µA

V_CC= V_CCMax

_IN= V_CCor GND

V

I_LO

Output Leakage Current

1

±10

µA

V_CC= V_CCMax

_out= V_CCor GND

V

I_CCS

V_CCStandby Current

1,3,6

25

100

CMOS Inputs

_CC= V_CCMax

V

CE_X# = RP# = V_CC± 0.2V

0.4

2

mA

TTL Inputs

V

_CC= V_CCMax

CE_X# = RP# = V_IH

I_CCD

I_CCR

V_CCDeep Power-Down Current

V_CCRead Current

1

20

50

µA

RP# = GND ± 0.2V

I

_OUT(RY/BY#) = 0 mA

1,5,6

mA

CMOS Inputs

V

_CC= V_CCMax

CE_X# = GND

f = 8 MHz, I_OUT= 0 mA

65

35

mA

TTL Inputs

V

_CC= V_CCMax

CE_X# = V_IL

f = 8 MHz, I_OUT= 0 mA

I_CCW

V_CCProgramming and Set Lock-

Bit Current

1,7

V_PP= V_PPH

I_CCE

V_CCBlock Erase or Clear Block

Lock-Bits Current

1,7

1,2

1

30

10

mA

µA

V_PP= V_PPH

I_CCWSV_CCProgram Suspend or Block

I_CCESErase Suspend Current

CEX# = V_IH

I_PPS

I_PPR

V_PPStandby or V_PPRead

Current

± 2

± 15

V

_PP≤ V_CC

10

200

5

µA

_PP≥ V_CC

I_PPD

I_PPW

V_PPDeep Power-Down Current

1

0.1

RP# = GND ± 0.2V

V_PP= V_PPH

V_PPProgram or Set Lock-Bit

Current

1,7

80

mA

I_PPE

V_PPBlock Erase or Clear Block

Lock-Bits Current

1,7

1

40

mA

µA

V_PP= V_PPH

I_PPWSV_PPProgram Suspend or Block

Erase Suspend Current

10

200

I_PPES

41

ADVANCE INFORMATION

28F160S5, 28F320S5

E

Table 19. DC Characteristics (Continued)

Sym

V_IL

Parameter

Notes

Min

–0.5

2.0

Max

Unit

V

Conditions

Input Low Voltage

Input High Voltage

Output Low Voltage

7

0.8

V_IH

V_CC+ 0.5

0.45

V

V_OL

3,7

V

V_CC= V_CCMin

_OL= 5.8 mA

I

V_OH1

Output High Voltage (TTL)

3,7

2.4

V

V_CC= V_CCMin

_OH= –2.5 mA

I

V_OH2

Output High Voltage (CMOS)

0.85 ×

V_CC

V_CC= V_CCMin

_OH= –2.5 mA

I

V_CC– 0.4

V_CC= V_CCMin

_OH= –100 µA

I

V_PPLKV_PPLockout Voltage

4,7

4

1.5

5.5

V

V_PPH

V_PPVoltage

4.5

2.0

V_LKO

V_CCLockout Voltage

8

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at nominalV_CCvoltage and T_A= +25°C. These currents are

valid for all product versions (packages and speeds).

2.

I

_CCWSand I_CCESare specified with the device de-selected. If read or programmed while in erase suspend mode, the

device’s current is the sum of I_CCWSor I_CCESand I_CCRor I_CCW

3. Includes STS in level RY/BY# mode.

4. Block erase, program, and lock-bit configurations are inhibited when V_PP≤ V_PPLK, and not guaranteed in the range between

_PPLK(max) and V_PPH(min), and above V_PPH(max).

5. Automatic Power Savings (APS) reduces typical I_CCRto 1 mA at 5V V static operation.

.

V

CC

6. CMOS inputs are either V_CC± 0.2V or GND ± 0.2V. TTL inputs are either V_ILor V_IH

7. Sampled, not 100% tested.

.

8. With V_CC≤ V_LKOflash memory writes are inhibited.

42

ADVANCE INFORMATION

E

28F160S5, 28F320S5

6.2.4

AC CHARACTERISTICS - READ-ONLY OPERATIONS

Table 20. AC Read Characteristics ^(1,5), T_A= –40^oC to +85^oC

Versions⁽⁴⁾

(All units in ns unless otherwise noted)

Sym Parameter

5V ± 5% V_CC

5V ± 10% V_CC

-70/-90

-80/-100

-100/-110

#

Notes Min

Max

Min

80

Max

Min

Max

R1 t_AVAVRead/Write Cycle Time

R2 t_AVQVAddress to Output Delay

R3 t_ELQVCEX# to Output Delay

16 Mbit

32 Mbit

16 Mbit

32 Mbit

16 Mbit

32 Mbit

1

2

70

90

100

110

100

70

90

80

100

80

100

110

100

110

400

40

70

90

100

400

35

R4 t_PHQVRP# High to Output Delay

R5 t_GLQVOE# to Output Delay

R6 t_ELQXCEX# to Output in Low Z

400

30

2

3

0

R7 t_EHQZCEX# High to Output in High Z

R8 t_GLQXOE# to Output in Low Z

25

10

30

10

35

15

R9 t_GHQZOE# High to Output in High Z

R10 t_OH

Output Hold from Address, CEX#, or

OE# Change, Whichever Occurs First

R11 t_ELFLCEX# Low to BYTE# High or Low

t_ELFH

3

5

R12 t_FLQVBYTE# to Output Delay

t_FHQV

16 Mbit

70

80

100

32 Mbit

3

90

25

100

30

110

30

R13 t_FLQZBYTE# to Output in High Z

NOTES:

1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.

2. OE# may be delayed up to t_ELQV-t_GLQVafter the falling edge of CEX# without impact on t_ELQV

.

3. Sampled, not 100% tested.

4. See Ordering Information for device speeds (valid operational combinations).

5. See Figures 13 through 15 for testing characteristics.

43

ADVANCE INFORMATION

28F160S5, 28F320S5

E

Note: CE_X# is the latter of CE₀# and CE₁# low or the first of CE₀# or CE₁# high.

0608_17

Figure 16. AC Waveform for Read Operations

44

ADVANCE INFORMATION

E

28F160S5, 28F320S5

6.2.5

AC CHARACTERISTICS - WRITE OPERATIONS

Table 21. Write Operations^(1,6), T_A= –40°C to +85°C

Versions⁽⁶⁾

5V ± 5%

5V ± 10% V_CC

Valid for All

Speeds

#

Sym

t_{PHWL ( PHEL)}

t_ELWL

Parameter

Notes

Min

1

Max Unit

W1

t

RP# High Recovery to WE# (CE_X# ) Going Low

CE_X# Setup to WE# Going Low

(WE# Setup to CE_X# Going Low)

WE# Pulse Width

2

µs

ns

W2

10

0

t

( WLEL)

W3

t_WLWH

40

50

40

10

0

t

(CE_X# Pulse Width)

( ELEH)

W4

W5

W6

t_{DVWH ( DVEH)}

t_{AVWH ( AVEH)}

t_WHEH

t

Data Setup to WE# (CE_X# ) Going High

Address Setup to WE# (CE_X# ) Going High

CE_X# Hold from WE# High

3

t

(WE# Hold from CE_X# High)

( EHWH)

W7

W8

W9

t_{WHDX ( EHDX)}

t_{WHAX ( EHAX)}

t_WHWL

t

Data Hold from WE# (CE_X# ) High

Address Hold from WE# (CE_X# ) High

WE# Pulse Width High

5

t

5

30

25

100

0

t

(CE_X# Pulse Width High)

( EHEL)

W10 t_{SHWH ( SHEH)}

W11 t_{VPWH ( VPEH)}

W12 t_{WHGL ( EHGL)}

W13 t_{WHRL ( EHRL)}

t

WP# V_IHSetup to WE# (CE_X# ) Going High

V_PPSetup to WE# (CE_X# ) Going High

Write Recovery before Read

t

2

t

WE# High to STS in RY/BY# Low

WP# V_IHHold from Valid SRD

V_PPHold from Valid SRD, STS in RY/BY# High

90

W14 t_QVSL

2,4

0

W15 t_QVVL

NOTES:

1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during

read-only operations. Refer to AC Characteristics for read-only operations.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid A_INand D_INfor block erase, program, or lock-bit configuration.

4.

V_PPshould be at V_PPHuntil determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0).

5. See Ordering Information for device speeds (valid operational combinations).

6. See Figures 13 through 15 for testing characteristics.

45

ADVANCE INFORMATION

28F160S5, 28F320S5

E

NOTES:

A.

B.

C.

D.

E.

F.

V

power-up and standby.

CC

Write block erase or program setup.

Write block erase confirm or valid address and data..

Automated erase or program delay.

Read Status Register data.

Write Read Array command.

CE_X# is the latter of CE₀# and CE₁# low or the first of CE₀# or CE₁# high.

0608_18

Figure 17. AC Waveform for Write Operations

46

ADVANCE INFORMATION

E

28F160S5, 28F320S5

6.2.6

RESET OPERATIONS

Figure 18. AC Waveform for Reset Operation

Table 22. Reset AC Specifications⁽¹⁾

#

Sym

Parameter

Notes

Min

Max

Unit

P1 t_PLPHRP# Pulse Low Time

100

ns

(If RP# is tied to V_CC, this specification is not applicable)

P2 t_PLRHRP# Low to Reset during Block Erase, Program, or Lock-

Bit Configuration

2,3

12

µs

P3 t_5VPHV_CCat 4.5V to RP# High

50

µs

NOTES:

1. These specifications are valid for all product versions (packages and speeds).

2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing, the reset will complete

within t

.

PLPH

3. A reset time, t_PHQV, is required from the latter of STS in RY/BY# mode or RP# going high until outputs are valid.

47

ADVANCE INFORMATION

28F160S5, 28F320S5

E

6.2.7

ERASE, PROGRAM, AND LOCK-BIT CONFIGURATION PERFORMANCE

Table 23. Erase/Write/Lock Performance^(3,4)

5V ± 5%,

5V ± 10% V_CC

Version

5V V_PP

#

Sym

Parameter

Notes Typ⁽¹⁾Max Units

W16

Byte/word program time (using write buffer)

Per byte program time (without write buffer)

5

2

TBD

µs

W16 t_WHQV1

t_EHQV1

2

9.24 TBD

W16 t_WHQV1

t_EHQV1

Per word program time (without write buffer)

2

9.24 TBD

µs

W16

Block program time (byte mode)

Block program time (word mode)

Block program time (using write buffer)

Block erase time

2

0.5

TBD

sec

0.38 TBD

0.13 TBD

0.34 TBD

W16 t_WHQV2

t_EHQV2

W16

10.7

sec

µs

Full chip erase time

16 Mbit

32 Mbit

21.4

W16 t_WHQV3

t_EHQV3

Set Lock-Bit time

2

9.24 TBD

W16 t_WHQV4

t_EHQV4

Clear block lock-bits time

0.34 TBD

sec

µs

W16 t_WHRH1

t_EHRH1

Program suspend latency time to read

Erase suspend latency time to read

5.6

9.4

7

W16 t_WHRH2

t_EHRH2

13.1

µs

NOTES:

1. Typical values measured at T_A= +25°C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to

change based on device characterization.

2. Excludes system-level overhead.

3. These performance numbers are valid for all speed versions.

4. Sampled but not 100% tested.

5. Uses whole buffer.

48

ADVANCE INFORMATION

E

28F160S5, 28F320S5

APPENDIX A

DEVICE NOMENCLATURE AND ORDERING

INFORMATION

Product line designator for all Intel Flash products

TE28 F1 6 0S5 - 7 0

Package

Access Speed (ns)

DT = Extended Temp.

56-Lead SSOP

70 ns (5V, 30 pF), 80 ns (5V)

TE = Extended Temp.

56-Lead TSOP

Device Type

5 = 5V V_CC, 5V V_PP

Device Density

160 = 16-Mbit

320 = 32-Mbit

Product Family

S = FlashFile™ Memory

0609_20

Order Code by Density

Valid Operational Combinations

10% V_CC

100 pF load

(16 Mb / 32 Mb)

5% V_CC

30 pF load

(16 Mb / 32 Mb)

16 Mb

32 Mb

E28F160S5-70

E28F160S5-100

DA28F160S5-70

DA28F160S5-100

E28F320S5-90

E28F320S5-110

DA28F320S5-90

DA28F320S5-110

-80 / -100

-100 / -110

-80 / -100

-100 / -110

-70 / -90

-70 / -100

49

ADVANCE INFORMATION

28F160S5, 28F320S5

E

APPENDIX B

(1,2)

ADDITIONAL INFORMATION

Order Number

290608

Document/Tool

Word-Wide FlashFile™Memory Family 28F160S3, 28F320S3 Datasheet

AP-645 28F160S3/S5 Compatibility with 28F016SA/SV

AP-646 Common Flash Interface and Command Sets

28F016SV 16-Mb (1Mbit x 16, 2Mbit x 8) FlashFile™ Memory Datasheet

28F016SA 16-Mb (1Mbit x 16, 2Mbit x 8) FlashFile™ Memory Datasheet

16-Mbit Flash Product Family User’s Manual

292203

292204

290528

290489

297372

292123

AP-374 Flash Memory Write Protection Techniques

292144

AP-393 28F016SV Compatibility with 28F016SA

292159

AP-607 Multi-Site Layout Planning with Intel’s FlashFile™ Components,

Including ROM Capability

292163

AP-610 Flash Memory In-System Code and Data Update Techniques

CFI - Common Flash Interface Reference Code

Contact Intel/Distribution

Sales Office

NOTES:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should

contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools.

50

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型号：	DA28F160S5-100
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文件：	总50页 (文件大小：1219K)
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