KC80524TX400256_技术文档

MOBILE PENTIUM II PROCESSOR IN

Micro-PGA AND BGA PACKAGES AT 400 MHz, 366 MHz,

333 MHz, 300PE MHz, AND 266PE MHz

Available at 400 MHz, 366 MHz, 333 MHz,

300PE MHz, and 266PE MHz

Fully compatible with previous Intel

microprocessors

— Binary compatible with all applications

— Support for MMX™ technology

Supports the Intel Architecture with

Dynamic Execution

Integrated primary 16-Kbyte instruction

cache and 16-Kbyte write back data cache

Power Management Features

— Quick Start and Deep Sleep modes

provide extremely low power

dissipation

Integrated second level cache (256-Kbyte)

Micro-PGA and BGA packaging

technologies

Low-Power GTL+ processor system bus

interface

— Supports thin form factor notebook

designs

Integrated math co-processor

Integrated thermal diode

— Exposed die enables more efficient heat

dissipation

The Intel Mobile Pentium II processor introduces a higher level of performance for today’s mobile

computing environment, including multimedia enhancements and improved Internet and communications

capabilities. It provides an improved performance¹available for applications running on advanced operating

systems such as Windows* 98. On top of its built-in power management capabilities, the Pentium II

processor takes advantage of software designed for Intel’s MMX technology to unleash enhanced color,

smoother graphics and other multimedia and communications enhancements.

The Mobile Pentium II processor may contain design defects or errors know as errata that may cause the

product to deviate from published specifications. Current characterized errata are available upon request.

1.

Refer to the Mobile Pentium ^{II Processor Performance Brief}.

INTEL CORPORATION

ORDER NUMBER: 245103-003

MOBILE PENTIUM^®II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHz, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

otherwise, to any intellectual property rights is granted by this document or by the sale of Intel products. Except as provided in

Intel's terms and conditions of sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or

implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular

purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving or life sustaining applications.

Intel retains the right to make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel

reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from

future changes to them.

The Mobile Pentium® II processor may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be

obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com

.

*Third-party brands and names are the property of their respective owners

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AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

CONTENTS

PAGE

3.4 Maximum Ratings .................................... 16

3.5 DC Specifications..................................... 18

3.6 AC Specifications..................................... 23

1. INTRODUCTION .............................................. 1

1.1 Overview.................................................... 2

1.2 Terminology............................................... 2

1.3 References ................................................ 2

3.6.1 System Bus, Clock, APIC, TAP,

CMOS and Open-Drain AC

Specifications ................................. 23

2. MOBILE PENTIUM^®II PROCESSOR

FEATURES ...................................................... 4

4. SYSTEM SIGNAL SIMULATIONS ................. 37

2.1 Feature Differences between the Mobile

Pentium^®II Processor at 400 MHz and

Mobile Pentium^®II Processor at 366 MHz

and

4.1 System Bus Clock (BCLK) Signal Quality

Specifications........................................... 37

4.2 Low Power GTL+ Signal Quality

Specifications........................................... 38

below ........................................................ 4

2.2 Power Management................................... 4

2.2.1 Clock Control Architecture................ 4

2.2.2 Normal State .................................... 6

2.2.3 Auto Halt State ................................. 6

2.2.4 STOP GRANT State......................... 6

2.2.5 QUICK START State........................ 6

2.2.6 HALT/GRANT SNOOP State............ 7

2.2.7 SLEEP State .................................... 8

2.2.8 Deep Sleep State ............................. 8

4.3 Non-Low Power GTL+ Signal Quality

Specifications........................................... 41

4.3.1 Overshoot and Undershoot Guidelines42

4.3.1 Ringback Specification.................... 43

4.3.2 Settling Limit Guideline................... 43

5. MECHANICAL SPECIFICATIONS ................. 44

5.1 Dimensions of the Micro-PGA Package ... 44

5.2 Dimensions of the BGA Package............. 46

5.3 Signal Listings.......................................... 49

2.2.9 Operating System Implications of

Quick Start and Sleep States............ 8

6. THERMAL SPECIFICATIONS........................ 62

6.1 Thermal Diode.......................................... 63

6.2 Case Temperature ................................... 64

2.3 Low Power GTL+ ....................................... 8

2.3.1 GTL+ Signals.................................... 9

2.4 Mobile Pentium^®II Processor CPUID......... 9

7. PROCESSOR INITIALIZATION AND

CONFIGURATION.......................................... 65

3. ELECTRICAL SPECIFICATIONS .................. 11

3.1 Processor System Signals ....................... 11

3.1.1 Power Sequencing Requirements... 12

3.1.2 Test Access Port (TAP) Connection13

3.1.3 Catastrophic Thermal Protection .... 13

3.1.4 Unused Signals .............................. 13

3.1.5 Signal State in Low Power States... 13

3.2 Power Supply Requirements.................... 14

3.2.1 Decoupling Recommendations....... 14

3.2.2 Voltage Planes ............................... 14

3.3 System Bus Clock and Processor Clocking15

7.1 Description............................................... 65

7.1.1 Quick Start Enable.......................... 65

7.1.2 System Bus Frequency................... 65

7.1.3 APIC Disable .................................. 65

7.2 Clock Frequencies and Ratios.................. 65

8. PROCESSOR INTERFACE............................ 66

8.1 Alphabetical Signal Reference ................. 66

8.2 Signal Summaries.................................... 72

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MOBILE PENTIUM^®II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHz, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

LIST OF FIGURES

PAGE

Figure 1.1 Signal Groups of a Mobile Pentium^®II

Processor-Based System .................... 1

Figure 2.1 Clock Control States............................. 5

Figure 3.1 Ramp Rate Requirement..................... 13

Figure 3.2 PLL LC Filter ...................................... 14

Figure 3.3 Generic Clock Waveform.................... 30

Figure 3.4 Valid Delay Timings............................ 31

Figure 3.5 Setup and Hold Timings ..................... 31

Figure 3.6 Reset and Configuration Timings........ 32

Figure 3.7 Power-On Reset Timings.................... 33

Figure 3.8 Test Timings (Boundary Scan) ........... 34

Figure 3.9 Test Reset Timings............................. 34

Figure 3.10 Quick Start/Deep Sleep Timing......... 35

Figure 3.11 Stop Grant/Sleep/Deep Sleep Timing36

Figure 4.1 BCLK Generic Clock Waveform ......... 38

Figure 4.2 GTL+ Receiver Ringback Tolerance.... 39

Figure 4.3 Maximum Acceptable GTL+

Overshoot/Undershoot Waveform for

the Mobile Pentium® II Processor at

400 MHz ............................................ 41

Figure 4.4 Non-GTL+ Signal Ringback and Settling

Limit................................................... 42

Figure 5.1 Micro-PGA Package-Top and Side

View................................................... 45

Figure 5.2 Micro-PGA Package - Bottom View.... 46

Figure 5.3 Surface-Mount BGA Package - Top and

Side View........................................... 48

Figure 5.4 Surface-Mount BGA Package - Bottom

View................................................... 49

Figure 5.5 Pin/Ball Map - Top View ..................... 50

Figure 6.1 Technique for Measuring Case

Temperature...................................... 64

Figure 8.1 PWRGOOD Relationship at Power-On70

iv

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MOBILE PENTIUM II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

LIST OF TABLES

PAGE

Table 2.1 VTOL, CMOS and Open Drain Signal

Table 3.19 TAP Signal AC Specifications............ 28

Table 3.20 Quick Start/Deep Sleep AC

Characteristics..................................... 4

Table 2.2 Clock State Characteristics.................... 7

Table 2.3 Mobile Pentium II Processor CPUID .... 9

Table 2.4 Mobile Pentium II Processor CPUID

Cache and TLB Descriptors................. 9

Table 3.1 System Signal Groups......................... 11

Table 3.2 Recommended Resistors for Open Drain

Signals............................................... 12

Table 3.3 LC Filter Specifications........................ 15

Table 3.4 Core Frequency to System Bus Ratio

Configuration ..................................... 15

Table 3.5 Absolute Maximum Ratings for Mobile

Pentium II Processor at 400 MHz .... 16

Table 3.6 Absolute Maximum Ratings for Mobile

Pentium II Processor at 366 MHz and

Specifications..................................... 29

Table 3.21 Stop Grant/Sleep/Deep Sleep AC

Specifications..................................... 29

Table 4.1 BCLK Signal Quality Specifications...... 37

Table 4.2 Low Power GTL+ Signal Group Ringback

Specification for the Mobile Pentium® II

Processor .......................................... 39

Table 4.3. GTL+ Signal Group

Overshoot/Undershoot Tolerance at the

Processor Core for the Mobile

Pentium® II Processor at

400 MHz ............................................ 40

Table 4.4 Signal Ringback Specifications for Non-

GTL+ Signals for the Mobile Pentium®

Below................................................. 17

Table 3.7 Power Specifications for Mobile

Pentium® II Processor at 400 MHz.... 18

Table 3.8 Power Specifications for Mobile

Pentium® II Processor at 366 MHz and

Below................................................. 19

Table 3.9 Power Specifications for Low Voltage

Pentium® II Processor....................... 20

Table 3.10 Low Power GTL+ Signal Group DC

Specifications .................................... 21

Table 3.11. Low Power GTL+ Bus DC

II Processor at 400 MHz..................... 43

Table 4.5 Signal Ringback Specifications for Non-

GTL+ Signals for the Mobile Pentium®

II Processor at 366 MHz and Below... 43

Table 5.1 Micro-PGA Package Mechanical

Specifications..................................... 44

Table 5.2 Surface-Mount BGA Package

Specifications..................................... 47

Table 5.3 Signal Listing in Order by Pin/Ball

Number.............................................. 51

Table 5.4 Signal Listing in Order by Signal Name 57

Table 5.5 Voltage and No-Connect Ball/Pin

Locations ........................................... 61

Table 6.1 Mobile Pentium II Processor (0.18 m)

Power Specifications.......................... 62

Table 6.2 Thermal Diode Interface....................... 63

Table 6.3. Thermal Diode Specifications ............. 63

Table 8.1 Input Signals........................................ 73

Table 8.2 Output Signals ..................................... 74

Table 8.3 Input/Output Signals (Single Driver)..... 74

Table 8.4 Input/Output Signals (Multiple Driver)... 75

Specifications .................................... 21

Table 3.12 Clock, APIC, TAP, CMOS and Open-

Drain Signal Group DC Specifications

for the Mobile Pentium® II Processor at

400 MHz ............................................ 22

Table 3.13 Clock, APIC, TAP, CMOS and Open-

Drain Signal Group DC Specifications

for the Mobile Pentium® II Processor at

366 MHz and Below........................... 23

Table 3.14 System Bus Clock AC Specifications. 24

Table 3.15 Valid Mobile Pentium II Processor

Frequencies....................................... 25

Table 3.16 Low Power GTL+ Signal Groups AC

Specifications .................................... 25

Table 3.17 CMOS and Open-Drain Signal Groups

AC Specifications .............................. 26

Table 3.18 Reset Configuration AC Specifications27

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MOBILE PENTIUM II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

64-bit high performance system bus. The integrated

L2 cache is designed to help improve performance;

1. INTRODUCTION

it complements the system bus by providing critical

data faster and reducing total system power

consumption. The Mobile Pentium® II processor’s

64-bit wide Low Power Gunning Transceiver Logic

(GTL+) system bus is compatible with the 440BX

AGPSet and provides a glue-less, point-to-point

interface for an I/O bridge/memory controller.

Figure 1.1 shows the various parts of a Mobile

Pentium II processor-based system and how the

Mobile Pentium II processor connects to them.

The Mobile Pentium® II processor is now offered at

400 MHz, 366 MHz, 333 MHz, 300PE MHz, and

266PE MHz, with a system bus speed of 66 MHz.

The Mobile Pentium® II processor at 400 MHz in

Micro-PGA and BGA packages are the first mobile

processors manufactured in 0.18 m technology.

Processors at frequencies 366 MHz and below are

manufactured in 0.25 m processing technology.

The Mobile Pentium® II processor consists of a

processor core with an integrated L2 cache and a

Thermal

Sensor

Mobile

Pentium® II

Processor

TAP

System

Bus

DRAM

443BX

North Bridge

PCI

OR

PIIX4E/M

South Bridge

System

Controller

V0000-05

ISA/EIO

Figure 1.1 Signal Groups of a Mobile Pentium^®II Processor-Based System

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the name of the signal) it is in an electrical low state.

1.1 Overview

Otherwise, signals are driven in an electrical high

state when they are asserted. In state machine

diagrams, a signal name in a condition indicates the

condition of that signal being asserted. If the signal

name is preceded by a ‘!’ symbol, then it indicates

the condition of that signal not being asserted. For

example, the condition ‘!STPCLK# and HS’ is

equivalent to ‘the active low signal STPCLK# is

unasserted (i.e., it is at 1.5V for the 400 MHz, and

2.5V for the 366 MHz and below) and the HS

condition is true.’ The symbols ‘L’ and ‘H’ refer

respectively to electrical low and electrical high

signal levels. The symbols ‘0’ and ‘1’ refer

respectively to logical low and logical high signal

levels. For example, BD[3:0] = ‘1010’ = ‘HLHL’

refers to a hexadecimal ‘A’, and D[3:0]# = ‘1010’ =

‘LHLH’ also refers to a hexadecimal ‘A’.

•

Performance improved over existing mobile

processors

•

Supports the Intel Architecture with Dynamic

Execution

Supports the Intel Architecture MMX

technology

Integrated Intel Floating-Point Unit

compatible with the IEEE 754 standard

•

Integrated primary (L1) instruction and data

caches

•

4-way set associative, 32-byte line size,

1 line per sector

16-Kbyte instruction cache and 16-Kbyte

writeback data cache

Cacheable range programmable by

processor programmable registers

1.3

References

•

Integrated second level (L2) cache

Pentium^®II Processor at 233 MHz, 266 MHz, 300

MHz and 333 MHz (Order Number 243335)

•

4-way set associative, 32-byte line size, 1

line per sector

•

Operates at full core speed

Pentium^®II Processor Developer’s Manual

(Order Number 243502)

256-Kbyte, ECC protected cache data array

4 Gbyte cacheable range

CKDM66-M Clock Driver Specification

Low Power GTL+ system bus interface

(Contact your Intel Field Sales Representative)

•

64-bit data bus, 66-MHz operation

Uniprocessor, two loads only (processor and

I/O bridge/memory controller)

CK97 Clock Driver Specification

(Contact your Intel Field Sales Representative)

•

Short trace length and low capacitance

allows for single ended termination

Intel Architecture Software Developer’s Manual

(Order Number 243193)

•

Voltage reduction technology

Volume I: Basic Architecture

(Order Number 243190)

Volume II: Instruction Set Reference

(Order Number 243191)

Advanced processor clock control

•

Quick Start for low power, low exit latency

clock “throttling”

•

Deep Sleep mode for extremely low power

dissipation

Volume III: System Programming Guide

(Order Number 243192)

•

Thermal diode for measuring processor

temperature

Mobile Pentium II Processor (0.18 m)I/O Buffer

Models, IBIS Format (Available in electronic form;

contact your Intel Field Sales Representative)

1.2

Terminology

Mobile Pentium^®II Processor System Bus Layout

Guideline (Order Number 243672-001)

In this document a ‘#’ symbol following a signal

name indicates that the signal is active low. This

means that when the signal is asserted (based on

2

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MOBILE PENTIUM II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

Mobile Pentium^®II Processor Mechanical and

Thermal Design Guide (Order Number 243671-001)

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MOBILE PENTIUM^®II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHz, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

2. MOBILE PENTIUM^®II PROCESSOR

FEATURES

Pull-up/pull-down recommendation for almost

all signals

CMOS signal DC specifications

CMOS signal AC specifications

VTOL pin impedance

2.1 Feature Differences between the

Mobile Pentium^®II Processor at

400 MHz and Mobile Pentium^®II

Processor at 366 MHz and below

Core voltages, V_CCand V_CCP

Power specifications

CPUID

CMOS/Open Drain signal voltage tolerance

Table 2.1 VTOL, CMOS and Open Drain Signal Characteristics

Mobile Pentium® II

Processor

VTOL Pin

CMOS/Open Drain Signal

Voltage Tolerance (V_CMOS

)

Trip Voltage (V_TRIP

)

400 MHz

Short to Vss

1.5V

2.5V

0.75V

366 MHz and below High Impedance

1.25V

not in mobile systems. Performing state transitions

not shown in Figure 2.1 is neither recommended nor

supported.

2.2 Power Management

2.2.1

Clock Control Architecture

The Mobile Pentium II processor clock control

architecture (Figure 2.1) has been optimized for

leading edge “Deep Green” desktop and mobile

computer designs.

The clock control architecture consists of seven

different clock states: Normal, Auto Halt, Stop

Grant, Quick Start, HALT/Grant Snoop, Sleep and

Deep Sleep states. The Stop Grant and Quick Start

clock states are mutually exclusive, i.e., a strapping

option on signal A15# chooses which state is

entered when the STPCLK# signal is asserted.

Strapping the A15# signal to ground at Reset

enables the Quick Start state; otherwise, asserting

the STPCLK# signal puts the processor into the

Stop Grant state. The Stop Grant state has a higher

power level than the Quick Start state and is

designed for SMP platforms. The Quick Start state

has a much lower power level, but it can only be

used in uniprocessor platforms. Table 2.2 provides

clock state characteristics (power numbers based

on estimates for a Mobile Pentium II processor at

400 MHz and 366 MHz), which are described in

detail in the following sections.

The Auto Halt state provides a low power clock state

that can be controlled through the software

execution of the HLT instruction. The Quick Start

state provides a very low power, low exit latency

clock state that can be used for hardware controlled

“idle” computer states. The Deep Sleep state

provides an extremely low power state that can be

used for “Power-on Suspend” computer states,

which is an alternative to shutting off the processor’s

power. Compared to the Pentium processor exit

latency of 1 msec, the exit latency of the Deep

Sleep state has been reduced to 30 sec in the

Mobile Pentium II processor. The Stop Grant and

Sleep states shown in Figure 2.1 are intended for

use in “Deep Green” desktop and server systems —

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STPCLK# and

QSE and SGA

Quick

Normal

HS=false

Start

(!STPCLK# and !HS)

or RESET#

HLT and

halt bus cycle

STPCLK# and

QSE and SGA

BCLK

stopped

halt

break

!STPCLK#

and HS

BCLK on

and QSE

STPCLK# and

!QSE and SGA

Auto

Halt

HS=true

Snoop

serviced occurs

Snoop

Deep

Sleep

(!STPCLK#

and !HS) or

stop break

!STPCLK#

and HS

Snoop

occurs

Snoop

serviced

STPCLK# and

!QSE and SGA

Snoop

occurs

Stop

Grant

HALT/Grant

Snoop

serviced

SLP#

BCLK on

and !QSE

BCLK

stopped

!SLP# or

RESET#

Sleep

V0001-00

NOTES: halt break - A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#

HLT - HLT instruction executed

HS - Processor Halt State

QSE - Quick Start State Enabled

SGA - Stop Grant Acknowledge bus cycle issued

Stop break - BINIT#, FLUSH#, RESET#

Figure 2.1 Clock Control States

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be serviced when the processor returns to the

Normal state. Only one occurrence of each interrupt

event will be latched. A transition back to the

Normal state can be made by the de-assertion of

the STPCLK# signal, or the occurrence of a stop

break event (a BINIT#, FLUSH# or RESET#

assertion).

2.2.2

Normal State

The Normal state of the processor is the normal

operating mode where the processor’s internal clock

is running and the processor is actively executing

instructions.

2.2.3

Auto Halt State

The processor will return to the Stop Grant state

after the completion of a BINIT# bus initialization

unless STPCLK# has been de-asserted. RESET#

assertion will cause the processor to immediately

initialize itself, but the processor will stay in the Stop

Grant state after initialization until STPCLK# is

deasserted. If the FLUSH# signal is asserted, the

processor will flush the on-chip caches and return to

the Stop Grant state. A transition to the Sleep state

can be made by the assertion of the SLP# signal.

This is a low power mode entered by the processor

through the execution of the HLT instruction. The

power level of this mode is similar to the Stop Grant

state. A transition to the Normal state is made by a

halt break event (one of the following signals going

active: NMI, INTR, BINIT#, INIT#, RESET#,

FLUSH# or SMI#).

Asserting the STPCLK# signal while in the Auto Halt

state will cause the processor to transition to the

Stop Grant or Quick Start state, where a Stop Grant

Acknowledge bus cycle will be issued. Deasserting

STPCLK# will cause the processor to return to the

Auto Halt state without issuing a new Halt bus cycle.

While in the Stop Grant state, assertions of SMI#,

INIT#, INTR and NMI will be latched by the

processor. These latched events will not be serviced

until the processor returns to the Normal state. Only

one of each event will be recognized upon return to

the Normal state.

The SMI# interrupt is recognized in the Auto Halt

state. The return from the System Management

Interrupt (SMI) handler can be to either the Normal

state or the Auto Halt state. See the Intel^®

Architecture Software Developer’s Manual, Volume

III: System Programmer’s Guide for more

information. No Halt bus cycle is issued when

returning to the Auto Halt state from System

Management Mode (SMM).

2.2.5

QUICK START State

This is a mode entered by the processor with the

assertion of the STPCLK# signal when it is

configured for the Quick Start state (via the A15#

strapping option). In the Quick Start state the

processor is only capable of acting on snoop

transactions generated by the system bus priority

device. Because of its snooping behavior, Quick

Start can only be used in a Uniprocessor (UP)

configuration.

The FLUSH# signal is serviced in the Auto Halt

state. After the on-chip and off-chip caches have

been flushed, the processor will return to the Auto

Halt state without issuing

Transitions in the A20M# and PREQ# signals are

recognized while in the Auto Halt state.

a Halt bus cycle.

A transition to the Deep Sleep state can be made by

stopping the clock input to the processor.

A

transition back to the Normal state (from the Quick

Start state) is made only if the STPCLK# signal is

deasserted.

2.2.4

STOP GRANT State

The processor enters this mode with the assertion

of the STPCLK# signal when it is configured for

Stop Grant state (via the A15# strapping option).

The processor is still able to respond to snoop

requests and latch interrupts. Latched interrupts will

While in this state the processor is limited in its

ability to respond to input. It is incapable of latching

any interrupts, servicing snoop transactions from

symmetric bus masters or responding to FLUSH# or

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BINIT# assertions. While the processor is in the

progress while the processor is in the Quick Start

state.

Quick Start state, it will not respond properly to any

input signal other than STPCLK#, RESET# or

BPRI#. If any other input signal changes, then the

behavior of the processor will be unpredictable. No

serial interrupt messages may begin or be in

RESET# assertion will cause the processor to

immediately initialize itself, but the processor will

stay in the Quick Start state after initialization until

STPCLK# is deasserted.

Table 2.2 Clock State Characteristics

Clock State

Normal

Exit Latency

Power

Varies

1.25 W

Snooping?

Yes

System Uses

N/A

Normal program execution

Auto Halt

Approximately 10 bus clocks

Yes

S/W controlled entry idle

mode

Stop Grant

Quick Start

Approximately 10 bus clocks

1.25 W

Yes

H/W controlled entry/exit

mobile throttling

Through snoop, to

HALT/Grant Snoop state:

immediate

0.5 W

H/W controlled entry/exit

mobile throttling

Through STPCLK#, to Normal

state: 8 bus clocks

HALT/Grant A few bus clocks after the end Not specified

Yes

No

Supports snooping in the low

power states

Snoop

of snoop activity.

Sleep

To Stop Grant state 10 bus

clocks

0.5 W

H/W controlled entry/exit

desktop idle mode support

Deep Sleep

30 sec

150 mW

No

H/W controlled entry/exit

powered-on suspend support

NOTE: Not 100% tested. Specified at 50°C by design/characterization.

2.2.6

HALT/GRANT SNOOP State

snoop has been serviced, the processor will return

to its previous state. If the HALT/Grant Snoop state

is entered from the Quick Start state, then the input

signal restrictions of the Quick Start state still apply

in the HALT/Grant Snoop state, except for those

signal transitions that are required to perform the

snoop.

The processor will respond to snoop transactions on

the system bus while in the Auto Halt, Stop Grant or

Quick Start state. When a snoop transaction is

presented on the system bus the processor will

enter the HALT/Grant Snoop state. The processor

will remain in this state until the snoop has been

serviced and the system bus is quiet. After the

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The input signal restrictions for the Deep Sleep

state are the same as for the Sleep state, except

that RESET# assertion will result in unpredictable

behavior.

2.2.7

SLEEP State

The Sleep state is a very low power state in which

the processor maintains its context and the phase-

locked loop (PLL) maintains phase lock. The Sleep

state can only be entered from the Stop Grant state.

After entering the Stop Grant state, the SLP# signal

can be asserted, causing the processor to enter the

Sleep state. The SLP# signal is not recognized in

the Normal or Auto Halt states.

2.2.9

Operating System Implications of

Quick Start and Sleep States

There are a number of architectural features of the

Mobile Pentium^®II processor that are not available

when the Quick Start state is enabled or do not

function in the Quick Start or Sleep state as they do

in the Stop Grant state. These features are part of

the time-stamp counter and performance monitor

counters. The time-stamp counter and the

performance monitor counters are not guaranteed to

count in the Quick Start or Sleep states.

The processor can be reset by the RESET# signal

while in the Sleep state. If RESET# is driven active

while the processor is in the Sleep state then SLP#

and STPCLK# must immediately be driven inactive

to ensure that the processor correctly initializes

itself.

Input signals (other than RESET#) may not change

while the processor is in the Sleep state or

transitioning into or out of the Sleep state. Input

signal changes at these times will cause

unpredictable behavior. Thus, the processor is

incapable of snooping or latching any events in the

Sleep state.

2.3

Low Power GTL+

The Mobile Pentium^®II processor system bus

signals use a variation of the low voltage swing GTL

signaling technology. The Mobile Pentium II

processor system bus specification is similar to the

Pentium II processor system bus specification,

which is a version of GTL with enhanced noise

margins and less ringing. The Mobile Pentium II

processor system bus specification reduces system

cost and power consumption by raising the

termination voltage and termination resistance and

changing the termination from dual ended to single

ended. Because the specification is different from

the standard GTL specification and from the

Pentium II processor GTL+ specification, it is

referred to as Low Power GTL+.

While in the Sleep state, the processor can enter its

lowest power state, the Deep Sleep state. Removing

the processor’s input clock puts the processor in the

Deep Sleep state. PICCLK may be removed in the

Sleep state.

2.2.8

Deep Sleep State

The Deep Sleep state is the lowest power mode the

processor can enter while maintaining its context.

The Deep Sleep state is entered by stopping the

BCLK input to the processor, while it is in the Sleep

or Quick Start state. For proper operation, the BCLK

input should be stopped in the low state.

The Pentium II processor GTL+ system bus

depends on incident wave switching and uses flight

time for timing calculations of the GTL+ signals. The

Low Power GTL+ system bus is short and lightly

loaded. With Low Power GTL+ signals, timing

calculations are based on capacitive derating.

Analog signal simulation of the system bus including

trace lengths is highly recommended to ensure that

there are no significant transmission line effects.

Contact your field sales representative to receive

the IBIS models for the Mobile Pentium II processor.

The processor will return to the Sleep or Quick Start

state from the Deep Sleep state when the BCLK

input is restarted. Due to the PLL lock latency, there

is a 30 sec delay after the clocks have started

before this state transition happens. PICCLK may

be removed in the Deep Sleep state. PICCLK

should be designed to turn on when BCLK turns on

when transitioning out of the Deep Sleep state.

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The GTL+ system bus of the Pentium II processor

PRDY# and RESET#. These two signals connect to

the debug port and might not meet the maximum

length requirements. If PRDY# or RESET# do not

meet the layout requirements for Low Power GTL+,

then they must be terminated using dual-ended

termination at 120 . Higher resistor values can be

used if simulations show that the signal quality

specifications in Section 4 are met.

was designed to support high-speed data transfers

with multiple loads on a long bus that behaves like a

transmission line. However, in a mobile system, the

system bus only has two loads (the processor and

the chipset) and the bus traces are short enough

that transmission line effects are not significant. It is

possible to change the layout and termination of the

system bus to take advantage of the mobile

environment using the same GTL+ I/O buffers. The

benefit is that it reduces the number of terminating

resistors in half and substantially reduces the AC

and DC power dissipation of the system bus. Low

Power GTL+ uses GTL+ I/O buffers but only two

loads are allowed. The trace length is limited and

the bus is terminated at one end only. Since the

system bus is small and lightly loaded, it behaves

like a capacitor, and the GTL+ I/O buffers behave

like high-speed open-drain buffers. With a 66-MHz

bus frequency, the pull-up would be 120 . If 100

2.4

Mobile Pentium^®II Processor

CPUID

The Mobile Pentium II processor has the same

CPUID family and model number as some

Celeron™ processors. The Mobile Pentium II

processor can be distinguished from these Celeron

processors by looking at the stepping number and

the CPUID cache descriptor information. A Mobile

Pentium II processor has a stepping number in the

range of 0AH to 0FH (0AH to 0CH for the 400 MHz,

0DH to 0FH for the 366 MHz and below) and an L2

cache descriptor of 042H (256-Kbyte L2 cache). If

the stepping number is less than 0AH or the L2

cache descriptor is not 042H then the processor is a

Celeron processor. The L2 cache must be properly

initialized for the L2 cache descriptor information to

be correct. After a power-on RESET, or when the

CPUID instruction is executed, the EAX register

contains the values shown in Table 2.3. After the L2

cache is initialized, the CPUID cache/TLB

descriptors will be the values shown in Table 2.4.

termination resistors are used rather than 120

then 20% more power will be dissipated in the

termination resistors. 120 termination is

recommended to conserve power.

,

Refer to the Mobile Pentium^®II Processor System

Bus Layout Guideline (Order Number 243672-001)

for details on laying out the Low Power GTL+

system bus.

2.3.1

GTL+ Signals

Two signals of the system bus can potentially not

meet the Low Power GTL+ layout requirements:

Table 2.3 Mobile Pentium II Processor CPUID

Type [13:12] Family [11:8] Model [7:4]

Reserved [31:14]

Stepping [3:0]

0DH– 0FH (400 MHz)

X

0

6

0AH – 0CH (366 MHz and below)

Table 2.4 Mobile Pentium II Processor CPUID Cache and TLB Descriptors

01H, 02H, 03H, 04H, 08H, 0CH, 42H

Cache and TLB Descriptors

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All Low Power GTL+ signals are synchronous with

3. ELECTRICAL SPECIFICATIONS

3.1 Processor System Signals

the BCLK signal. All TAP signals are synchronous

with the TCK signal except TRST#. All CMOS input

signals can be applied asynchronously.

Table 3.1 lists the processor system signals by type.

Table 3.1 System Signal Groups

Signals

Group Name

Low Power GTL+ Input

Low Power GTL+ Output

Low Power GTL+ I/O

BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#

PRDY#

A[35:3]#, ADS#, AERR#⁵, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#,

BPM[1:0]#, BREQ0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#,

LOCK#, REQ[4:0]#, RP#

CMOS Input ^{1, 2}

A20M#, BSEL, FLUSH#, IGNNE#, INIT#, INTR, NMI, PREQ#, PWRGOOD,

SLP#, SMI#, STPCLK#

Open Drain Output ²

Clock ³

FERR#, IERR#, VTOL

BCLK

APIC Clock ²

APIC I/O ²

PICCLK

PICD[1:0]

Thermal Diode

TAP Input ²

THERMDA, THERMDC

TCK, TDI, TMS, TRST#

TDO

TAP Output ²

Power/Other ⁴

EDGECTRLN, NC, PLL1, PLL2, TESTHI, TESTHI2, TESTHI3, TESTLO, V_CC,

V_CCP, V_REF, V_SS

NOTES:

1. See Section 8 for information on the PWRGOOD signal.

2. Except for the 1.6V tolerant VTOL, these signals are tolerant to 1.5V for the 400 MHz, and 2.5V tolerant

for the 366 MHz and below. See Table 3.2 for the recommended pull-up resistor.

3. BCLK is a 2.5V tolerant signal.

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4. V_CCis the power supply for the core logic.

PLL1 and PLL2 are the power supply for the PLL analog section.

V_CCPis the power supply for the CMOS voltage references.

V_REFis the voltage reference for the Low Power GTL+ input buffers.

V_SSis system ground.

5. The AERR# processor bus pin is removed as a processor feature for the 400 MHz. The pin must still be

terminated to V_CCthrough a 120 pull-up resistor. But the processor must not be configured to drive or

observe the pin.

The CMOS and TAP inputs can be driven from

ground to V_CMOS. The TAP outputs are open

drain and should be pulled up to V_CMOSusing

resistors with the values shown in Table 3.2. If

open drain drivers are used for input signals, then

they should also be pulled up to V_CMOSusing

resistors with the values shown in Table 3.2.

Table 3.2 Recommended Resistors for Open Drain Signals

Recommended

Resistor Value (

Open Drain Signal ¹

)

150 pull-up

680 pull-up

1K pull-up

TDI, TDO, TESTHI3 ²

STPCLK#

INIT#, TCK, TESTHI, TESTHI2, TESTHI3 ², TMS

TRST#

680 - 1K pull-down

1.5K pull-up (400 MHz)

A20M#, FERR#, FLUSH#, IERR#, IGNNE#, INTR, NMI, PREQ#,

PWRGOOD, SLP#, SMI#, VTOL

4.7K pull-up (366 MHz and

Below)

NOTE:

1. Refer to Section 3.1.4 for the required pull-up or pull-down resistors for signals that are not being used.

2. The TESTHI3 signal must be pulled up to V_CCusing a 150 resistor on 400 MHz processors. On

366 MHz and below the resistor may be between 150 and 1K

.

3.1.1

Power Sequencing Requirements

The V_CCpower plane must not rise too fast. At least

200 sec (T_R) must pass from the time that V_CCis at

10% of its nominal value until the time that V_CCis at

90% of its nominal value (See Figure 3.1).

The Mobile Pentium^®II processor has no power

sequencing requirements. It is recommended that

all of the processor power planes rise to their

specified values within one second of each other.

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thermal diode to protect the processor and the

system against excessive temperatures.

3.1.4

Unused Signals

All signals named NC must be unconnected. All

signals named TESTLO must be pulled down to

V_SS, or tied directly to V_SS. All signals named

TESTHI or TESTHI3 must be pulled up to V_CCwith

a resistor. All signals named TESTHI2 must be

pulled up to V_CCPwith a resistor. Each TESTHI and

TESTHI2 signal must have an individual, 1k pull-

up resistor. The TESTHI3 signals can share a single

pull-up of 150 for the 400 MHz processor and

150 to 1K for 366 MHz and below.

V_cc

90%V_cc(nominal)

10%V_cc(nominal)

Volts

T_R

Time

Figure 3.1 Ramp Rate Requirement

Test Access Port (TAP) Connection

Unused Low Power GTL+ inputs, outputs and bi-

directional signals should be individually connected

to V_CCwith 120 pull-up resistors. Unused CMOS

3.1.2

active low inputs should be connected to V_CMOS

Unused active high inputs should be connected to

V_SSUnused open-drain outputs should be

unconnected. If the processor is configured to enter

the Quick Start state rather than the Stop Grant

state, then the SLP# signal should be connected to

V_CMOS. When tying any signal to power or ground, a

resistor will allow for system testability. For unused

signals, it is suggested that 1k resistors be used

for pull-ups and for pull-downs.

.

The TAP interface is an implementation of the

IEEE 1149.1 (“JTAG”) standard. Due to the voltage

levels supported by the TAP interface, it is

recommended that the Mobile Pentium II processor

and the other 1.5V/2.5V JTAG specification

compliant devices be last in the JTAG chain after

any devices with 3.3V or 5V JTAG interfaces within

the system. A translation buffer should be used to

reduce the TDO output voltage of the last 3.3/5V

device down to the V_CMOSrange that the Mobile

Pentium II processor can tolerate. Multiple copies of

TCK, TMS, and TRST# must be provided, one for

each voltage level.

.

PICCLK and PICD[1:0] must be tied to V_SSwith a

1k resistor. BSEL must be connected to V_SS.

A Debug Port and connector may be placed at the

start and end of the JTAG chain containing the

processor, with TDI to the first component coming

from the Debug Port and TDO from the last

component going to the Debug Port. There are no

requirements for placement of the Mobile Pentium II

processor in the JTAG chain, except for those that

are dictated by voltage requirements of the TAP

signals.

3.1.5

Signal State in Low Power States

3.1.5.1 System Bus Signals

All of the system bus signals have Low Power GTL+

input, output or input/output drivers. Except when

servicing snoops, the system bus signals are tri-

stated and pulled up by the termination resistors.

Snoops are not permitted in the Sleep and Deep

Sleep states.

3.1.3

Catastrophic Thermal Protection

3.1.5.2 CMOS and Open-Drain Signals

The Mobile Pentium II processor does not support

catastrophic thermal protection or the THERMTRIP#

signal. An external thermal sensor should use the

The CMOS input signals are allowed to be in either

the logic high or low state when the processor is in a

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low power state. In the Auto Halt and Stop Grant

states these signals are allowed to toggle. These

input buffers have no internal pull-up or pull-down

resistors and system logic can use CMOS or open-

drain drivers to drive them.

strong function of the power supply design. Contact

your Intel Field Sales Representative for tools to

help determine how much decoupling is required.

The processor core power plane (V_CC) should have

at least twenty-six 0.1 F high frequency decoupling

capacitors. The CMOS voltage reference power

The open-drain output signals have open drain

drivers and external pull-up resistors are required.

plane (V_CCP) requires 50 to 100 F of bulk

decoupling and at least eight 0.1 F high frequency

decoupling capacitors.

One of the two output signals (IERR#) is

a

catastrophic error indicator and is tri-stated (and

pulled-up) when the processor is functioning

normally. The FERR# output can be either tri-stated

or driven to V_SSwhen the processor is in a low

power state, depending on the condition of the

floating point unit. Since this signal is a DC current

path when it is driven to V_SS, it is recommended that

the software clears or masks any floating point error

condition before putting the processor into the Deep

Sleep state.

For the Low Power GTL+ pull-up resistors, one

0.1 F high frequency decoupling capacitor is

recommended per resistor pack. There should be

no more than eight pull-up resistors per resistor

pack. The Low Power GTL+ voltage reference

power plane (V_REF) should have at least three 0.1 F

high frequency decoupling capacitors.

3.2.2

Voltage Planes

3.1.5.3 Other Signals

All V_CCand V_SSballs/pins must be connected to the

appropriate voltage plane. All V_CCPand V_REF

balls/pins must be connected to the appropriate

traces on the system electronics.

The system bus clock (BCLK) must be driven in all

of the low power states except the Deep Sleep

state.

In addition to the main V_CC, V_CCPand V_SSpower

supply signals, PLL1 and PLL2 provide isolated

power to the PLL section. PLL1 and PLL2 should be

connected according to Figure 3.2. Do not connect

PLL2 directly to V_SS. A separate power supply

should be used to generate V_CCPto isolate the PLL

from processor core noise. Table 3.3 contains the

requirements for C1 and L1.

3.2

Power Supply Requirements

3.2.1

Decoupling Recommendations

The amount of bulk decoupling required to meet the

processor voltage tolerance requirements is

a

L1

PLL1

V_CCP

C1

V0027-00

PLL2

Figure 3.2 PLL LC Filter

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Table 3.3 LC Filter Specifications

Symbol

Parameter

Min

Max

Unit

Notes

C1

LC Filter Capacitance

47

F

30% tolerance, 1 max series resistance,

~2nH series inductance

L1

LC Filter Inductance

20

47

H

low-Q type choke, 30% tolerance, 1.5

max series resistance, 50mA current,

self-resonant frequency >10 MHz

3.3

System Bus Clock and

Processor Clocking

The Mobile Pentium® II processor (0.18 m) at 400

MHz is implemented with the Bus Fraction Locking

scheme, which allows the processor to operate at

the marked core frequency only. The bus ratio

configuration signals are not effective. However, if

desired, the signals can be set accordingly to Table

3.4.

The 2.5V BCLK clock input directly controls the

operating speed of the system bus interface. All

system bus timing parameters are specified with

respect to the rising edge of the BCLK input. The

Mobile Pentium II processor core frequency is a

multiple of the BCLK frequency.

Table 3.4 Core Frequency to System Bus Ratio Configuration

Processor Core Frequency to

NMI

INTR IGNNE# A20M#

Powerup Configuration

[25:22]

System Bus Frequency Ratio

4/1 (266 MHz)

L

H

L

H

L

H

L

0010

0110

0000

0100

1011

9/2 (300 MHz)

5/1 (333 MHz)

H

L

11/2 (366 MHz)

H

L

6/1 (400 MHz)

The mobile Pentium II processors at 366 MHz and

below frequencies are implemented with a Bus

fraction Limiting scheme. A multiplexer is required

between the system electronics and the processor

to drive the bus ratio configuration signals during

Reset. Figure 3.6 and Table 3.18 describe the

timing requirements for this operation. The 443BX

CRESET# signal has suitable timing to control the

multiplexer. After RESET# and PWRGOOD are

asserted, the multiplexer logic must guarantee that

the bus ratio configuration signals encode one of the

bus ratios in Table 3.4 and that the bus ratio

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corresponds to a core frequency at or below the

marked core frequency for the processor. The

selected bus ratio is visible to software in the Power-

On configuration register, see Section 7.2 for

details.

not be changed during Deep Sleep state (see

Section 2.2.8).

3.4

Maximum Ratings

Table 3.5 and Table 3.6 contains the Mobile

Pentium II processor stress ratings. Functional

operation at the absolute maximum and minimum is

neither implied nor guaranteed. The processor

should not receive a clock while subjected to these

conditions. Functional operating conditions are

provided in the AC and DC tables. Extended

exposure to the maximum ratings may affect device

reliability. Furthermore, although the processor

contains protective circuitry to resist damage from

static electric discharge, one should always take

precautions to avoid high static voltages or electric

fields.

Multiplying the bus clock frequency is necessary to

increase performance while allowing for easier

distribution of signals within the system. Clock

multiplication within the processor is provided by the

internal Phase Lock Loop (PLL), which requires a

constant frequency BCLK input. During Reset, or on

exit from the Deep Sleep state, the PLL requires

some amount of time to acquire the phase of BCLK.

This time is called the PLL lock latency, which is

specified in Section 3.6, AC timing parameters T18

and T47. Except for the 400 MHz processor, the

system bus frequency ratio can be changed when

RESET# is active, assuming that all Reset

specification are met. The BCLK frequency should

Table 3.5 Absolute Maximum Ratings for Mobile Pentium II Processor at 400 MHz

Symbol

T_Storage

Parameter

Storage Temperature

Min

–40

Max

85

Unit

°C

V

Notes

Note1

V_CC(Abs)

V_CCP

Supply Voltage with respect to V_SS

–0.5

–0.3

2.0

CMOS Reference Voltage with respect to V_SS

GTL+ Buffer DC Input Voltage with respect to V_SS

1.5V Buffer DC Input Voltage with respect to V_SS

BLCK Buffer DC Input Voltage with respect to V_SS

V

V_IN

–0.3 V_CC+ 0.5

V

Note 2

Note 3

V_IN15

–0.3

2.0

3.3

V

V_BLCK

V

NOTES:

1. The shipping container is only rated for 65°C.

2. Parameter applies to the Low Power GTL+ signal groups only.

3. Parameter applies to CMOS, Open-Drain, APIC and TAP bus signal groups only.

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Table 3.6 Absolute Maximum Ratings for Mobile Pentium II Processor at 366 MHz and Below

Symbol

T_Storage

Parameter

Storage Temperature

Min

–40

Max

85

Unit

°C

V

Notes

Note1

V_CC(Abs)

V_CCP

Supply Voltage with respect to V_SS

–0.5

–0.3

3.0

CMOS Reference Voltage with respect to V_SS

GTL+ Buffer DC Input Voltage with respect to V_SS

2.5V Buffer DC Input Voltage with respect to V_SS

V

V_IN

–0.3 V_CC+ 0.7

–0.3 3.3

V

Note 2

Note 3

V_BLCK

V

NOTES:

1. The shipping container is only rated for 65°C.

2. Parameter applies to the Low Power GTL+ signal groups only.

3. Parameter applies to CMOS, Open-Drain, APIC and TAP bus signal groups only.

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specifications for case temperature, clock frequency

and input voltages. Care should be taken to read all

notes associated with each parameter.

3.5

DC Specifications

Table 3.7 through Table 3.12 list the DC

specifications for the Mobile Pentium II processor .

Specifications are valid only while meeting

Table 3.7 Power Specifications for Mobile Pentium® II Processor at 400 MHz

T_CASE= 0 to T_CASE,max; V_CC= 1.5V ±115mV; V_CCP= 1.5V ±90mV

Symbol

V_CC

Parameter

V_CCfor core logic

V_CCfor CMOS voltage references

Min

Typ

Max

1.615

1.590

7.10

Unit

V

Notes

±115 mV

1.385

1.410

1.500

V_CCP

I_CC

V

±90 mV

Note 3

I_CCfor V_CCat core

frequency

@ 400 MHz

A

I_CCP

Current for V_CCP

100

mA

A

Notes 1, 2, 3

Note 3

I_CC,SG

Processor Stop Grant and

Auto Halt current

1.29

I_CC,QS

Processor Quick Start and

Sleep current

994

700

20

mA

Note 3

I_CC,DSLPProcessor Deep Sleep leakage

current

Note 3

dI_CC/dt

V_CCpower supply current slew rate

A/ s

Notes 4, 5

NOTES:

1. I_CCPis the current supply for the CMOS voltage references.

2. Not 100% tested. Specified by design/characterization.

3. I_CCx,maxspecifications are specified at V_CC,max, V_CCP,maxand 100°C and under maximum signal loading

conditions.

4. Based on simulations and averaged over the duration of any change in current. Use to compute the

maximum inductance and reaction time of the voltage regulator. This parameter is not tested.

5. Maximum values specified by design/characterization at nominal V_CCand V_CCP

.

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Table 3.8 Power Specifications for Mobile Pentium® II Processor at 366 MHz and Below

T

_CASE= 0 to T_CASE,max; V_CC= 1.6V ±135mV; V_CCP= 1.8V ±90mV

Symbol

Parameter

Min

Typ

Max

Unit

Notes

±135 mV

V_CC

V_CCof core logic for regular voltage

processors

1.465

1.600

1.735

V

V_CC,LP

V_CCP

I_CC

V_CCwhen I_CC< 300 mA

1.465

1.710

1.600

1.800

1.805

1.890

V

+205/-135 mV ¹

1.8V ±90 mV

Note 4

V_CCfor CMOS voltage references

I_CCfor V_CCat core

frequency

@ 366 MHz

@ 333 MHz

8.87

7.95

7.49

6.63

A

@ 300PE MHz

@ 266PE MHz

I_CCP

Current for V_CCP

75

mA

Notes 2, 3, 4

Note 4

I_CC,SG

Processor Stop Grant and

Auto Halt current

1190

I_CC,QS

Processor Quick Start and

Sleep current

880

650

20

mA

Note 4

I_CC,DSLPProcessor Deep Sleep leakage

current

Note 4

dI_CC/dt

V_CCpower supply current slew rate

A/ s

Notes 5, 6

NOTES:

1. A higher VCC,MAX is allowed when the processor is in a low power state to enable high efficiency, low

current modes in the power regulator.

2. I_CCPis the current supply for the CMOS voltage references.

3. Not 100% tested. Specified by design/characterization.

4. I_CCx,maxspecifications are specified at V_CC,max, V_CCP,maxand 100°C and under maximum signal loading

conditions.

5. Based on simulations and averaged over the duration of any change in current. Use to compute the

maximum inductance and reaction time of the voltage regulator. This parameter is not tested.

6. Maximum values specified by design/characterization at nominal V_CCand V_CCP

.

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Table 3.9 Power Specifications for Low Voltage Pentium® II Processor

T_CASE= 0 to T_CASE,max; V_CC= 1.5V ±135mV; V_CCP= 1.8V ±90mV

Symbol Parameter

Min

Typ

Max

Unit

Notes

V_CC

Vcc of core logic for 266PE MHz at

1.365

1.500

1.635

V

±135 mV

low voltage

V_CC,LP

V_CCP

I_CC

V_CCwhen I_CC< 300 A

V_CCfor CMOS voltage references

1.365

1.710

1.500

1.800

1.705

1.890

5.90

V

A

+205/-135 mV ¹

1.8V ±90 mV

Note 4

I_CCfor V_CCat core frequency

@ 266PE MHz at low voltage

I_CCP

Current for V_CCP

75

mA

Notes 2, 3, 4

Note 4

I_CC,SG

Processor Stop Grant and

Auto Halt current

940

I_CC,QS

Processor Quick Start and

Sleep current

630

400

20

mA

Note 4

I_CC,DSLPProcessor Deep Sleep leakage

current

Note 4

dI_CC/dt

V_CCpower supply current slew rate

A/ s

Notes 5, 6

NOTES:

1. A higher V_CC,MAXis allowed when the processor is in a low power state to enable high efficiency, low

current modes in the power regulator.

2. I_CCPis the current supply for the CMOS voltage references.

3. Not 100% tested. Specified by design/characterization.

4. I_CCx,maxspecifications are specified at V_CC,max, V_CCP,maxand 100°C and under maximum signal loading

conditions.

5. Based on simulations and averaged over the duration of any change in current. Use to compute the

maximum inductance and reaction time of the voltage regulator. This parameter is not tested.

6. Maximum values specified by design/characterization at nominal V_CCand V_CCP

.

The signals on the Mobile Pentium II processor

system bus are included in the Low Power GTL+

signal group. These signals are specified to be

terminated to V_CC. The DC specifications for these

signals are listed in Table 3.10; the termination and

signals are listed in Table 3.11. The Mobile Pentium

II processor requires external termination and a

V_REF. Refer to Mobile Pentium^®II Processor System

Bus Layout Guideline (Order Number 243672-001)

for full details of system V_TTand V_REFrequirements.

reference

voltage

specifications

for

these

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Table 3.10 Low Power GTL+ Signal Group DC Specifications

T_CASE= 0 to T_CASE,max; V_CC= 1.5V ± 115mV, V_CC= 1.6V ± 135mV, or 1.5V ± 135mV; V_CCP= 1.5V ± 90mV,

or V_CCP= 1.8V ± 90mV

Symbol

V_IL

Parameter

Input Low Voltage

Input High Voltage

Output High Voltage

Min

–0.3

Max

⁵/₉V_TT– 0.2

V_CC

Unit

V

Notes

Table 3.11 ¹

See

V_IH

⁵/₉V_TT+ 0.2

—

V

Note 1

V_OH

—

V

See V_TTmax in

Table 3.11

.

R_ON

I_L

Output Low Drive Strength

Leakage Current for inputs

35

ohms

±100

±30

A

Note 2

I_LO

Leakage Current for outputs

& I/Os

366 MHz and below ³

400 MHz ³

I_LO

Leakage Current for outputs

and I/Os

±100

A

NOTES:

1. V_REFworst case, not nominal. Noise on V_REFshould be accounted for.

2. (0 V_INV_CC).

3. (0 V_outV_CC).

Table 3.11. Low Power GTL+ Bus DC Specifications

T_CASE= 0 to T_CASE,max; V_CC= 1.5V ± 115mV, V_CC= 1.6V ± 135mV, or 1.5V ± 135mV; V_CCP= 1.5V ± 90mV,

or V_CCP= 1.8V ± 90mV

Symbol

V_TT

Parameter

Min

Typ

V_CC

Max

Unit

V

Notes

Bus Termination Voltage

Input Reference Voltage

V_CC,MIN

V_CC,MAX

Note 1

±2% ²

V_REF

⁵/₉V_TT– 2%

⁵/₉V_TT

⁵/₉V_TT+ 2%

V

NOTES:

1. The intent is to use the same power supply for V_CCand V_TT

.

2. V_REFfor the system logic should be created from V_TTby a voltage divider.

The CMOS, Open-Drain and TAP signals are

designed to interface at V_CMOSto allow connection

to other devices. BCLK is a 2.5V clock. The DC

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specifications for these signals are listed in Table

3.12.

Table 3.12 Clock, APIC, TAP, CMOS and Open-Drain Signal Group DC Specifications for

the Mobile Pentium® II Processor at 400 MHz

T_CASE= 0 to T_CASE,max; V_CC= 1.5V ± 115mV, V_CCP= 1.5V ± 90mV

Symbol

Parameter

Input Low Voltage

Min

–0.3

1.135

1.8

Max

0.6

Unit

V

Notes

V_IL

V_IL,BCLKInput Low Voltage, BCLK

V_IHInput High Voltage

V_IH,BCLKInput High Voltage, BCLK

0.7

V

1.615

2.625

0.4

V

V_OL

V_OH

I_OL

I_L

Output Low Voltage

Output High Voltage

Output Low Current

V

Note 1

N/A

1.615

14

V

All outputs are open-drain

mA

A

Leakage Current for inputs,

outputs, and I/Os

±100

Note 2

NOTES:

1. Parameter measured at 14 mA.

2. (0 V_IN/OUT1.615V).

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Table 3.13 Clock, APIC, TAP, CMOS and Open-Drain Signal Group DC Specifications for

the Mobile Pentium® II Processor at 366 MHz and Below

T_CASE= 0 to T_CASE,max; V_CC= 1.6V ± 135mV, or V_CC= 1.5V ± 115mV, V_CCP= 1.8V ± 90mV

Symbol

Parameter

Input Low Voltage

Min

–0.3

Max

0.7

Unit

V

Notes

V_IL

V_IL,BCLKInput Low Voltage, BCLK

V_IHInput High Voltage

V_IH,BCLKInput High Voltage, BCLK

–0.3

0.7

V

1.700

1.800

2.625

0.4

V

V_OL

V_OH

I_OL

Output Low Voltage

V

Note 1

Output High Voltage

N/A

2.625

14

V

All outputs are open-drain

Output Low Current

mA

A

I_L

Input Leakage Current

Output and I/O Leakage Current

±100

±30

Note 2

I_LO

A

NOTES:

1. Parameter measured at 14 mA.

2. (0 V_IN/OUT2.625V).

3.17 contains the CMOS and Open-Drain signal

groups specifications; Table 3.18 contains timings

for the reset conditions; Table 3.19 contains the

TAP specifications; and Table 3.20 and Table 3.21

3.6

AC Specifications

3.6.1

System Bus, Clock, APIC, TAP, CMOS

and Open-Drain AC Specifications

contain

the

power

management

timing

specifications.

Table 3.14 through Table 3.21 provide AC

specifications associated with the Mobile Pentium II

processor. The AC specifications are divided into

the following categories: Table 3.14 contains the

system bus clock specifications; Table 3.15

contains the processor core frequencies; Table 3.16

contains the Low Power GTL+ specifications; Table

All system bus AC specifications for the Low Power

GTL+ signal group are relative to the rising edge of

the BCLK input at 1.25V. All Low Power GTL+

timings are referenced to V_REFfor both ‘0’ and ‘1’

logic levels unless otherwise specified.

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Table 3.14 System Bus Clock AC Specifications¹

T_CASE= 0 to T_CASE,max; V_CC= 1.5V ± 115mV, V_CC= 1.6V ± 135mV, or 1.5V ± 135mV; V_CCP= 1.5V ± 90mV,

or V_CCP= 1.8V ± 90mV

Symbol

Parameter

System Bus Frequency

BCLK Period

Min

Typ

66.67

15

Max

Unit

MHz

ns

Figure

Notes

3.3

T1

T2

Note 2

BCLK Period Stability

BCLK High Time

BCLK Low Time

±250

ps

Notes 3, 4

@>1.8V

3.3

T3

5.0

ns

T4

ns

@<0.7V

T5

BCLK Rise Time

BCLK Fall Time

0.175

0.875

ns

(0.9V – 1.6V) ⁴

(1.6V – 0.9V) ⁴

T6

ns

NOTES:

1. All AC timings for Low Power GTL+ and CMOS signals are referenced to the BCLK rising edge at 1.25V.

All CMOS signals are referenced at V_TRIP

.

2. The BCLK period allows a +0.5ns tolerance for clock driver variation.

3. Not 100% tested. Specified by design/characterization.

4. Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a

component of BCLK skew between devices.

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Table 3.15 Valid Mobile Pentium II Processor Frequencies

T_CASE= 0 to T_CASE,max; V_CC= 1.5V ± 115mV, V_CC= 1.6V ± 135mV, or 1.5V ± 135mV; V_CCP= 1.5V ± 90mV,

or V_CCP= 1.8V ± 90mV

BCLK Frequency (MHz)

Frequency Multiplier

Core Frequency (MHz)

66.67

4

9/2

5

266.67

300.00

333.33

366.67

400.00

11/2

6

NOTE: Because of the Bus Fraction Locking scheme implemented in this processor, the frequency

multiplier is internally set to a fixed value of six (6). The processor operates only at a core

frequency of 400 MHz.

Table 3.16 Low Power GTL+ Signal Groups AC Specifications¹

R_TT= 120 terminated to V_CC; V_REF= 5/9 V_CC; load = 0pF

T

_CASE= 0 to T_CASE,max; V_CC= 1.5V ± 115mV, V_CC= 1.6V ± 135mV, or 1.5V ± 135mV; V_CCP= 1.5V ± 90mV,

or V_CCP= 1.8V ± 90mV

Symbol

Parameter

Min

0.00

2.98

0.90

1

Max

Unit

ns

Figure

3.4

Notes

T7

T8

T9

Low Power GTL+ Output Valid Delay

Low Power GTL+ Input Setup Time

Low Power GTL+ Input Hold Time

RESET# Pulse Width

7.78

3.5

ns

Notes 2, 3

Note 4

3.5

ns

3.6 3.7

T10

ms

Note 5

NOTES:

1. All AC timings for Low Power GTL+ signals are referenced to the BCLK rising edge at 1.25V. All Low

Power GTL+ signals are referenced at V_REF

.

2. RESET# can be asserted (active) asynchronously, but must be de-asserted synchronously.

3. Specification is for a minimum 0.40V swing.

4. Specification is for a maximum 1.0V swing.

5. After V_CC, V_CCPand BCLK become stable and PWRGOOD is asserted.

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Table 3.17 CMOS and Open-Drain Signal Groups AC Specifications^{1, 2}

T_CASE= 0 to T_CASE,max; V_CC= 1.5V ± 115mV, V_CC= 1.6V ± 135mV, or 1.5V ± 135mV; V_CCP= 1.5V ± 90mV,

or V_CCP= 1.8V ± 90mV

Symbol

Parameter

Min

Max

Unit

Figure

Notes

3.4

T14

CMOS Input Pulse Width, except

PWRGOOD

2

BCLKs

Active and

Inactive

states

3.7

T15

PWRGOOD Inactive Pulse Width

10

BCLKs

Notes 3, 4

NOTES:

1. All AC timings for CMOS and Open-Drain signals are referenced to the BCLK rising edge at 1.25V. All

CMOS and Open-Drain signals are referenced at V_TRIP

.

2. Minimum output pulse width on CMOS outputs is 2 BCLKs.

3. When driven inactive, or after V_CC, V_CCPand BCLK become stable. PWRGOOD must remain below

V

_IL,maxfrom Table 3.12 until all the voltage planes meet the voltage tolerance specifications in Table 3.7,

and BCLK has met the BCLK AC specifications in Table 3.14 for at least 10 clock cycles. PWRGOOD

must rise glitch-free and monotonically to V_CMOS

.

4. If the BCLK signal meets its AC specification within 150ns of turning on then the PWRGOOD Inactive

Pulse Width specification (T15) is waived and BCLK may start after PWRGOOD is asserted. PWRGOOD

must still remain below V_IL,maxuntil all the voltage planes meet the voltage tolerance specifications.

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Table 3.18 Reset Configuration AC Specifications

T_CASE= 0 to T_CASE,max; V_CC= 1.5V ±115mV; V_CCP= 1.5V ±90mV

Symbol

Parameter

Min

Max

Unit

Figure

Notes

Before

3.5 3.6

T16

Reset Configuration Signals (A[15:5]#,

BREQ0#, FLUSH#, INIT#, PICD0)

Setup Time

4

BCLKs

deassertion of

RESET#

3.5 3.6

3.7

T17

T18

Reset Configuration Signals (A[15:5]#,

BREQ0#, FLUSH#, INIT#, PICD0)

Hold Time

2

1

20

BCLKs

ms

After clock that

deasserts

RESET#

Reset Configuration Signals (A20M#,

IGNNE#, INTR, NMI) Setup Time

Before

deassertion of

RESET# ¹

3.7

T19

T20

Reset Configuration Signals (A20M#,

IGNNE#, INTR, NMI) Delay Time

5

BCLKs

After assertion of

RESET# ²

3.5 3.7

Reset Configuration Signals (A20M#,

IGNNE#, INTR, NMI) Hold Time

2

20

After clock that

deasserts

RESET#

NOTES:

1. At least 1 ms must pass after PWRGOOD rises above V_IH,minfrom Table 3.12, and BCLK meets its AC

timing specification, until RESET# may be deasserted.

2. For a Reset, the clock ratio defined by these signals must be a safe value (their final value or a lower

multiplier) within this delay after RESET# is asserted unless PWRGOOD is inactive (below V_IL,max).

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Table 3.19 TAP Signal AC Specifications¹

T_CASE= 0 to T_CASE,max; V_CC= 1.5V ±115mV; V_CCP= 1.5V ±90mV

Symbol

T30

Parameter

TCK Frequency

Min

—

Max

16.67

—

Unit

MHz

ns

Figure

Notes

T31

TCK Period

60

3.3

T32

T33

T34

T35

TCK High Time

TCK Low Time

TCK Rise Time

TCK Fall Time

25.0

ns

1.135V ²

0.60V ²

5.0

(0.60V-1.135V) ^2,3

(1.135V-0.60V) ^2,3

3.3

3.9

3.8

T36

T37

T38

T39

T40

T41

T42

T43

TRST# Pulse Width

40.0

5.0

ns

Asynchronous ²

Note 4

TDI, TMS Setup Time

TDI, TMS Hold Time

14.0

1.0

Note 4

TDO Valid Delay

10.0

25.0

Notes 5, 6

TDO Float Delay

Notes 2, 5, 6

Notes 5, 7, 8

Notes 2, 5, 7, 8

Notes 4, 7, 8

All Non-Test Outputs Valid Delay

All Non-Test Outputs Float Delay

All Non-Test Inputs Setup Time

All Non-Test Inputs Hold Time

2.0

5.0

T44

13.0

NOTES:

1. All AC timings for TAP signals are referenced to the TCK rising edge at V_TRIP. All CMOS signals are

referenced at V_TRIP

.

2. Not 100% tested. Specified by design/characterization.

3. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 MHz.

4. Referenced to TCK rising edge.

5. Referenced to TCK falling edge.

6. Valid delay timing for this signal is specified into 150 terminated to V_CMOSand 0pF of external load. For

real system timings these specifications must be derated for external capacitance at 105 ps/pF.

7. Non-Test Outputs and Inputs are the normal output or input signals (except TCK, TRST#, TDI, TDO and

TMS). These timings correspond to the response of these signals due to boundary scan operations.

8. During Debug Port operation use the normal specified timings rather than the TAP signal timings.

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Table 3.20 Quick Start/Deep Sleep AC Specifications

T_CASE= 0 to T_CASE,max; V_CC= 1.5V ± 115mV, V_CC= 1.6V ± 135mV, or 1.5V ± 135mV; V_CCP= 1.5V ± 90mV,

or V_CCP= 1.8V ± 90mV

Symbol

T45

Parameter

Min

Max

Unit

BCLKs

ns

Figure

3.10

Stop Grant Cycle Completion to Clock Stop

Stop Grant Cycle Completion to Input Signals Stable

Deep Sleep PLL Lock Latency

100

T46

0

T47

30

s

T48

STPCLK# Hold Time from PLL Lock

0

8

ns

T49

Input Signal Hold Time from STPCLK# Deassertion

BCLKs

NOTE: Input signals other than RESET# and BPRI# must be held constant in the Quick Start state.

Table 3.21 Stop Grant/Sleep/Deep Sleep AC Specifications

T

_CASE= 0 to T_CASE,max; V_CC= 1.5V ± 115mV, V_CC= 1.6V ± 135mV, or 1.5V ± 135mV; V_CCP= 1.5V ± 90mV,

or V_CCP= 1.8V ± 90mV

Symbol

Parameter

Min

Max

Unit

BCLKs

ns

Figure

3.11

T50

T51

T52

T54

T55

T56

SLP# Signal Hold Time from Stop Grant Cycle Completion

SLP# Assertion to Input Signals Stable

SLP# Assertion to Clock Stop

100

0

10

0

BCLKs

ns

SLP# Hold Time from PLL Lock

STPCLK# Hold Time from SLP# Deassertion

Input Signal Hold Time from SLP# Deassertion

10

BCLKs

NOTE: Input signals other than RESET# must be held constant in the Sleep state.

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Figure 3.3 through Figure 3.11 are to be used in conjunction with Table 3.14 through Table 3.21.

T

r2

T

h

T

r1

V_IH

1.6V

0.9V

CLK

V_TRIP

V_IL

T

f1

T

f2

T

l

T

p

D0003-02

NOTES:

T_r1

T_f1

T_h

T_l

=

T5, T_r2= T34 (Rise Time)

T6, T_f2= T35 (Fall Time)

T3, T32 (High Time)

T4, T33 (Low Time)

T1, T31 (Period)

T_p

Figure 3.3 Generic Clock Waveform

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CLK

T

x

T

x

Signal

V

Valid

T

pw

D0004-00

NOTES:

T_x

T_pw

V

=

T7, T11 (Valid Delay)

T14 (Pulse Width)

V_REFfor Low Power GTL+ signals; V_TRIPfor CMOS, Open-Drain, and TAP signal groups

Figure 3.4 Valid Delay Timings

CLK

T

s

T

h

Signal

V Valid

D0005-00

NOTES:

T_s

T_h

V

=

T8, T12 (Setup Time)

T9, T13 (Hold Time)

V_REFfor Low Power GTL+ signals; V_TRIPfor CMOS, Open-Drain, and TAP signal groups

Figure 3.5 Setup and Hold Timings

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BCLK

T

u

T

t

RESET#

T

v

T

x

y

z

Configuration

(A20M#, IGNNE#,

INTR, NMI)

Valid

Safe

T

w

Configuration

(A[15:5], BREQ0#,

FLUSH#, INIT#,

PICD0)

D0006-01

NOTES:

T_t

=

T9 (Low Power GTL+ Input Hold Time)

T8 (Low Power GTL+ Input Setup Time)

T10 (RESET# Pulse Width)

T16 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0)

Setup Time)

T_u

T_v

T_w

=

T_x

=

T17 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0)

Hold Time)

T20 (Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Hold Time)

T19 (Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Delay Time)

T18 (Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Setup Time)

T_y

T_z

=

Figure 3.6 Reset and Configuration Timings

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BCLK

V

,

CCP,

V

,

CC

REF

V

V_IH,min

PWRGOOD

V_IL,max

T

a

T

b

RESET#

T

c

Configuration

(A20M#, IGNNE#,

INTR, NMI)

Valid Ratio

D0007-01

NOTES:

T_a

T_b

T_c

=

T15 (PWRGOOD Inactive Pulse Width)

T10 (RESET# Pulse Width)

T20 (Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Hold Time)

Figure 3.7 Power-On Reset Timings

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TCK

T

w

v

TDI, TMS

V_TRIP

T

s

r

Input

Signals

T

u

x

TDO

T

z

y

Output

Signals

D0008-02

NOTES:

T_r

=

T43 (All Non-Test Inputs Setup Time)

T44 (All Non-Test Inputs Hold Time)

T40 (TDO Float Delay)

T37 (TDI, TMS Setup Time)

T38 (TDI, TMS Hold Time)

T39 (TDO Valid Delay)

T41 (All Non-Test Outputs Valid Delay)

T42 (All Non-Test Outputs Float Delay)

T_s

T_u

T_v

T_w

T_x

T_y

T_z

Figure 3.8 Test Timings (Boundary Scan)

V_TRIP

TRST#

T

q

D0009-02

NOTE:

T_q

=

T36 (TRST# Pulse Width)

Figure 3.9 Test Reset Timings

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Normal

Quick Start

Running

Deep Sleep

Normal

Quick Start

Running

BCLK

T_v

STPCLK#

T_y

T_x

CPU bus

SLP#

stpgnt

T_z

T_w

Changing

Compatibility

Signals

Frozen

V0010-00

NOTES:

T_v

T_w

T_x

T_y

T_z

=

T45 (Stop Grant Acknowledge Bus Cycle Completion to Clock Shut Off Delay)

T46 (Setup Time to Input Signal Hold Requirement)

T47 (Deep Sleep PLL Lock Latency)

T48 (PLL lock to STPCLK# Hold Time)

T49 (Input Signal Hold Time)

Figure 3.10 Quick Start/Deep Sleep Timing

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Stop

Grant

Stop

Grant

Normal

Running

Sleep

T_v

Deep Sleep

Sleep

Normal

BCLK

Running

STPCLK#

T_y

CPU bus

SLP#

stpgnt

T_w

T_x

T_t

T_u

T_z

Compatibility

Signals

Changing

Frozen

V0011-00

NOTES:

T_t

=

T50 (Stop Grant Acknowledge Bus Cycle Completion to SLP# Assertion Delay)

T51 (Setup Time to Input Signal Hold Requirement)

T52 (SLP# assertion to clock shut off delay)

T47 (Deep Sleep PLL lock latency)

T54 (SLP# Hold Time)

T55 (STPCLK# Hold Time)

T_u

T_v

T_w

T_x

T_y

T_z

T56 (Input Signal Hold Time)

Figure 3.11 Stop Grant/Sleep/Deep Sleep Timing

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4. SYSTEM SIGNAL SIMULATIONS

4.1

System Bus Clock (BCLK)

Signal Quality Specifications

Many scenarios have been simulated to generate

a set of Low Power GTL+ processor system bus

layout guidelines which are available in the

Mobile Pentium^®II Processor System Bus Layout

Guideline (Order Number 243672-001). Systems

must be simulated using the IBIS models to

determine if they are compliant with this

specification. There are different IBIS models for

the 400 MHz and for the 366 MHz and below

Table 4.1 and Figure 4.1 show the signal quality

for the system bus clock (BCLK) signal as

measured at the processor. The timings

illustrated in Figure 4.1 are taken from Table

3.14. BCLK is a 2.5V clock.

Table 4.1 BCLK Signal Quality Specifications

Symbol

V1

Parameter

Min

Max

Unit

V

Figure

4.1

Notes

V_IL,BCLK

V_IH,BCLK

0.7

Note 1

4.1

V2

1.8

–0.7

–0.8

1.8

V

V3

V_INAbsolute Voltage Range

Rising Edge Ringback

3.5

V

Undershoot, Overshoot ²

Undershoot, Overshoot ³

Absolute Value ⁴

4.1

V3

V

4.1

V4

V

Absolute Value ⁴

4.1

V5

Falling Edge Ringback

0.7

4

V

4.1

BCLK rising/falling slew rate

0.8

V/ns

NOTES:

1. BCLK must rise/fall monotonically between V_IL,BCLKand V_IH,BCLK

.

2. 400 MHz processor only.

3. 366 MHz and below.

4. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling)

absolute voltage the BCLK signal can dip back to after passing the V_IH,BCLK(rising) or V_IL,BCLK(falling)

voltage limits.

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T3

V3

V4

V2

V1

V5

T6

V3

T5

T4

V0012-00

Figure 4.1 BCLK Generic Clock Waveform

has additional specifications on maximum allowable

overshoot and undershoot for a given duration of

time, as listed in Table 4.3. Contact your Intel Field

4.2

Low Power GTL+ Signal Quality

Specifications

Sales representative for

OVERSHOOT_CHECKER

OVERSHOOT_CHECKER determines if a specific

waveform meets the overshoot/undershoot

specification. Figure 4.3 shows the overshoot/

undershoot waveform.

a

copy of the

tool.

Table 4.2 and Figure 4.2 illustrate the GTL+ signal

quality specifications for the Mobile Pentium II

processor. Refer to the Pentium^®II Processor

Developer’s Manual for the GTL+ buffer

specification.

The Mobile Pentium® II processor at 400 MHz also

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Table 4.2 Low Power GTL+ Signal Group Ringback Specification for

the Mobile Pentium® II Processor

Symbol

Parameter

Min

100

1

Unit

mV

ns

Figure

4.2

Notes

Notes 1, 2

Overshoot

4.2

Minimum Time at High

Amplitude of Ringback

Final Settling Voltage

Notes 1, 2

Notes 1, 2, 3

Notes 1, 2

4.2

-100

100

N/A

mV

ns

4.2

Duration of Sequential Ringback

NOTES:

1. Specified for the edge rate of 0.3 – 0.8 V/ns. See Figure 4.2 for the generic waveform.

2. All values determined by design/characterization.

3. Ringback below V_REF+100 mV is not authorized during low to high transitions. Ringback above V_REF

100mV is not authorized during high to low transitions.

-

V_IH,BCLK

V_REF+0.2V

V_REF

V_REF-0.2V

V_IL,BCLK

V_start

Clock

V0014-00

Time

NOTE: High-to-low case is analogous.

Figure 4.2 GTL+ Receiver Ringback Tolerance

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Table 4.3. GTL+ Signal Group Overshoot/Undershoot Tolerance at the Processor Core ^{1, 4, 5}for

the Mobile Pentium® II Processor at 400 MHz

Pulse Duration

0.1 ns

Allowed Overshoot ²

Allowed Undershoot ³

2.0V

1.9V

1.8V

-0.35V

-0.25V

-0.15V

0.3 ns

1.0 ns

NOTES:

1. Under no circumstances should the GTL+ signal voltage ever exceed 2.0V maximum with respect to

ground or -2.0V minimum with respect to V_CCT(i.e., V_CCT- 2.0V) under operating conditions.

2. Ring-backs below V_CCTcannot be subtracted from overshoots. Lesser undershoot does not allocate

longer or larger overshoot.

3. Ring-backs above ground cannot be subtracted from undershoots. Lesser overshoot does not allocate

longer or larger undershoot.

4. System designers are encouraged to follow Intel provided GTL+ layout guidelines.

5. All values are specified by design characterization, and are not tested.

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Time Dependent Overshoot

.1ns

.3ns

1ns

2.0v Max

1.9v

Vtt

1.8v

ꢂ

ꢀ

ꢁ

ꢀ

ꢁ

ꢂ

Vss

-.15v

-.25v

-.35v Min

.1ns

.3ns

1ns

Time Dependent Undershoot

NOTE:

The total overshoot/undershoot budget for one clock cycle is fully consumed by the

,

or waveforms.

Figure 4.3 Maximum Acceptable GTL+ Overshoot/Undershoot Waveform for

the Mobile Pentium® II Processor at 400 MHz

reliability of the processor. There are three signal

4.3

Non-Low Power GTL+ Signal

Quality Specifications

quality parameters defined: overshoot/ undershoot,

ringback and settling limit. The ringback and settling

limit signal quality parameters are shown in Figure

4.4 for non-GTL+ signal groups. The overshoot and

undershoot specifications for non-GTL+ signals are

the same as for GTL+ signals; see Section 4.2.

Signals driven to the Mobile Pentium II processor

should meet signal quality specifications to ensure

that the processor reads data properly and that

incoming signals do not affect the long-term

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Settling Limit

Overshoot

V_CMOS

Rising-Edge

Ringback

Falling-Edge

Ringback

Settling Limit

V_LO

V_SS

Undershoot

V0015-01

Time

Figure 4.4 Non-GTL+ Signal Ringback and Settling Limit

However, excessive ringback is the dominant

detrimental system timing effect resulting from

4.3.1

Overshoot and Undershoot Guidelines

overshoot/undershoot

(i.e.,

violating

the

Overshoot (or undershoot) is the absolute value of

the maximum voltage above the nominal high

voltage or below V_SS. The overshoot/undershoot

guideline limits transitions beyond V_CCor V_SSdue to

the fast signal edge rates. The processor can be

damaged by repeated overshoot events on V_CMOS

tolerant buffers if the charge is large enough (i.e., if

the overshoot is great enough).

overshoot/undershoot guideline will make it difficult

to satisfy the ringback specification). The

overshoot/undershoot guideline is 0.7V for the 400

MHz, 0.8V for the 366 MHz and below and assumes

the absence of diodes on the input. These

guidelines should be verified in simulations without

the on-chip ESD protection diodes present because

the diodes will begin clamping the V_CMOStolerant

signals beginning at approximately 1.25V above V_CC

and 0.5V below V_SS. If the signals do not reach the

clamping voltage, then this will not be an issue. A

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system should not rely on the diodes for

overshoot/undershoot protection as this will

negatively affect the life of the components and

make meeting the ringback specification very

difficult.

4.3.2

Settling Limit Guideline

4.3.1

Ringback Specification

Settling limit defines the maximum amount of

ringing at the receiving signal that a signal may

reach before its next transition. The amount allowed

is 10% of the total signal swing (V_HI– V_LO) above

and below its final value. A signal should be within

the settling limits of its final value, when either in its

high state or low state, before its next transition.

Ringback refers to the amount of reflection seen

after signal has switched. The ringback

a

specification is the voltage to which the signal rings

back after achieving its maximum absolute value.

Excessive ringback can cause false signal detection

or extend the propagation delay. The ringback

specification applies to the input signal of each

receiving agent. Violations of the signal ringback

specification are not allowed under any

circumstances for the non-GTL+ signals.

Signals that are not within their settling limit before

transitioning are at risk of unwanted oscillations that

could jeopardize signal integrity. Simulations to

verify settling limit may be done either with or

without the input protection diodes present. Violation

of the settling limit guideline is acceptable if

simulations of 5 to 10 successive transitions do not

show the amplitude of the ringing increasing in the

subsequent transitions.

Ringback can be simulated with or without the input

protection diodes that can be added to the input

buffer model. However, signals that reach the

clamping voltage should be evaluated further. See

Table 4.4 for the signal ringback specifications for

non-GTL+ signals.

Table 4.4 Signal Ringback Specifications for Non-GTL+ Signals for

the Mobile Pentium® II Processor at 400 MHz

Input Signal Group

Transition

Maximum Ringback

Figure

(with Input Diodes Present)

4.4

Non-GTL+ Signals

0

1

0

1.135 V

0.600 V

Table 4.5 Signal Ringback Specifications for Non-GTL+ Signals for

the Mobile Pentium® II Processor at 366 MHz and Below

Input Signal Group

Transition

Maximum Ringback

Figure

(with Input Diodes Present)

4.4

Non-GTL+ Signals

0

1

0

1.700 V

0.700 V

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5. MECHANICAL SPECIFICATIONS

5.1

Dimensions of the Micro-PGA

Package

The Mobile Pentium® II processor are available in a

PPGA-B615 package (also known as Micro-PGA) or

in a PBGA-B615 package (also known as BGA).

The back of the processor die exposed on top of

both packages. This section contains information

describing the packages and the signal pin

assignments.

The Micro-PGA dimensions are given in Table 5.1,

and shown in Figure 5.1 and Figure 5.2. For

component handling, the substrate may only be

contacted within the region between the keepout

outline and the edge of the substrate.

Table 5.1 Micro-PGA Package Mechanical Specifications

Parameter Min

op of die to seating plane of the

Symbol

Max

Unit

Overall Height, t

interposer

A

3.23

3.83

mm

A₁

A₂

B

Pin length

1.25 REF

mm

Die Height

Pin Diameter

0.854 REF

0.30 REF

D

Die Substrate Width

30.85

31.15

D₁

D₂

E

Die Width

10.36 REF

32.60 REF

Package Width

Die Substrate Length

Die Length

34.85

35.15

E₁

E₂

e

17.36 REF

36.80 REF

1.27

Package Length

Pin pitch

Pin Tip Radial True Position

Pin Count

<=1.27

N

615

each

mm

Pin row A to short edge of interposer

Pin column 1 to long edge of interposer

Allowable Pressure on the Die for Thermal Solution

Package Weight

S₁

S₂

P_DIE

W

2.220 REF

1.415 REF

mm

—

689

kPa

7.5 REF

grams

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NOTE: Dimensions in parentheses are for reference only. All dimensions are in millimeters.

Figure 5.1 Micro-PGA Package-Top and Side View

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NOTE: Dimensions in parentheses are for reference only. All dimensions are in millimeters.

Figure 5.2 Micro-PGA Package - Bottom View

5.2

Dimensions of the BGA

Package

package and, and Figure 5.4 shows the bottom view

of the surface-mount package. For component

handling, the substrate may only be contacted within

the shaded region between the keepout outline and

the edge of the substrate.

The mechanical specifications for the surface-mount

package are provided in Table 5.2. Figure 5.3

shows the top and side views of the surface-mount

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Table 5.2 Surface-Mount BGA Package Specifications

Symbol

Parameter

Overall Height, as delivered (USE THIS FOR 5.2)

Substrate Height, as delivered

Die Height

Min

Max

Unit

mm

each

mm

kPa

grams

A

2.29

2.79

A₁

A₂

b

1.50 REF

0.854 REF

0.78 REF

Ball Diameter

D

Package Width

30.85

10.36 REF

34.85 35.15

31.15

D₁

E

Die Width

Package Length

e

Ball Pitch

1.27

E₁

N

Die Length

17.36 REF

615

Ball Count

S₁

S₂

P_DIE

W

Outer Ball Center to Short Edge of Substrate

Outer Ball Center to Long Edge of Substrate

Allowable Pressure on the Die for Thermal Solution

Package Weight

1.625 REF

0.895 REF

—

689

3.71

4.52

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A₁

die

(7.0 TYP)

(Ø 0.65)

(5.0 TYP)

A₂

D

ink swatch

E

E₁

(2x 1.50)

(2x 2.032)

(2x 0.57)

(Ø 1.15)

D₁

A

substrate

keepout

outline

(2x 1.800)

0.20 REF

V0026-00

NOTE: Dimensions in parentheses are for reference only. All dimensions are in millimeters.

Figure 5.3 Surface-Mount BGA Package - Top and Side View

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Øb

e

S₂

S₁

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

e

N

M

L

K

J

H

G

F

E

D

C

B

A

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

V0025-01

NOTE: Dimensions in parentheses are for reference only. All dimensions are in millimeters.

Figure 5.4 Surface-Mount BGA Package - Bottom View

pins/balls called out. Table 5.3 lists the signals in

pin/ball number order. Table 5.4 and Table 5.5 list

5.3

Signal Listings

the signals in signal name order.

Figure 5.5 is a topside view of the ball/pin map of

the Mobile Pentium® II processor with the voltage

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1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

A

B

VSS

A35#

NC

A29#

A19#

A25#

VSS

A22#

A17#

A26#

A30#

A31#

A23#

NC

A34#

VSS

NC

VSS

NC

VSS

NC

D0#

D6#

D4#

VREF

D12#

NC

VSS

D15#

D1#

D9#

D11#

NC

VSS

D17#

D10#

VSS

D30#

NC

D5#

D2#

D14#

D20#

D23#

NC

D3#

D7#

D19#

D22#

D25#

NC

VSS

D13#

D21#

VSS

D18#

D26#

D24#

D32#

VREF

D36#

VSS

D16#

D31#

D27#

D28#

D34#

D43#

D44#

D51#

D41#

VSS

D29#

VSS

D39#

NC

VSS

D35#

D33#

NC

EDG

CTRLN

VSS

A24# TESTHI NC

C

NC

A33# RESET# BERR#

NC

D

A28#

A16#

A11#

VSS TESTLO TESTLO VSS

A20#

A21#

NC

VSS

VREF

NC

A27#

A18#

NC

VREF

A32#

NC

VSS

NC

VSS

D8#

NC

E

A12#

A3#

A8#

A7#

A13# TESTLO VSS

NC

VSS

F

A15#

A6#

A5#

VSS

A9#

A10#

A14#

AP0#

VREF

NC

D37

VCCP

G

NC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

NC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

NC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

NC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

NC

D38

NC

H

A4#

NC

D45#

D48#

D59#

D54#

D61#

DEP7#

D42#

D47#

VSS

D49#

D52#

D57#

D46#

D58#

D62#

J

TESTHI3 BNR#

RSP#

AP1#

NC

D40#

VSS

D53#

D60#

VSS

K

VSS TESTHI3 VSS

VSS TESTHI3 NC

NC

L

REQ1# BPRI# REQ4# REQ0# TESTHI NC

NC

VREF

D56#

VSS

D55#

D50#

D63#

M

N

DEFER# REQ2# TESTHI3 LOCK# TRDY#

NC

VSS

REQ3# HITM#

VSS

VREF

HIT#

NC

P

DBSY#

RP#

DRDY#

NC

DEP0# DEP3# DEP5# DEP6#

R

BREQ0# RS0#

RS2# RS1# PW RGOOD NC

NC

BPM1# VREF DEP1# DEP2# DEP4#

T

VSS

ADS# THERMDA VSS

SLP#

TDI

NC

BP3#

VSS

PRDY# BINIT#

VSS

U

AERR# VCCP THERMDC NC

NC

PICD1 PICCLK TESTHI3 BP2# BPM0#

V

BSEL

TRST#

TCK

NC

TMS

VSS

VCCP

NC

INTR PREQ# TESTHI

W

Y

VSS

NC

VSS

NC

VSS

PICD0

VSS

SMI# FERR# TESTLO NC

NC

VCCP VCCP

VSS

NMI

NC

AA

AB

AC

AD

AE

AF

STPCLK# A20M# INIT#

IERR#

VCCP

NC

TDO IGNNE#

NC

FLUSH# TESTHI2 NC

VSS TESTLO

NC

VTOL

NC

VSS

NC

VSS

NC

VSS

NC

VCCP

VSS

VCC TESTHI2 NC

NC

VSS

PLL1

NC

VSS

BCLK

PLL2

NC

V0024-04

VCC

VCCP

VSS

Other

Analog

Decoupling

Figure 5.5 Pin/Ball Map - Top View

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Table 5.3 Signal Listing in Order by Pin/Ball Number

No.

A2

Signal Name

VSS

No.

B8

Signal Name

No.

C14

Signal Name

NC

No.

D20

Signal Name

VSS

TESTHI

NC

A3

VSS

A29#

VSS

A26#

A34#

VSS

NC

B9

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

D1

D4#

D21

D22

D23

D24

E1

D32#

D28#

VSS

A4

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

C1

NC

D1#

A5

NC

D10#

D14#

D19#

D21#

D24#

D27#

D29#

D35#

A28#

VSS

A6

NC

D33#

A16#

A12#

A13#

TESTLO

VSS

A7

NC

A8

NC

E2

A9

D6#

E3

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

B1

D15#

D17#

D2#

E4

VSS

NC

E5

E6

NC

D7#

E7

A21#

VREF

A18#

A32#

NC

VSS

D0#

D13#

D26#

D31#

VSS

NC

D2

E8

D3

TESTLO

VSS

E9

VSS

D5#

D4

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

F1

D5

D6

A23#

A20#

VSS

NC

D3#

D7

NC

VSS

D18#

D16#

VSS

NC

C2

D8

D8#

C3

NC

D9

A27#

VREF

VSS

D12#

D11#

D30#

D23#

D25#

VSS

C4

A25#

A17#

A31#

A33#

RESET#

BERR#

NC

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

C5

C6

NC

VSS

EDGCTRLN

A35#

A19#

A22#

A30#

A24#

C7

NC

B2

C8

VSS

B3

C9

VREF

D9#

VREF

D34#

D39#

NC

B4

C10

C11

C12

C13

B5

NC

VSS

B6

NC

D20#

D22#

B7

NC

A11#

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Table 5.3 Signal Listing in Order by Pin/Ball Number

No.

F2

Signal Name

A3#

No.

G8

Signal Name

NC

No.

H15

Signal Name

VCC

No.

J21

Signal Name

D47#

D41#

D52#

D40#

VSS

TESTHI3

VSS

TESTHI3

NC

F3

A15#

A5#

A10#

NC

G9

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

H16

H17

H18

H19

H20

H21

H22

H23

J1

VSS

NC

J22

J23

J24

K1

F4

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

H2

F5

NC

F6

NC

F7

NC

D45#

D42#

D51#

D49#

TESTHI3

BNR#

RSP#

AP1#

VREF

NC

K2

F8

NC

K3

F9

NC

K4

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

G2

NC

K5

NC

K6

NC

J2

K7

NC

J3

K8

NC

D38#

VSS

D44#

NC

J4

K9

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

NC

J5

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

L1

NC

J6

NC

J7

NC

A7#

A4#

A9#

AP0#

NC

J8

NC

H3

J9

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

D37#

D36#

D43#

NC

H4

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

H5

H6

H7

NC

VCCP

A8#

A6#

VSS

A14#

NC

H8

NC

H9

VCC

VSS

VCC

VSS

VCC

VSS

D59#

VSS

D57#

VSS

REQ1#

G3

H10

H11

H12

H13

H14

G4

G5

NC

G6

NC

G7

NC

D48#

52

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AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

Table 5.3 Signal Listing in Order by Pin/Ball Number

No.

L2

Signal Name

No.

M8

Signal Name

NC

No.

N14

Signal Name

VCC

No.

P20

Signal Name

BPRI#

REQ4#

REQ0#

TESTHI

NC

DEP0#

DEP3#

DEP5#

DEP6#

VSS

L3

M9

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

NC

N15

N16

N17

N18

N19

N20

N21

N22

N23

N24

P1

VSS

VCC

NC

P21

P22

P23

P24

R1

L4

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

M23

M24

N1

L5

L6

NC

L7

NC

BREQ0#

RS0#

RS2#

RS1#

PWRGOOD

NC

L8

NC

DEP7#

VSS

D63#

D62#

VSS

DBSY#

RP#

DRDY#

HIT#

NC

R2

L9

VSS

R3

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

M1

M2

M3

M4

M5

M6

M7

VCC

R4

VSS

R5

VCC

NC

R6

VSS

NC

R7

NC

VCC

D61#

D56#

D50#

D58#

D60#

VSS

REQ3#

HITM#

VSS

VREF

NC

P2

R8

NC

VSS

P3

R9

VSS

VCC

P4

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

T1

VCC

NC

P5

VSS

NC

P6

VCC

NC

P7

NC

VSS

D54#

VREF

D55#

D46#

D53#

DEFER#

REQ2#

TESTHI3

LOCK#

TRDY#

NC

N2

P8

NC

VCC

N3

P9

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

NC

VSS

N4

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

VCC

N5

NC

N6

NC

N7

NC

N8

NC

BPM1#

VREF

DEP1#

DEP2#

DEP4#

VSS

N9

VSS

VCC

VSS

VCC

VSS

N10

N11

N12

N13

NC

INTEL CORPORATION

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MOBILE PENTIUM^®II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHz, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

Table 5.3 Signal Listing in Order by Pin/Ball Number

No.

T2

Signal Name

No.

U8

Signal Name

NC

No.

V15

Signal Name

VCC

No.

W23

Signal Name

ADS#

THERMDA

VSS

PICD0

VSS

T3

U9

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

V16

V17

V18

V19

V20

V21

V22

V23

W2

VSS

NC

Y1

T4

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

V2

Y2

TCK

T5

SLP#

NC

Y3

SMI#

FERR#

TESTLO

NC

T6

NC

Y4

T7

NC

Y5

T8

NC

INTR

PREQ#

TESTHI

TRST#

VSS

VCCP

NC

Y6

T9

VCC

VSS

Y7

NC

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

U1

Y8

NC

VCC

VSS

Y9

VCC

VSS

NC

W3

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

AA1

AA2

AA3

AA4

AA5

VCC

VSS

NC

W4

VCC

VSS

PICD1

PICCLK

TESTHI3

BP2#

BPM0#

BSEL

NC

W5

VCC

VSS

W6

VCC

VSS

W7

NC

W8

NC

VCC

VSS

NC

W9

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

NC

BP3#

VSS

V3

NC

V4

TMS

VCCP

NC

PRDY#

BINIT#

VSS

V5

NC

V6

NC

V7

NC

VCCP

VSS

AERR#

VCCP

THERMDC

NC

V8

NC

U2

V9

VCC

VSS

VCC

VSS

VCC

VSS

U3

V10

V11

V12

V13

V14

NC

STPCLK#

A20M#

INIT#

IERR#

NC

U4

NC

U5

TDI

NC

U6

NC

VSS

U7

NC

54

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MOBILE PENTIUM II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

Table 5.3 Signal Listing in Order by Pin/Ball Number

No.

AA6

Signal Name

NC

No.

Signal Name

NC

No.

Signal Name

NC

No.

Signal Name

NC

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AC1

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AD1

AD24

AE1

AA7

NC

VSS

NC

AA8

NC

AE2

AA9

NC

VTOL

NC

AE3

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AB1

NC

AE4

NC

VSS

VCCP

VCC

TESTHI2

NC

AE5

NC

AE6

NC

AE7

NC

AD2

AE8

NC

AD3

AE9

NC

AD4

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AF1

NC

AD5

NC

AD6

NC

FLUSH#

TESTHI2

NC

AD7

NC

AC2

AD8

NC

AC3

AD9

NC

AC4

VSS

TESTLO

NC

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

NC

AC5

NC

NMI

TDO

IGNNE#

NC

AC6

NC

AC7

NC

AB2

AC8

NC

AB3

AC9

NC

AB4

VCCP

NC

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

NC

AB5

NC

AB6

NC

AB7

NC

AB8

NC

AF2

VSS

BCLK

VSS

PLL2

AB9

NC

AF3

AB10

AB11

NC

AF4

NC

AF5

INTEL CORPORATION

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MOBILE PENTIUM^®II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHz, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

Table 5.3 Signal Listing in Order by Pin/Ball Number

No.

AF6

Signal Name

No.

Signal Name

NC

No.

Signal Name

NC

No.

Signal Name

NC

PLL1

VSS

NC

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF7

AF8

AF9

AF10

NC

56

INTEL CORPORATION

MOBILE PENTIUM II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

Table 5.4 Signal Listing in Order by Signal Name

No.

Signal

Name

Signal Buffer Type

No.

Signal

Name

Signal Buffer Type

F2

A3#

A4#

A5#

A6#

A7#

A8#

A9#

Low Power GTL+ I/O

C7

A33#

Low Power GTL+ I/O

CMOS Input

H3

F4

G3

H2

G2

H4

F5

F1

E2

E3

G5

F3

E1

C5

E9

B4

D7

E7

B5

D6

B7

C4

A6

D9

D1

A4

B6

C6

E10

A7

A34#

A35#

A20M#

ADS#

AERR#

AP0#

AP1#

BCLK

BERR#

BINIT#

BNR#

BP2#

BP3#

BPM0#

BPM1#

BPRI#

BREQ0#

BSEL

D0#

B3

AA2

T2

Low Power GTL+ I/O

Processor Clock Input

Low Power GTL+ I/O

Low Power GTL+ Input

Low Power GTL+ I/O

CMOS Input

U1

H5

A10#

A11#

A12#

A13#

A14#

A15#

A16#

A17#

A18#

A19#

A20#

A21#

A22#

A23#

A24#

A25#

A26#

A27#

A28#

A29#

A30#

A31#

A32#

J4

AF3

C9

T23

J2

U23

T20

U24

R20

L2

R1

V2

A15

C16

B18

A19

C15

A18

B15

B19

E14

D16

C17

Low Power GTL+ I/O

D1#

D2#

D3#

D4#

D5#

D6#

D7#

D8#

D9#

D10#

INTEL CORPORATION

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MOBILE PENTIUM^®II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHz, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

Table 5.4 Signal Listing in Order by Signal Name

No.

Signal

Name

Signal Buffer Type

No.

Signal

Name

Signal Buffer Type

E16

D11#

Low Power GTL+ I/O

J22

D41#

Low Power GTL+ I/O

Low Power GTL+ Input

Low Power GTL+ I/O

E15

B20

C18

B16

A22

B17

A21

C19

D18

C20

D19

E18

C21

E19

B21

C22

D22

C23

E17

B22

D21

D24

E22

C24

F21

F20

G20

E23

J24

D12#

D13#

D14#

D15#

D16#

D17#

D18#

D19#

D20#

D21#

D22#

D23#

D24#

D25#

D26#

D27#

D28#

D29#

D30#

D31#

D32#

D33#

D34#

D35#

D36#

D37#

D38#

D39#

D40#

H21

F22

G22

H20

L23

J21

J20

H23

M22

H22

J23

L24

L20

L22

M21

K23

M23

K20

M24

M20

N23

N22

P2

D42#

D43#

D44#

D45#

D46#

D47#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63#

DBSY#

DEFER#

DEP0#

DEP1#

DEP2#

DEP3#

DEP4#

M1

P20

R22

R23

P21

R24

58

INTEL CORPORATION

MOBILE PENTIUM II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

Table 5.4 Signal Listing in Order by Signal Name

No.

Signal

Name

Signal Buffer Type

No.

Signal

Name

Signal Buffer Type

P22

DEP5#

Low Power GTL+ I/O

Low Power GTL+ Control

Open Drain Output

CMOS Input

R2

RS0#

Low Power GTL+ Input

CMOS Input

P23

N20

P4

DEP6#

DEP7#

DRDY#

EDGCTRLN

FERR#

FLUSH#

HIT#

R4

R3

J3

RS1#

RS2#

RSP#

B2

T5

SLP#

Y4

Y3

SMI#

CMOS Input

AC1

P5

AA1

Y2

STPCLK#

TCK

CMOS Input

Low Power GTL+ I/O

Open Drain Output

CMOS Input

JTAG Clock Input

JTAG Input

N3

HITM#

IERR#

U5

AB1

B8

TDI

AA4

AB2

AA3

V21

M4

TDO

JTAG Output

IGNNE#

INIT#

TESTHI

TESTHI2

TESTHI3

TESTLO

THERMDA

THERMDC

TMS

GTL+ Test Input

CMOS Test Input

GTL+ Test Input

Test Input

CMOS Input

L5

INTR

CMOS Input

V23

AC2

AD4

J1

LOCK#

Low Power GTL+ I/O

CMOS Input

AA24 NMI

U21

W23

U20

AF6

AF5

T22

V22

R5

PICCLK

APIC Clock Input

Open Drain I/O

PICD0

PICD1

PLL1

K2

Open Drain I/O

K5

PLL Analog Voltage

Low Power GTL+ Output

CMOS Input

M3

U22

D3

D4

E4

PLL2

PRDY#

PREQ#

PWRGOOD

REQ0#

REQ1#

REQ2#

REQ3#

REQ4#

RESET#

RP#

Test Input

CMOS Input

Test Input

L4

Low Power GTL+ I/O

Low Power GTL+ Input

Low Power GTL+ I/O

Y5

Test Input

L1

AC5

T3

Test Input

M2

N2

Thermal Diode Anode

Thermal Diode Cathode

JTAG Input

U3

V4

L3

C8

M5

J5

TRDY#

VREF

Low Power GTL+ Input

GTL+ Reference Voltage

P3

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MOBILE PENTIUM^®II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHz, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

Table 5.4 Signal Listing in Order by Signal Name

No.

Signal

Name

Signal Buffer Type

No.

Signal

Name

Signal Buffer Type

D10

VREF

GTL+ Reference Voltage

JTAG Input

L21

VREF

GTL+ Reference Voltage

Voltage Tolerance

D15

E8

VREF

TRST#

N5

VREF

R21

E21

W2

AC21 VTOL

NOTE: Except for BCLK, the CMOS signals are 1.5V tolerant for 400 MHz; and 2.5V tolerant for 366 MHz

and below.

60

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AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

Table 5.5 Voltage and No-Connect Ball/Pin Locations

Ball Numbers

Signal

Name

NC

A10, A12, A13, A24, B9, B10, B11, B12, B13, B14, C2, C3, C10, C11, C12, C13, C14, D12, D13,

E6, E11, E12, E13, E24, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F23,

G6, G7, G8, G17, G18, G19, G23, H6, H7, H8, H17, H18, H19, J6, J7, J8, J17, J18, J19, K6, K7,

K8, K17, K18, K19, L6, L7, L8, L17, L18, L19, M6, M7, M8, M17, M18, M19, N6, N7, N8, N17, N18,

N19, P6, P7, P8, P17, P18, P19, R6, R7, R8, R17, R18, R19, T6, T7, T8, T17, T18, T19, U4, U6,

U7, U8, U17, U18, U19, V3, V6, V7, V8, V17, V18, V19, V20, W6, W7, W8, W17, W18, W19,

W20, Y6, Y7, Y8, Y17, Y18, Y19, Y20, Y21, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13,

AA14, AA15, AA16, AA17, AA18, AA19, AA20, AA21, AA22, AA23, AB3, AB5, AB6, AB7, AB8,

AB9, AB10, AB11, AB12, AB13, AB14, AB15, AB16, AB17, AB18, AB19, AB20, AB21, AB22,

AB23, AB24, AC3, AC6, AC7, AC8, AC9, AC10, AC11, AC12, AC13, AC14, AC15, AC16, AC17,

AC18, AC19, AC20, AC22, AD5, AD6, AD7, AD8, AD9, AD10, AD11, AD12, AD13, AD14, AD15,

AD16, AD17, AD18, AD19, AD20, AD21, AD22, AD23, AD24, AE8, AE9, AE10, AE11, AE12,

AE13, AE14, AE15, AE16, AE17, AE18, AE19, AE20, AE21, AE22, AE23, AE24, AF1, AF8, AF9,

AF10, AF11, AF12, AF13, AF14, AF15, AF16, AF17, AF18, AF19, AF20, AF21, AF22, AF23, AF24

VCC

G10, G12, G14, G16, H9, H11, H13, H15, J10, J12, J14, J16, K9, K11, K13, K15, L10, L12, L14,

L16, M9, M11, M13, M15, N10, N12, N14, N16, P9, P11, P13, P15, R10, R12, R14, R16, T9, T11,

T13, T15, U10, U12, U14, U16, V9, V11, V13, V15, W10, W12, W14, W16, Y9, Y11, Y13, Y15,

AD3

VCCP

VSS

F24, U2, V5, W5, Y22, Y23, AB4, AD2

A2, A3, A5, A8, A9, A11, A14, A16, A17, A20, A23, B1, B23, B24, C1, D2, D5, D8, D11, D14, D17,

D20, D23, E5, E20, G4, G9, G11, G13, G15, G21, H10, H12, H14, H16, J9, J11, J13, J15, K1, K3,

K4, K10, K12, K14, K16, K21, K22, K24, L9, L11, L13, L15, M10, M12, M14, M16, N1, N4, N9,

N11, N13, N15, N21, N24, P1, P10, P12, P14, P16, P24, R9, R11, R13, R15, T1, T4, T10, T12,

T14, T16, T21, T24, U9, U11, U13, U15, V10, V12, V14, V16, W3, W4, W9, W11, W13, W15,

W21, W22, Y1, Y10, Y12, Y14, Y16, Y24, AC4, AC23, AC24, AD1, AE1, AE2, AE3, AE4, AE5,

AE6, AE7, AF2, AF4, AF7

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MOBILE PENTIUM^®II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHz, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

During all operating environments, the processor

case temperature, T_CASEmust be within the

6. THERMAL SPECIFICATIONS

,

specified range of 0°C to 100°C. An A/D converter

attached to the thermal diode can be used to

measure the processor core temperature to ensure

compliance with this specification. The designer is

responsible for insuring that the thermal diode and

A/D converter accurately track the processor

temperature. The designer should verify this by

In order to achieve proper cooling of the processor,

a thermal solution (e.g., heat spreader, heat pipe, or

other heat transfer system) must make firm contact

to the exposed processor die. The processor die

must be clean before the thermal solution is

attached or the processor may be damaged.

correlating “sensor” output temperature with

a

thermocouple placed directly on the die surface.

Refer to Section 6.2 for more details.

Table 6.1 Mobile Pentium II Processor (0.18 m) Power Specifications

Symbol

Parameter

Thermal Design Power

Min

Typ¹

Max

Unit

Notes

TDP

@ 400 MHz

@ 366 MHz

@ 333 MHz

—

9.80

W

at 100 °C ^{2, 3}

—

13.10

11.80

11.10

9.80

W

@ 300PE MHz

@ 266PE MHz

@ 266PE MHz Low Voltage

7.90

P_SGNT

P_QS

Stop Grant and Auto Halt power

1.25

500

150

100

W

at 50°C ³

Quick Start and Sleep power

Deep Sleep power

mW

°C

P_DSLP

T_CASE

Case Temperature

0

NOTES:

1. TDP_TYPis a recommendation based on the power dissipation of the processor while executing publicly

available software under normal operating conditions at nominal voltages. Contact your Intel Field Sales

Representative for further information.

2. TDP_MAXis a specification of the total power dissipation of the processor while executing a worst-case

instruction mix under normal operating conditions at nominal voltages. It includes the power dissipated by

all of the components within the processor. Specified by design/characterization.

3. Not 100% tested or guaranteed. The power specifications are composed of the current of the processor

on the various voltage planes. These currents are measured and specified at high temperature in Table

3.10. These 50°C power specifications are determined by characterization of the processor currents at

higher temperatures.

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system electronics may use the diode to monitor the

die temperature of the processor for thermal

6.1

Thermal Diode

management purposes. Table 6.2 and Table 6.3

provide the diode interface and specifications.

The Mobile Pentium II processor has an on-die

diode that can be used to monitor the die

temperature.

A thermal sensor located on the

Table 6.2 Thermal Diode Interface

Signal Name

Ball/Pin Number

Signal Description

Thermal diode anode

Thermal diode cathode

THERMDA

THERMDC

T3

U3

Table 6.3. Thermal Diode Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Notes

Note 1

I_FW

n

Forward Bias Current

Diode Ideality Factor

5

500

A

1.0057 1.0080 1.0125

1.0000 1.0065 1.0173

Notes 2, 4, 5

Notes 3, 4, 5

n

NOTES:

1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not

support or recommend operation of the thermal diode when the processor power supplies are not within

their specified tolerance range.

2. For the 400 MHz processor. Characterized at 100°C.

3. For the 366 MHz processor and below. Characterized at 35°C.

4. Not 100% tested. Specified by design/characterization.

5. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode I/V

equation:

qV_D

I

I_O

1

nkT

e

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Attach the thermocouple bead or junction to

the center of the die on the top package

surface using highly thermally conductive

cements. Intel’s laboratory testing was done

using Omega Bond (part number: OB100).

6.2

Case Temperature

To verify that the proper T_CASE(case temperature) is

maintained for the processor, it should be measured

at the center of the die on the package top surface.

To minimize any measurement errors, the following

techniques are recommended:

Thermal

grease

provides

equivalent

temperature measurement results when used

correctly but is not as mechanically resilient as

cement.

Use 36 gauge or finer diameter K, T or J type

thermocouples. Intel’s laboratory testing was

done using a thermocouple made by Omega

(part number: 5TC-TTK-36-36).

The thermocouple should be attached at a 90°

angle as shown in Figure 6.1. A horizontal

thermocouple mount is acceptable.

V0028-00

Figure 6.1 Technique for Measuring Case Temperature

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7. PROCESSOR INITIALIZATION

AND CONFIGURATION

7.1.2

System Bus Frequency

7.1

Description

The current generation Mobile Pentium II

processor will only function with a system bus

frequency of 66 MHz, but future generations may

operate at 100 MHz. Bit position 19 of the Power-

On Configuration register indicates at which

speed a processor will run. A ‘0’ in bit 19

indicates a 66-MHz bus frequency and a ‘1’

indicates a 100-MHz bus frequency.

The Mobile Pentium^®II processor has some

configuration options that are determined by

hardware and some that are determined by

software. The processor samples its hardware

configuration at reset, on the active-to-inactive

transition of RESET#. Most of the configuration

options for the Mobile Pentium II processor are

identical to those of the Pentium II processor. The

Pentium^®II Processor Developer’s Manual (order

number 243502) describes these configuration

options. New configuration options for the Mobile

Pentium II processor are described in the

remainder of this section.

7.1.3

APIC Disable

The APIC has been removed as a feature of the

Mobile Pentium II processor. The PICCLK and

PICD[1:0] signals must be tied to V_SSwith a 1K

resistor to disable the APIC. Driving PICD0 low at

reset has the effect of clearing the APIC Global

Enable bit in the APIC Base MSR. This bit is

normally set when the processor is reset, but

when it is cleared the APIC is completely disabled

until the next reset.

7.1.1

Quick Start Enable

The processor normally enters the Stop Grant

state when the STPCLK# signal is asserted, but it

will enter the Quick Start state instead if A15# is

sampled active on the RESET# signal’s active-to-

inactive transition. The Quick Start state supports

snoops from the bus priority device like the Stop

Grant state, but it does not support symmetric

master snoops, nor is the latching of interrupts

supported. A ‘1’ in bit position 5 of the Power-On

Configuration register indicates that the Quick

Start state has been enabled.

7.2

Clock Frequencies and

Ratios

The Mobile Pentium II processor uses a clock

design in which the bus clock is multiplied by a

ratio to produce the processor’s internal (or

“core”) clock. The Bus Fraction Locking scheme

implemented in the processor permanently sets

the clock ratio multiplier to the corresponding

processor marked frequency. Section 3.3

describes how this is done. The bus ratio

programmed into the processor is visible in bit

positions 22 to 25 of the Power-On Configuration

register. Table 3.4 shows the 4-bit codes in the

Power-On Configuration register and their

corresponding bus ratios.

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to the appropriate balls/pins on both agents on the

system bus.

8. PROCESSOR INTERFACE

8.1

Alphabetical Signal Reference

AERR# (I/O - Low Power GTL+)

Except for BCLK, the 1.5V Tolerant signals are for

the 400 MHz; the 2.5V tolerant signals are for the

366 MHz and below.

The AERR# (Address Parity Error) signal is

observed and driven by both system bus agents,

and if used, must be connected to the appropriate

balls of both agents on the system bus. AERR#

observation is optionally enabled during power-on

configuration; if enabled, a valid assertion of AERR#

aborts the current transaction.

A[35:3]# (I/O - Low Power GTL+)

The A[35:3]# (Address) signals define a 2³⁶-byte

physical memory address space. When ADS# is

active, these signals transmit the address of a

transaction; when ADS# is inactive, these signals

transmit transaction information. These signals must

be connected to the appropriate balls/pins of both

agents on the system bus. The A[35:24]# signals

are protected with the AP1# parity signal, and the

A[23:3]# signals are protected with the AP0# parity

signal.

If AERR# observation is disabled during power-on

configuration,

a central agent may handle an

assertion of AERR# as appropriate to the error

handling architecture of the system.

The AERR# processor bus pin is removed as a

processor feature for mobile Pentium® II processor

at 400 MHz. The pin must still be terminated to Vcc

through a 120 pull-up resistor. But the processor

must not be configured to drive or observe the pin.

On the active-to-inactive transition of RESET#, each

processor bus agent samples A[35:3]# signals to

determine its power-on configuration. See Section 7

of this document and the Pentium^®II Processor

Developer’s Manual for details.

AP[1:0]# (I/O - Low Power GTL+)

The AP[1:0]# (Address Parity) signals are driven by

the request initiator along with ADS#, A[35:3]#,

REQ[4:0]# and RP#. AP1# covers A[35:24]#. AP0#

covers A[23:3]#. A correct parity signal is high if an

even number of covered signals are low and low if

an odd number of covered signals are low. This

allows parity to be high when all the covered signals

are high. AP[1:0]# should be connected to the

appropriate balls/pins on both agents on the system

bus.

A20M# (I - 1.5V/2.5V tolerant)

If the A20M# (Address-20 Mask) input signal is

asserted, the processor masks physical address bit

20 (A20#) before looking up a line in any internal

cache and before driving a read/write transaction on

the bus. Asserting A20M# emulates the 8086

processor's address wrap-around at the 1-Mbyte

boundary. Assertion of A20M# is only supported in

real mode.

BCLK (I - 2.5V tolerant)

ADS# (I/O - Low Power GTL+)

The BCLK (Bus Clock) signal determines the

system bus frequency. Both system bus agents

must receive this signal to drive their outputs and

latch their inputs on the BCLK rising edge. All

external timing parameters are specified with

respect to the BCLK signal.

The ADS# (Address Strobe) signal is asserted to

indicate the validity of a transaction address on the

A[35:3]# signals. Both bus agents observe the

ADS# activation to begin parity checking, protocol

checking, address decode, internal snoop or

deferred reply ID match operations associated with

the new transaction. This signal must be connected

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accept new bus transactions. During a bus stall, the

current bus owner cannot issue any new

transactions.

BERR# (I/O - Low Power GTL+)

The BERR# (Bus Error) signal is asserted to

indicate an unrecoverable error without

a bus

Since multiple agents may need to request a bus

stall simultaneously, BNR# is a wired-OR signal

which must be connected to the appropriate

balls/pins of both agents on the system bus. In order

to avoid wire-OR glitches associated with

simultaneous edge transitions driven by multiple

drivers, BNR# is activated on specific clock edges

and sampled on specific clock edges.

protocol violation. It may be driven by either system

bus agent, and must be connected to the

appropriate balls/pins of both agents, if used.

However, the Mobile Pentium® II processor does

not observe assertions of the BERR# signal.

BERR# assertion conditions are defined by the

system configuration. Configuration options enable

the BERR# driver as follows:

BP[3:2]# (I/O - Low Power GTL+)

Enabled or disabled

Asserted optionally for internal errors along with

IERR#

The BP[3:2]# (Breakpoint) signals are the System

Support group Breakpoint signals. They are outputs

from the processor that indicate the status of

breakpoints.

Asserted optionally by the request initiator of a

bus transaction after it observes an error

Asserted by any bus agent when it observes an

error in a bus transaction

BPM[1:0]# (I/O - Low Power GTL+)

BINIT# (I/O - Low Power GTL+)

The BPM[1:0]# (Breakpoint Monitor) signals are

breakpoint and performance monitor signals. They

are outputs from the processor that indicate the

status of breakpoints and programmable counters

used for monitoring processor performance.

The BINIT# (Bus Initialization) signal may be

observed and driven by both system bus agents,

and must be connected to the appropriate balls/pins

of both agents, if used. If the BINIT# driver is

enabled during the power-on configuration, BINIT#

is asserted to signal any bus condition that prevents

reliable future information.

BPRI# (I - Low Power GTL+)

The BPRI# (Bus Priority Request) signal is used to

arbitrate for ownership of the system bus. It must be

connected to the appropriate balls/pins on both

agents on the system bus. Observing BPRI# active

(as asserted by the priority agent) causes the

processor to stop issuing new requests, unless such

requests are part of an ongoing locked operation.

The priority agent keeps BPRI# asserted until all of

its requests are completed, and then releases the

bus by deasserting BPRI#.

If BINIT# is enabled during power-on configuration,

and BINIT# is sampled asserted, all bus state

machines are reset and any data which was in

transit is lost. All agents reset their rotating ID for

bus arbitration to the state after reset, and internal

count information is lost. The L1 and L2 caches are

not affected.

If BINIT# is disabled during power-on configuration,

a central agent may handle an assertion of BINIT#

as appropriate to the Machine Check Architecture

(MCA) of the system.

BREQ0# (I/O - Low Power GTL+)

The BREQ0# (Bus Request) signal is a processor

Arbitration Bus signal. The processor indicates that

it wants ownership of the system bus by asserting

the BREQ0# signal.

BNR# (I/O - Low Power GTL+)

The BNR# (Block Next Request) signal is used to

assert a bus stall by any bus agent that is unable to

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During power-up configuration, the central agent

must assert the BREQ0# bus signal. The processor

samples BREQ0# on the active-to-inactive transition

of RESET#.

balls/pins on both agents on the system bus if they

are used. During power-on configuration, DEP[7:0]#

signals can be enabled for ECC checking or

disabled for no checking.

BSEL (I - 1.5V/2.5V tolerant)

DRDY# (I/O - Low Power GTL+)

The BSEL (System Bus Speed Select) signal is

used to configure the processor for the system bus

The DRDY# (Data Ready) signal is asserted by the

data driver on each data transfer, indicating valid

data on the data bus. In a multi-cycle data transfer,

DRDY# can be deasserted to insert idle clocks. This

signal must be connected to the appropriate

balls/pins on both agents on the system bus.

frequency.

processor for 100 MHz operation and

configures it for 66 MHz operation. This signal must

be connected to V_SS

A

‘1’ on this signal configures the

a

‘0’

.

D[63:0]# (I/O - Low Power GTL+)

EDGCTRLN (analog)

The D[63:0]# (Data) signals are the data signals.

These signals provide a 64-bit data path between

both system bus agents, and must be connected to

the appropriate balls/pins on both agents. The data

driver asserts DRDY# to indicate a valid data

transfer.

This signal is used to configure the edge rate of the

Low Power GTL+ output buffers. Connect the

EDGCTRLN (Edge Rate Control N-FET) signal to

V_CCwith a 51 , 1% resistor.

FERR# (O - 1.5V/2.5V tolerant open-drain)

DBSY# (I/O - Low Power GTL+)

The FERR# (Floating-point Error) signal is asserted

when the processor detects an unmasked floating-

point error. FERR# is similar to the ERROR# signal

on the Intel387 coprocessor, and is included for

compatibility with systems using DOS-type floating-

point error reporting.

The DBSY# (Data Bus Busy) signal is asserted by

the agent responsible for driving data on the system

bus to indicate that the data bus is in use. The data

bus is released after DBSY# is deasserted. This

signal must be connected to the appropriate

balls/pins on both agents on the system bus.

FLUSH# (I - 1.5V/2.5V tolerant)

DEFER# (I - Low Power GTL+)

When the FLUSH# (Flush) input signal is asserted,

the processor writes back all internal cache lines in

the Modified state and invalidates all internal cache

lines. At the completion of a flush operation, the

processor issues a Flush Acknowledge transaction.

The processor stops caching any new data while the

FLUSH# signal remains asserted.

The DEFER# (Defer) signal is asserted by an agent

to indicate that the transaction cannot be

guaranteed in-order completion. Assertion of

DEFER# is normally the responsibility of the

addressed memory agent or I/O agent. This signal

must be connected to the appropriate balls/pins on

both agents on the system bus.

On the active-to-inactive transition of RESET#, each

processor bus agent samples FLUSH# to determine

its power-on configuration.

DEP[7:0]# (I/O - Low Power GTL+)

The DEP[7:0]# (Data Bus ECC Protection) signals

provide optional ECC protection for the data bus.

They are driven by the agent responsible for driving

D[63:0]#, and must be connected to the appropriate

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floating-point registers. The processor begins

execution at the power-on reset vector configured

during power-on configuration. The processor

continues to handle snoop requests during INIT#

assertion. INIT# is an asynchronous input.

HIT# (I/O - Low Power GTL+), HITM#

(I/O - Low Power GTL+)

The HIT# (Snoop Hit) and HITM# (Hit Modified)

signals convey transaction snoop operation results,

and must be connected to the appropriate balls/pins

on both agents on the system bus. Either bus agent

can assert both HIT# and HITM# together to

indicate that it requires a snoop stall, which can be

continued by reasserting HIT# and HITM# together.

If INIT# is sampled active on RESET#'s active-to-

inactive transition, then the processor executes its

built-in self test (BIST).

INTR (I - 1.5V/2.5V tolerant)

IERR# (O - 1.5V/2.5V tolerant open-drain)

The INTR (Interrupt) signal indicates that an

external interrupt has been generated. The interrupt

is maskable using the IF bit in the EFLAGS register.

If the IF bit is set, the processor vectors to the

interrupt handler after completing the current

instruction execution. Upon recognizing the interrupt

request, the processor issues a single Interrupt

Acknowledge (INTA) bus transaction. INTR must

remain active until the INTA bus transaction to

guarantee its recognition. INTR must be deasserted

for a minimum of two clocks to guarantee its

inactive recognition.

The IERR# (Internal Error) signal is asserted by the

processor as the result of an internal error.

Assertion of IERR# is usually accompanied by a

SHUTDOWN transaction on the system bus. This

transaction may optionally be converted to an

external error signal (e.g., NMI) by system logic. The

processor will keep IERR# asserted until it is

handled in software or with the assertion of

RESET#, BINIT or INIT#.

IGNNE# (I - 1.5V/2.5V tolerant)

LOCK# (I/O - Low Power GTL+)

The IGNNE# (Ignore Numeric Error) signal is

asserted to force the processor to ignore a numeric

error and continue to execute non-control floating-

point instructions. If IGNNE# is deasserted, the

processor freezes on a non-control floating-point

instruction if a previous instruction caused an error.

IGNNE# has no effect when the NE bit in control

register 0 (CR0) is set.

The LOCK# (Lock) signal indicates to the system

that

a sequence of transactions must occur

atomically. This signal must be connected to the

appropriate balls/pins on both agents on the system

bus. For a locked sequence of transactions, LOCK#

is asserted from the beginning of the first

transaction through the end of the last transaction.

During active RESET#, the processor begins

sampling the A20M#, IGNNE#, INTR and NMI

values to determine the ratio of core-clock

frequency to bus-clock frequency (see Table 3.4).

On the active-to-inactive transition of RESET#, the

processor latches these signals and freezes the

frequency ratio internally. System logic must then

release these signals for normal operation.

When the priority agent asserts BPRI# to arbitrate

for bus ownership, it waits until it observes LOCK#

deasserted. This enables the processor to retain

bus ownership throughout the bus locked operation

and guarantee the atomicity of lock.

NMI (I - 1.5V/2.5V tolerant)

The NMI (Non-Maskable Interrupt) indicates that an

external interrupt has been generated. Asserting

NMI causes an interrupt with an internally supplied

vector value of 2. An external interrupt-acknowledge

transaction is not generated. If NMI is asserted

during the execution of an NMI service routine, it

INIT# (I - 1.5V/2.5V tolerant)

The INIT# (Initialization) signal is asserted to reset

integer registers inside the processor without

affecting the internal (L1 or L2) caches or the

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remains pending and is recognized after the IRET is

executed by the NMI service routine. At most, one

assertion of NMI is held pending. NMI is rising-edge

sensitive. Active and inactive pulse widths must be

a minimum of two clocks.

PREQ# (I - 1.5V/2.5V tolerant)

The PREQ# (Probe Request) signal is used by

debug tools to request debug operation of the

processor.

PICCLK (I - 1.5V/2.5V tolerant)

PWRGOOD (I - 2.5V/2.5V tolerant)

The PICCLK (APIC Clock) signal is an input clock to

the processor and system logic or I/O APIC that is

required for operation of the processor, system logic

and I/O APIC components on the APIC bus.

PWRGOOD (Power Good) is a 1.5V tolerant input

for the 400 MHz, and 2.5V tolerant for the 366 MHz

and below. The processor requires this signal to be

a

clean indication that clocks and the power

supplies (V_CC, V_CCP, etc.) are stable and within their

specifications. Clean implies that the signal will

remain low, (capable of sinking leakage current) and

without glitches, from the time that the power

supplies are turned on, until they come within

specification. The signal will then transition

monotonically to a high (1.5V or 2.5V) state. Figure

8.1 illustrates the relationship of PWRGOOD to

other system signals. PWRGOOD can be driven

inactive at any time, but clocks and power must

again be stable before the rising edge of

PWRGOOD. It must also meet the minimum pulse

width specified in Table 3.16 (Section 3.5), and be

followed by a 1 ms RESET# pulse.

PICD[1:0] (I/O - 1.5V/2.5V tolerant open-drain)

The PICD[1:0] (APIC Data) signals are used for

bidirectional serial message passing on the APIC

bus. They must be connected to the appropriate

balls/pins of all APIC bus agents, including the

processor and the system logic or I/O APIC

components. If the PICD0 signal is sampled low on

the active-to-inactive transition of the RESET#

signal, then the APIC is hardware disabled.

PRDY# (O - Low Power GTL+)

The PRDY# (Probe Ready) signal is a processor

output used by debug tools to determine processor

debug readiness.

BCLK

V_CC

,

V_CCP

,

V_REF

V_IH,min

PWRGOOD

1 msec

RESET#

D0026-00

Figure 8.1 PWRGOOD Relationship at Power-On

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The PWRGOOD signal, which must be supplied to

A correct parity signal is high if an even number of

covered signals are low, and low if an odd number

of covered signals are low. This definition allows

parity to be high when all covered signals are high.

the processor, is used to protect internal circuits

against voltage sequencing issues. The PWRGOOD

signal should be driven high throughout boundary

scan operation.

RS[2:0]# (I - Low Power GTL+)

REQ[4:0]# (I/O - Low Power GTL+)

The RS[2:0]# (Response Status) signals are driven

by the response agent (the agent responsible for

completion of the current transaction), and must be

connected to the appropriate balls/pins on both

agents on the system bus.

The REQ[4:0]# (Request Command) signals must

be connected to the appropriate balls/pins on both

agents on the system bus. They are asserted by the

current bus owner when it drives A[35:3]# to define

the currently active transaction type.

RSP# (I - Low Power GTL+)

RESET# (I - Low Power GTL+)

The RSP# (Response Parity) signal is driven by the

response agent (the agent responsible for

completion of the current transaction) during

assertion of RS[2:0]#. RSP# provides parity

protection for RS[2:0]#. RSP# should be connected

to the appropriate balls/pins on both agents on the

system bus.

Asserting the RESET# signal resets the processor

to a known state and invalidates the L1 and L2

caches without writing back Modified (M state) lines.

For a power-on type reset, RESET# must stay

active for at least 1 msec after V_CCand BCLK have

reached their proper DC and AC specifications and

after PWRGOOD has been asserted. When

observing active RESET#, all bus agents will

deassert their outputs within two clocks.

A correct parity signal is high if an even number of

covered signals are low, and low if an odd number

of covered signals are low. During Idle state of

RS[2:0]# (RS[2:0]#=000), RSP# is also high since it

is not driven by any agent guaranteeing correct

parity.

A number of bus signals are sampled at the active-

to-inactive transition of RESET# for the power-on

configuration. The configuration options are

described in Section 7 and in the Pentium^®II

Processor Developer’s Manual.

SLP# (I - 1.5V/2.5V tolerant)

Unless its outputs are tri-stated during power-on

configuration, after an active-to-inactive transition of

RESET#, the processor optionally executes its built-

in self-test (BIST) and begins program execution at

reset-vector 000FFFF0H or FFFFFFF0H. RESET#

must be connected to the appropriate balls/pins on

both agents on the system bus.

The SLP# (Sleep) signal, when asserted in the Stop

Grant state, causes the processor to enter the Sleep

state. During the Sleep state, the processor stops

providing internal clock signals to all units, leaving

only the Phase-Locked Loop (PLL) still running. The

processor will not recognize snoop and interrupts in

the Sleep state. The processor will only recognize

changes in the SLP#, STPCLK# and RESET#

signals while in the Sleep state. If SLP# is

deasserted, the processor exits Sleep state and

returns to the Stop Grant state in which it restarts its

internal clock to the bus and APIC processor units.

RP# (I/O - Low Power GTL+)

The RP# (Request Parity) signal is driven by the

request initiator, and provides parity protection on

ADS# and REQ[4:0]#. RP# should be connected to

the appropriate balls/pins on both agents on the

system bus.

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SMI# (I - 1.5V/2.5V tolerant)

THERMDA, THERMDC (analog)

The SMI# (System Management Interrupt) is

asserted asynchronously by system logic. On

accepting a System Management Interrupt, the

processor saves the current state and enters

System Management Mode (SMM). An SMI

Acknowledge transaction is issued, and the

processor begins program execution from the SMM

handler.

The THERMDA (Thermal Diode Anode) and

THERMDC (Thermal Diode Cathode) signals

connect to the anode and cathode of the on-die

thermal diode.

TMS (I - 1.5V/2.5V tolerant)

The TMS (Test Mode Select) signal is a JTAG

support signal used by debug tools.

STPCLK# (I - 1.5V/2.5V tolerant)

TRDY# (I - Low Power GTL+)

The STPCLK# (Stop Clock) signal, when asserted,

causes the processor to enter a low-power Stop

Grant state. The processor issues a Stop Grant

Acknowledge special transaction, and stops

providing internal clock signals to all units except

the bus and APIC units. The processor continues to

snoop bus transactions and service interrupts while

in the Stop Grant state. When STPCLK# is

deasserted, the processor restarts its internal clock

to all units and resumes execution. The assertion of

STPCLK# has no effect on the bus clock.

The TRDY# (Target Ready) signal is asserted by

the target to indicate that the target is ready to

receive write or implicit writeback data transfer.

TRDY# must be connected to the appropriate

balls/pins on both agents on the system bus.

TRST# (I - 1.5V/2.5V tolerant)

The TRST# (Test Port Reset) signal resets the Test

Access Port (TAP) logic. The Mobile Pentium® II

processor does not self-reset during power-on;

therefore, it is necessary to drive this signal low

during power-on reset.

TCK (I - 1.5V/2.5V tolerant)

The TCK (Test Clock) signal provides the clock

input for the test bus (also known as the test access

port).

VTOL (O – 1.6V tolerant open-drain)

The VTOL (Voltage Tolerance) signal indicates

whether the processor has 2.5V tolerant CMOS

signals or 1.5V tolerant CMOS signals. This signal

is a high impedance pin on the 2.5V tolerant Mobile

Pentium® II processor at 366 MHz and below, and

is shorted to VSS on the 1.5V tolerant Mobile

Pentium® II processor at 400 MHz. It is safe to

connect this signal to 1.6V with a pull-up resistor..

TDI (I - 1.5V/2.5V tolerant)

The TDI (Test Data In) signal transfers serial test

data to the processor. TDI provides the serial input

needed for JTAG support.

TDO (O - 1.5V/2.5V tolerant open-drain)

The TDO (Test Data Out) signal transfers serial test

data from the processor. TDO provides the serial

output needed for JTAG support.

8.2

Signal Summaries

Table 8.1 through Table 8.4 list the attributes of the

processor input, output, and I/O signals.

72

INTEL CORPORATION

MOBILE PENTIUM II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

Table 8.1 Input Signals

Name

A20M#

Active Level

Low

Clock

Asynch

—

Signal Group

CMOS

Qualified

Always

BCLK

High

Low

System Bus

Implementation

System Bus

CMOS

BPRI#

BSEL

BCLK

Asynch

BCLK

Asynch

—

High

Low

DEFER#

FLUSH#

IGNNE#

INIT#

Low

CMOS

Low

System Bus

CMOS

INTR

High

Low

APIC disabled mode

Always

NMI

CMOS

PICCLK

PREQ#

PWRGOOD

RESET#

RS[2:0]#

RSP#

APIC

Asynch

BCLK

Asynch

—

Implementation

System Bus

Implementation

CMOS

Always

High

Low

Always

Low

Always

Low

Always

SLP#

Low

Stop Grant state

Always

SMI#

Low

STPCLK#

TCK

Low

Implementation

JTAG

Always

High

TDI

TCK

JTAG

TMS

TCK

JTAG

TRDY#

TRST#

Low

BCLK

Asynch

System Bus

JTAG

Response phase

INTEL CORPORATION

73

MOBILE PENTIUM^®II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHz, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

Table 8.2 Output Signals

Name

Active Level

Low

Clock

Asynch

BCLK

Signal Group

Open-Drain

FERR#

IERR#

PRDY#

TDO

Low

Open-Drain

Implementation

JTAG

Low

High

TCK

VTOL

High

Asynch

Implementation

Table 8.3 Input/Output Signals (Single Driver)

Name

Active Level

Low

Clock

BCLK

Signal Group

System Bus

Qualified

A[35:3]#

ADS#

ADS#, ADS#+1

Always

Low

AP[1:0]#

BREQ0#

BP[3:2]#

Low

ADS#, ADS#+1

Always

Low

Always

BPM[1:0]#

D[63:0]#

DBSY#

Low

Always

Low

DRDY#

Low

Always

DEP[7:0]#

DRDY#

LOCK#

Low

DRDY#

Low

Always

Low

Always

REQ[4:0]#

RP#

Low

ADS#, ADS#+1

Low

74

INTEL CORPORATION

MOBILE PENTIUM II PROCESSOR IN MICRO-PGA AND BGA PACKAGES

AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ

Table 8.4 Input/Output Signals (Multiple Driver)

Name

AERR#

Active Level

Low

Clock

BCLK

PICCLK

Signal Group

System Bus

APIC

Qualified

ADS#+3

Always

BERR#

BINIT#

BNR#

Low

HIT#

Low

HITM#

PICD[1:0]

Low

High

INTEL CORPORATION

75

UNITED STATES, Intel Corporation

2200 Mission College Blvd., P.O. Box 58119, Santa Clara, CA 95052-8119

Tel: +1 408 765-8080

JAPAN, Intel Japan K.K.

5-6 Tokodai, Tsukuba-shi, Ibaraki-ken 300-26

Tel: + 81-29847-8522

FRANCE, Intel Corporation S.A.R.L.

1, Quai de Grenelle, 75015 Paris

Tel: +33 1-45717171

UNITED KINGDOM, Intel Corporation (U.K.) Ltd.

Pipers Way, Swindon, Wiltshire, England SN3 1RJ

Tel: +44 1-793-641440

GERMANY, Intel GmbH

Dornacher Strasse 1

85622 Feldkirchen/ Muenchen

Tel: +49 89/99143-0

HONG KONG, Intel Semiconductor Ltd.

32/F Two Pacific Place, 88 Queensway, Central

Tel: +852 2844-4555

CANADA, Intel Semiconductor of Canada, Ltd.

190 Attwell Drive, Suite 500

Rexdale, Ontario M9W 6H8

Tel: +416 675-2438

BRAZIL, Intel Semicondutores do Brasil

Centro Empresarial Nações Unidas - Edifício Torre Oeste

Av. das Nações Unidas, 12.901 - 18o. andar - Brooklin Novo

04578.000 São Paulo - S.P. – Brasil

Tel: +55-11-5505-2296


型号：	KC80524TX400256
厂家：	INTEL
描述：	RISC Microprocessor, 32-Bit, 400MHz, PBGA615
文件：	总81页 (文件大小：593K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KC80524TX400256 [INTEL]

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