NG80960KA16_技术文档

80960KA

EMBEDDED 32-BIT MICROPROCESSOR

■ High-Performance Embedded Architecture

■ Built-in Interrupt Controller

— 25 MIPS Burst Execution at 25 MHz

— 9.4 MIPS* Sustained Execution at 25 MHz

— 31 Priority Levels, 256 Vectors

— 3.4 µs Latency @ 25 MHz

■ 512-Byte On-Chip Instruction Cache

■ Easy to Use, High Bandwidth 32-Bit Bus

— Direct Mapped

— Parallel Load/Decode for Uncached Instruc-

tions

— 66.7 Mbytes/s Burst

— Up to 16 Bytes Transferred per Burst

■ 132-Lead Packages:

■ Multiple Register Sets

— Pin Grid Array (PGA)

— Plastic Quad Flat-Pack (PQFP)

— Sixteen Global 32-Bit Registers

— Sixteen Local 32-Bit Registers

— Four Local Register Sets Stored On-Chip

— Register Scoreboarding

■ 4 Gigabyte, Linear Address Space

■ Pin Compatible with 80960KB

The 80960KA is a member of Intel’s i960® 32-bit processor family, which is designed especially for embedded

applications. It includes a 512-byte instruction cache and a built-in interrupt controller. The 80960KA has a large

register set, multiple parallel execution units and a high-bandwidth burst bus. Using advanced RISC technology,

this high performance processor is capable of execution rates in excess of 9.4 million instructions per second^*.

The 80960KA is well-suited for a wide range of applications including non-impact printers, I/O control and

specialty instrumentation.

64- BY 32-BIT

LOCAL

REGISTER

CACHE

SIXTEEN

32-BIT GLOBAL

REGISTERS

32-BIT

INSTRUCTION

EXECUTION

UNIT

32-BIT

BUS

CONTROL

LOGIC

MICRO-

INSTRUCTION

SEQUENCER

512-BYTE

INSTRUCTION

CACHE

MICRO-

INSTRUCTION

ROM

32-BIT

BURST

BUS

INSTRUCTION

FETCH UNIT

INSTRUCTION

DECODER

Figure 1. The 80960KA Processor’s Highly Parallel Architecture

*

Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment

Corporation)

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent

licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. August 2004

80960KA

EMBEDDED 32-BIT MICROPROCESSOR

1.0 THE i960® PROCESSOR ................................ 1

FIGURES

1.1. Key Performance Features .......................... 2

1.1.1. Memory Space And Addressing Modes . 4

1.1.2. Data Types ............................................. 4

1.1.3. Large Register Set ................................. 4

1.1.4. Multiple Register Sets ............................ 5

1.1.5. Instruction Cache ................................... 5

1.1.6. Register Scoreboarding ......................... 5

1.1.7. High Bandwidth Local Bus ..................... 6

1.1.8. Interrupt Handling ................................... 6

1.1.9. Debug Features ..................................... 6

1.1.10. Fault Detection ..................................... 7

1.1.11. Built-in Testability ................................. 7

1.1.12. CHMOS ................................................ 7

Figure 1.

The 80960KA Processor’s Highly

Parallel Architecture ............................ i

Figure 2.

80960KA Programming

Environment ........................................ 1

Figure 3.

Figure 4.

Instruction Formats ............................. 4

Multiple Register Sets Are Stored

On-Chip ............................................... 6

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Connection Recommendations

for Low Current Drive Network .......... 11

Connection Recommendations

for High Current Drive Network ......... 11

Typical Supply Current vs.

Case Temperature ............................ 12

Typical Current vs. Frequency

(Room Temp) .................................... 12

2.0 ELECTRICAL SPECIFICATIONS .................. 10

2.1. Power and Grounding ................................ 10

2.2. Power Decoupling Recommendations ....... 10

2.3. Connection Recommendations .................. 11

2.4. Characteristic Curves ................................. 11

2.5. Test Load Circuit ........................................ 14

2.6. Absolute Maximum Ratings ....................... 15

2.7. DC Characteristics ..................................... 15

2.8. AC Specifications ....................................... 16

2.8.1. AC Specification Tables ....................... 17

Typical Current vs. Frequency

(Hot Temp) ........................................ 13

Figure 10. Worst-Case Voltage vs. Output

Current on Open-Drain Pins .............. 13

Figure 11. Capacitive Derating Curve ................ 13

Figure 12. Test Load Circuit for Three-State

Output Pins ...................................... 14

Figure 13. Test Load Circuit for Open-Drain

Output Pins ...................................... 14

3.0 MECHANICAL DATA ..................................... 21

3.1. Packaging .................................................. 21

3.1.1. Pin Assignment .................................... 21

3.2. Pinout ......................................................... 25

3.3. Package Thermal Specification ................. 29

Figure 14. Drive Levels and Timing Relationships

for 80960KA Signals ......................... 16

Figure 15. Processor Clock Pulse (CLK2) .......... 20

Figure 16. RESET Signal Timing ....................... 20

Figure 17. 32-Lead Pin-Grid Array

(PGA) Package ................................. 21

4.0. WAVEFORMS ............................................... 33

5.0. REVISION HISTORY ..................................... 38

Figure 18. 80960KA PGA Pinout—View from

Bottom (Pins Facing Up) ................... 22

Figure 19. 80960KA PGA Pinout—View from

Top (Pins Facing Down) .................... 23

Figure 20. 80960KA 132-Lead Plastic Quad

Flat-Pack (PQFP) Package ............... 23

Figure 21. PQFP Pinout - View From Top .......... 24

Figure 22. HOLD Timing .................................... 30

Figure 23. 16 MHz Maximum Allowable

Ambient Temperature ....................... 31

ii

CONTENTS

Figure 24. 20 MHz Maximum Allowable

Ambient Temperature ....................... 31

Figure 25. 25 MHz Maximum Allowable

Ambient Temperature ....................... 32

TABLES

Table 1.

Table 2.

Table 3.

80960KA Instruction Set ..................... 3

Memory Addressing Modes ................ 4

80960KA Pin Description:

L-Bus Signals ...................................... 8

Figure 26. Maximum Allowable Ambient

Temperature for the Extended

Temperature 80960KA at

20 MHz in PGA Package .................. 32

Figure 27. Non-Burst Read and Write

Transactions Without Wait States ..... 33

Table 4.

80960KA Pin Description:

Support Signals ................................... 9

Table 5.

Table 6.

DC Characteristics ............................ 15

80960KA AC Characteristics

(16 MHz) ........................................... 17

Figure 28. Burst Read and Write Transaction

Without Wait States ......................... 34

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

80960KA AC Characteristics

(20 MHz) ........................................... 18

Figure 29. Burst Write Transaction with

2, 1, 1, 1 Wait States ........................ 35

80960KA AC Characteristics

(25 MHz) ........................................... 19

Figure 30. Accesses Generated by Quad Word

Read Bus Request, Misaligned Two

80960KA PGA Pinout —

In Pin Order ....................................... 25

Bytes from Quad Word Boundary

(1, 0, 0, 0 Wait States) ...................... 36

80960KA PGA Pinout —

In Signal Order .................................. 26

Figure 31. Interrupt Acknowledge Transaction .. 37

80960KA PQFP Pinout —

In Pin Order ....................................... 27

80960KA PQFP Pinout —

In Signal Order .................................. 28

80960KA PGA Package

Thermal Characteristics .................... 29

80960KA PQFP Package

Thermal Characteristics .................... 30

iii

80960KA

All members of the i960 processor family share a

1.0 THE i960® PROCESSOR

common core architecture which utilizes RISC

technology so that, except for special functions, the

family members are object-code compatible. Each

new processor in the family adds its own special set

of functions to the core to satisfy the needs of a

specific application or range of applications in the

embedded market.

The 80960KA is a member of the 32-bit architecture

from Intel known as the i960 processor family. These

were especially designed to serve the needs of

embedded applications. The embedded market

includes applications as diverse as industrial

automation, avionics, image processing, graphics and

networking. These types of applications require high

integration, low power consumption, quick interrupt

response times and high performance. Since time to

market is critical, embedded microprocessors need to

be easy to use in both hardware and software

designs.

Software written for the 80960KA will run without

modification on any other member of the 80960

Family. It is also pin-compatible with the 80960KB

which includes an integrated floating-point unit and

the 80960MC which is a military-grade version that

supports multitasking, memory management, multi-

processing and fault tolerance.

0000 0000H

FFFF FFFFH

ADDRESS SPACE

ARCHITECTURALLY

DEFINED

DATA STRUCTURES

FETCH

LOAD

STORE

INSTRUCTION CACHE

INSTRUCTION

STREAM

INSTRUCTION

EXECUTION

g0

g15

SIXTEEN 32-BIT GLOBAL REGISTERS

PROCESSOR STATE

REGISTERS

REGISTER CACHE

INSTRUCTION

POINTER

r0

r15

SIXTEEN 32-BIT LOCAL REGISTERS

ARITHMETIC

CONTROLS

FOUR 80-BIT FLOATING POINT REGISTERS

CONTROL REGISTERS

PROCESS

CONTROLS

TRACE

CONTROLS

Figure 2. 80960KA Programming Environment

1

80960KA

5. Overlapped Instruction Execution. Load

1.1. Key Performance Features

operations allow execution of subsequent instructions

to continue before the data has been returned from

memory, so that these instructions can overlap the

load. The 80960KA manages this process transpar-

ently to software through the use of a register score-

board. Conditional instructions also make use of a

scoreboard so that subsequent unrelated instructions

may be executed while the conditional instruction is

pending.

The 80960 architecture is based on the most recent

advances in microprocessor technology and is

grounded in Intel’s long experience in the design and

manufacture of embedded microprocessors. Many

features contribute to the 80960KA’s exceptional

performance:

1. Large Register Set. Having a large number of

registers reduces the number of times that

a

processor needs to access memory. Modern

compilers can take advantage of this feature to

optimize execution speed. For maximum flexibility, the

80960KA provides thirty-two 32-bit registers. (See

Figure 2.)

6. Integer Execution Optimization. When the

result of an arithmetic execution is used as an

operand in a subsequent calculation, the value is sent

immediately to its destination register. Yet at the same

time, the value is put on a bypass path to the ALU,

thereby saving the time that otherwise would be

required to retrieve the value for the next operation.

2. Fast Instruction Execution. Simple functions

make up the bulk of instructions in most programs so

that execution speed can be improved by ensuring

that these core instructions are executed as quickly

as possible. The most frequently executed instruc-

tions such as register-register moves, add/subtract,

logical operations and shifts execute in one to two

cycles. (Table 1 contains a list of instructions.)

7. Bandwidth Optimizations. The 80960KA gets

optimal use of its memory bus bandwidth because the

bus is tuned for use with the on-chip instruction

cache: instruction cache line size matches the

maximum burst size for instruction fetches. The

80960KB automatically fetches four words in a burst

and stores them directly in the cache. Due to the size

of the cache and the fact that it is continually filled in

anticipation of needed instructions in the program

flow, the 80960KA is relatively insensitive to memory

wait states. The benefit is that the 80960KA delivers

3. Load/Store Architecture. One way to improve

execution speed is to reduce the number of times that

the processor must access memory to perform an

operation. As with other processors based on RISC

technology, the 80960KA has a Load/Store archi-

tecture. As such, only the LOAD and STORE instruc-

tions reference memory; all other instructions operate

on registers. This type of architecture simplifies

instruction decoding and is used in combination with

other techniques to increase parallelism.

outstanding performance even with

memory system.

a low cost

8. Cache Bypass. If a cache miss occurs, the

processor fetches the needed instruction then sends

it on to the instruction decoder at the same time it

updates the cache. Thus, no extra time is spent to

load and read the cache.

4. Simple Instruction Formats. All instructions in

the 80960KA are 32 bits long and must be aligned on

word boundaries. This alignment makes it possible to

eliminate the instruction alignment stage in the

pipeline. To simplify the instruction decoder, there are

only five instruction formats; each instruction uses

only one format. (See Figure 3.)

2

80960KA

Table 1. 80960KA Instruction Set

Data Movement

Load

Arithmetic

Logical

Bit and Bit Field

Set Bit

Add

And

Store

Move

Load Address

Subtract

Multiply

Divide

Remainder

Modulo

Shift

Not And

And Not

Or

Exclusive Or

Not Or

Clear Bit

Not Bit

Check Bit

Alter Bit

Scan For Bit

Scan Over Bit

Extract

Or Not

Exclusive Nor

Not

Modify

Nand

Rotate

Comparison

Branch

Call/Return

Fault

Compare

Unconditional Branch

Conditional Branch

Compare and Branch

Call

Conditional Fault

Synchronize Faults

Conditional Compare

Compare and Increment

Compare and Decre-

ment

Call Extended

Call System

Return

Branch and Link

Debug

Miscellaneous

Decimal

Modify Trace Controls

Mark

Force Mark

Atomic Add

Atomic Modify

Flush Local Registers

Modify Arithmetic Con-

trols

Decimal Move

Decimal Add with Carry

Decimal Subtract with

Carry

Scan Byte for Equal

Test Condition Code

Modify Process Controls

Synchronous

Synchronous Load

Synchronous Move

3

80960KA

Opcode

Displacement

Control

Compare and

Branch

Reg/Lit

Reg

M

Displacement

Register to

Register

Reg/Lit

Modes

Ext’d Op

Reg/Lit

Memory Access—

Short

Opcode

Reg

Base

M

X

Offset

Memory Access—

Long

Mode

Scale

xx

Offset

Displacement

Figure 3. Instruction Formats

1.1.1. Memory Space And Addressing Modes

1.1.2. Data Types

The 80960KA offers a linear programming environ-

ment so that all programs running on the processor

are contained in a single address space. Maximum

address space size is 4 Gigabytes (2³²bytes).

The 80960KA recognizes the following data types:

Numeric:

•

8-, 16-, 32- and 64-bit ordinals

8-, 16-, 32- and 64-bit integers

For ease of use the 80960KA has a small number of

addressing modes, but includes all those necessary

to ensure efficient execution of high-level languages

such as C. Table 2 lists the modes.

Non-Numeric:

•

Bit

Bit Field

Table 2. Memory Addressing Modes

Triple Word (96 bits)

Quad-Word (128 bits)

•

12-Bit Offset

32-Bit Offset

1.1.3. Large Register Set

Register-Indirect

The 80960KA programming environment includes a

large number of registers. In fact, 32 registers are

available at any time. The availability of this many

registers greatly reduces the number of memory

accesses required to perform algorithms, which leads

to greater instruction processing speed.

Register + 12-Bit Offset

Register + 32-Bit Offset

Register + (Index-Register x Scale-Factor)

Register x Scale Factor + 32-Bit Displacement

Register + (Index-Register x Scale-Factor) +

32-Bit Displacement

There are two types of general-purpose registers:

local and global. The global registers consist of

sixteen 32-bit registers (G0 though G15). These

registers perform the same function as the general-

•

Scale-Factor is 1, 2, 4, 8 or 16

4

80960KA

purpose registers provided in other popular micropro-

cessors. The term global refers to the fact that these

registers retain their contents across procedure calls.

To load the instruction cache, instructions are fetched

in 16-byte blocks; up to four instructions can be

fetched at one time. An efficient prefetch algorithm

increases the probability that an instruction will

already be in the cache when it is needed.

The local registers, on the other hand, are procedure

specific. For each procedure call, the 80960KA

allocates 16 local registers (R0 through R15). Each

local register is 32 bits wide.

Code for small loops often fits entirely within the

cache, leading to a great increase in processing

speed since further memory references might not be

necessary until the program exits the loop. Similarly,

when calling short procedures, the code for the

calling procedure is likely to remain in the cache so it

will be there on the procedure’s return.

1.1.4. Multiple Register Sets

To further increase the efficiency of the register set,

multiple sets of local registers are stored on-chip (See

Figure 4). This cache holds up to four local register

frames, which means that up to three procedure calls

can be made without having to access the procedure

stack resident in memory.

1.1.6. Register Scoreboarding

The instruction decoder is optimized in several ways.

One optimization method is the ability to overlap

instructions by using register scoreboarding.

Although programs may have procedure calls nested

many calls deep, a program typically oscillates back

and forth between only two to three levels. As a

result, with four stack frames in the cache, the proba-

bility of having a free frame available on the cache

when a call is made is very high. In fact, runs of repre-

sentative C-language programs show that 80% of the

calls are handled without needing to access memory.

Register scoreboarding occurs when a LOAD moves

a variable from memory into a register. When the

instruction initiates, a scoreboard bit on the target

register is set. Once the register is loaded, the bit is

reset. In between, any reference to the register

contents is accompanied by a test of the scoreboard

bit to ensure that the load has completed before

processing continues. Since the processor does not

need to wait for the LOAD to complete, it can execute

additional instructions placed between the LOAD and

the instruction that uses the register contents, as

shown in the following example:

If four or more procedures are active and a new

procedure is called, the 80960KA moves the oldest

local register set in the stack-frame cache to a

procedure stack in memory to make room for a new

set of registers. Global register G15 is the frame

pointer (FP) to the procedure stack.

ld data_2, r4

Global registers are not exchanged on a procedure

call, but retain their contents, making them available

to all procedures for fast parameter passing.

ld data_2, r5

Unrelated instruction

add R4, R5, R6

1.1.5. Instruction Cache

In essence, the two unrelated instructions between

LOAD and ADD are executed “for free” (i.e., take no

apparent time to execute) because they are executed

while the register is being loaded. Up to three load

instructions can be pending at one time with three

corresponding scoreboard bits set. By exploiting this

feature, system programmers and compiler writers

have a useful tool for optimizing execution speed.

To further reduce memory accesses, the 80960KA

includes a 512-byte on-chip instruction cache. The

instruction cache is based on the concept of locality

of reference; most programs are not usually executed

in a steady stream but consist of many branches,

loops and procedure calls that lead to jumping back

and forth in the same small section of code. Thus, by

maintaining a block of instructions in cache, the

number of memory references required to read

instructions into the processor is greatly reduced.

5

80960KA

REGISTER

CACHE

LOCAL REGISTER SET

ONE OF FOUR

LOCAL

REGISTER SETS

R₀

R₁₅

0

31

Figure 4. Multiple Register Sets Are Stored On-Chip

interrupt controller. Two of the interrupt pins can be

configured to provide 8259A-style handshaking for

expansion beyond four interrupt lines.

1.1.7. High Bandwidth Local Bus

The 80960KA CPU resides on a high-bandwidth

address/data bus known as the local bus (L-Bus). The

L-Bus provides a direct communication path between

the processor and the memory and I/O subsystem

interfaces. The processor uses the L-Bus to fetch

instructions, manipulate memory and respond to

interrupts. L-Bus features include:

1.1.9. Debug Features

The 80960KA has built-in debug capabilities. There

are two types of breakpoints and six trace modes.

Debug features are controlled by two internal 32-bit

registers: the Process-Controls Word and the Trace-

Controls Word. By setting bits in these control words,

a software debug monitor can closely control how the

processor responds during program execution.

•

32-bit multiplexed address/data path

Four-word burst capability which allows transfers

from 1 to 16 bytes at a time

•

High bandwidth reads and writes with

66.7 MBytes/s burst (at 25 MHz)

The 80960KA provides two hardware breakpoint

registers on-chip which, by using a special command,

can be set to any value. When the instruction pointer

matches either breakpoint register value, the

breakpoint handling routine is automatically called.

Table 3 defines L-bus signal names and functions;

Table 4 defines other component-support signals

such as interrupt lines.

The 80960KA also provides software breakpoints

through the use of two instructions: MARK and

FMARK. These can be placed at any point in a

program and cause the processor to halt execution at

that point and call the breakpoint handling routine.

The breakpoint mechanism is easy to use and

provides a powerful debugging tool.

1.1.8. Interrupt Handling

The 80960KA can be interrupted in two ways: by the

activation of one of four interrupt pins or by sending a

message on the processor’s data bus.

The 80960KA is unusual in that it automatically

handles interrupts on a priority basis and can keep

track of pending interrupts through its on-chip

Tracing is available for instructions (single step

execution), calls and returns and branching. Each

trace type may be enabled separately by a special

6

80960KA

debug instruction. In each case, the 80960KA

1.1.11. Built-in Testability

executes the instruction first and then calls a trace

handling routine (usually part of a software debug

monitor). Further program execution is halted until the

routine completes, at which time execution resumes

at the next instruction. The 80960KA’s tracing

mechanisms, implemented completely in hardware,

greatly simplify the task of software test and debug.

Upon reset, the 80960KA automatically conducts an

exhaustive internal test of its major blocks of logic.

Then, before executing its first instruction, it does a

zero check sum on the first eight words in memory to

ensure that the memory image was programmed

correctly. If a problem is discovered at any point

during the self-test, the 80960KA asserts its FAILURE

pin and will not begin program execution. Self test

takes approximately 47,000 cycles to complete.

1.1.10. Fault Detection

The 80960KA has an automatic mechanism to handle

faults. Fault types include trace and arithmetic faults.

When the processor detects a fault, it automatically

calls the appropriate fault handling routine and saves

the current instruction pointer and necessary state

information to make efficient recovery possible. Like

interrupt handling routines, fault handling routines are

usually written to meet the needs of specific applica-

tions and are often included as part of the operating

system or kernel.

System manufacturers can use the 80960KA’s self-

test feature during incoming parts inspection. No

special diagnostic programs need to be written. The

test is both thorough and fast. The self-test capability

helps ensure that defective parts are discovered

before systems are shipped and, once in the field, the

self-test makes it easier to distinguish between

problems caused by processor failure and problems

resulting from other causes.

For each of the fault types, there are numerous

subtypes that provide specific information about a

fault. The fault handler can use this specific infor-

mation to respond correctly to the fault.

1.1.12. CHMOS

The 80960KA is fabricated using Intel’s CHMOS IV

(Complementary High Speed Metal Oxide Semicon-

ductor) process. The 80960KA is currently available

in 16, 20 and 25 MHz versions.

7

80960KA

Table 3. 80960KA Pin Description: L-Bus Signals (Sheet 1 of 2)

NAME

CLK2

TYPE

DESCRIPTION

I

SYSTEM CLOCK provides the fundamental timing for 80960KA systems. It is divided

by two inside the 80960KA to generate the internal processor clock.

LAD31:0

I/O

LOCAL ADDRESS / DATA BUS carries 32-bit physical addresses and data to and

from memory. During an address (T_a) cycle, bits 2-31 contain a physical word

T.S.

address (bits 0-1 indicate SIZE; see below). During a data (T_d) cycle, bits 0-31

contain read or write data. These pins float to a high impedance state when not

active.

Bits 0-1 comprise SIZE during a T_acycle. SIZE specifies burst transfer size in words.

LAD1

LAD0

0

1

0

1

0

1

1 Word

2 Words

3 Words

4 Words

ALE

ADS

O

T.S.

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is

asserted during a T_acycle and deasserted before the beginning of the T_dstate. It is

active LOW and floats to a high impedance state during a hold cycle (T_h).

O

O.D.

ADDRESS/DATA STATUS indicates an address state. ADS is asserted every T_a

state and deasserted during the following T_dstate. For a burst transaction, ADS is

asserted again every T_dstate where READY was asserted in the previous cycle.

W/R

O

WRITE/READ specifies, during a T_acycle, whether the operation is a write or read. It

O.D.

is latched on-chip and remains valid during T_dcycles.

DT/R

O

DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the

L-Bus. It is low during T_aand T_dcycles for a read or interrupt acknowledgment; it is

O.D.

high during T_aand T_dcycles for a write. DT/R never changes state when DEN is

asserted.

READY

LOCK

I

READY indicates that data on LAD lines can be sampled or removed. If READY is not

asserted during a T_dcycle, the T_dcycle is extended to the next cycle by inserting a

wait state (T_w) and ADS is not asserted in the next cycle.

I/O

O.D.

BUS LOCK prevents bus masters from gaining control of the L-Bus during

Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert

LOCK.

At the start of a RMW operation, the processor examines the LOCK pin. If the pin is

already asserted, the processor waits until it is not asserted. If the pin is not asserted,

the processor asserts LOCK during the T_acycle of the read transaction. The

processor deasserts LOCK in the T_acycle of the write transaction. During the time

LOCK is asserted, a bus agent can perform a normal read or write but not a RMW

operation.

The processor also asserts LOCK during interrupt-acknowledge transactions.

Do not leave LOCK unconnected. It must be pulled high for the processor to function

properly.

I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state

8

80960KA

Table 3. 80960KA Pin Description: L-Bus Signals (Sheet 2 of 2)

NAME

BE3:0

TYPE

DESCRIPTION

O

BYTE ENABLE LINES specify the data bytes (up to four) on the bus which are used

in the current bus cycle. BE3 corresponds to LAD31:24; BE0 corresponds to LAD7:0.

O.D.

The byte enables are provided in advance of data:

•

Byte enables asserted during T_aspecify the bytes of the first data word.

Byte enables asserted during T_dspecify the bytes of the next data word, if any (the

word to be transmitted following the next assertion of READY).

Byte enables that occur during T_dcycles that precede the last assertion of READY

are undefined. Byte enables are latched on-chip and remain constant from one T_d

cycle to the next when READY is not asserted.

For reads, byte enables specify the byte(s) that the processor will actually use. L-Bus

agents are required to assert only adjacent byte enables (e.g., asserting just BE0 and

BE2 is not permitted) and are required to assert at least one byte enable. Address

bits A₀and A₁can be decoded externally from the byte enables.

HOLD

I

HOLD: A request from an external bus master to acquire the bus. When the

processor receives HOLD and grants bus control to another master, it floats its three-

state bus lines and open-drain control lines, asserts HLDA and enters the T_hstate.

When HOLD deasserts, the processor deasserts HLDA and enters the T_ior T_astate.

HLDA

O

HOLD ACKNOWLEDGE: Notifies an external bus master that the processor has

relinquished control of the bus.

T.S.

CACHE

O

CACHE indicates when an access is cacheable during a T_acycle. It is not asserted

T.S.

during any synchronous access, such as a synchronous load or move instruction

used for sending an IAC message. The CACHE signal floats to a high impedance

state when the processor is idle.

I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state

Table 4. 80960KA Pin Description: Support Signals (Sheet 1 of 2)

NAME

TYPE

DESCRIPTION

BADAC

I

BAD ACCESS, if asserted in the cycle following the one in which the last READY of a

transaction is asserted, indicates an unrecoverable error occurred on the current bus

transaction or a synchronous load/store instruction has not been acknowledged.

During system reset the BADAC signal is interpreted differently. If the signal is high, it

indicates that this processor will perform system initialization. If it is low, another

processor in the system will perform system initialization instead.

RESET

I

RESET clears the processor’s internal logic and causes it to reinitialize.

During RESET assertion, the input pins are ignored (except for BADAC and

IAC/INT₀), the three-state output pins are placed in a high impedance state and other

output pins are placed in their non-asserted states.

RESET must be asserted for at least 41 CLK2 cycles for a predictable RESET. The

HIGH to LOW transition of RESET should occur after the rising edge of both CLK2

and the external bus clock and before the next rising edge of CLK2.

I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state

9

80960KA

Table 4. 80960KA Pin Description: Support Signals (Sheet 2 of 2)

NAME

TYPE

DESCRIPTION

FAILURE

O

O.D.

INITIALIZATION FAILURE indicates that the processor did not initialize correctly.

After RESET deasserts and before the first bus transaction begins, FAILURE asserts

while the processor performs a self-test. If the self-test completes successfully, then

FAILURE deasserts. The processor then performs a zero checksum on the first eight

words of memory. If it fails, FAILURE asserts for a second time and remains

asserted. If it passes, system initialization continues and FAILURE remains

deasserted.

IAC/INT₀

I

INTERAGENT COMMUNICATION REQUEST/INTERRUPT 0 indicates an IAC

message or an interrupt is pending. The bus interrupt control register determines how

the signal is interpreted. To signal an interrupt or IAC request in a synchronous

system, this pin — as well as the other interrupt pins — must be enabled by being

deasserted for at least one bus cycle and then asserted for at least one additional

bus cycle. In an asynchronous system the pin must remain deasserted for at least

two bus cycles and then asserted for at least two more bus cycles.

During system reset, this signal must be in the logic high condition to enable normal

processor operation. The logic low condition is reserved.

INT₁

I

INTERRUPT 1, like INT₀, provides direct interrupt signaling.

INT₂/INTR

INTERRUPT2/INTERRUPT REQUEST: The interrupt control register determines

how this pin is interpreted. If INT₂, it has the same interpretation as the INT₀and INT₁

pins. If INTR, it is used to receive an interrupt request from an external interrupt

controller.

INT₃/INTA

I/O

INTERRUPT3/INTERRUPT ACKNOWLEDGE: The bus interrupt control register

determines how this pin is interpreted. If INT₃, it has the same interpretation as the

O.D.

INT₀, INT1 and INT2 pins. If INTA, it is used as an output to control interrupt-

acknowledge transactions. The INTA output is latched on-chip and remains valid

during T_dcycles; as an output, it is open-drain.

N.C.

N/A

NOT CONNECTED indicates pins should not be connected. Never connect any pin

marked N.C. as these pins may be reserved for factory use.

I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state

2.0 ELECTRICAL SPECIFICATIONS

2.1. Power and Grounding

2.2. Power Decoupling

Recommendations

Place a liberal amount of decoupling capacitance

near the 80960KA. When driving the L-bus the

processor can cause transient power surges, particu-

larly when connected to a large capacitive load.

The 80960KA is implemented in CHMOS IV

technology and therefore has modest power require-

ments. Its high clock frequency and numerous output

buffers (address/data, control, error and arbitration

signals) can cause power surges as multiple output

buffers simultaneously drive new signal levels. For

clean on-chip power distribution, V_CCand V_SSpins

separately feed the device’s functional units. Power

and ground connections must be made to all

80960KA power and ground pins. On the circuit

board, all V_ccpins must be strapped closely together,

preferably on a power plane; all V_sspins should be

strapped together, preferably on a ground plane.

Low inductance capacitors and interconnects are

recommended for best high frequency electrical

performance. Inductance is reduced by shortening

board traces between the processor and decoupling

capacitors as much as possible.

10

80960KA

2.3. Connection Recommendations

V

CC

For reliable operation, always connect unused inputs

to an appropriate signal level. In particular, if one or

more interrupt lines are not used, they should be

pulled up. No inputs should ever be left floating.

OPEN-DRAIN OUTPUT

180 Ω

390 Ω

All open-drain outputs require a pullup device. While

in most cases a simple pullup resistor is adequate, a

network of pullup and pulldown resistors biased to a

valid V_IH(>3.0 V) and terminated in the characteristic

impedance of the circuit board is recommended to

limit noise and AC power consumption. Figure 5 and

Figure 6 show recommended values for the resistor

network for low and high current drive, assuming a

characteristic impedance of 100 Ω. Terminating

output signals in this fashion limits signal swing and

reduces AC power consumption.

High Drive Network:

= 3.4 V

V

OH

= 25.3 mA

I

OL

Figure 6. Connection Recommendations

for High Current Drive Network

2.4. Characteristic Curves

Figure 7 shows typical supply current requirements

over the operating temperature range of the

processor at supply voltage (V_CC) of 5 V. Figure 8 and

NOTE:

Do not connect external logic to pins marked N.C.

Figure 9 show the typical power supply current (I_CC

)

V

CC

that the 80960KA requires at various operating

frequencies when measured at three input voltage

(V_CC) levels and two temperatures.

OPEN-DRAIN OUTPUT

220 Ω

330 Ω

For a given output current (I_OL) the curve in Figure 10

shows the worst case output low voltage (V_OL). Figure

11 shows the typical capacitive derating curve for the

80960KA measured from 1.5V on the system clock

(CLK) to 1.5V on the falling edge and 1.5V on the

rising edge of the L-Bus address/data (LAD) signals.

Low Drive Network:

V

= 3.0 V

= 20.7 mA

OH

I

OL

Figure 5. Connection Recommendations

for Low Current Drive Network

11

80960KA

380

360

340

320

300

280

V_CC= 5.0 V

25 MHz

20 MHz

16 MHz

260

240

220

200

-60 -40 -20

0

20 40 60 80 100 120 140

CASE TEMPERATURE (°C)

Figure 7. Typical Supply Current vs. Case Temperature

400

TEMP = +22°C

380

360

340

320

300

280

260

240

220

@5.5V

@5.0V

@4.5V

200

180

16

20

25

OPERATING FREQUENCY (MHz)

Figure 8. Typical Current vs. Frequency (Room Temp)

12

80960KA

380

360

340

320

300

280

260

240

220

TEMP = +22°C

@5.5V

@5.0V

@4.5V

200

180

160

16

20

25

OPERATING FREQUENCY (MHz)

Figure 9. Typical Current vs. Frequency (Hot Temp)

(TEMP = +85°C, V_CC= 4.5V)

30

FALLING

25

20

15

10

0.8

0.6

0.4

0.2

0.0

RISING

5

0

10 20 30 40 50

0

20 40 60 80 100

OUTPUT LOW CURRENT(mA)

CAPACITIVE LOAD(pF)

Figure 10. Worst-Case Voltage vs. Output Current

on Open-Drain Pins

Figure 11. Capacitive Derating Curve

13

80960KA

2.5. Test Load Circuit

Figure 12 illustrates the load circuit used to test the

80960KA’s three-state pins; Figure 13 shows the load

circuit used to test the open drain outputs. The open

drain test uses an active load circuit in the form of a

matched diode bridge. Since the open-drain outputs

sink current, only the I_OLlegs of the bridge are

necessary and the I_OHlegs are not used. When the

80960KA driver under test is turned off, the output pin

is pulled up to V_REF(i.e., V_OH). Diode D₁is turned off

and the I_OLcurrent source flows through diode D₂.

THREE-STATE OUTPUT

C

L

C

= 50 pF for all signals

L

Figure 12. Test Load Circuit for Three-State Output Pins

I

OL

When the 80960KA open-drain driver under test is

on, diode D₁is also on and the voltage on the pin

being tested drops to V_OL. Diode D₂turns off and I_OL

flows through diode D₁.

OPEN-DRAIN OUTPUT

D

2

1

C

L

I

Tested at 25 mA

OL

V

= V

REF

D1 and D are matched

CC

2

C

= 50 pF for all signals

L

Figure 13. Test Load Circuit for Open-Drain Output Pins

14

80960KA

NOTICE: This is a production data sheet. The specifi-

cations are subject to change without notice.

2.6. Absolute Maximum Ratings

Operating Temperature (PGA).............. 0°C to +85°C Case

(PQFP) ......... 0°C to +100°C Case

Storage Temperature ................................. –65°C to +150°C

*WARNING: Stressing the device beyond the “Absolute Maxi-

mum Ratings” may cause permanent damage. These are

stress ratings only. Operation beyond the “Operating Condi-

tions” is not recommended and extended exposure beyond the

“Operating Conditions” may affect device reliability.

Voltage on Any Pin................................. –0.5V to V

+0.5V

CC

Power Dissipation .......................................... 2.5W (25 MHz)

2.7. DC Characteristics

PGA:

80960KA (16 MHz) T_CASE= 0°C to +85°C, V_CC= 5V ± 10%

80960KA (20 and 25 MHz) T_CASE= 0°C to +85°C, V_CC= 5V ± 5%

80960KA (16 MHz) T_CASE= 0°C to +100°C, V_CC= 5V ± 10%

80960KA (20 and 25 MHz) T_CASE= 0°C to +100°C, V_CC= 5V ± 5%

PQFP:

Table 5. DC Characteristics

Symbol

V_IL

Parameter

Input Low Voltage

Min

–0.3

Max

+0.8

Units

Notes

V

V_IH

Input High Voltage

2.0

V_CC+ 0.3

+0.8

V_CL

CLK2 Input Low Voltage

CLK2 Input High Voltage

Output Low Voltage

Output High Voltage

–0.3

V_CH

V_OL

0.55 V_CC

V_CC+ 0.3

0.45

(1,2)

(3,4)

V_OH

I_CC

2.4

Power Supply Current:

16 MHz

315

360

420

mA

(5)

20 MHz

25 MHz

I_LI

Input Leakage Current

Output Leakage Current

Input Capacitance

±15

10

µA

pF

0 ≤ V_IN≤ V_CC

0.45 ≤ V_O≤ V_CC

f_C= 1 MHz (6)

I_LO

C_IN

C_O

Output Capacitance

Clock Capacitance

12

C_CLK

10

NOTES:

1. For three-state outputs, this parameter is measured at:

Address/Data............................................................................................................................................................................................. 4.0 mA

Controls ...................................................................................................................................................................................................... 5.0 mA

2. For open-drain outputs ................................................................................................................................................................................ 25 mA

3. This parameter is measured at:

Address/Data ........................................................................................................................................................................................... -1.0 mA

Controls .................................................................................................................................................................................................... -0.9 mA

ALE .......................................................................................................................................................................................................... -5.0 mA

4. Not measured on open-drain outputs.

5. Measured at worst case frequency, V_CCand temperature, with device operating and outputs loaded to the test conditions in Figures 12 and 13.

Figure 7, Figure 8 and Figure 9 indicate typical values.

6. Input, output and clock capacitance are not tested.

15

80960KA

For input timings the specifications refer to the time at

2.8. AC Specifications

which the signal reaches (for input setup) or leaves

(for hold time) the TTL levels of LOW (0.8 V) or HIGH

(2.0 V). All AC testing should be done with input

voltages of 0.4 V and 2.4 V, except for the clock

(CLK2), which should be tested with input voltages of

This section describes the AC specifications for the

80960KA pins. All input and output timings are

specified relative to the 1.5 V level of the rising edge

of CLK2. For output timings the specifications refer to

the time it takes the signal to reach 1.5 V.

0.45 V and 0.55 V_CC

.

D

A

B

C

B

C

EDGE

CLK2

1.5V

9

1.5V

0.8V

T

6

OUTPUTS:

LAD 31:0

ADS

1.5V

VALID OUTPUT

W/R, DEN

BE3:0

HLDA

CACHE

LOCK, INTA

T

8

T

14

8

13

1.5V

ALE

T

7

T

6

9

VALID OUTPUT

1.5V

DT/R

T

10

11

INPUTS:

LAD31:0

BADAC

2.0V 2.0V

0.8V 0.8V

IAC/INT0, INT1

INT2/INTR, INT3

T

VALID INPUT

12

11

HOLD

LOCK

READY

2.0V 2.0V

0.8V 0.8V

Figure 14. Drive Levels and Timing Relationships for 80960KA Signals

16

80960KA

2.8.1. AC Specification Tables

Table 6. 80960KA AC Characteristics (16 MHz)

Symbol

Input Clock

T₁

Parameter

Min

Max

Units

Notes

Processor Clock Period (CLK2)

31.25

125

ns

V_IN= 1.5V

T₂

T₃

Processor Clock Low Time (CLK2)

8

V_IL= 10% Point = 1.2V

Processor Clock High Time

(CLK2)

V_IH= 90% Point = 0.1V + 0.5 V_CC

T₄

T₅

Processor Clock Fall Time (CLK2)

Processor Clock Rise Time (CLK2)

10

ns

V_IN= 90% Point to 10% Point (1)

V_IN= 10% Point to 90% Point (1)

Synchronous Outputs

T₆

Output Valid Delay

2

4

25

28

ns

T_6H

T₇

HLDA Output Valid Delay

ALE Width

15

2

T₈

ALE Output Valid Delay

Output Float Delay

18

20

T₉

2

(2)

T_9H

HLDA Output Float Delay

4

Synchronous Inputs

T₁₀

T₁₁

T_11H

T₁₂

T₁₃

T₁₄

T₁₅

T₁₆

Input Setup 1

3

5

ns

(3)

Input Hold

HOLD Input Hold

Input Setup 2

4

8

Setup to ALE Inactive

Hold after ALE Inactive

Reset Hold

10

8

3

(3)

Reset Setup

5

(3)

T₁₇

Reset Width

1281

41 CLK2 Periods Minimum

NOTES:

1. Clock rise and fall times are not tested.

2. A float condition occurs when the maximum output current becomes less than I_LO. Float delay is not tested; however, it should not be longer than

the valid delay.

3. LAD31:0, BADAC, HOLD, LOCK and READY are synchronous inputs. IAC/INT₀, INT₁, INT₂/INT_Rand INT₃may be synchronous or asynchronous.

17

80960KA

Table 7. 80960KA AC Characteristics (20 MHz)

Symbol

Input Clock

T₁

Parameter

Min

Max

Units

Notes

Processor Clock Period (CLK2)

25

6

125

ns

V_IN= 1.5V

T₂

T₃

Processor Clock Low Time (CLK2)

V_IL= 10% Point = 1.2V

Processor Clock High Time

(CLK2)

6

V_IH= 90% Point = 0.1V + 0.5 V_CC

T₄

T₅

Processor Clock Fall Time (CLK2)

Processor Clock Rise Time (CLK2)

10

ns

V_IN= 90% Point to 10% Point (1)

V_IN= 10% Point to 90% Point (1)

Synchronous Outputs

T₆

Output Valid Delay

2

4

20

23

ns

T_6H

T₇

HLDA Output Valid Delay

ALE Width

12

2

T₈

ALE Output Valid Delay

Output Float Delay

18

20

T₉

2

(2)

T_9H

HLDA Output Float Delay

4

Synchronous Inputs

T₁₀

T₁₁

T_11H

T₁₂

T₁₃

T₁₄

T₁₅

T₁₆

Input Setup 1

3

5

ns

(3)

Input Hold

HOLD Input Hold

Input Setup 2

4

7

Setup to ALE Inactive

Hold after ALE Inactive

Reset Hold

10

8

3

Reset Setup

5

T₁₇

Reset Width

1025

41 CLK2 Periods Minimum

NOTES:

1. Clock rise and fall times are not tested.

2. A float condition occurs when the maximum output current becomes less than I_LO. Float delay is not tested; however, it should not be longer than

the valid delay.

3. LAD31:0, BADAC, HOLD, LOCK and READY are synchronous inputs. IAC/INT₀, INT₁, INT₂/INT_Rand INT₃may be synchronous or asynchronous.

18

80960KA

Table 8. 80960KA AC Characteristics (25 MHz)

Symbol

Input Clock

T₁

Parameter

Min

Max

Units

Notes

Processor Clock Period (CLK2)

20

5

125

ns

V_IN= 1.5V

T₂

T₃

Processor Clock Low Time (CLK2)

V_IL= 10% Point = 1.2V

Processor Clock High Time

(CLK2)

5

V_IH= 90% Point = 0.1V + 0.5 V_CC

T₄

T₅

Processor Clock Fall Time (CLK2)

Processor Clock Rise Time (CLK2)

10

ns

V_IN= 90% Point to 10% Point (1)

V_IN= 10% Point to 90% Point (1)

Synchronous Outputs

T₆

Output Valid Delay

2

4

18

23

ns

T_6H

T₇

HLDA Output Valid Delay

ALE Width

12

2

T₈

ALE Output Valid Delay

Output Float Delay

18

20

T₉

2

(2)

T_9H

HLDA Output Float Delay

4

Synchronous Inputs

T₁₀

T₁₁

T_11H

T₁₂

T₁₃

T₁₄

T₁₅

T₁₆

Input Setup 1

3

5

ns

(3)

Input Hold

HOLD Input Hold

Input Setup 2

4

7

Setup to ALE Inactive

Hold after ALE Inactive

Reset Hold

8

3

Reset Setup

5

T₁₇

Reset Width

820

41 CLK2 Periods Minimum

NOTES:

1. Clock rise and fall times are not tested.

2. A float condition occurs when the maximum output current becomes less than I_LO. Float delay is not tested; however, it should not be longer than

the valid delay.

3. LAD31:0, BADAC, HOLD, LOCK and READY are synchronous inputs. IAC/INT₀, INT₁, INT₂/INT_Rand INT₃may be synchronous or asynchronous.

19

80960KA

T

1

T

3

HIGH LEVEL (MIN) 0.55V

CC

90%

1.5 V

LOW LEVEL (MAX) 0.8V

10%

T

2

T

5

4

Figure 15. Processor Clock Pulse (CLK2)

FIRST

A

B

C

D

A

...

CLK2

CLK

T

16

15

...

RESET

T

17

...

OUTPUTS

INIT PARAMETERS (BADAC,

T

= RESET HOLD

= RESET SETUP

= RESET WIDTH

15

16

17

INT /IAC) MUST BE SET UP 8 CLOCKS

0

PRIOR TO THIS CLK2 EDGE

INIT PARAMETERS MUST BE HELD

BEYOND THIS CLK2 EDGE

Figure 16. RESET Signal Timing

20

80960KA

3.0 MECHANICAL DATA

3.1.1. Pin Assignment

The PGA and PQFP have different pin assignments.

Figure 18 shows the view from the PGA bottom (pins

facing up) and Figure 19 shows a view from the PGA

top (pins facing down). Figure 20 shows the PQFP

package; Figure 21 shows the PQFP pinout with

signal names. Notice that the pins are numbered in

order from 1 to 132 around the package perimeter.

Table 9 and Table 10 list the function of each PGA

pin; Table 11 and Table 12 list the function of each

PQFP pin.

3.1. Packaging

The 80960KA is available in two package types:

•

132-lead ceramic pin-grid array (PGA). Pins are

arranged 0.100 inch (2.54 mm) center-to-center, in

a 14 by 14 matrix, three rows around (see Figure

17).

•

132-lead plastic quad flat pack (PQFP). This

package uses fine-pitch gull wing leads arranged in

a single row along the package perimeter with

0.025 inch (0.64 mm) spacing (see Figure 20).

Dimensions for both package types are given in the

Intel Packaging handbook (Order #240800).

1

2

3

4

5

6

7

8

9

10

11

12

13

14

A

B

C

D

E

F

G

H

J

K

L M N P

Figure 17. 132-Lead Pin-Grid Array (PGA) Package

21

80960KA

1

2

3

4

5

6

7

8

9

10

11

12

13

14

P

V_CCN.C. N.C. N.C. N.C. N.C.

N.C. N.C. N.C. N.C. N.C. N.C. V_SSV_CC

N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.

N

V_SS

N.C. N.C. N.C. N.C. N.C.

M

V_SS

V_SSV_CC

V_SS

V_CC

N.C.

N.C. N.C. N.C.

N.C. V_CCN.C.

V_SSN.C. N.C.

V_CCN.C. N.C.

N.C. N.C.

L

K

J

L

K

J

DEN N.C. V_CC

BE₃FAIL V_SS

N.C. N.C. N.C.

DT/R BE₂V_SS

W/R BE₀LOCK

H

G

F

H

G

F

LAD₃₀READY BE₁

CACHE

LAD₂₉LAD₃₁

N.C. N.C. N.C.

N.C. V_SSN.C.

V_CCN.C. N.C.

E

D

E

D

LAD₂₈

LAD₂₆LAD₂₇

ALE ADS HLDA

C

B

A

C

B

A

HOLD LAD₂₅BADAC V_CCV_SSLAD₂₀

LAD₈LAD₃V_CC

V_SSINT₃INT₁INT₀

LAD₁₃

V_SS

LAD₂₃LAD₂₄LAD₂₂LAD₂₁LAD₁₈LAD₁₅LAD₁₂LAD₁₀LAD₆LAD₂CLK2 LAD₀RESET

LAD₁₇

LAD₁₉

LAD₁₁

LAD₉LAD₇LAD₅LAD₄LAD₁INT₂V_CC

V_CC

V_SS

LAD₁₆LAD₁₄

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Figure 18. 80960KA PGA Pinout—View from Bottom (Pins Facing Up)

22

80960KA

14

13

12

11

10

9

8

7

6

5

4

3

2

1

P

V_CCV_SSN.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. V_CC

N

V_SS

N.C. N.C.

N.C.

V_CCV_SS

N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.

M

V_CCV_SS

N.C. N.C. N.C.

N.C. N.C. V_SS

N.C. N.C. V_CC

N.C. N.C. N.C.

N.C. N.C. N.C. N.C.

V_SS

V_CC

V_SS

V_CCN.C.

N.C. DEN

FAIL BE₃

BE₂DT/R

L

K

J

K

J

H

G

F

E

D

H

G

F

E

D

LOCK BE₀W/R

BE₁READY LAD₃₀

CACHE LAD₃₁LAD₂₉

LAD₂₇LAD₂₆LAD₂₈

V_SS

N.C.

V_CC

N.C. N.C.

HLDA ADS ALE

C

B

A

C

B

A

INT₀INT₁INT₃V_SSV_CCLAD₃LAD₈LAD₁₃LAD₂₀V_SSV_CCBADAC LAD₂₅HOLD

V_SSRESET LAD₀CLK2 LAD₂LAD₆LAD₁₀LAD₁₂LAD₁₅LAD₁₈LAD₂₁LAD₂₂LAD₂₄LAD₂₃

V_CCINT₂LAD₁LAD₄LAD₅LAD₇LAD₉LAD₁₁LAD₁₄LAD₁₆LAD₁₇LAD₁₉V_SSV_CC

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Figure 19. 80960KA PGA Pinout—View from Top (Pins Facing Down)

Figure 20. 80960KA 132-Lead Plastic Quad Flat-Pack (PQFP) Package

23

NOTE: To address the fact that many of the package prefix variables have changed,

all package prefix variables in this document are now indicated with an "x".

80960KA

99 98 97

100

96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68

⁶⁷66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

NC

LAD0

LAD1

LAD2

V_SS

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

1

NC

V_SS

V_CC

LAD3

LAD4

LAD5

LAD6

LAD7

LAD8

LAD9

LAD10

LAD11

LAD12

V_SS

NC

V_SS

NC

LAD13

LAD14

LAD15

LAD16

LAD17

LAD18

LAD19

NC

V_SS

V_CC

LAD20

LAD21

LAD22

V_SS

LAD23

LAD24

NC

V_CC

LAD25

BADAC

HOLD

NC

ADS

2

3

4

5

6

7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Figure 21. PQFP Pinout - View From Top

NOTE: To address the fact that many of the package prefix variables have changed,

all package prefix variables in this document are now indicated with an "x".

24

80960KA

3.2. Pinout

Table 9. 80960KA PGA Pinout — In Pin Order

A1

Signal

C6

Signal

LAD₂₀

H1

Signal

W/R

Signal

V_CC

M10

V_SS

V_CC

A2

A3

A4

A5

A6

A7

A8

A9

V_SS

C7

LAD₁₃

LAD₈

H2

H3

H12

H13

H14

J1

BE₀

M11

M12

M13

M14

N1

LAD₁₉

LAD₁₇

LAD₁₆

LAD₁₄

LAD₁₁

LAD₉

LAD₇

C8

LOCK

N.C.

DT/R

BE₂

N.C.

V_SS

C9

LAD₃

C10

C11

C12

C13

C14

V_CC

V_SS

INT₃/INTA

INT₁

N2

N.C.

J2

N3

IAC/INT₀

J3

V_SS

N4

A10

A11

A12

A13

LAD₅

LAD₄

D1

ALE

J12

J13

J14

K1

N.C.

BE₃

N5

N6

N7

N8

N.C.

D2

ADS

HLDA

V_CC

LAD₁

D3

INT₂/INTR

D12

A14

B1

V_CC

D13

D14

N.C.

K2

K3

FAILURE

V_SS

N9

N.C.

LAD₂₃

N10

B2

B3

B4

LAD₂₄

LAD₂₂

LAD₂₁

E1

E2

E3

LAD₂₈

LAD₂₆

LAD₂₇

K12

K13

K14

V_CC

N.C.

N11

N12

N13

N.C.

B5

B6

LAD₁₈

LAD₁₅

E12

E13

N.C.

V_SS

L1

L2

DEN

N.C.

N14

P1

N.C.

V_CC

B7

B8

B9

LAD₁₂

LAD₁₀

LAD₆

E14

F1

N.C.

L3

V_CC

V_SS

N.C.

P2

P3

P4

N.C.

LAD₂₉

LAD₃₁

L12

L13

F2

B10

B11

B12

LAD₂

CLK2

LAD₀

F3

CACHE

N.C.

L14

M1

M2

N.C.

V_CC

P5

P6

P7

N.C.

F12

F13

N.C.

B13

B14

C1

RESET

V_SS

F14

G1

G2

G3

N.C.

M3

M4

M5

M6

V_SS

V_CC

N.C.

P8

N.C.

LAD₃₀

READY

BE₁

P9

HOLD

LAD₂₅

P10

P11

C2

C3

C4

BADAC

V_CC

G12

G13

N.C.

M7

M8

N.C.

P12

P13

N.C.

V_SS

C5

V_SS

G14

N.C.

M9

N.C.

P14

V_CC

NOTE: Do not connect any external logic to any pins marked N.C.

25

80960KA

Table 10. 80960KA PGA Pinout — In Signal Order

Signal

ADS

D2

D1

C3

H2

G3

J2

Signal

LAD₁₅

B6

A5

A4

B5

A3

C6

B4

B3

Signal

N.C.

J14

K13

K14

L13

L14

M1

Signal

N.C.

P9

ALE

LAD₁₆

LAD₁₇

LAD₁₈

LAD₁₉

LAD₂₀

LAD₂₁

LAD₂₂

N.C.

P10

P11

P12

L2

BADAC

BE₀

N.C.

BE₁

N.C.

BE₂

READY

RESET

V_CC

G2

BE₃

K1

F3

M6

B13

A1

CACHE

M7

CLK2

B11

L1

LAD₂₃

LAD₂₄

LAD₂₅

LAD₂₆

LAD₂₇

LAD₂₈

LAD₂₉

LAD₃₀

LAD₃₁

LOCK

N.C.

B1

B2

N.C.

M8

M9

M12

M13

M14

N2

V_CC

V_SS

W/R

A14

C4

DEN

DT/R

J1

C2

C10

D12

K12

L3

FAILURE

HLDA

HOLD

IAC/INT₀

INT₁

K2

E2

D3

E3

C1

E1

C14

C13

A13

C12

B12

A12

B10

C9

F1

N3

M2

M5

M11

P1

G1

N4

INT₂/INTR

INT₃/INTA

LAD₀

F2

N5

H3

N6

D13

D14

E12

E14

F12

F13

F14

G12

G13

G14

H12

H13

H14

J12

J13

N7

P14

A2

LAD₁

N.C.

N8

LAD₂

N.C.

N9

B14

C5

LAD₃

N.C.

N10

N11

N12

N13

N14

P2

LAD₄

A11

A10

B9

N.C.

C11

E11

J3

LAD₅

N.C.

LAD₆

N.C.

LAD₇

A9

N.C.

K3

LAD₈

C8

N.C.

L12

M3

M4

M10

N1

LAD₉

A8

N.C.

P3

LAD₁₀

LAD₁₁

LAD₁₂

LAD₁₃

LAD₁₄

B8

N.C.

P4

A7

N.C.

P5

B7

N.C.

P6

C7

N.C.

P7

P13

H1

A6

N.C.

P8

NOTE: Do not connect any external logic to any pins marked N.C.

26

80960KA

Table 11. 80960KA PQFP Pinout — In Pin Order

1

Signal

HLDA

ALE

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

Signal

N.C.

V_CC

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

Signal

V_SS

Signal

LAD₀

LAD₁

LAD₂

V_SS

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

2

V_SS

3

LAD₂₆

LAD₂₇

LAD₂₈

LAD₂₉

LAD₃₀

LAD₃₁

V_SS

V_CC

N.C.

V_CC

4

N.C.

V_CC

5

V_CC

LAD₃

LAD₄

LAD₅

LAD₆

LAD₇

LAD₈

LAD₉

LAD₁₀

LAD₁₁

LAD₁₂

V_SS

6

N.C.

V_SS

7

8

V_CC

9

V_SS

N.C.

V_SS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

CACHE

W/R

N.C.

V_SS

READY

DT/R

BE₀

V_SS

BE₁

N.C.

V_CC

BE₂

LAD₁₃

LAD₁₄

LAD₁₅

LAD₁₆

LAD₁₇

LAD₁₈

LAD₁₉

LAD₂₀

LAD₂₁

LAD₂₂

V_SS

BE₃

V_CC

FAILURE

V_SS

IAC/INT₀

INT₁

INT₂/INTR

INT₃/INTA

N.C.

V_SS

LOCK

DEN

V_SS

N.C.

V_CC

V_SS

V_CC

N.C.

V_SS

N.C.

CLK2

V_CC

V_SS

RESET

N.C.

V_SS

LAD₂₃

LAD₂₄

LAD₂₅

BADAC

HOLD

N.C.

V_CC

N.C.

V_SS

ADS

NOTE: Do not connect any external logic to any pins marked N.C.

27

80960KA

Table 12. 80960KA PQFP Pinout — In Signal Order

Signal

ADS

Signal

LAD₁₅

Signal

N.C.

Signal

132

117

49

V_CC

V_SS

41

ALE

2

LAD₁₆

LAD₁₇

LAD₁₈

LAD₁₉

LAD₂₀

LAD₂₁

LAD₂₂

LAD₂₃

LAD₂₄

LAD₂₅

LAD₂₆

LAD₂₇

LAD₂₈

LAD₂₉

LAD₃₀

LAD₃₁

LOCK

N.C.

118

119

120

121

122

123

124

126

127

128

3

N.C.

READY

RESET

V_CC

50

51

54

58

59

60

61

62

63

64

65

66

69

72

75

76

77

78

81

89

94

95

96

97

98

131

12

93

29

30

35

36

55

56

70

71

74

82

83

92

9

BADAC

BE₀

129

14

BE₁

15

BE₂

16

BE₃

17

CACHE

CLK2

DEN

10

91

21

DT/R

13

19

22

23

26

27

32

33

42

52

53

57

67

68

73

79

80

84

90

99

103

114

125

11

FAILURE

HLDA

HOLD

IAC/INT₀

INT₁

18

1

4

130

85

5

6

86

7

INT₂/INTR

INT₃/INTA

LAD₀

87

8

88

20

24

25

28

31

34

37

38

39

40

43

44

45

46

47

48

100

101

102

104

105

106

107

108

109

110

111

112

113

115

116

LAD₁

N.C.

LAD₂

N.C.

LAD₃

N.C.

LAD₄

N.C.

LAD₅

N.C.

LAD₆

N.C.

LAD₇

N.C.

LAD₈

N.C.

LAD₉

N.C.

LAD₁₀

LAD₁₁

LAD₁₂

LAD₁₃

LAD₁₄

N.C.

V_CC

N.C.

V_CC

N.C.

V_CC

W/R

NOTE: Do not connect any external logic to any pins marked N.C.

28

80960KA

Maximum allowable ambient temperature (T_A)

permitted without exceeding T_Cis shown by the

graphs in Figures 23, 24, 25 and 26. The curves

3.3. Package Thermal Specification

The 80960KA is specified for operation when case

temperature is within the range 0°C to 85°C (PGA) or

0°C to 100°C (PQFP). Measure case temperature at

the top center of the package. Ambient temperature

can be calculated from:

assume the maximum permitted supply current (I_CC

)

at each speed, V_CCof +5.0 V and a T_CASEof +85°C

(PGA) or +100°C (PQFP).

If the 80960KA is to be used in a harsh environment

where the ambient temperature may exceed the limits

for the normal commercial part, consider using an

extended temperature device. These components are

T_J= T_C+ P*θ_jc

T_A= T_J+ P*θ_ja

MHz in the ceramic

PGA package. Extended operating temperature

range is –40° .C to +125°C (case)

20 and 25

available at 16,

T_C= T_A+ P*[θ_ja−θ_jc]

Values for θ_jaand θ_jcfor various airflows are given in

Table 13 for the PGA package and in Table 14 for the

PQFP package. The PGA’s θ_jacan be reduced by

adding a heatsink. For the PQFP, however, a heatsink

is not generally used since the device is intended to

be surface mounted.

Figure 26 shows the maximum allowable ambient

temperature for the 20 MHz extended temperature

TA80960KA at various airflows. The curve assumes

an I_CCof 420 mA, V_CCof 5.0 V and a T_CASEof

+125°C.

Table 13. 80960KA PGA Package Thermal Characteristics

Thermal Resistance — °C/Watt

Airflow — ft./min (m/sec)

Parameter

0

50

100

200

400

600

800

(0)

(0.25)

(0.50)

(1.01)

(2.03)

(3.04)

(4.06)

θ Junction-to-Case

2

9

θ Case-to-Ambient

(No Heatsink)

19

18

17

15

12

10

θ_JA

θ_J-PIN

θ_JC

θ Case-to-Ambient

(Omnidirectional

Heatsink)

16

15

14

13

12

11

9

8

7

6

5

θ_J-CAP

θ Case-to-Ambient

(Unidirectional

Heatsink)

NOTES:

3.

θ

_J-CAP= 4°C/W (approx.)

_J-PIN= 4°C/W (inner pins) (approx.)

_J-PIN= 8°C/W (outer pins) (approx.)

1. This table applies to 80960KA PGA plugged into

socket or soldered directly to board.

2.

θ_JA= θ_JC+ θ_CA

29

80960KA

Table 14. 80960KA PQFP Package Thermal Characteristics

Thermal Resistance — °C/Watt

Airflow — ft./min (m/sec)

Parameter

0

50

100

200

400

600

800

(0)

(0.25)

(0.50)

(1.01)

(2.03)

(3.04)

(4.06)

θ Junction-to-Case

9

8

θ Case-to-Ambient

(No Heatsink)

22

19

18

16

11

NOTES:

3.

θ

_JL= 18°C/W (approx.)

_JB= 18°C/W (approx.)

1. This table applies to 80960KA PQFP soldered

directly to board.

2.

θ_JA= θ_JC+ θ_CA

θ_JC

θ_JL

θ_JB

T

h

CLK2

CLK

T

12

11

HOLD

HLDA

T

6H

9H

Figure 22. HOLD Timing

30

80960KA

90

85

80

75

70

65

60

55

0

200

400

600

800

AIRFLOW (ft/min)

PQFP

PGA with no

heatsink

PGA with omni-

directional heatsink

PGA with uni-

directional heatsink

Figure 23. 16 MHz Maximum Allowable Ambient Temperature

90

85

80

75

70

65

60

55

50

0

200

400

600

800

AIRFLOW (ft/min)

PQFP

PGA with no

heatsink

PGA with omni-

directional heatsink

PGA with uni-

directional heatsink

Figure 24. 20 MHz Maximum Allowable Ambient Temperature

31

80960KA

85

80

75

70

65

60

55

50

45

40

0

100

200

300

400

500

600

700

800

AIRFLOW (ft/min)

PQFP

PGA with no

heatsink

PGA with omni-

directional heatsink

PGA with uni-

directional heatsink

Figure 25. 25 MHz Maximum Allowable Ambient Temperature

120

115

110

105

100

95

90

0

100

200

300

400

500

600

700

800

AIRFLOW (ft/min)

PGA with no

heatsink

PGA with omni-

directional heatsink

PGA with uni-

directional heatsink

Figure 26. Maximum Allowable Ambient Temperature

for the Extended Temperature TA-80960KA at 20 MHz in PGA Package

32

80960KA

4.0 WAVEFORMS

Figures 27, 28, 29 and 30 show the waveforms for various transactions on the 80960KA’s local bus.

T

r

a

d

r

a

d

CLK2

CLK

LAD31:0

ALE

ADS

BE3:0

W/R

DT/R

DEN

READY

Figure 27. Non-Burst Read and Write Transactions Without Wait States

33

80960KA

T

a

T

r

T

a

d

r

d

CLK2

CLK

LAD31:0

ALE

ADS

BE3:0

W/R

DT/R

DEN

READY

Figure 28. Burst Read and Write Transaction Without Wait States

34

80960KA

T

r

a

w

d

w

d

w

d

w

d

CLK2

CLK

LAD31:0

ALE

ADS

BE3:0

W/R

DT/R

DEN

READY

Figure 29. Burst Write Transaction with 2, 1, 1, 1 Wait States

35

80960KA

T

r

a

w

d

r

a

w

d

CLK2

CLK

LAD31:0

ALE

ADS

BE3:2

BE1:0

W/R

DT/R

DEN

READY

Figure 30. Accesses Generated by Quad Word Read Bus Request,

Misaligned Two Bytes from Quad Word Boundary (1, 0, 0, 0 Wait States)

36

80960KA

INTERRUPT

ACKNOWLEDGEMENT

INTERRUPT

ACKNOWLEDGEMENT

IDLE

(5 BUS STATES)

CYCLE 1

CYCLE 2

T

r

X

a

d

r

I

a

w

d

CLK2

CLK

INTR

VECTOR

ADDR

LAD31:0

ALE

ADS

INTA

DT/R

DEN

LOCK

READY

NOTE:

INTR can go low no sooner than the input hold time following the beginning of interrupt acknowledgment cycle 1.

For a second interrupt to be acknowledged, INTR must be low for at least three cycles before it can be reasserted.

Figure 31. Interrupt Acknowledge Transaction

37

80960KA

5.0 REVISION HISTORY

Revision -006

To address the fact that many of the package prefix variables have changed,

all package prefix variables in this document are now indicated with an "x".

No revision history was maintained in earlier revisions of this data sheet. All errata that has been identified to

date is incorporated into this revision. The sections significantly changed since the previous revision are:

Last

Rev.

Section

Description

Table 3. 80960KA Pin Description:

L-Bus Signals (pg. 8)

-004

LOCK pin description rewritten for clarity.

2.3. Connection Recommenda-

tions (pg. 11)

-004

Changed suggested open-drain termination networks to

reflect more realistic operating conditions with reduction in

DC power consumption.

Figure 9. Typical Current vs. Fre-

quency (Hot Temp) (pg. 13)

-004

Added figure for typical power supply current at hot tempera-

ture to aid thermal analysis.

Figure 12. Test Load Circuit for

Three-State Output Pins (pg. 14)

All outputs now specified with standard 50 pF test loads to

agree with actual test methodology.

Figure 13. Test Load Circuit for

Open-Drain Output Pins (pg. 14)

2.7. DC Characteristics (pg. 15)

-004

ICC max specification reduced:

WAS:

IS:

AT:

375 mA

420 mA

480 mA

315 mA

360 mA

420 mA

16 MHz

20 MHz

25 MHz

Figures 7, 8, 9, 23, 24, 25 and 26 have also been changed

accordingly.

2.8. AC Specifications (pg. 16)

-004

25 MHz operation extended to product in PQFP package. T₈

min. improved at all frequencies from 0 ns to 2 ns and T₈

max. improved from 20 ns to 18 ns.

T_8Hmax improvement:

WAS:

31ns

26ns

24ns

IS:

AT:

28ns

23ns

16 MHz

20 MHz

25 MHz

Functional Waveforms

Various

-004

Redrawn for clarity. CLK signal drawn with more likely phase

relationship to CLK2. Open-drain output signals drawn to

show correct inactive states.

Deleted all references to 10 MHz. Intel no longer offers a

10 MHz 80960KA device.

38


型号：	NG80960KA16
厂家：	INTEL
描述：	RISC Microprocessor, 32-Bit, 16MHz, CMOS, PQFP132, PLASTIC, QFP-132 时钟外围集成电路装置
文件：	总41页 (文件大小：2661K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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