NLXT905PE.C2SE001 [INTEL]
Ethernet Transceiver, 1-Trnsvr, CMOS, PQCC28, PLASTIC, LCC-28;
| 型号： | NLXT905PE.C2SE001 |
| 厂家： | 
INTEL |
| 描述： | Ethernet Transceiver, 1-Trnsvr, CMOS, PQCC28, PLASTIC, LCC-28 以太网：16GBASE-T 电信 电信集成电路 |
| 文件： | 总37页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® LXT905 Universal 10BASE-T
Transceiver with 3.3 V Support
Datasheet
The Intel® LXT905 Universal 10BASE-T Transceiver is designed for IEEE 802.3 physical layer
applications. It provides, in a single CMOS device, all of the active circuitry for interfacing most
standard IEEE 802.3 controllers to 10BASE- T media.
The LXT905 functions include the following:
Manchester encoding/decoding
Receiver squelch and transmit pulse shaping,
Jabber
Link integrity testing
Reversed polarity detection/correction.
The LXT905 drives the 10BASE-T twisted-pair cable, with only a simple isolation transformer,
using a single 3.3 V or 5 V power supply. Integrated filters simplify the design work required for
FCC-compliant EMI performance.
The LXT905 is part of the Intel Carrier Class Ethernet family of products. The LXT905
Universal Transceiver offers 10BASE-T connectivity solutions that support operations over an
extended temperature range, while providing features that increase reliability. The device has an
operational lifetime of at least ten years, with less than 100 failures per billion hours, and is
available a minimum of five years after the introduction of the product.
Intel Carrier Class Ethernet products are ideal for applications where equipment must function
reliably under environmentally controlled conditions, such as base stations, telecom/network
switches, factory floor equipment, and industrial computers.
Applications
Access devices (DSL, Cable Modems, and
Set-top Boxes)
Routers/Bridges/Switches/Hubs
Telecom Backplane
USB to Ethernet Converters
Product Features
Transparent 3.3V or 5V operation
Full-duplex capability
Integrated filters – Simplifies FCC
compliance
Integrated Manchester encoder/decoder
10BASE-T compliant transceiver
Automatic polarity correction
SQE enable/disable
Power-down mode with tri-state
Available in 28-pin PLCC and 32-pin
LQFP packages
Commercial Temperature Range (0 to
+70ºC)
Extended Temperature Range (-40 to
+85ºC)
Four LED drivers
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
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in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® LXT905 PHY Transceiver may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
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*Other names and brands may be claimed as the property of others.
Copyright © 2004, Intel Corporation
2
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
Universal 10BASE-T Transceiver with 3.3V Support—LXT905
Contents
1.0 Pin Assignments and Signal Descriptions...................................................................7
2.0 Functional Description........................................................................................................10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Introduction .........................................................................................................................10
Controller Compatibility Modes...........................................................................................11
Transmit Function ...............................................................................................................11
Jabber Control Function .....................................................................................................12
SQE Function .....................................................................................................................13
Receive Function ................................................................................................................13
Polarity Reverse Function...................................................................................................14
Collision Detection Function ...............................................................................................14
Loopback Functions............................................................................................................15
2.9.1 Internal Loopback ..................................................................................................15
2.9.2 External Loopback/Full Duplex ..............................................................................15
2.10 Link Integrity Test Function.................................................................................................16
3.0 Application Information ......................................................................................................18
3.1
Introduction .........................................................................................................................18
3.1.1 Termination Circuitry..............................................................................................18
3.1.2 Twisted-Pair Interface............................................................................................18
3.1.3 RBIAS Pin..............................................................................................................18
3.1.4 Crystal Information.................................................................................................18
3.1.5 Magnetic Information .............................................................................................19
Typical 10BASE-T Application............................................................................................19
Dual Network Support - 10BASE-T and Token Ring ..........................................................21
Simple 10BASE-T Connection............................................................................................22
3.2
3.3
3.4
4.0 Test Specifications ...............................................................................................................23
4.1
4.2
4.3
4.4
Timing Diagrams for Mode 1 (MD1 = Low, MD0 = Low) ....................................................27
Timing Diagrams for Mode 2 (MD1 = Low, MD0 = High)....................................................29
Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low)....................................................31
Timing Diagrams for Mode 4 (MD1 = High, MD0 = High)...................................................33
5.0 Mechanical Specifications.................................................................................................35
6.0 Ordering Information ...........................................................................................................37
Figures
1
2
3
4
5
6
7
8
Intel® LXT905 PHY Block Diagram...............................................................................................6
Intel® LXT905 PHY Pin Assignments ...........................................................................................7
Intel® LXT905 PHY TPO Output Waveform ...............................................................................10
Jabber Control Function .............................................................................................................12
SQE Function .............................................................................................................................13
Collision Detection Function .......................................................................................................15
Link Integrity Test Function.........................................................................................................17
Intel® Controller Application (Mode 2) ........................................................................................20
3
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
Universal 10BASE-T Transceiver with 3.3V Support—LXT905
9
Intel® LXT905 PHY/Texas Instruments* 380C26 Interface for Dual 10BASE-T
and Token Ring Support (Mode 4) .............................................................................................21
10 Intel® LXT905 PHY/Motorola* MC68EN360 Interface for Full-Duplex
10BASE-T (Mode 1) ...................................................................................................................22
11 Mode 1 RCLK/Start-of-Frame Timing.........................................................................................27
12 Mode 1 RCLK/End-of-Frame Timing ..........................................................................................27
13 Mode 1 Transmit Timing.............................................................................................................28
14 Mode 1 COL Output Timing........................................................................................................28
15 Mode 2 RCLK/Start-of-Frame.....................................................................................................29
16 Mode 2 RCLK/End-of-Frame Timing ..........................................................................................29
17 Mode 2 Transmit Timing.............................................................................................................30
18 Mode 2 COL Output Timing........................................................................................................30
19 Mode 3 RCLK/Start-of-Frame Timing.........................................................................................31
20 Mode 3 RCLK/End-of-Frame Timing ..........................................................................................31
21 Mode 3 Transmit Timing.............................................................................................................32
22 Mode 3 COL Output Timing........................................................................................................32
23 Mode 4 RCLK/Start-of-Frame Timing.........................................................................................33
24 Mode 4 RCLK/End-of-Frame Timing .........................................................................................33
25 Mode 4 Transmit Timing.............................................................................................................34
26 Mode 4 COL Output Timing........................................................................................................34
27 Intel® LXT905PC PHY Package Specifications.........................................................................35
28 Intel® LXT905LC PHY Package Specifications..........................................................................36
29 Ordering Information - Sample ...................................................................................................37
Tables
1
Intel® LXT905 PHY Signal Descriptions....................................................................................... 8
2
3
4
5
6
7
8
9
Controller Compatibility Mode Options .......................................................................................11
Loopback Modes ........................................................................................................................16
Suitable Crystals.........................................................................................................................18
Absolute Maximum Values.........................................................................................................23
Recommended Operating Conditions ........................................................................................23
I/O Electrical Characteristics ......................................................................................................23
TP Electrical Characteristics.......................................................................................................24
Switching Characteristics ...........................................................................................................24
10 RCLK/Start-of-Frame Timing......................................................................................................25
11 RCLK/End-of-Frame Timing.......................................................................................................25
12 Transmit Timing..........................................................................................................................25
13 Miscellaneous Timing .................................................................................................................26
14 Plastic Leaded Chip Carrier........................................................................................................35
15 Quad Flat Package.....................................................................................................................36
16 Product Information ....................................................................................................................37
4
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
Universal 10BASE-T Transceiver with 3.3V Support—LXT905
Revision History
Revision Number: 003
Revision Date: February 6, 2004
Page
Description
Modified Table 16 “Product Information” under Section 6.0, “Ordering Information” (replaced MM
numbers).
37
Revision Number: 002
Revision Date: June 2001
Page
Description
1
1
New information under “Applications”.
Added new carrier class information (paragraphs 3 and 4).
Added +5V to Line Status, Figure 8.
22
23
Added +5V to Line Status, Figure 9.
Added second paragraph under Test Specifications “Note” regarding Quality and Reliability
issues.
25
25
37
Deleted Ambient operating temperatures from Table 5.
Added new diagram and table for LXT905PC/PE mechanical specifications.
5
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
Figure 1. Intel® LXT905 PHY Block Diagram
Mode Select Logic
Controller
Compatibility /
MD0
MD1
LI
Loopback /
Link Test
TCLK
RC
RC
CLKI
CLKO
TEN
Pulse
Shaper
&
XTAL
OSC
Watch-Dog
Timer
TPOP
TPON
CMO
S
TX
D
Manchester
Encoder
Filter
TXD
Loopback
Control
CD
Squelch/
Link Detect
Collision/
Polarity
Detect/
Correct
TPIP
TPIN
LEDL
RCLK
RXD
RX
Slicer
Manchester
Decoder
Collision
Logic
COL
LEDR
LEDT/PDN
DSQE
LBK
LEDC/FDE
6
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
1.0
Pin Assignments and Signal Descriptions
Figure 2. Intel® LXT905 PHY Pin Assignments
24
23
22
21
20
19
18
17
MD1
MD0
1
2
3
4
5
6
7
8
LBK
TEN
TCLK
TXD
COL
LBK
TEN
TCLK
TXD
COL
MD0
5
6
7
8
9
25
24
23
22
21
20
19
TPON
GND2
VCC2
TPOP
DSQE
RBIAS
TPON
GND3
VCC2
TPOP
DSQE
RBIAS
Rev #
LQFP
Rev #
PLCC
LXT905LC/LE XX
XXXXXX
Part #
LOT #
FPO #
Part # LXT905PC/PE XX
LOT # XXXXXX
XXXXXXXX
LEDC/FDE
LEDT/PDN
LEDR
10 FPO # XXXXXXXX
LEDC/FDE
LEDT/PDN
11
7
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
L
Table 1. Intel® LXT905 PHY Signal Descriptions (Sheet 1 of 2)
LQFP
Pin #
PLCC
Pin #
Symbol
I/O
Description
13
20
27
28
29
1
22
–
VCC1
VCC2
VCC3
VCC4
VCC5
–
–
–
–
–
Power Inputs 1 through 5. Power supply inputs of 3.3 V or
5 V.
–
–
30
31
2
3
CLKI
I
Crystal Oscillator. Connect a 20 MHz crystal across these
pins, or apply a 20 MHz clock at CLKI, with CLKO left open.
CLKO
O
11
12
21
32
15
23
4
GND1
GND2
GND3
GND4
–
–
–
–
Ground.
–
Loopback. When High, forces internal loopback. Disables
collision and the transmission of both data and link pulses.
Pulled Low internally.1
1
5
LBK
I
Transmit Enable. Enables data transmission and starts the
Watch-Dog Timer (WDT). Synchronous to TCLK. Pulled Low
internally1.
2
3
4
5
6
7
8
9
TEN
TCLK
TXD
I
O
I
Transmit Clock. A 10 MHz clock output. Connect this clock
signal directly to the transmit clock input of the controller.
Transmit Data. Input signal containing NRZ data to transmit
on the network. Connect TXD directly to the transmit data
output of the controller. Pulled Low internally1.
Collision Signal. Output that drives the collision detect input
of the controller.
COL
O
LED Collision or Full-Duplex Enable.
LEDC is an open drain driver for the collision indicator, and
pulls Low during collision. Extends LED “on” (which is Low
output) time by approximately 100 ms.
O
I
LEDC/
FDE
6
7
10
11
FDE enables full-duplex mode (external loopback) if tied Low
externally. Pulled High internally1.
LED Transmit or Power Down.
LEDT is an open drain driver for the transmit indicator.
Extends LED “on” (which is Low output) time by
LEDT/
PDN
O
I
approximately 100 ms. Pulls output Low during transmit.2
If externally tied Low, the LXT905 goes to power down state
(PDN). In power-down mode, LEDT tristates all logic inputs
and outputs.
LED Receive. Open drain driver for the receive indicator
LED. Extends LED “on” (which is Low output) time by
approximately 100 ms. Pulls output Low during receive.
Pulled High internally1.
8
9
12
13
LEDR
LEDL
O
O
LED Link. Open drain driver for link integrity indicator. Pulls
output Low during link test pass. Pulled High internally1.
1. Externally pull-up or pull-down each pin separately using a 10 k Ω, 1% termination resistor, or tie directly to
VCC or ground.
2. Do not allow this pin to float. If unused, tie High.
8
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
Table 1. Intel® LXT905 PHY Signal Descriptions (Sheet 2 of 2)
LQFP
Pin #
PLCC
Pin #
Symbol
I/O
Description
Carrier Detect. An output for notifying the controller that
activity exists on the network.
10
14
15
14
16
17
CD
O
Receive Clock. A recovered 10 MHz clock that is
synchronous to the received data and connects to the
controller receive clock input.
RCLK
RXD
O
O
Receive Data. Output signal connected directly to the
receive data input of the controller.
Link Enable. Controls link integrity test.
• Enabled when LI is High.
16
17
18
19
LI
I
I
• Disabled when LI is Low.
Bias Circuitry. A 7.5 kW 1% resistor to ground at this pin
controls operating circuit bias.
RBIAS
SQE Disable.
• When DSQE is High, the SQE function is disabled.
• When DSQE is Low, the SQE function is enabled.
18
20
DSQE
I
Disable SQE for normal operation in Hub/Switch/Repeater
applications. Pulled Low internally1.
19
22
21
24
TPOP
TPON
O
O
Twisted-Pair Outputs. Differential outputs to the twisted-
pair cable. The outputs are pre-equalized.
Mode Select 0 and 1. Mode select pins determine controller
compatibility mode in accordance with Table 2. Pulled Low
internally1.
23
24
25
26
MDO
MDI
I
I
Twisted-Pair Inputs. A differential input pair from the twisted-
pair cable. Receive filter is integrated on-chip. Does not
require external filters.
25
26
27
28
TPIP
TPIN
I
I
1. Externally pull-up or pull-down each pin separately using a 10 k Ω, 1% termination resistor, or tie directly to
VCC or ground.
2. Do not allow this pin to float. If unused, tie High.
9
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
2.0
Functional Description
2.1
Introduction
The Intel® LXT905 Universal 10BASE-T Transceiver performs the physical layer signaling (PLS)
and Media Attachment Unit (MAU) functions, as defined in the IEEE 802.3 specification. It
functions as an integrated PLS/MAU for use with 10BASE-T twisted-pair networks.
The LXT905 interfaces a back-end controller to a twisted-pair (TP) cable. The controller interface
includes a transmit and receive clock and NRZ data channels, and mode control logic and
signaling. The twisted-pair interface comprises the following two circuits:
• Twisted-Pair Input (TPI)
• Twisted-Pair Output (TPO).
In addition to the two basic interfaces, the LXT905 contains an internal crystal oscillator, and four
LED drivers for visual status reporting.
The back-end controller side of the interface defines functions.
• The LXT905 transmit function refers to data transmitted by the back-end to the twisted-pair
network.
• The LXT905 receive function refers to data received by the back-end of the twisted-pair
network.
The LXT905 performs all required functions defined in the IEEE 802.3 10BASE-T MAU
specification as follows:
• Collision detection
• Link integrity testing
• Signal quality error messaging
• Jabber control
• Loopback
Figure 3. Intel® LXT905 PHY TPO Output Waveform
10
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
2.2
2.3
Controller Compatibility Modes
The LXT905 is compatible with most industry standard controllers, including devices from
Advanced Micro Devices* (AMD), Fujitsu*, National Semiconductor*, Seeq*, Motorola*, and
Texas Instruments*. Four different control signal timing and polarity schemes (Modes 1 through 4)
provide this compatibility. The MD0 and MD1 mode select pins determine controller compatibility
modes (see Table 2). Refer to Section 4.0, “Test Specifications” on page 23 for timing diagrams
and parameters.
Transmit Function
The LXT905 receives NRZ data from the controller at the TXD input, as shown in Figure 1 “Intel®
LXT905 PHY Block Diagram” on page 6, and passes it through a Manchester encoder. The
LXT905 then transfers encoded data to the twisted-pair network (TPO circuit). The advanced
integrated pulse shaping and filtering network produces the output signal on TPON and TPOP, as
shown in Figure 3 “Intel® LXT905 PHY TPO Output Waveform” on page 10. The TPO output is
pre-distorted and pre-filtered to meet the 10BASE-T jitter template. An internal, continuous
resistor-capacitor filter removes any high-frequency clocking noise from the pulse shaping
circuitry. Integrated filters simplify the design work required for FCC compliant EMI performance.
During idle periods, the LXT905 transmits link integrity test pulses on the TPO circuit (if LI is
enabled and LBK is disabled).
Table 2. Controller Compatibility Mode Options
Controller Mode
MD1
MD0
Mode 1 - For Motorola* MC68EN360 or compatible controllers (AMD* AM7990)
Mode 2 - For Intel* 82596 or compatible controllers1
Low
Low
High
High
Low
High
Low
High
Mode 3 - For Fujitsu* MB86950, MB86960 or compatible controllers (Seeq* 8005)2
Mode 4 - For TI* TMS380C26 or compatible controllers
1. Refer to the MAC Interface Design Guide for Intel Controllers Application Note when designing with Intel
controllers.
2. SEEQ* controllers require inverters on CLKI, LBK, RCLK, and COL.
11
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
2.4
Jabber Control Function
Figure 4 is a state diagram of the LXT905 jabber control function. The LXT905 on-chip Watch-
Dog Timer (WDT) prevents the DTE from locking into a continuous transmit mode. When a
transmission exceeds the time limit, the WDT disables the transmit and loopback functions and
activates the COL pin. Once the LXT905 is in the jabber state, the TXD circuit must remain idle
for a period of 0.25 to 0.75 seconds before it exits the jabber state.
Figure 4. Jabber Control Function
Power On
No Output
DO=Active
Nonjabber Output
Start_XMIT_MAX_Timer
DO=Idle
DO=Active ∗
XMIT_Max_Timer_Done
Jab
XMIT=Disable
LPBK=Disable
CI=SQE
DO=Idle
Unjab Wait
Start_Unjab_Timer
XMIT=Disable
LPBK=Disable
CI=SQE
Unjab_ Timer_Done
DO=Active ∗
Unjab_Timer_Not_Done
12
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
2.5
SQE Function
The LXT905 supports the Signal Quality Error (SQE) function (see Figure 5). After every
successful transmission on the 10BASE-T network, the LXT905 transmits the SQE signal for
10 bit times (BT) ± 5BT on the COL pin of the device.
• To disable the SQE function for repeater/switch applications, set DSQE High.
• To enable the SQE function, set DSQE Low.
Figure 5. SQE Function
Power On
Output Idle
DO=Active
Output Detected
DO=Idle ∗
DSQE=0
DSQE=1
SQE Wait Test
Start_SQE_Test__Wait_Timer
XMIT=Disable
SQE_Test__Wait_Timer_Done ∗
XMIT=Enable
SQE Test
Start_SQE_Test_Timer
CI=SQE
SQE_Test_Timer_Done
2.6
Receive Function
The LXT905 receive function acquires timing and data from the twisted-pair network (TPI circuit).
The LXT905 passes valid received signals through the on-chip filters and Manchester decoder,
then outputs them as decoded NRZ data on the RXD pin, and as receive timing on the RCLK pin.
An internal RC filter and an intelligent squelch function discriminate noise from link test pulses
and valid data streams. The receive function activates only when receiving valid data streams
above the squelch level with proper timing.
If the differential signal at the TPI circuit inputs falls below 85 percent of the threshold level
(unsquelched) for 8 bit times (typical), the LXT905 receive function enters the idle state. The
LXT905 automatically corrects reversed polarity on the TPI circuit.
13
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
2.7
Polarity Reverse Function
The LXT905 polarity reverse function uses both link pulses and end-of-frame data to determine the
polarity of the received signal.
• If you disable Link Integrity testing, polarity detection is based only on received data. A
reversed polarity condition exists if the LXT905 detects eight consecutive opposite receive
link pulses, without receiving a link pulse of the expected polarity.
• Reversed polarity also occurs if the LXT905 receives four consecutive frames with a reversed
start-of-idle.
• Whenever the LXT905 receives a correct polarity frame or a correct link pulse, it resets these
two counters to zero.
• If the LXT905 enters the link fail state, and does not receive any valid data or link pulses
within 96 to 128 ms, it resets the polarity to the default non-flipped condition.
Polarity correction is always enabled.
2.8
Collision Detection Function
A collision is the simultaneous presence of valid signals on both the TPI circuit and the TPO
circuit. The LXT905 reports collisions to the back-end via the COL pin. If the TPI circuit becomes
active while there is activity on the TPO circuit, the TPI data passes to the back-end over the RXD
circuit, disabling normal loopback. Figure 6 is a state diagram of the LXT905 collision detection
function.
14
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
Figure 6. Collision Detection Function
A
Power On
TEN=Active ∗
TPI=Idle ∗
XMIT=Enable
Idle
TPI=Active
Output
Input
RXD=TPI
TPO=TXD
RXD=TXD
TEN=Active ∗
TEN=Active ∗
TPI=Active ∗
XMIT=Enable
TPI=Active ∗
XMIT=Enable
Collision
TPO=TXD
RXD=TPI
COL=ACTIVE
A
A
TEN=Idle +
XMIT=Disable
TPI=Idle
TEN=Active ∗
TPI=Idle
TEN=Idle
2.9
Loopback Functions
2.9.1
Internal Loopback
The LXT905 provides a standard loopback mode, as specified in the IEEE specification for the
twisted-pair port. It also provides a forced internal loopback mode. Loopback mode operates in
conjunction with the transmit function. The LXT905 internally loops back data that the MAC
transmits, from the TXD pin, through the Manchester encoder/decoder, to the RXD pin, and
returning to the MAC.
A data collision disables standard loopback mode, clearing the RXD circuit for the TPI data. Link
fail, jabber, and full-duplex states also disable standard loopback. Loopback is always enabled
during forced internal loopback mode.
2.9.2
External Loopback/Full Duplex
The LXT905 also provides an external loopback test mode for system-level testing. When both
LEDC/FDE and LBK are Low, the LXT905 enables external loopback and full-duplex mode, and
disables internal loopback circuits, SQE, and collision detection. Refer to Table 3 for a summary of
loopback and duplex modes.
15
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
Table 3. Loopback Modes
Pin Settings
Mode Description
LBK
LEDC/FDE
Disable internal loopback.
Low
Low
Enable external loopback test mode and full-duplex mode.
Standard loopback mode (default).
Internally loops back data that the MAC transmitted, and returns the data to the
MAC, except during collision.
Low
High
A data collision disables standard loopback, clearing RXD for data on the twisted-
pair port.
High
High
Low
Not Used.
Forced internal loopback.
High
Loops-back transmit data on the receive data bus, and ignores the twisted-pair
port.
2.10
Link Integrity Test Function
Figure 7 is a state diagram of the LXT905 link integrity test function. The link integrity test
determines the status of the receive side twisted-pair cable. Link integrity testing is enabled when
LI is tied High. When enabled, the receiver recognizes link integrity pulses that transmit in the
absence of receive traffic. If the LXT905 does not detect any serial data stream or link integrity
pulses within 50~150 ms, the chip enters a link fail state and disables the transmit and normal
loopback functions. The LXT905 ignores any link integrity pulse with an interval less than 2~7 ms.
The LXT905 remains in the link fail state until it detects either a serial data packet, or two or more
link integrity pulses.
16
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
Figure 7. Link Integrity Test Function
Power On
Idle Test
Start_Link_Loss_Timer
Start_Link_Test_Min_Timer
TPI=Active +
(Link_Test_Rcvd=True ∗
Link_Test_Min_Timer_Done)
Link_Loss_Timer_Done ∗
TPI=Idle ∗
Link_Test_Rcvd=False
Link Test Fail Reset
Link Test Fail Wait
Link_Count=0
XMIT=Disable
RCVR=Disable
LPBK=Disable
XMIT=Disable
RCVR=Disable
LPBK=Disable
Link_Count=Link_Count + 1
Link_Test_Rcvd=False
∗ TPI=Idle
TPI=Active
TPI=Active
Link_Test_Rcvd=Idle
∗ TPI=Idle
Link Test Fail
Start_Link_Test_Min_Timer
Start_Link_Test_Max_Timer
XMIT=Disable
RCVR=Disable
LPBK=Disable
TPI=Active +
Link_Count=LC_Max
Link_Test_Min_Timer_Done
∗ Link_Test_Rcvd=True
Link Test Fail Extended
XMIT=Disable
RCVR=Disable
LPBK=Disable
(TPI=Idle ∗ Link_Test_Max_Timer_Done) +
(Link_Test_Min_Timer_Not_Done ∗
Link_Test_Rcvd=True)
TPI=Idle ∗
DO=Idle
17
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
3.0
Application Information
3.1
Introduction
Figure 8 “Intel® Controller Application (Mode 2)” on page 20 through Figure 10 “Intel® LXT905
PHY/Motorola* MC68EN360 Interface for Full-Duplex 10BASE-T (Mode 1)” on page 22 show
typical LXT905 applications. These diagrams group similar pins; they do not portray the actual
chip pinout. The controller interface pins [Transmit Data (TXD), Transmit Clock (TCLK) Transmit
Enable (TEN), Receive Data (RXD), Receive Clock (RCLK), Collision Signal (COL), and Carrier
Detect (CD)] are at the upper left of the diagram.
Power and ground pins are at the bottom of each diagram. VCC1 and VCC2 use a single power
supply, with decoupling capacitors installed between the power and ground buses. Either a 5 V or
3.3 V supply can power Vcc.
3.1.1
Termination Circuitry
The LXT905 pulls several I/O pins up or down internally, to keep the signals from floating. Intel
recommends hard-wiring these pins either High or Low. Externally pull-up pins (LEDT/PDN,
LEDC/FDE, LEDR, LEDL) and pull-down pins (LBK, TEN, TXD, DSQE, MDO, MDI)
separately, using a 10 k Ω, 1% resistor, or tie them directly to VCC or ground.
3.1.2
3.1.3
Twisted-Pair Interface
The Twisted-Pair interface (TPOP/N and TPIP/N) is at the upper right of the diagram. The I/O
pairs have impedance-matching resistors for 100 Ω UTP, but do not require any external filters.
RBIAS Pin
The RBIAS pin sets the levels for the LXT905 output drivers. The LXT905 requires a 7.5 k Ω, 1%
resistor directly connected between the RBIAS pin and ground. Locate this resistor as close to the
device as possible. Keep the traces as short as possible, isolated from all other high-speed signals.
3.1.4
Crystal Information
Table 4 lists some suitable crystals based on limited evaluation. Test and validate all crystals before
committing to a specific component.
Table 4. Suitable Crystals
Manufacturer
Part Number
MP-1
MP-2
MTRON
18
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
3.1.5
Magnetic Information
The LXT905 requires a 1:1 turns ratio for the receive transformer, and a 1:2 turns ratio for the
transmit transformer. The Intel® Magnetic Manufacturers Application Note (document number
248991) lists transformers suitable for the applications described in this datasheet.
Note: Test and validate all magnetics before committing to a specific component.
3.2
Typical 10BASE-T Application
Figure 8 is a typical LXT905 application. The DTE connects to a 10BASE-T network through the
twisted-pair RJ-45 connector. With MD0 tied high and MD1 grounded, this example sets the
LXT905 logic and framing to Mode 2 (compatible with Intel* 82596 controllers). Connect a 20
MHz system clock input at CLKI (leave CLKO open). The LI pin externally controls the link test
function.
Note: Refer to the Intel® MAC Interface Design Guide for Intel Controllers Application Note (document
number 249007) when designing with Intel controllers.
19
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
Figure 8. Intel® Controller Application (Mode 2)
1
0.1 µF
RJ-45
Not Connected
1
3
1:1 16
CLKO
CLKI
TXD
TEN
TCLK
RCLK
RXD
CD
TPIN
6
5
4
3
2
1
CLK
TXD
20 MHz System Clock
50 Ω 1%
50 Ω 1%
RTS
TXC
RXC
RXD
82596
Back-End/
Controller
Interface
14
TPIP
6 1:2 11
TPON
CRS
CDT
11.8 Ω 1%
COL
11.8 Ω 1%
8
9
TPOP
Programming
Options
MD0
MD1
DSQE
LI
100 pF
100 pF
Link Test Enable
Loopback Enable
LBK
Line Status
10K
LEDL
10K
+5V
LEDC/FDE
LEDT/PDN
10K
7.5 kΩ 1%
RBIAS
GND2
VCC1
VCC2
+5V
GND1
Power
Down
Full
Duplex
0.1 µF
1
Optional: Center tap capacitor may improve EMC depending on board layout and system design.
20
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
3.3
Dual Network Support - 10BASE-T and Token Ring
Figure 9 on page 21 shows the LXT905 with a Texas Instruments* 380C26 CommProcessor. The
380C26 is compatible with Mode 4 (MD0 and MD1 both high). When you use the LXT905 with
the 380C26, you can tie both the LXT905 and a TMS38054* Token Ring transceiver to a single
RJ-45, allowing dual network support from a single connector.
Figure 9. Intel® LXT905 PHY/Texas Instruments* 380C26 Interface for Dual 10BASE-T and
Token Ring Support (Mode 4)
From TI TMS38054
Token Ring
To TI TMS38054
Token Ring
20 MHz
20 pF
CLKI CLKO
Transceiver
Transceiver
20 pF
1
0.1 µF
2
RJ-45
TXD
TXE
TXC
RXC
RXD
CRS
COL
LBK
TXD
TEN
1
3
1:1 16
TPIN
6
5
4
3
2
1
50 Ω 1%
50 Ω 1%
TCLK
RCLK
RXD
CD
14
TPIP
COL
LBK
6 1:2 11
TPON
11.8 Ω 1%
MD0
MD1
LI
11.8 Ω 1%
8
9
TPOP
+5V
Line Status
100 pF
300
300
300
Red
300
Red
100 pF
LEDR
Green Red
LEDC/FDE
LEDT/PDN
LEDL
7.5 kΩ 1%
+5V
VCC1
VCC2
RBIAS
GND1 GND2 GND3
0.1 µF
Optional: Center tap capacitor may improve EMC depending on board layout and system design.
Additional magnetics and switching logic (not shown) are required to implement the dual network solution.
1
2
21
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
3.4
Simple 10BASE-T Connection
Figure 10 shows a simple 10BASE-T application, using an LXT905 transceiver and a Motorola*
MC68EN360. The MC68EN360 is compatible with Mode 1 (MD0 and MD1 both Low).
Figure 10. Intel® LXT905 PHY/Motorola* MC68EN360 Interface for Full-Duplex 10BASE-T
(Mode 1)
20 MHz
System
Clock
CLKO
TPIN
Not Connected
MC68EN360
CLKI
RJ-45
CLK1-4
CLK1-4
TXD
RCLK
TCLK
TXD
RXD
TEN
CD
1
1:1 16
6
5
4
3
2
1
100 Ω
RXD
RTS
14
3
CD
TPIP
CTS
COL
LBK
6 1:2 11
TPON
11.8 Ω 1%
DSQE
+5V
Parallel
I/O
11.8 Ω 1%
10 kΩ
8
9
1
TPOP
LEDC/FDE
100 pF
MD0
MD1
+5V
100 pF
300 Ω
Green
LEDL
+5V
VCC1
VCC2
LI
7.5 kΩ 1%
RBIAS
GND1 GND2 GND3
0.1 µF
LEDC/FDE requires an open-collector driver.
1
22
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
4.0
Test Specifications
Note: The minimum and maximum values in Table 5 through Table 13 on page 26 and Figure 11 on
page 27 through Figure 26 on page 34 represent the performance specifications of the LXT905.
These specifications are guaranteed by test, except where noted by design. Minimum and
maximum values in Table 7 through Table 13 on page 26 apply over the recommended operating
conditions specified in Table 6.
For all Quality and Reliability issues (for example, parts packaging and thermal specifications),
please send your questions to Intel at the following e-mail address: qr.requests@intel.com.
Table 5. Absolute Maximum Values
Parameter
Symbol
Min
Max
Units
Supply voltage
VCC
TST
-0.3
-65
+6
V
Storage temperature
+150
ºC
Caution:
Exceeding these values can cause permanent damage. Functional operation under these
conditions is not implied. Exposure to maximum rating conditions for extended periods can
affect device reliability.
Table 6. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Recommended supply voltage1
VCC
TOP
TOP
3.135
0
5.0
–
5.25
+70
+85
V
Recommended operating temperature (Commercial)
Recommended operating temperature (Extended)
ºC
ºC
-40
–
1. Voltage is with respect to ground, unless otherwise specified.
Table 7. I/O Electrical Characteristics (Sheet 1 of 2)
Parameter
Input low voltage2
Sym
Min
Typ1
Max
Units
Test Conditions
VIL
VIH
VOL
VOL
–
2.0
–
–
–
–
–
0.8
–
V
V
Input high voltage2
0.4
10
V
IOL = 1.6 mA
Output low voltage
µ
A
–
%VCC
IOL < 10
Output low voltage
(Open drain LED driver)
VOLL
–
–
0.7
%VCC
IOLL = 10 mA
µ
µ
VOH
VOH
–
2.4
90
–
–
–
3
–
–
V
%VCC
ns
IOH = 40
IOH < 10
A
Output high voltage
A
Output rise
time
CMOS
TTL
15
CLOAD = 20 pF
–
–
2
15
ns
TCLK & RCLK
1. Typical values are at 25 °C, are for design aid only, are not guaranteed, and are not subject to production
testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed
at levels of 0V and 3V. This applies to all inputs except TPIP and TPIN.
23
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
Table 7. I/O Electrical Characteristics (Sheet 2 of 2)
Parameter
CMOS
TTL
Sym
Min
–
Typ1
Max
15
Units
ns
Test Conditions
Output fall
time
–
–
–
3
2
–
CLOAD= 20 pF
–
15
ns
TCLK & RCLK
CLKI rise time (externally driven)
–
10
ns
CLKI duty cycle (externally
driven)
–
–
50/50
40/60
%
ICC
ICC
–
–
40
70
80
mA
mA
Idle Mode
Normal Mode
Supply current
100
Transmitting on TP
Power Down
Mode
µ
A
ICC
–
0.01
1
1. Typical values are at 25 °C, are for design aid only, are not guaranteed, and are not subject to production
testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed
at levels of 0V and 3V. This applies to all inputs except TPIP and TPIN.
Table 8. TP Electrical Characteristics
Parameter
Symbol
Min
Typ1
Max
Units
Test Conditions
Transmit output impedance
Transmit timing jitter addition2
ZOUT
–
–
5
–
Ω
–
0 line length for internal
MAU
–
±6.4
±10
ns
After line model
specified in IEEE 802.3
for 10BASE-T internal
MAU
Transmit timing jitter that the
MAU and PLS sections add2, 3
–
–
±3.5
±5.5
ns
Receive input impedance
ZIN
–
24
–
kΩ
Between TPIP/TPIN
5 MHz square wave
input
Differential squelch threshold
VDS
300
420
585
mV
1. Typical values are at 25 °C, are for design aid only, are not guaranteed, and are not subject to production
testing.
2. Parameter is guaranteed by design; not subject to production testing.
3. IEEE 802.3 specifies maximum jitter additions at 0.5 ns from the encoder, and 3.5 ns from the MAU.
Table 9. Switching Characteristics
Parameter
Maximum transmit time
Symbol
Minimum
Typical1
Maximum
Units
–
–
–
–
–
–
20
250
50
2
–
–
150
750
150
7
ms
ms
ms
ms
ms
ms
Jabber Timing
Unjab time
Time link loss receive
Link min receive
Link max receive
Link transmit period
–
–
Link Integrity
Timing
50
8
–
150
24
10
1. Typical values are at 25 °C, are for design aid only, are not guaranteed, and are not subject to production
testing.
24
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
Table 10. RCLK/Start-of-Frame Timing
Parameter
Decoder acquisition time
Symbol
Min
Typ1
Max
Units
tDATA
tCD
–
–
1300
400
70
1500
ns
ns
ns
ns
ns
ns
ns
CD turn-on delay
550
–
Mode 1
tRDS
tRDS
tRDH
tRDH
tsws
60
30
10
30
–
Receive data setup from
RCLK
Modes 2, 3, and 4
Mode 1
45
–
20
–
Receive data hold from RCLK
Modes 2, 3, and 4
45
–
RCLK shut off delay from CD assert (Mode 3)
±100
–
1. Typical values are at 25 °C, are for design aid only, are not guaranteed, and are not subject to production
testing.
Table 11. RCLK/End-of-Frame Timing
Parameter
Type
Sym
Mode 1 Mode 2
Mode 3
Mode 4
Units
RCLK after CD off
Min
Max
Max
tRC
tRD
5
1
–
5
BT
ns
Rcv data through-put delay
CD turn-off delay 2
400
500
5
375
475
50
375
475
–
375
475
–
tCDOFF
tIFG
ns
Receive block out after TEN off 3 Typical1
BT
RCLK switching delay after CD
off
Typical1
tswe
–
–
120 (±80)
–
ns
1. Typical figures are at 25 °C, are for design aid only are not guaranteed, and are not subject to production
testing.
2. CD Turnoff delay, measured from the middle of the last bit: timing specification. The value of the last bit
does not affect this value.
3. Disables blocking of Carrier Detect during full-duplex operation.
Table 12. Transmit Timing
Parameter
Symbol
Minimum
Typical1
Maximum
Units
TEN setup from TCLK
TXD setup from TCLK
TEN hold after TCLK
TXD hold after TCLK
Transmit start-up delay
Transmit through-put delay
tEHCH
tDSCH
tCHEL
tCHDU
tSTUD
tTPD
22
22
5
–
–
–
–
ns
ns
ns
ns
ns
ns
–
–
5
–
–
–
350
338
450
350
–
1. Typical values are at 25 °C, are for design aid only, are not guaranteed, and are not subject to production
testing.
25
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
Table 13. Miscellaneous Timing
Parameter
Symbol
Minimum
Typical1
Maximum
Units
COL (SQE) Delay after TEN off 2
COL (SQE) Pulse Duration2
Power Down recovery time
tSQED
tSQEP
tPDR
0.65
500
–
–
–
1.6
1500
–
s
µ
ns
25
ms
1. Typical values are at 25 °C, are for design aid only, are not guaranteed, and are not subject to production
testing.
2. When SQE is enabled (DSQE is Low).
26
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
4.1
Timing Diagrams for Mode 1 (MD1 = Low, MD0 = Low)
Timing diagrams for Mode 1 include Figure 11 through Figure 14.
Figure 11. Mode 1 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
TPIP/TPIN
tCD
CD
RCLK
tRDS
tRDH
tDATA
RXD
1
0
1
0
1
0
1
0
1
1
1
0
1
Figure 12. Mode 1 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
CD
tCDOFF
tRD
tRC
RCLK
RXD
PTM1_2
Mode 1 RCLK EoF
1
0
1
0
1
0
1
0
0
27
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
Figure 13. Mode 1 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tDSCH
tCHDU
TXD
tSTUD
tTPD
TPO
Figure 14. Mode 1 COL Output Timing
TEN
tSQED
COL
tSQEP
28
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
4.2
Timing Diagrams for Mode 2 (MD1 = Low, MD0 = High)
Timing diagrams for Mode 2 include Figure 15 through Figure 18.
Figure 15. Mode 2 RCLK/Start-of-Frame
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
TPIP/TPIN
CD
tCD
RCLK
tRDS
tRDH
1
tDATA
RXD
1
0
1
0
0
1
0
1
1
1
0
1
NOTE:
1. RXD changes at the rising edge of RCLK. Mode 2 samples the controller at the falling edge.
Figure 16. Mode 2 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
CD
tCDOFF
tRD
RCLK
PTM2_2
Mode 2 RCLK EoF
RXD
1
0
1
0
1
0
1
0
0
NOTE:
1. RXD changes at the rising edge of RCLK. Mode 2 samples the controller at the falling edge.
29
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
Figure 17. Mode 2 Transmit Timing
TEN
tEHCH
TCLK
tCHEL
tDSCH
tCHDU
PTM2_3
Mode 2 Txmit
TXD
tSTUD
tTPD
TPO
Figure 18. Mode 2 COL Output Timing
tIFG
TEN
tSQED
COL
tSQEP
NOTE:
1. CD output is disabled for a maximum of 55 bit times after TEN turns off.
30
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
4.3
Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low)
Timing diagrams for Mode 3 include Figure 19 through Figure 22.
Figure 19. Mode 3 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
TPIP/TPIN
CD
tCD
tSWS
Recovered from Input Data Stream
RCLK
tRDS
1
Generated from TCLK
tDATA
tRDH
1
RXD
0
1
0
0
1
0
1
1
1
0
1
NOTE:
1. RXD changes at the rising edge of RCLK. Mode 3 samples the controller at the falling edge.
Figure 20. Mode 3 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
tCDOFF
CD
tRD
tSWE
RCLK
Recovered Clock
Generated from TCLK
RXD
1
0
1
0
1
0
1
0
0
NOTE:
1. RSD changes at the rising edge of RCLK. Mode 3 samples the controller at the falling edge.
31
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
Figure 21. Mode 3 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tCHDU
tDSCH
TXD
TPO
tSTUD
tTPD
Figure 22. Mode 3 COL Output Timing
TEN
tSQED
tSQEP
COL
32
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
4.4
Timing Diagrams for Mode 4 (MD1 = High, MD0 = High)
Timing diagrams for Mode 4 include Figure 23 through Figure 26.
Figure 23. Mode 4 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
TPIP/TPIN
tCD
CRS
RCLK
RXD
tRDS
tRDH
tDATA
1
0
1
0
1
0
1
0
1
1
1
0
1
NOTE:
1. RXD changes at the falling edge of RCLK. Mode 4 samples the controller at the rising edge.
Figure 24. Mode 4 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
tCDOFF
CD
tRD
RCLK
RXD
1
0
1
0
1
0
1
0
0
NOTE:
1. RXD changes at the falling edge of RCLK. Mode 4 samples the controller at the rising edge.
33
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
Figure 25. Mode 4 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tDSCH
tCHDU
TXD
TPO
tTPD
tSTUD
Figure 26. Mode 4 COL Output Timing
TEN
tSQED
COL
tSQEP
34
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
5.0
Mechanical Specifications
Figure 27. Intel® LXT905PC PHY Package Specifications
28-Pin PLCC
• Part Number LXT905PC (Commercial Temperature Range)
• Part Number LXT905PE (Extended Temperature Range)
Table 14. Plastic Leaded Chip Carrier
Inches
Min Max
Millimeters
Dim
Min
Max
A
A1
A2
B
0.165 0.180 4.191
0.090 0.120 2.286
0.062 0.083 1.575
4.572
3.048
2.108
–
0.050
–
1.270
C
0.026 0.032 0.660
0.813
D
0.485 0.495 12.319 12.573
35
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
Figure 28. Intel® LXT905LC PHY Package Specifications
32-Pin LQFP
• Part Number LXT905LC (Commercial Temperature Range)
• Part Number LXT905LE (Extended Temperature Range)
D
D1
e
E1
E
e
/
2
11/13o 8 PLACES
0o MIN.
0.08/0.20 R.
0 - 7o
- H -
A
A2
- C -
L
b
M
0.08 R. MIN.
A1
0.20 MIN.
1.00 REF.
All Dimensions in millimeters
NOTES:
Table 15. Quad Flat Package
1. All dimensions are in millimeters.
2. This package conforms to JEDEC publication 95
registration MO-136, variation BC.
All Dimensions in millimeters
Dim.
3. Datum plane -H- located at mold parting line and is
coincident with leads where leads exit plastic body at
bottom of parting line.
4. Measured at seating plane -C-.
5. Measured at datum plane -H-.
6. Dimensions D1 and E1 do not include mold protrusion.
Allowable mold protrusion is 0.254 mm.
7. Package top dimensions are smaller than bottom
dimensions. Top of package will not overhang bottom of
package.
8. Dimension b does not include dambar protrusion.
Allowable dambar protrusion is no more than 0.08 mm.
Min.
Typ.
Max.
Notes
A
A1
A2
D
---
---
1.60
0.15
1.4
0.05
1.35
0.10
1.40
9.00 BSC.
7.00 BSC.
9.00 BSC
7.00 BSC
0.60
5
D1
E
6, 7, 8
5
E1
L
6, 7, 8
0.45
0.15
0.30
0.75
---
M
b
---
0.37
0.45
9
e
0.80 BSC.
36
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
6.0
Ordering Information
Table 16. Product Information
Number
DJLXT905LC.C2
Revision
C2
Qualification
MM Number
Ship Media
Tray
S
S
831645
DJLXT905LC.C2 E001
C2
Tape & Reel
831804
831661
831817
831646
831805
831662
831818
NLXT905PC.C2
C2
C2
C2
C2
C2
C2
S
S
S
S
S
S
Tube
Tape & Reel
Tray
NLXT905PC.C2 E001
DJLXT905LE.C2
DJLXT905LE.C2 E001
NLXT905PE.C2
Tape & Reel
Tube
NLXT905PE.C2 E001
Tape & Reel
Figure 29. Ordering Information - Sample
DJ
LXT
905
L
C
C2
S
E001
Build Format
= Tray
E000
E001 = Tape and reel
Qualification
= Pre-production material
= Production material
Q
S
Product Revision
= 2 Alphanumeric characters
xn
Temperature Range
= Ambient (0 - 55° C)
= Commercial (0 - 70° C)
= Extended (-40 - +85° C)
A
C
E
Internal Package Designator
= LQFP
L
= PLCC
= DIP
= PQFP
= QFP with heat spreader
= TQFP
P
N
Q
H
T
= BGA
= TBGA
= HSBGA (BGA with heat slug)
B
E
K
xxxx
= 3-5 Digit Alphanumeric Product Code
IXA Product Prefix
= PHY layer device
= Switching engine
= Formatting device (MAC)
= Network processor
LXT
IXE
IXF
IXP
Intel Package Designator
DJ
FA
FL
FW
HB
HD
HG
S
= LQFP
= TQFP
= PBGA (<1.0 mm pitch)
= PBGA (1.27 mm pitch)
= QFP with heat spreader
= QFP with heat slug
= SOIC
= QFP
GC
N
= TBGA
= PLCC
37
Datasheet
Document Number: 249271
Revision Number: 003
Revision Date: February 6, 2004
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