8102404VA [INTERSIL]
1024 x 4 CMOS RAM; 1024 ×4 CMOS RAM
| 型号： | 8102404VA |
| 厂家： | 
Intersil |
| 描述： | 1024 x 4 CMOS RAM |
| 文件： | 总7页 (文件大小：44K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM-6514
1024 x 4 CMOS RAM
March 1997
Features
Description
• Low Power Standby. . . . . . . . . . . . . . . . . . . 125µW Max The HM-6514 is a 1024 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. The device utilizes
synchronous circuitry to achieve high performance and low
• Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max
power operation.
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible Input/Output
On-chip latches are provided for addresses allowing efficient
interfacing with microprocessor systems. The data output
can be forced to a high impedance state for use in expanded
memory arrays.
• Common Data Input/Output
• Three-State Output
Gated inputs allow lower operating current and also elimi-
nate the need for pull up or pull down resistors. The
HM-6514 is a fully static RAM and may be maintained in any
state for an indefinite period of time.
• Standard JEDEC Pinout
• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Pin Package for High Density
• On-Chip Address Register
Data retention supply voltage and supply current are guaran-
teed over temperature.
• Gated Inputs - No Pull Up or Pull Down Resistors
Required
Ordering Information
120ns
HM3-6514S-9
HM1-6514S-9
24502BVA
8102402VA
-
200ns
300ns
HM3-6514-9
HM1-6514-9
-
TEMPERATURE RANGE
PACKAGE
PDIP
PKG. NO.
E18.3
o
o
HM3-6514B-9
-40 C to +85 C
o
o
HM1-6514B-9
-40 C to +85 C
CERDIP
JAN#
F18.3
F18.3
F18.3
J18.B
J18.B
-
-
-
8102404VA
8102406VA
-
SMD#
CLCC
o
o
-
-
-40 C to +85 C
o
o
-
HM4-6514-B
-55 C to +125 C
Pinouts
HM-6514 (PDIP, CERDIP)
HM-6514 (CLCC)
TOP VIEW
TOP VIEW
PIN
A
DESCRIPTION
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
A6
A5
V
CC
2
1
18 17
A7
Address Input
Chip Enable
Write Enable
Data Input
16
A8
3
4
5
6
7
A4
A3
A0
A1
A2
A4
A8
E
15 A9
A3
A9
W
D
A0
DQ0
DQ1
DQ2
DQ3
W
14 DQ0
A1
13
12
DQ1
DQ2
A2
Q
Data Output
E
8
9
10 11
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2995.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19996-1
HM-6514
Functional Diagram
A
A
LSB A9
A8
6
LATCHED
ADDRESS
REGISTER
GATED
ROW
DECODER
A7
A6
A5
64 x 64
MATRIX
64
A4
6
L
L
G
16 16 16 16
LSB A2
A1
A
GATED
COLUMN
I/O SELECT
LATCHED
ADDRESS
REGISTER
4
A0
A3
A
4
G
4
1 OF 4
E
W
DQ
6-2
HM-6514
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V Thermal Resistance (Typical)
θ
o
θ
JC
JA
o
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
+0.3V
CC
CERDIP Package . . . . . . . . . . . . . . . . 75 C/W
PDIP Package . . . . . . . . . . . . . . . . . . . 75 C/W
15 C/W
N/A
o
o
o
CLCC Package . . . . . . . . . . . . . . . . . . 90 C/W
33 C/W
o
o
Maximum Storage Temperature Range . . . . . . . . .-65 C to +150 C
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300 C
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Ranges:
HM-6514S-9, HM-6514B-9, HM-6514-9 . . . . . . . . -40 C to +85 C
o
o
o
o
o
o
o
HM-6514B-8, HM-6514-8 . . . . . . . . . . . . . . . . . . -55 C to +125 C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
o
DC Electrical Specifications V = 5V ±10%; T = -40 C to +85 C (HM-6514S-9, HM-6514B-9, HM-6514-9)
CC
A
o
o
T = -55 C to +125 C (HM-6514B-8, HM-6514-8)
A
LIMITS
SYMBOL
PARAMETER
MIN
MAX
25
UNITS
µA
TEST CONDITIONS
IO = 0mA, E = V -0.3V, V = 5.5V
CC
ICCSB
Standby Supply Current
HM-6514-9
HM-6514-8
-
-
-
CC
50
µA
ICCOP
ICCDR
Operating Supply Current (Note 1)
7
mA
E = 1MHz, IO = 0mA, VI = GND,
= 5.5V
V
CC
Data Retention Supply
Current
HM-6514-9
HM-6514-8
-
15
25
µA
µA
V
IO = 0mA, V
= 2.0V, E = V
CC
CC
-
VCCDR
II
Data Retention Supply Voltage
Input Leakage Current
Input/Output Leakage Current
Input Low Voltage
2.0
-1.0
-1.0
-0.3
-
+1.0
+1.0
0.8
µA
µA
V
VI = V
or GND, V
= 5.5V
CC
CC
IIOZ
VIL
VIO = V
or GND, V
= 5.5V
CC
CC
V
V
= 4.5V
= 5.5V
CC
CC
VIH
Input High Voltage
V
V
-2.0
V
+0.3
V
CC
CC
VOL
VOH1
VOH2
Output Low Voltage
-
0.4
V
IO = 2.0mA, V
= 4.5V
= 4.5V
CC
Output High Voltage
2.4
-
-
V
IO = -1.0mA, V
CC
CC
Output High Voltage (Note 2)
-0.4
V
IO = -100µA, V
= 4.5V
CC
o
Capacitance T = +25 C
A
SYMBOL
PARAMETER
MAX
8
UNITS
TEST CONDITIONS
CI
Input Capacitance (Note 2)
pF
pF
f = 1MHz, All measurements are
referenced to device GND
CIO
Input/Output Capacitance (Note 2)
10
NOTES:
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
6-3
HM-6514
o
o
AC Electrical Specifications V = 5V ±10%; T = -40 C to +85 C (HM-6514S-9, HM-6514B-9, HM-6514-9)
CC
A
o
o
T = -55 C to +125 C (HM-6514B-8, HM-6514-8)
A
LIMITS
HM-6514S-9
HM-6514B-9
HM-6514-9
MIN MAX
300
TEST
CONDITIONS
SYMBOL
(1) TELQV
(2) TAVQV
(3) TELQX
PARAMETER
MIN
MAX
120
120
-
MIN
MAX
220
220
-
UNITS
ns
Chip Enable Access Time
Address Access Time
-
-
-
-
-
(Notes 1, 3)
(Notes 1, 3, 4)
(Notes 2, 3)
-
320
-
ns
Chip Enable Output Enable
Time
5
5
5
ns
(4) TEHQZ
(5) TELEH
(6) TEHEL
Chip Enable Output Disable
Time
-
50
-
-
80
-
-
100
ns
ns
ns
(Notes 2, 3)
(Notes 1, 3)
(Notes 1, 3)
Chip Enable Pulse Negative
Width
120
50
200
90
300
120
-
-
Chip Enable Pulse Positive
Width
-
-
(7) TAVEL
(8) TELAX
(9) TWLWH
(10) TWLEH
Address Setup Time
Address Hold Time
0
-
-
-
-
20
50
-
-
-
-
20
50
-
-
-
-
ns
ns
ns
ns
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
40
Write Enable Pulse Width
120
120
200
200
300
300
Chip Enable Write Pulse
Setup Time
(11) TELWH
Chip Enable Write Pulse Hold
Time
120
-
200
-
300
-
ns
(Notes 1, 3)
(12) TDVWH
(13) TWHDX
(14) TWLDV
(15) TWLEL
(16) TEHWH
(17) TELEL
Data Setup Time
50
0
-
-
-
-
-
-
120
0
-
-
-
-
-
-
200
0
-
-
-
-
-
-
ns
ns
ns
ns
ns
-
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
Data Hold Time
Write Data Delay Time
Early Output High-Z Time
Late Output High-Z Time
Read or Write Cycle Time
70
0
80
0
100
0
0
0
0
170
290
420
NOTES:
1. Input pulse levels: 0.8V to V
- 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
CC
1 TTL gate equivalent, C = 50pF (min) - for C greater than 50pF, access time is derated by 0.15ns per pF.
L
L
2. Tested at initial design and after major design changes.
3. V = 4.5V and 5.5V.
CC
4. TAVQV = TELQV + TAVEL.
6-4
HM-6514
Timing Waveforms
(2) TAVQV
(17) TELEL
(7)
(8)
TAVEL
TELAX
(7) TAVEL
A
E
VALID ADD
NEXT ADD
(2) TAVQY
(6)
TEHEL
(6)
TEHEL
(5) TELEH
(1) TELQV
(3) TELQX
(4) TEHQZ
VALID DATA OUT
HIGH Z
HIGH Z
DQ
W
TIME
REFERENCE
-1
0
1
2
3
4
5
FIGURE 1. READ CYCLE
TRUTH TABLE
INPUTS
TIME
DATA I/O
REFERENCE
E
W
X
A
X
V
X
X
X
X
V
DQ
FUNCTION
-1
0
1
2
3
4
5
H
Z
Memory Disabled
H
H
H
H
X
Z
Cycle Begins, Addresses are Latched
Output Enabled
L
L
X
V
Output Valid
V
Read Accomplished
H
Z
Prepare for Next Cycle (Same as -1)
H
Z
Cycle Ends, Next Cycle Begins (Same as 0)
The address information is latched in the on-chip registers enabled, but data is not valid until during time (T = 2). W
on the falling edge of E (T = 0). Minimum address set up and must remain high throughout the read cycle. After the output
hold time requirements must be met. After the required hold data has been read, E may return high (T = 3). This will dis-
time, the addresses may change state without affecting able the output buffer and all inputs, and ready the RAM for
device operation. During time (T = 1) the output becomes
the next memory cycle (T = 4).
6-5
HM-6514
Timing Waveforms (Continued)
TELAX
TAVEL
TEVAL
NEXT ADD
A
E
VALID ADD
TELEL
TEHEL
TELEH
TEHEL
TWLEH
TWLWH
TELWL
TWHEH
W
TWLDV
HIGH Z
HIGH Z
DQ
VALID DATA INPUT
TDVWH
TWHDZ
TELWH
TIME
REFERENCE
-1
0
1
2
3
4
5
FIGURE 2. WRITE CYCLE
TRUTH TABLE
INPUTS
TIME
REFERENCE
E
W
X
X
L
A
X
V
X
X
X
X
V
DQ
Z
FUNCTION
-1
0
1
2
3
4
5
H
Memory Disabled
Z
Cycle Begins, Addresses are Latched
Write Period Begins
L
L
Z
V
Z
Data In is Written
H
X
X
Write Completed
H
Z
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)
Z
The write cycle is initiated by the falling edge of E (T = 0), This E and W control timing will guarantee that the data out-
which latches the address information in the on-chip regis- puts will stay disabled throughout the cycle, thus, simplifying
ters. There are two basic types of write cycles, which differ in the data input timing. TWLEL and TEHWH must be met, but
the control of the common data-in/data-out bus.
TWLDV becomes meaningless and can be ignored. In this
cycle TDVWH and TWHDX become TDVEH and TEHDX. In
other words, reference data setup and hold times to the E
rising edge.
Case 1: E falls before W falls
The output buffers may become enabled (reading) if E falls
before W falls. W is used to disable (three-state) the outputs
so input data can be applied. TWLDV must be met to allow
the W signal time to disable the outputs before applying
input data. Also, at the end of the cycle the outputs may
become active if W rises before E. The RAM outputs and all
inputs will three-state after E rises (TEHQZ). In this type of
write cycle TWLEL and TEHWH may be ignored.
IF
OBSERVE
IGNORE
Case 1
Case 2
E falls before W
TWLDV
TWLEL
E falls after W and
E rises before W
TWLEL
TEHWH
TWLDV
TWHDX
If a series of consecutive write cycles are to be performed,
W may be held low until all desired locations have been writ-
ten (an extension of Case 2).
Case 2: E falls equal to or after W falls, and E rises before
or equal to W rising
6-6
HM-6514
Test Load Circuit
DUT
(NOTE 1) C
L
+
IOH
1.5V
IOL
-
EQUIVALENT CIRCUIT
NOTE:
1. Test head capacitance.
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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6-7
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