EL7531IY-T13 [INTERSIL]
Monolithic 1A Step-Down Regulator with Low Quiescent Current; 单片1A降压型稳压器具有低静态电流型号: | EL7531IY-T13 |
厂家: | Intersil |
描述: | Monolithic 1A Step-Down Regulator with Low Quiescent Current |
文件: | 总10页 (文件大小:492K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EL7531
®
Data Sheet
August 5, 2005
FN7428.6
Monolithic 1A Step-Down Regulator with
Low Quiescent Current
Features
2
2
• Less than 0.15 in (0.97 cm ) footprint for the complete 1A
converter
The EL7531 is a synchronous, integrated FET 1A step-down
regulator with internal compensation. It operates with an
input voltage range from 2.5V to 5.5V, which accommodates
supplies of 3.3V, 5V, or a Li-Ion battery source. The output
• Components on one side of PCB
• Max height 1.1mm MSOP10
can be externally set from 0.8V to V with a resistive
• Power-Good (PG) output
IN
divider.
• Internally-compensated voltage mode controller
• Up to 94% efficiency
The EL7531 features automatic PFM/PWM mode control, or
PWM mode only. The PWM frequency is typically 1.4MHz
and can be synchronized up to 12MHz. The typical no load
quiescent current is only 120µA. Additional features include
a Power-Good output, <1µA shut-down current, short-circuit
protection, and over-temperature protection.
• <1µA shut-down current
• 120µA quiescent current
• Overcurrent and over-temperature protection
• External synchronizable up to 12MHz
• Pb-Free plus anneal available (RoHS compliant)
The EL7531 is available in the 10-pin MSOP package,
2
making the entire converter occupy less than 0.15 in of
PCB area with components on one side only. The 10-pin
MSOP package is specified for operation over the full -40°C
to +85°C temperature range.
Applications
• PDA and pocket PC computers
• Bar code readers
Ordering Information
• Cellular phones
PART NUMBER
TAPE &
REEL
PKG.
(BRAND)
PACKAGE
DWG. #
• Portable test equipment
• Li-Ion battery powered devices
• Small form factor (SFP) modules
EL7531IY
(BEAAA)
10-Pin MSOP
-
MDP0043
MDP0043
MDP0043
MDP0043
MDP0043
MDP0043
EL7531IY-T7
(BEAAA)
10-Pin MSOP
10-Pin MSOP
7”
Pinout and Typical Application Diagram
EL7531IY-T13
(BEAAA)
13”
-
EL7531
TOP VIEW
EL7531IYZ
(BHAAA) (Note)
10-Pin MSOP
(Pb-free)
EL7531IYZ-T7
(BHAAA) (Note)
10-Pin MSOP
(Pb-free)
7”
R *
1
100kΩ
1
2
3
4
5
SGND
PGND
LX
FB 10
C
4
R *
2
124kΩ
EL7531IYZ-T13
(BHAAA) (Note)
10-Pin MSOP
(Pb-free)
13”
470pF
VO
PG
9
8
7
6
C
1
C
10µF
2
L
1
10µF
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
PG
1.8µH
V
(1.8V@1A)
O
VIN
EN
EN
R
100Ω
3
V
(2.5V-6V)
S
VDD
SYNC
SYNC
C
3
R
6
0.1µF
100kΩ
R
R
100kΩ
100kΩ
4
5
* V = 0.8V * (1 + R / R )
O
2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL7531
Absolute Maximum Ratings (T = 25°C)
A
V
, V , PG to SGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2A
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
IN DD
LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (V + +0.3V)
IN
SYNC, EN, V , FB to SGND. . . . . . . . . . . . . -0.3V to (V + +0.3V)
IN
O
PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications
V
= V = V
IN
= 3.3V, C1 = C2 = 10µF, L = 1.8µH, V = 1.8V (as shown in Typical Application Diagram),
EN O
DD
unless otherwise specified.
DESCRIPTION
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
DC CHARACTERISTICS
V
Feedback Input Voltage
vs Temperature
PWM mode
790
800
0.3
810
mV
%
FB
/V
∆V
V
Junction temperature = -40°C to +85°C
(see Figure 7)
OUT OUT
FB
∆V
∆V
/V
OUT OUT
Line Regulation
V
= 3.3V to 5V, I = 1A (see Figure 7)
0.1
0.4
%
%
nA
V
IN
I = 0A to 1A, V = 3.3V (see Figure 7)
O
O
/V
OUT OUT
Load Regulation
IN
I
Feedback Input Current
Input Voltage
100
5.5
2.2
2.4
FB
, V
V
2.5
2
IN DD
V
Minimum Voltage for Shutdown
Maximum Voltage for Startup
Input Supply Quiescent Current
Active - PFM Mode
V
V
falling
rising
V
IN,OFF
IN
IN
V
2.2
V
IN,ON
I
S
V
V
= 0V
120
6.5
400
0.1
70
145
7.5
500
1
µA
mA
µA
µA
mΩ
mΩ
A
SYNC
SYNC
Active - PWM Mode
Supply Current
= 3.3V
I
PWM, V = V
IN DD
= 5V
= 5V
DD
EN = 0, V = V
IN
DD
R
PMOS FET Resistance
NMOS FET Resistance
Current Limit
V
= 5V, wafer test only
= 5V, wafer test only
100
75
DS(ON)-PMOS
DD
DD
R
V
45
DS(ON)-NMOS
I
1.5
145
130
LMAX
T
Over-temperature Threshold
Over-temperature Hysteresis
EN, SYNC Current
T rising
T falling
°C
°C
µA
V
OT,OFF
T
OT,ON
, I
I
V
V
V
V
V
, V
EN RSI
= 0V and 3.3V
-1
2.4
9
1
EN SYNC
, V
V
V
EN, SYNC Rising Threshold
EN, SYNC Falling Threshold
= 3.3V
= 3.3V
rising
1.8
1.4
EN1 SYNC1
, V
DD
DD
0.8
95
V
EN2 SYNC2
V
Minimum V for PG, WRT Targeted
FB
%
PG
FB
V
Value
FB
falling
86
%
FB
V
PG Voltage Drop
I
= 3.3mA
35
1.4
650
70
mV
OLPG
SINK
AC CHARACTERISTICS
F
PWM Switching Frequency
Minimum SYNC Pulse Width
Soft-start Time
1.25
25
1.6
MHz
ns
PWM
t
Guaranteed by design
SYNC
t
µs
SS
FN7428.6
2
August 5, 2005
EL7531
Pin Descriptions
PIN NUMBER
PIN NAME
PIN FUNCTION
1
2
3
4
5
6
SGND
PGND
LX
Negative supply for the controller stage
Negative supply for the power stage
Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage
Positive supply for the power stage
VIN
VDD
SYNC
Power supply for the controller stage
SYNC input pin; when connected to HI, regulator runs at forced PWM mode; when connected to Low, auto
PFM/PWM mode; when connected to external sync signal, at external PWM frequency up to 12MHz
7
8
EN
PG
VO
FB
Enable
Power-Good open drain output
Output voltage sense
9
10
Voltage feedback input; connected to an external resistor divider between V and SGND for variable
O
output
Block Diagram
100Ω
V
V
DD
INDUCTOR SHORT
+
O
0.1µF
10pF
V
IN
C4
-
124K
CURRENT
SENSE
470pF
5M
FB
-
+
PWM
COMPENSATION
+
-
PWM
P-DRIVER
100K
COMPARATOR
1.8µH
LX
PFM
ON-TIME
CONTROL
SYNC
EN
RAMP
GENERATOR
CONTROL
LOGIC
1.8V
0 TO 1A
SYNC
EN
CLOCK
SOFT-
START
+
-
10µF
10µF
PWM
N-DRIVER
COMPARATOR
UNDER-
VOLTAGE
LOCKOUT
+
3.3V
–
PGND
PG
BANDGAP
REFERENCE
+
-
100K
TEMPERATURE
SENSE
SYNCHRONOUS
RECTIFIER
PG
SGND
POWER
GOOD
FN7428.6
3
August 5, 2005
EL7531
Performance Curves and Waveforms
All waveforms are taken at V =3.3V, V =1.8V, I =1A with component values shown on page 1 at room ambient temperature, unless otherwise
IN
O
O
noted.
100
95
90
85
80
75
70
65
60
55
50
45
40
100
90
80
70
60
50
40
30
20
10
0
V
=3.3V
O
V
=3.3V
O
V
=2.5V
O
V
=2.5V
O
V
=1.8V
O
V
=1.8V
O
V
=1.0V
V
=1.5V
O
O
V
=1.5V
O
V
=1.2V
O
V
=0.8V
O
V
=1.0V
O
V
=1.2V
O
V
=0.8V
O
V
=5V
IN
V
=5V
IN
0.001
0.010
0.100
1.000
0.001
0.010
0.100
1.000
I
(A)
O
I (A)
O
FIGURE 1. EFFICIENCY vs I (PFM/PWM MODE)
FIGURE 2. EFFICIENCY vs I (PWM MODE)
O
O
100
100
95
90
85
80
75
70
65
60
55
50
45
40
V
V
=2.5V
=1.8V
V
V
=2.5V
=1.8V
O
90
80
70
60
50
40
30
20
10
0
O
O
O
V
=1.5V
O
V
=1.2V
O
V
=1.5V
O
V
=1.2V
O
V
=1.0V
O
V
=1.0V
O
V
=0.8V
O
V
=0.8V
(A)
O
V
=3.3V
IN
V
=3.3V
IN
0.001
0.010
0.100
1.000
0.001
0.010
0.100
1.000
I
I
(A)
O
O
FIGURE 3. EFFICIENCY vs I (PFM/PWM MODE)
O
FIGURE 4. EFFICIENCY vs I (PWM MODE)
O
1.44
0.1%
0.0%
V
=3.3V I =1A
O
IN
V
=5V I =1A
O
IN
V
=5V I =0A
O
IN
1.42
1.4
-0.1%
V
=3.3V I =0A
O
IN
V
=3.3V
IN
1.38
1.36
1.34
1.32
-0.2%
-0.3%
-0.4%
-0.5%
V
=5V
IN
0
0.2
0.4
0.6
0.8
1
-50
0
50
100
150
T
(°C)
A
I
(A)
O
FIGURE 5. F vs JUNCTION TEMPERATURE (PWM MODE)
S
FIGURE 6. LOAD REGULATIONS (PWM MODE)
FN7428.6
August 5, 2005
4
EL7531
Performance Curves and Waveforms (Continued)
All waveforms are taken at V =3.3V, V =1.8V, I =1A with component values shown on page 1 at room ambient temperature, unless otherwise
IN
O
O
noted.
0.1%
0.0%
12
10
8
V
=5V I =0A
IN
O
V
=3.3V I =0A
IN
O
-0.1%
-0.2%
-0.3%
-0.4%
-0.5%
V
=3.3V I =1A
6
4
2
0
IN
O
V
=5V I =1A
O
-0.6%
-0.7%
IN
-50
0
50
100
150
3.5
4
4.5
5
2.5
3
T
(°C)
J
V
(V)
S
FIGURE 7. PWM MODE LOAD/LINE REGULATIONS vs
JUNCTION TEMPERATURE
FIGURE 8. NO LOAD QUIESCENT CURRENT (PWM MODE)
140
100
V
=3.3V
O
1.4MHz
130
V
=1.8V
O
120
110
100
80
5MHz
12MHz
60
40
20
0
V
=1.5V
O
V
=1.2V V =1.0V
O
O
90
V
=0.8V
O
80
70
60
50
2.0
0
200
400
600
800
1K
1.2K
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
6.0
V
I
(mA)
S
O
FIGURE 9. NO LOAD QUIESCENT CURRENT (PFM MODE)
FIGURE 10. EFFICIENCY vs I (PWM MODE)
O
1
0.5
0.3
12MHz
0.6
1.4MHz
12MHz
0.2
0.1
5MHz
1.4MHz
-0.1
0
5MHz
-0.2
-0.6
-0.3
-0.5
2.5
0
200
400
600
800
1K
1.2K
3
3.5
4
4.5
5
5.5
I
(mA)
V
(V)
O
IN
FIGURE 11. LOAD REGULATION (PWM MODE)
FIGURE 12. LINE REGULATION @ 500mA (PWM MODE)
FN7428.6
August 5, 2005
5
EL7531
Performance Curves and Waveforms (Continued)
All waveforms are taken at V =3.3V, V =1.8V, I =1A with component values shown on page 1 at room ambient temperature, unless otherwise
IN
O
O
noted.
V
IN
(2V/DIV)
EN
I
IN
(0.5A/DIV)
I
IN
(0.5A/DIV)
V
O
(2V/DIV)
V
PG
O
(2V/DIV)
PG
500µs/DIV
200µs/DIV
FIGURE 13. START-UP AT I = 1A
O
FIGURE 14. ENABLE AND SHUT-DOWN
LX
(2V/DIV)
LX
(2V/DIV)
I
L
I
(0.5A/DIV)
L
(0.5A/DIV)
∆V
O
∆V
(10mV/DIV)
O
(50mV/DIV)
0.5µs/DIV
2µs/DIV
FIGURE 15. PFM STEADY-STATE OPERATION WAVEFORM
(I = 100mA)
FIGURE 16. PWM STEADY-STATE OPERATION (I = 1A)
O
O
SYNC
(2V/DIV)
SYNC
(2V/DIV)
LX
LX
(2V/DIV)
(2V/DIV)
I
I
L
L
(0.5A/DIV)
(0.5A/DIV)
20ns/DIV
0.2µs/DIV
FIGURE 17. EXTERNAL SYNCHRONIZATION TO 2MHz
FIGURE 18. EXTERNAL SYNCHRONIZATION TO 12MHz
FN7428.6
6
August 5, 2005
EL7531
Performance Curves and Waveforms (Continued)
All waveforms are taken at V =3.3V, V =1.8V, I =1A with component values shown on page 1 at room ambient temperature, unless otherwise
IN
O
O
noted.
I
I
O
O
(0.5A/DIV)
(0.5A/DIV)
∆V
∆V
O
O
(100mV/DIV)
(100mV/DIV)
50µs/DIV
100µs/DIV
FIGURE 19. LOAD TRANSIENT RESPONSE (22mA to 1A)
FIGURE 20. PWM LOAD TRANSIENT RESPONSE (0A TO 1A)
I
=150mA
O
SYNC
(2V/DIV)
I
O
(0.5A/DIV)
∆V
O
(100mV/DIV)
LX
(2V/DIV)
2µs/DIV
50µs/DIV
FIGURE 21. PWM LOAD TRANSIENT RESPONSE (0.25A TO
0.75A)
FIGURE 22. PFM-PWM TRANSITION TIME
3
2
I
=50mA
O
SYNC
(2V/DIV)
1
0
-1
LX
PFM
PWM
600
(2V/DIV)
-2
-3
0
200
400
800
1000
1200
I
(mA)
2µs/DIV
OUT
FIGURE 23. PFM-PWM TRANSITION TIME
FIGURE 24. PFM-PWM LOAD REGULATION
FN7428.6
August 5, 2005
7
EL7531
Performance Curves and Waveforms (Continued)
All waveforms are taken at V =3.3V, V =1.8V, I =1A with component values shown on page 1 at room ambient temperature, unless otherwise
IN
O
O
noted.
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
870mW
486mW
0
25
50
75 85 100
125
0
25
50
75 85 100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
and the inductor current linearly decreases to zero current.
The N channel MOSFET is then turned off, and an anti-
Applications Information
Product Description
The EL7531 is a synchronous, integrated FET 1A step-down
regulator which operates from an input of 2.5V to 5.5V. The
output voltage is user-adjustable with a pair of external
resistors.
ringing MOSFET is turned on to clamp the V pin to V .
LX
O
The inductor current looks like triangular pulses. The
frequency of the pulses is mainly a function of output current.
The higher the load, the higher the frequency of the pulses
until the inductor current becomes continuous. At this point,
the controller automatically changes to PWM operation.
When the load is very light, the regulator automatically
operates in the PFM mode, thus achieving high efficiency at
light load (>70% for 1mA load). When the load increases to
typically 250mA, the regulator automatically switches over to
a voltage-mode PWM operating at nominal 1.4MHz
switching frequency. The efficiency is up to 94%.
PWM Operation
The regulator operates the same way in the forced PWM or
synchronized PWM mode. In this mode, the inductor current
is always continuous and does not stay at zero.
In this mode, the P channel MOSFET and N channel
MOSFET always operate complementary. When the
PMOSFET is on and the NMOSFET off, the inductor current
increases linearly. The input energy is transferred to the
output and also stored in the inductor. When the P channel
MOSFET is off and the N channel MOSFET on, the inductor
current decreases linearly, and energy is transferred from
the inductor to the output. Hence, the average current
through the inductor is the output current. Since the inductor
and the output capacitor act as a low pass filter, the duty
It can also operate in a fixed PWM mode or be synchronized
to an external clock up to 12MHz for improved EMI
performance.
PFM Operation
The heart of the EL7531 regulator is the automatic
PFM/PWM controller.
If the SYNC pin is connected to ground, the regulator
operates automatically in either the PFM or PWM mode,
depending on load. When the SYNC pin is connected to V
,
cycle ratio is approximately equal to V divided by V
.
IN
O
IN
the regulator operates in the fixed PWM mode. When the pin
is connected to an external clock ranging from 1.6MHz to
12MHz, the regulator is in the fixed PWM mode and
synchronized to the external clock frequency.
The output LC filter has a second order effect. To maintain
the stability of the converter, the overall controller must be
compensated. This is done with the fixed internally
compensated error amplifier and the PWM compensator.
Because the compensations are fixed, the values of input
and output capacitors are 10µF to 22µF ceramic and
inductor is 1.5µH to 2.2µH.
In the automatic PFM/PWM operation, when the load is light,
the regulator operates in the PFM mode to achieve high
efficiency. The top P channel MOSFET is turned on first. The
inductor current increases linearly to a preset value before it
is turned off. Then the bottom N channel MOSFET turns on,
FN7428.6
August 5, 2005
8
EL7531
Forced PWM Mode/SYNC Input
Component Selection
Pulling the SYNC pin HI (>2.5V) forces the converter into
PWM mode in the next switching cycle regardless of output
current. The duration of the transition varies depending on
the output current. Figures 22 and 23 (under two different
loading conditions) show the device goes from PFM to PWM
mode
Because of the fixed internal compensation, the component
choice is relatively narrow. For a regulator with fixed output
voltage, only two capacitors and one inductor are required.
We recommend 10µf to 22µF multi-layer ceramic capacitors
with X5R or X7R rating for both the input and output
capacitors, and 1.5 to 2.2µH for the inductor.
The RMS current present at the input capacitor is decided by
the following formula:
Start-Up and Shut-Down
When the EN pin is tied to V , and V reaches
IN
IN
approximately 2.4V, the regulator begins to switch. The
inductor current limit is gradually increased to ensure proper
soft-start operation.
V
× (V – V
)
O
IN
O
-----------------------------------------------
I
=
× I
INRMS
O
V
IN
When the EN pin is connected to a logic low, the EL7531 is
in the shut-down mode. All the control circuitry and both
This is about half of the output current I for all the V . This
O
O
input capacitor must be able to handle this current.
MOSFETs are off, and V
falls to zero. In this mode, the
OUT
The inductor peak-to-peak ripple current is given as:
total input current is less than 1µA.
(V – V ) × V
O
IN
O
When the EN reaches logic HI, the regulator repeats the
start-up procedure, including the soft-start function.
-------------------------------------------
=
∆I
IL
L × V × f
IN
S
Current Limit and Short-Circuit Protection
L is the inductance
the switching frequency (nominally 1.4MHz)
The current limit is set at about 2A for the PMOS. When a
short-circuit occurs in the load, the preset current limit
restricts the amount of current available to the output, which
causes the output voltage to drop below the preset voltage.
In the meantime, the excessive current heats up the
regulator until it reaches the thermal shut-down point.
f
S
The inductor must be able to handle I for the RMS load
O
current, and to assure that the inductor is reliable, it must
handle the 2A surge current that can occur during a current
limit condition.
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
Thermal Shut-Down
Once the junction reaches about 145°C, the regulator shuts
down. Both the P channel and the N channel MOSFETs turn
off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will soon cool down.
Once the junction temperature drops to about 130°C, the
regulator will restart again in the same manner as EN pin
connects to logic HI.
1. Separate the Power Ground ( ) and Signal Ground
(
); connect them only at one point right at the pins
2. Place the input capacitor as close to V and PGND pins
IN
as possible
3. Make the following PC traces as small as possible:
4. from LX pin to L
Thermal Performance
The EL7531 is available in a fused-lead MSOP10 package.
Compared with regular MSOP10 package, the fused- lead
5. from C to PGND
O
package provides lower thermal resistance. The θ is
6. If used, connect the trace from the FB pin to R and R
JA
1
2
100°C/W on a 4-layer board and 125°C/W on 2-layer board.
Maximizing the copper area around the pins will further
improve the thermal performance.
as close as possible
7. Maximize the copper area around the PGND pin
8. Place several via holes under the chip to additional
ground plane to improve heat dissipation
Output Voltage Selection
Users can set the output voltage of the variable version with
a resister divider, which can be chosen based on the
following formula:
The demo board is a good example of layout based on this
outline. Please refer to the EL7531 Application Brief.
R
R
2
------
V
= 0.8 × 1 +
O
1
FN7428.6
9
August 5, 2005
EL7531
MSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
<http://www.intersil.com/design/packages/index.asp>
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7428.6
10
August 5, 2005
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