HA-5195_04 [INTERSIL]
150MHz, Fast Settling Operational Amplifier; 150MHz的，快速建立运算放大器
| 型号： | HA-5195_04 |
| 厂家： | 
Intersil |
| 描述： | 150MHz, Fast Settling Operational Amplifier |
| 文件： | 总9页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA-5195
®
November 19, 2004
FN2914.6
150MHz, Fast Settling Operational
Amplifier
Features
• Fast Settling Time (0.1%). . . . . . . . . . . . . . . . . . . . . 70ns
The HA-5195 is a operational amplifier featuring a
combination of speed, precision, and bandwidth. Employing
monolithic bipolar construction coupled with Dielectric
Isolation, this device is capable of delivering 200V/µs slew
rate with a settling time of 70ns (0.1%, 5V output step). This
truly differential amplifier is designed to operate at gains ≥ 5
without the need for external compensation. Other
outstanding features are 150MHz gain bandwidth product
and 6.5MHz full power bandwidth. In addition to these
dynamic characteristics, this amplifier also has excellent
input characteristics such as 3mV offset voltage and
6.0nV/√Hz input voltage noise at 1kHz.
• Very High Slew Rate . . . . . . . . . . . . . . . . . . . . . . 200V/µs
• Wide Gain-Bandwidth (A ≥ 5). . . . . . . . . . . . . . . 150MHz
V
• Full Power Bandwidth. . . . . . . . . . . . . . . . . . . . . . 6.5MHz
• Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 3mV
• Input Noise Voltage . . . . . . . . . . . . . . . . . . . . . . 6nV/√Hz
• Bipolar D.I. Construction
Applications
• Fast, Precise D/A Converters
• High Speed Sample-Hold Circuits
• Pulse and Video Amplifiers
• Wideband Amplifiers
With 200V/µs slew rate and 70ns settling time, the HA-5195
is an ideal output amplifier for accurate, high speed D/A
converters or the main components in high speed
sample/hold circuits. The 5195 is also ideally suited for a
variety of pulse and wideband video amplifiers. Please refer
to Application Notes AN525 and AN526 for some of these
application designs.
Pinout
HA-5195 (CERDIP)
TOP VIEW
o
At temperatures above 75 C a heat sink is required for the
HA-5195 (see Note 2 and Application Note AN556).
1
2
3
4
5
6
14
13
12
11
10
9
NC
NC
NC
V+
NC
NC
NC
-IN
+IN
V-
Part Number Information
TEMP.
PKG.
DWG. #
o
PART NUMBER RANGE ( C)
PACKAGE
-
+
HA1-5195-5 0 to 75
14 Ld CERDIP
F14.3
OUT
NC
NC
8
7
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Harris Corporation 1998. Copyright Intersil Americas Inc. 2002, 2004. All Rights Reserved
1
HA-5195
o
Absolute Maximum Ratings T = 25 C
Thermal Information
A
o
o
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA (Peak)
Thermal Resistance (Typical, Note 2)
CERDIP Package. . . . . . . . . . . . . . . . . . .
θ
( C/W)
75
θ
( C/W)
JA
JC
20
o
Maximum Junction Temperature (Hermetic Package, Note 1) . .175 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
o
o
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Heat sinking may be required, especially at T ≥ 75 C.
o
A
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications
V
= ±15V, Unless Otherwise Specified
SUPPLY
o
PARAMETER
INPUT CHARACTERISTICS
Offset Voltage
TEST CONDITIONS
TEMP ( C)
MIN
TYP
MAX
UNITS
25
Full
Full
25
-
-
3
-
6
10
-
mV
mV
o
Average Offset Voltage Drift
Bias Current
-
20
5
-
µV/ C
-
15
20
4
6
-
µA
µA
Full
25
-
Offset Current
-
1
-
µA
Full
25
-
µA
Input Resistance
-
10
1
-
kΩ
Input Capacitance
25
-
-
pF
Common Mode Range
Input Noise Current
Full
25
±5
-
-
V
f = 1kHz, R = 0Ω
5
6
-
pA/√Hz
nV/√Hz
G
Input Noise Voltage
f = 1kHz, R = 0Ω
25
-
-
G
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 3)
25
Full
Full
25
10
5
30
-
-
-
-
-
-
kV/V
kV/V
dB
Common Mode Rejection Ratio
Minimum Stable Gain
Gain-Bandwidth-Product
OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 3)
Output Current (Note 3)
Output Resistance
∆V
= ±5V
74
5
95
-
CM
V/V
V
= 90mV, A = 10
25
150
-
MHz
OUT
V
Full
25
±5
±25
-
±8
±30
30
-
-
-
-
V
mA
Ω
Open Loop
25
Full Power Bandwidth (Notes 3, 4)
TRANSIENT RESPONSE (Note 5)
Rise Time
25
5
6.5
MHz
25
25
25
25
25
25
25
-
13
8
18
-
ns
%
Overshoot
-
160
70
-
Slew Rate
200
-
-
V/µs
ns
Settling Time (Note 5)
5V Step to 0.1%
5V Step to 0.01%
2.5V Step to 0.1%
2.5V Step to 0.01%
-
100
50
80
-
ns
-
-
ns
-
-
ns
POWER SUPPLY CHARACTERISTICS
Supply Current
Full
-
19
28
mA
FN2914.6
2
November 19, 2004
HA-5195
Electrical Specifications
V
= ±15V, Unless Otherwise Specified (Continued)
SUPPLY
o
PARAMETER
Power Supply Rejection Ratio
NOTES:
TEST CONDITIONS
TEMP ( C)
MIN
TYP
MAX
UNITS
∆V = ±10V to ±20V
Full
70
90
-
dB
S
3. R = 200Ω, C < 10pF, V
OUT
= ±5V.
L
L
Slew Rate
4. Full power bandwidth guaranteed based on slew rate measurement using: FPBW = ----------------------------.
5. Refer to Test Circuits section of the data sheet.
2πV
PEAK
Test Circuits and Waveforms
IN
+
OUT
-
1.6kΩ
400Ω
NOTES:
6. A = 5.
200Ω
V
7. C < 10pF.
L
FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT
+5V
90%
V
OUT
V
OUT
10%
-5V
+1V
V
IN
V
IN
-1V
Vertical Scale: V = 2.0V/Div., V
IN OUT
= 4.0/Div.
Vertical Scale: V = 50mV/Div., V = 100mV/Div.
IN OUT
Horizontal Scale: 100ns/Div.
Horizontal Scale: 100ns/Div
LARGE SIGNAL RESPONSE
SMALL SIGNAL RESPONSE
0.001µF
V+
NOTES:
8. A = -5.
V
400Ω
1µF
IN
-
9. Load Capacitance should be less than 10pF.
OUT
+
0.001µF
10. It is recommended that resistors be carbon composition and that
feedback and summing network ratios be matched to 0.1%.
PROBE
MONITOR
11. Settle Point (Summing Node) capacitance should be less than
10pF. For optimum settling time results, it is recommended that
the test circuit be constructed directly onto the device pins. A
Tektronix 568 Sampling Oscilloscope with S-3A sampling heads
is recommended as a settle point monitor.
1kΩ
V-
1µF
2kΩ
5kΩ
SETTLE
POINT
FIGURE 2. SETTLING TIME TEST CIRCUIT
FN2914.6
3
November 19, 2004
HA-5195
Schematic Diagram
V+
R
R
R
R
R
1
6
2
3
4
Q
P4
Q
Q
Q
P24
P6
Q
P23
Q
N56
Q
P3
R
P5
28
C
C
2
Q
Q
1
N22
R
7
R
R
8
R
29
Q
P20
Q
N49
Q
Q
N2
N1
Q
N21
9
C
3
Q
N50
R
R
25
P19
24
Q
N53
Q
Q
P33
P32
P35
D
D
34
37
+IN
-IN
51
R
32
R
R
27
Q
Q
26
OUT
P36
D
D
Q
52
P44
Q
R
P7
33
D
D
38
Q
Q
Q
P8
N39
N42
Q
N40
N43
Q
P54
41
Q
R
10
Q
N18
R
11
R
Q
Q
Q
Q
12
P55
N9
N10
N45
Q
P16
Q
Q
N46
Q
N17
R
13
Q
P15
R
R
14
15
Q
Q
Q
N47
Q
N11
N12
N14
Q
N13
N48
R
R
R
R
R
31
16
17
18
30
V-
Application Information
Power Supply Decoupling
Output Short Circuit
Although not absolutely necessary, it is recommended that
all power supply lines be decoupled with 0.01µF ceramic
capacitors to ground. Decoupling capacitors should be
located as near to the amplifier terminals as possible.
HA-5195 does not have output short circuit protection. Short
circuits to ground can be tolerated for approximately 10
seconds. Short circuits to either supply will result in
immediate destruction of the device.
Stability Considerations
Heavy Capacitive Loads
HA-5195 is stable at gains > 5. Gains < 5 are covered below.
Feedback resistors should be of carbon composition located
as near to the input terminals as possible.
When driving heavy capacitive loads (>100pF) a small
resistor (100Ω) should be connected in series with the
output and inside the feedback loop.
Wiring Considerations
Video pulse circuits should be built on a ground plane.
Minimum point to point connections directly to the amplifier
terminals should be used. When ground planes cannot be
used, good single point grounding techniques should be
applied.
FN2914.6
4
November 19, 2004
HA-5195
Typical Applications (Also see Application Notes AN525 and AN526)
IN
IN
+
+
11pF
(NOTE)
C
1
OUT
200Ω
1kΩ (NOTE)
OUT
-
-
200Ω
R
F
R
1kΩ (NOTE)
750Ω (NOTE)
F
OUTPUT
OUTPUT
INPUT
INPUT
Vertical Scale: 2V/Div.
Horizontal Scale: 100ns/Div.
Vertical Scale: 2V/Div.
Horizontal Scale: 100ns/Div
NOTE: Values were determined experimentally for optimum speed and settling time. R and C should be optimized for each
F
1
particular application to ensure best overall frequency response.
FIGURE 3. SUGGESTED COMPENSATION FOR NONINVERTING UNITY GAIN AMPLIFIER
1kΩ
OUTPUT
1kΩ
IN
-
OUT
+
200Ω
INPUT
Vertical Scale: 2V/Div.
Horizontal Scale: 50ns/Div.
FIGURE 4. SUGGESTED COMPENSATION FOR INVERTING UNITY GAIN AMPLIFIER
V+
200Ω
+
IN
1µF
1µF
-
+
50Ω
HA-5195
HA-5033
120Ω
1.6kΩ
400Ω
75Ω
50Ω
-
200Ω
1µF
5kΩ
1kΩ
1µF
V-
FIGURE 5. VIDEO PULSE AMPLIFIER/75Ω COAXIAL DRIVER
FIGURE 6. VIDEO PULSE AMPLIFIER COAXIAL LINE DRIVER
FN2914.6
5
November 19, 2004
HA-5195
o
Typical Performance Curves
V
= ±15V, T = 25 C, Unless Otherwise Specified
S
A
100
80
60
40
20
0
2.0
1.6
1.2
0.8
0.4
0
5
0
4
3
2
1
0
BIAS CURRENT
GAIN
45
90
PHASE
135
180
225
OFFSET VOLTAGE
-20
1K
10K
100K
1M
10M
100M
-80
-40
0
40
80
120
160
o
TEMPERATURE ( C)
FREQUENCY (Hz)
FIGURE 7. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs
TEMPERATURE
FIGURE 8. OPEN LOOP FREQUENCY RESPONSE
1.2
1.1
18
16
14
12
10
8
SLEW RATE
1.0
0.9
0.8
0.7
BANDWIDTH
6
4
1K
10K
100K
1M
10M
100M
-80
-40
0
40
80
120
160
o
FREQUENCY (Hz)
TEMPERATURE ( C)
FIGURE 9. OUTPUT VOLTAGE SWING vs FREQUENCY
FIGURE 10. NORMALIZED AC PARAMETERS vs
TEMPERATURE
1.2
1000
1000
1.1
100
100
10
1
BANDWIDTH
1.0
INPUT NOISE CURRENT
SLEW RATE
10
0.9
INPUT NOISE VOLTAGE
1
1
0.8
10
10
100
1K
10K
100K
100
200
250
LOAD CAPACITANCE (pF)
FREQUENCY (Hz)
FIGURE 11. NORMALIZED AC PARAMETERS vs LOAD
CAPACITANCE
FIGURE 12. INPUT NOISE VOLTAGE AND NOISE CURRENT vs
FREQUENCY
FN2914.6
6
November 19, 2004
HA-5195
o
Typical Performance Curves
V
= ±15V, T = 25 C, Unless Otherwise Specified (Continued)
S
A
12
10
8
5
5mV
0.5mV
2.5
0
6
-2.5
5mV
-5
0.5mV
4
2
0
200
400
600
800
1K
1.2K
0
10
20
30
40
50
60
70
80
90 100 110
LOAD RESISTANCE (Ω)
SETTLING TIME (ns)
FIGURE 13. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
FIGURE 14. SETTLING TIME FOR VARIOUS OUTPUT STEP
VOLTAGES
120
100
80
60
40
20
0
120
100
POSITIVE
SUPPLY
80
60
NEGATIVE
SUPPLY
40
20
0
100
1K
10K
100K
1M
100
1K
10K
100K
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 15. COMMON MODE REJECTION RATIO vs
FREQUENCY
FIGURE 16. POWER SUPPLY REJECTION RATIO vs
FREQUENCY
24
V
V
= ±15V
= ±10V
SUPPLY
SUPPLY
20
16
12
8
4
0
-80
120
160
-40
0
40
80
o
TEMPERATURE ( C)
FIGURE 17. POWER SUPPLY CURRENT vs TEMPERATURE
FN2914.6
7
November 19, 2004
HA-5195
Die Characteristics
DIE DIMENSIONS:
SUBSTRATE POTENTIAL (Powered Up):
54 mils x 88 mils x 19 mils
V-
1360µm x 2240µm x 483µm
TRANSISTOR COUNT:
49
METALLIZATION:
Type: Al, 1% Cu
Thickness: 16kÅ ±2kÅ
PROCESS:
Bipolar Dielectric Isolation
PASSIVATION:
Type: Nitride (Si N ) over Silox (SiO , 5% Phos.)
3
4
2
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1.5kÅ
Metallization Mask Layout
HA-5195
-IN
V+
OUTPUT
+IN
V-
FN2914.6
8
November 19, 2004
HA-5195
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
19.94
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
aaa
bbb
ccc
M
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
14
14
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN2914.6
9
November 19, 2004
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