HC55183ECMZ [INTERSIL]

Extended Reach Ringing SLIC Family; 大位移振铃SLIC家庭


型号：	HC55183ECMZ
厂家：	Intersil
描述：	Extended Reach Ringing SLIC Family 大位移振铃SLIC家庭电池电信集成电路
文件：	总21页 (文件大小：388K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HC55180, HC55181, HC55183,

HC55184

Data Sheet

J uly 13, 2005

FN4519.7

Extended Reach Ringing SLIC Family

Features

The RSLIC18™ family of ringing subscriber line interface

circuits (RSLIC) supports analog Plain Old Telephone

Service (POTS) in short and medium loop length, wireless

and wireline applications. Ideally suited for remote

subscriber units, this family of products offers flexibility to

designers with high ringing voltage and low power

consumption system requirements.

• Battery Operation to 100V

• Low Standby Power Consumption of 50mW

• Peak Ringing Amplitude 95V, 5 REN

• Sinusoidal or Trapezoidal Ringing Capability

• Integrated CODEC Ringing Interface

• Integrated MTU DC Characteristics

• Low External Component Count

The RSLIC18 family operates to 100V which translates

directly to the amount of ringing voltage supplied to the end

subscriber. With the high operating voltage, subscriber loop

lengths can be extended to 500Ω (i.e., 5,000 feet) and

beyond.

• Pulse Metering and On Hook Transmission

• Tip Open Ground Start Operation

• Thermal Shutdown with Alarm Indicator

• 28 Lead Surface Mount Packaging

• Dielectric Isolated (DI) High Voltage Design

Other key features across the product family include: low

power consumption, ringing using sinusoidal or trapezoidal

waveforms, robust auto-detection mechanisms for when

subscribers go on or off hook, and minimal external discrete

application components. Integrated test access features are

also offered on selected products to support loopback

testing as well as line measurement tests.

• HC55180

- Silent Polarity Reversal

- 53dB Longitudinal Balance

- Loopback Test Capability

• HC55181

- Integrated Battery Switch

- Silent Polarity Reversal

- 53dB Longitudinal Balance

- Loopback and Test Access Capability

There are five product offerings in the RSLIC18 family:

HC55180, HC55181, HC55183 and HC55184. The

architecture for this family is based on a voltage feed

amplifier design using low fixed loop gains to achieve high

analog performance with low susceptibility to system

induced noise.

• HC55183

- Integrated Battery Switch

- 45dB Longitudinal Balance

Block Diagram

• HC55184

- Integrated Battery Switch

- Silent Polarity Reversal

- 45dB Longitudinal Balance

POL

CDC

VBL

VBH

CONTROL

BATTERY

SWITCH

RINGING

PORT

VRS

VRX

• Pb-Free Plus Anneal Available (RoHS Compliant)

ILIM

Applications

• Wireless Local Loop (WLL)

TIP

VTX

-IN

2-WIRE

PORT

TRANSMIT

SENSING

4-WIRE

PORT

• Digital Added Main Line (DAML)/Pairgain

• Integrated Services Digital Network (ISDN)

• Small Office Home Office (SOHO) PBX

• Cable/Computer Telephony

RING

VFB

SW+

SW-

TEST

ACCESS

DETECTOR

LOGIC

CONTROL

LOGIC

Related Literature

• AN9814, User’s Guide for Development Board

RTD RD E0 DET ALM BSEL SWC

• AN9824, Modeling of the AC Loop

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

RSLIC18™ is a trademark of Intersil Corporation. All other trademarks mentioned are the property of their respective owners.

HC55180, HC55181, HC55183, HC55184

Ordering Information (PLCC Package Only)

LOOP

TEMP.

RANGE

(°C)

BAT POL FULL BACK

PKG.

PART NUMBER

HC55180DIM

100V 85V

REV TEST ONLY LB = 53dB LB = 58dB

PACKAGE

DWG. #

•

-40 to 85 28 Ld PLCC

N28.45

HC55181DIM

•

HC55183ECMZ (Note)

HC55183ECMZ96 (Note)

HC55183ECM

75V

45dB

0 to 70 28 Ld PLCC (Pb-free) N28.45

0 to 70 28 Ld PLCC

N28.45

HC55184ECM

•

HC55184ECMZ (Note)

0 to 70 28 Ld PLCC (Pb-free) N28.45

HC55184ECMZR4749

(Note)

HC55184ECMZ96R4749

(Note)

75V

•

45dB

0 to 70 28 Ld PLCC (Pb-free) N28.45

HC5518XEVAL1

Evaluation board platform, including CODEC.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Device Operating Modes

OPERATING

MODE

F0 E0 = 1 E0 = 0

DESCRIPTION

HC55180 HC55181 HC55183 HC55184

Low Power Standby

SHD

GKD MTU compliant standby mode with

active loop detector.

•

Forward Active

Unused

SHD

n/a

GKD Forward battery loop feed.

n/a

This is a reserved internal test mode.

Reverse Active

Ringing

SHD

RTD

GKD Reverse battery loop feed.

•

RTD Balanced ringing mode supporting

both sinusoidal, trapezoidal and

•

ringing waveforms with DC offset.

Forward Loop Back

Tip Open

SHD

GKD Internal device test mode.

•

GKD Tip amplifier disabled and ring

amplifier enabled. Intended for PBX

type applications.

Power Denial

n/a

Device shutdown.

•

HC55180, HC55181, HC55183, HC55184

Pinout

HC55180

(PLCC)

HC55181

(PLCC)

TOP VIEW

28 26

RTD

CDC

RTD

CDC

SW+

SW-

SW+

SW-

23 VCC

SWC

-IN

VFB

VTX

VRX

HC55183

(PLCC)

HC55184

(PLCC)

TOP VIEW

28 26

RTD

CDC

RTD

CDC

23 VCC

-IN

VFB

VTX

VRX

HC55180, HC55181, HC55183, HC55184

Absolute Maximum Ratings T = 25°C

Thermal Information

Maximum Supply Voltages

Thermal Resistance (Typical, Note 1)

(°C/W)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V

PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

- V

(180, 181). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110V

(183, 184). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85V

BAT

Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C

(PLCC - Lead Tips Only)

Uncommitted Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . -110V

Maximum Tip/Ring Negative Voltage Pulse (Note 18). . . . . . . -115V

Maximum Tip/Ring Positive Voltage Pulse (Note 18) . . . . . . . . . .8V

ESD (Human Body Model). . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V

Die Characteristics

Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

BAT

Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI

Operating Conditions

Temperature Range

Industrial (I Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C

Commercial (C Suffix) . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C

Positive Power Supply (V ). . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

Negative Power Supply (V , V ) (180, 181) . . . . . -16V to -100V

BH BL

Negative Power Supply (V , V ) (183, 184) . . . . . . -24V to -75V

BH BL

Uncommitted Switch (loop back or relay driver) . . . . . +5V to -100V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications Unless Otherwise Specified, T = 0°C to 70°C for the HC55183, 184 only, all others -40°C to 85°C, V = -24V,

= -100V, -85V or -75V, V

= +5V, AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are

specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection

resistors = 0Ω. These parameters apply generically to each product offering.

PARAMETER

RINGING PARAMETERS (Note 2)

VRS Input Impedance (Note 3)

Differential Ringing Gain

TEST CONDITIONS

MIN

TYP

MAX UNITS

480

kΩ

V/V

VRS to 2-Wire, R

LOAD

= ∞ (Note 4)

4-Wire to 2-Wire Ringing Off Isolation

2-Wire to 4-Wire Transmit Isolation

Active mode, referenced to VRS input.

Ringing mode referenced to the differential ringing

amplitude.

AC TRANSMISSION PARAMETERS (Notes 5, 6)

Receive Input Impedance (Note 3)

Transmit Output Impedance (Note 3)

4-Wire Port Overload Level

160

kΩ

3.1

Ω

THD = 1%

3.5

2-Wire Port Overload Level

THD = 1%

2-Wire Return Loss

f = 300Hz

f = 1kHz

f = 2.3kHz

f = 3.4kHz

Longitudinal Current Capability (Per Wire) (Note 3)

Test for False Detect

Test for False Detect, Low Power Standby

-0.20

RMS

4-Wire to 2-Wire Insertion Loss

2-Wire to 4-Wire Insertion Loss

4-Wire to 4-Wire Insertion Loss

Idle Channel Noise 2-Wire

0.0

+0.30

-6.22 -6.02 -5.82

-6.32 -6.02 -5.82

C-Message

Psophometric

C-Message

Psophometric

-73.5

-71

dBrnC

dBmp

dBrnC

dBmp

Idle Channel Noise 4-Wire

-79.5

-77

HC55180, HC55181, HC55183, HC55184

Electrical Specifications Unless Otherwise Specified, T = 0°C to 70°C for the HC55183, 184 only, all others -40°C to 85°C, V = -24V,

= -100V, -85V or -75V, V

= +5V, AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are

specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection

resistors = 0Ω. These parameters apply generically to each product offering. (Continued)

PARAMETER

DC PARAMETERS (Note 6)

TEST CONDITIONS

MIN

TYP

MAX UNITS

Loop Current Limit Programming Range (Note 5)

Loop Current During Low Power Standby

LOOP DETECTORS AND SUPERVISORY FUNCTIONS

Switch Hook Programming Range

Switch Hook Programming Accuracy

Dial Pulse Distortion

Max Low Battery = -52V

Forward polarity only.

± 10

Assumes 1% external programming resistor

± 2

1.0

2.7

Ring Trip Comparator Threshold

Ring Trip Programming Current Accuracy

Ground Key Threshold

2.4

3.0

± 10

175

°C

Thermal Alarm Output

IC junction temperature

LOGIC INPUTS (F0, F1, F2, E0, SWC, BSEL)

Input Low Voltage

0.8

Input High Voltage

2.0

-20

Input Low Current

= 0.4V

= 2.4V

µA

Input High Current

LOGIC OUTPUTS (DET, ALM)

Output Low Voltage

= 5mA

0.4

Output High Voltage

= 100µA

2.4

POWER SUPPLY REJECTION RATIO

to 2-Wire

f = 300Hz

f = 1kHz

f = 3.4kHz

to 4-Wire

f = 300Hz

f = 1kHz

f = 3.4kHz

to 2-Wire

to 4-Wire

to 2-Wire

to 4-Wire

300Hz ≤ f ≤ 3.4kHz

300Hz ≤ f ≤ 1kHz

1kHz < f ≤ 3.4kHz

NOTES:

2. These parameters are specified at high battery operation. For the HC55180 the external supply is set to high battery voltage, for the HC55181,

HC55183 and HC55184, BSEL = 1.

3. These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial

design release and upon design changes which would affect these characteristics.

4. Differential Ringing Gain is measured with VRS = 0.795 V

for -75V devices.

for -100V devices, VRS = 0.663 V

for -85V devices and VRS = 0.575 V

RMS RMS

RMS

5. These parameters are specified at low battery operation. For the HC55180, the external supply is set to low battery voltage, for the HC55181,

HC55183 and HC55184, BSEL = 0.

6. Forward Active and Reverse Active performance is guaranteed for the HC55180, HC55181 and HC55184 devices only. The HC55183 is

specified for Forward Active operation only.

Electrical Specifications Unless Otherwise Specified, T = 0°C to 70°C for the HC55183, 184 only, all others -40°C to 85°C, V = -24V, V = +5V, AGND = BGND = 0V,

loop current limit = 25mA. All AC Parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz.

Protection resistors = 0Ω.

HC55180 (NOTE 7)

HC55181

TEST CONDITIONS MIN

HC55183, HC55184

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

TYP

MAX

TEST CONDITIONS

MIN

TYP

MAX UNITS

RINGING PARAMETERS (Note 2)

Ringing Voltage

Open Circuit

(Note 8)

THD ≤ 0.5%

= -85V

THD ≤ 0.5%

= -85V

THD ≤ 0.5%

= -75V

PEAK

THD ≤ 0.5%

V = -100V

THD ≤ 0.5%

= -100V

(Note 9)

THD ≤ 3.0%

= -85V

Ringing Voltage

Load = 1.3K

(Notes 8, 10)

THD ≤ 3.0%

= -85V

THD ≤ 3.0%

= -75V

THD ≤ 3.0%

(Note 9)

= -100V

Tip Centering Voltage

Ring Centering Voltage

= -85V, R = ∞

±2.5

±2.0

±2.5

±2.0

= -85V, R = ∞

±2.5

= -75V, R = ∞

±3

= -100V, R = ∞

±2.0 (Note 9)

±2.5 = -75V, R = ∞

±2.0 (Note 9)

= -85V, R = ∞

±3

= -100V, R = ∞

AC TRANSMISSION PARAMETERS (Notes 5, 6)

2-Wire Longitudinal Balance (Note 11)

Grade E

(Notes 12, 13)

Grade C, D

(Note 11)

4-Wire Longitudinal Balance (Note 11)

Grade C, D

Grade E

Grade C, D

(Note 11)

2-Wire to 4-Wire Level Linearity +3 to -40dBm, 1kHz

4-Wire to 2-Wire Level

±0.02

+3 to -40dBm, 1kHz

±0.025

+3 to -40dBm, 1kHz

±0.02

Linearity

-40 to -50dBm, 1kHz

Referenced to -10dBm

±0.05

-40 to -50dBm, 1kHz

-50 to -55dBm, 1kHz

±0.050

±0.100

-40 to -50dBm, 1kHz

-50 to -55dBm, 1kHz

±0.05

-50 to -55dBm, 1kHz

±0.10

DC PARAMETERS

Loop Current Accuracy

(Notes 5, 6)

I = 25mA

± 8.5

= 25mA

± 8.5

I = 25mA

± 10

Open Circuit Voltage

(|Tip - Ring|, Note 6)

= -16V

= -24V

> -60V

7.5

15.5

= -16V

6.0

7.5

15.5

9.0

= -16V

7.5

15.5

= -24V

= -60V, BSEL = 1

Electrical Specifications Unless Otherwise Specified, T = 0°C to 70°C for the HC55183, 184 only, all others -40°C to 85°C, V = -24V, V = +5V, AGND = BGND = 0V,

loop current limit = 25mA. All AC Parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz.

Protection resistors = 0Ω. (Continued)

HC55180 (NOTE 7)

HC55181

TEST CONDITIONS MIN

HC55183, HC55184

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

TYP

MAX

TEST CONDITIONS

MIN

TYP

MAX UNITS

Low Power Standby

Open Circuit Voltage

(Tip - Ring, Note 2)

= -48V

> -60V

= -48V

= -60V, BSEL = 1

Absolute Open Circuit

Voltage (Note 6)

in LPS and FA

in RA

> -60V

-53

-56

in LPS and FA

in RA

= -60V, BSEL = 1

-53

-56

in LPS and FA

in RA

= -60V, BSEL = 1

-53

-56

TEST ACCESS FUNCTIONS

Switch On Voltage

(Note 14)

= 45mA

0.30

0.60 (Note 14)

52 (Note 15)

Loopback Max Battery

SUPPLY CURRENTS (Supply currents not listed are considered negligible and do not contribute significantly to total power dissipation. All measurements made under open circuit load conditions.)

Low Power Standby

(Note 2)

2.0

3.7

6.0

2.0

3.7

6.0

3.7

0.375

4.0

1.0

5.5

1.3

1.4

8.5

0.4

1.3

6.0

I , V = -100V, -85V

0.375 0.600

, V = -100V, -85V

0.375 0.600

, V

= -75V

BH BH

Forward or Reverse

(Note 5)

2.5

4.0

1.0

5.5

5.0

2.5

8.0

2.5

4.0

1.0

5.5

1.3

1.7

8.5

0.4

1.3

8.5

5.0

2.5

8.0

2.0

2.5

2.0

6.0

2.5

8.0

2.5

3.0

I , V = -24V

Forward

(Note 2)

3.5

2.0

(Note 7)

I , V = -100V, -85V

3.2

8.5

4.5

, V = -100V, -85V

, V

= -75V

BH BH

Ringing

(Note 2)

(Note 7)

2.0

2.5

2.0

2.5

I , V = -100V, -85V

2.3

8.5

5.0

10.0

25.5

5.5

1.0

6.0

0.5

, V = -100V, -85V

, V

BH BH

Forward Loopback

(Note 5)

10.0 (Note 15)

25.5

I , V = -24V

Tip Open

(Note 5)

5.5

1.0

6.0

0.5

(Note 16)

I , V = -24V

Power Denial

(Note 5)

0.5

3.0

0.2

0.5

3.0

0.2

3.0

0.2

6.0

0.5

I , V = -24V

ON HOOK POWER DISSIPATION (Note 17)

Forward or Reverse

(Notes 5, 6)

= -24V

V = -24V

Electrical Specifications Unless Otherwise Specified, T = 0°C to 70°C for the HC55183, 184 only, all others -40°C to 85°C, V = -24V, V = +5V, AGND = BGND = 0V,

loop current limit = 25mA. All AC Parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz.

Protection resistors = 0Ω. (Continued)

HC55180 (NOTE 7)

HC55181

TEST CONDITIONS MIN

HC55183, HC55184

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

TYP

MAX

TEST CONDITIONS

= -75V

MIN

TYP

MAX UNITS

Low Power Standby

(Note 2)

= -85V

= -100V

= -85V

= -100V

= -85V

= -100V

= -85V

= -100V

(Note 9)

= -75V

275

Ringing

(Note 2)

190

220

190

220

300

170

325 (Note 9)

OFF HOOK POWER DISSIPATION (Notes 5, 17)

Forward or Reverse

NOTES:

= -24V

290

= -24V

290

310

V = -24V

280

310

7. The HC55180 does not provide battery switch operation. Therefore all battery voltage references will be made to V . V is the voltage applied to the common connection of the device V

and V

pins. See the HC55180 Basic Application Circuit.

8. Ringing Voltage is measured with VRS = 0.839 V

for -100V devices, VRS = 0.707 V

for -85V devices and VRS = 0.619 V for -75V devices. All measurements are at T = 25°C.

RMS

9. The HC55183 and HC55184 devices are specified with a single high battery voltage grade.

10. The device represents a low output impedance during ringing. Therefore the voltage across the ringing load is determined by the voltage divider formed by the protection resistance, loop

resistance and ringing load impedance.

11. The HC55180, HC55183 and HC55184 are specified with a single longitudinal balance grade.

12. Longitudinal Balance is tested per IEEE455-1985, with 368Ω per Tip and Ring Terminal.

13. These parameters are tested 100% at room temperature. These parameters are guaranteed not tested across temperature via statistical characterization.

14. The HC55180, HC55183 and HC55184 do not support uncommitted switch operation.

15. The HC55183 and HC55184 do not support the Forward Loopback operating mode.

16. The HC55183 and HC55184 do not support the Tip Open operating mode.

17. The power dissipation numbers are actual device measurements and will be less than worse case calculations based on data sheet supply current limits.

18. Characterized with 2 x 10µs, and 10 x 1000µs first level lightning surge waveforms (GR-1089-CORE).

HC55180, HC55181, HC55183, HC55184

4-WIRE TO 2-WIRE GAIN

Des ign Equations

The 4-wire to 2-wire gain is defined as the receive gain. It is

a function of the terminating impedance, synthesized

impedance and protection resistors. Equation 6 calculates

Loop Supervis ion Thres holds

SWITCH HOOK DETECT

the receive gain, G

The switch hook detect threshold is set by a single external

resistor, R . Equation 1 is used to calculate the value of R

SH SH













(EQ. 6)

-----------------------------------------

= –2

(EQ. 1)

= 600 ⁄ I

+ 2R + Z

P L

The term I

is the desired DC loop current threshold. The

When the device source impedance and protection resistors

equals the terminating impedance, the receive gain equals

unity.

loop current threshold programming range is from 5mA to

15mA.

GROUND KEY DETECT

2-WIRE TO 4-WIRE GAIN

The ground key detector senses a DC current imbalance

between the Tip and Ring terminals when the ring terminal is

connected to ground. The ground key detect threshold is not

externally programmable and is internally fixed to 12mA

regardless of the switch hook threshold.

The 2-wire to 4-wire gain (G ) is the gain from tip and ring to

the VTX output. The transmit gain is calculated in Equation 7.













(EQ. 7)

-----------------------------------------

= –

+ 2R + Z

P L

RING TRIP DETECT

When the protection resistors are set to zero, the transmit

gain is -6dB.

The ring trip detect threshold is set by a single external

resistor, R . I should be set between the peak ringing

current and the peak off hook current while still ringing.

RT RT

TRANSHYBRID GAIN

The transhybrid gain is defined as the 4-wire to 4-wire gain

(EQ. 2)

(G ).

= 1800 ⁄ I













(EQ. 8)

--------------------------------------

= –

The capacitor C , in parallel with R , will set the ring trip

RT RT

+ 2R + Z

P L

response time.

Loop Current Limit

The loop current limit of the device is programmed by the

When the protection resistors are set to zero, the transhybrid

gain is -6dB.

external resistor R . The value of R can be calculated

IL IL

COMPLEX IMPEDANCE SYNTHESIS

using Equation 3.

1760

Substituting the impedance programming resistor, R , with a

complex programming network provides complex

impedance synthesis.

(EQ. 3)

= ------------

LIM

The term I

LIM

is the desired loop current limit. The loop

2-WIRE

NETWORK

PROGRAMMING

NETWORK

current limit programming range is from 15mA to 45mA.

Impedance Matching

The impedance of the device is programmed with the

external component R . R is the gain setting resistor for

the feedback amplifier that provides impedance matching. If

complex impedance matching is required, then a complex

network can be substituted for R .

FIGURE 1. COMPLEX PROGRAMMING NETWORK

The reference designators in the programming network

RESISTIVE IMPEDANCE SYNTHESIS

match the evaluation board. The component R has a

The source impedance of the device, Z , can be calculated

in Equation 4.

different design equation than the R used for resistive

impedance synthesis. The design equations for each

component are provided below.

(EQ. 4)

= 400(Z

)

(EQ. 9)

= 400 × (R – 2(R ))

1 P

The required impedance is defined by the terminating

impedance and protection resistors as shown in Equation 5.

(EQ. 10)

(EQ. 11)

= 400 × R

(EQ. 5)

= Z – 2R

L P

= C ⁄ 400

HC55180, HC55181, HC55183, HC55184

voltage exceeds the MTU reference of -49V (typically), the

Low Power Standby

Ring terminal will be clamped by the internal reference. The

same Ring relationships apply when operating from the low

battery voltage. For high battery voltages (VBH) less than or

equal to the internal MTU reference threshold:

Overview

The low power standby mode (LPS, 000) should be used

during idle line conditions. The device is designed to operate

from the high battery during this mode. Most of the internal

circuitry is powered down, resulting in low power dissipation.

If the 2-wire (tip/ring) DC voltage requirements are not

critical during idle line conditions, the device may be

operated from the low battery. Operation from the low

battery will decrease the standby power dissipation.

(EQ. 12)

= V

+ 4

RING

Loop Current

During LPS, the device will provide current to a load. The

current path is through resistors and switches, and will be

function of the off hook loop resistance (R

). This

LOOP

TABLE 1. DEVICE INTERFACES DURING LPS

includes the off hook phone resistance and copper loop

resistance. The current available during LPS is determined

by Equation 13.

INTERFACE

Receive

OFF

NOTES

AC transmission, impedance

matching and ringing are

disabled during this mode.

(EQ. 13)

Ringing

= (– 1 – (–49)) ⁄ (600 + 600 + R

)

LOOP

Transmit

2-Wire

Internal current limiting of the standby switches will limit the

maximum current to 20mA.

Amplifiers disabled.

Loop Detect

Switch hook or ground key.

Another loop current related parameter is longitudinal

current capability. The longitudinal current capability is

2-Wire Interface

reduced to 10mA

per pin. The reduction in longitudinal

RMS

During LPS, the 2-wire interface is maintained with internal

switches and voltage references. The Tip and Ring

amplifiers are turned off to conserve power. The device will

provide MTU compliance, loop current and loop supervision.

Figure 2 represents the internal circuitry providing the 2-wire

interface during low power standby.

current capability is a result of turning off the Tip and Ring

amplifiers.

On Hook Power Dis s ipation

The on hook power dissipation of the device during LPS is

determined by the operating voltages and quiescent currents

and is calculated using Equation 14.

GND

(EQ. 14)

= V

× I

+ V × I

+ V

× I

CC CCQ

LPS

BHQ

BLQ

600Ω

The quiescent current terms are specified in the electrical

tables for each operating mode. Load power dissipation is

not a factor since this is an on hook mode. Some

applications may specify a standby current. The standby

current may be a charging current required for modern

telephone electronics.

TIP AMP

TIP

RING

RING AMP

Standby Current Power Dis s ipation

600Ω

Any standby line current, I

, introduces an additional

SLC

. Equation 15 illustrates the

MTU REF

power dissipation term P

SLC

power contribution is zero when the standby line current is

FIGURE 2. LPS 2-WIRE INTERFACE CIRCUIT DIAGRAM

zero.

MTU Compliance

(EQ. 15)

= I

× ( V

– 49 + 1 + I

x1200)

SLC

Maintenance Termination Unit or MTU compliance places

DC voltage requirements on the 2-wire terminals during idle

line conditions. The minimum idle voltage is 42.75V. The

high side of the MTU range is 56V. The voltage is expressed

as the difference between Tip and Ring.

If the battery voltage is less than -49V (the MTU clamp is

off), the standby line current power contribution reduces to

Equation 16.

(EQ. 16)

= I

× ( V

+ 1 + I

x1200)

SLC

The Tip voltage is held near ground through a 600Ω resistor

and switch. The Ring voltage is limited to a maximum of

-49V (by MTU REF) when operating from either the high or

low battery. A switch and 600Ω resistor connect the MTU

reference to the Ring terminal. When the high battery

SLC

Most applications do not specify charging current

requirements during standby. When specified, the typical

charging current may be as high as 5mA.

HC55180, HC55181, HC55183, HC55184

filter is set by the external capacitor C . The value of the

external capacitor should be 4.7µF.

Forward Active

Overview

Most applications will operate the device from low battery

while off hook. The DC feed characteristic of the device will

drive Tip and Ring towards half battery to regulate the DC

loop current. For light loads, Tip will be near -4V and Ring

The forward active mode (FA, 001) is the primary AC

transmission mode of the device. On hook transmission, DC

loop feed and voice transmission are supported during forward

active. Loop supervision is provided by either the switch hook

detector (E0 = 1) or the ground key detector (E0 = 0). The

device may be operated from either high or low battery for on-

hook transmission and low battery for loop feed.

will be near V

+ 4V. The following diagram shows the DC

VBL

feed characteristic.

m = (∆V /∆I ) = 10kΩ

TR(OC)

On-Hook Trans mis s ion

The primary purpose of on hook transmission will be to

support caller ID and other advanced signalling features.

The transmission over load level while on hook is 3.5V

PEAK

LIM

(mA)

LOOP

When operating from the high battery, the DC voltages at Tip

and Ring are MTU compliant. The typical Tip voltage is -4V

and the Ring voltage is a function of the battery voltage for

battery voltages less than -60V as shown in Equation 17.

(EQ. 17)

FIGURE 4. DC FEED CHARACTERISTIC

The point on the y-axis labeled V

is the open circuit

TR(OC)

Tip to Ring voltage and is defined by the feed battery

= V

+ 4

RING

voltage.

(EQ. 18)

= V

– 8

Loop supervision is provided by the switch hook detector at

the DET output. When DET goes low, the low battery should

be selected for DC loop feed and voice transmission.

TR(OC)

The curve of Figure 5 determines the actual loop current for

a given set of loop conditions. The loop conditions are

determined by the low battery voltage and the DC loop

impedance. The DC loop impedance is the sum of the

protection resistance, copper resistance (ohms/foot) and the

telephone off hook DC resistance.

Feed Architecture

The design implements a voltage feed current sense

architecture. The device controls the voltage across Tip and

Ring based on the sensing of load current. Resistors are

placed in series with Tip and Ring outputs to provide the

current sensing. The diagram below illustrates the concept.

LIM

OUT

KNEE

(Ω)

LOOP

FIGURE 5. I

LOOP

vs R

LOAD CHARACTERISTIC

LOOP

The slope of the feed characteristic and the battery voltage

define the maximum loop current on the shortest possible

FIGURE 3. VOLTAGE FEED CURRENT SENSE DIAGRAM

loop as the short circuit current I

By monitoring the current at the amplifier output, a negative

feedback mechanism sets the output voltage for a defined

– 2R I

P LIM

TR(OC)

(EQ. 19)

= I

+ -----------------------------------------------------

LIM

10K

load. The amplifier gains are set by resistor ratios (R , R ,

R ) providing all the performance benefits of matched

The term I

is the programmed current limit, 1760/R . The

LIM

resistors. The internal sense resistor, R , is much smaller

line segment I represents the constant current region of the

loop current limit function.

than the gain resistors and is typically 20Ω for this device.

The feedback mechanism, K , represents the amplifier

– R

10K

LOOP LIM

TR(OC)

(EQ. 20)

configuration providing the negative feedback.

= I

+ --------------------------------------------------------------

LIM

DC Loop Feed

The maximum loop impedance for a programmed loop

The feedback mechanism for monitoring the DC portion of

the loop current is the loop detector. A low pass filter is used

in the feedback to block voice band signals from interfering

with the loop current limit function. The pole of the low pass

current is defined as R

KNEE

TR(OC)

(EQ. 21)

= -----------------------

KNEE

LIM

HC55180, HC55181, HC55183, HC55184

When R

is exceeded, the device will transition from

constant current feed to constant voltage, resistive feed. The

The AC feed back loop produces an echo at the V output

KNEE

of the signal injected at V . The echo must be cancelled to

line segment I represents the resistive feed portion of the

load characteristic.

maintain voice quality. Most applications will use a summing

amplifier in the CODEC front end as shown below to cancel

the echo signal.

TR(OC)

(EQ. 22)

= -----------------------

LOOP

Voice Trans mis s ion

VRX

VTX

RX OUT

The feedback mechanism for monitoring the AC portion of

the loop current consists of two amplifiers, the sense

amplifier (SA) and the transmit amplifier (TA). The AC

feedback signal is used for impedance synthesis. A detailed

model of the AC feed back loop is provided below.

1:1

TX IN

+2.4V

CODEC

-IN

HC5518x

VRX

FIGURE 7. TRANSHYBRID BALANCE INTERFACE

TIP

1:1

The resistor ratio, R /R , provides the final adjustment for

VTX

the transmit gain, G . The transmit gain is calculated using

RING

Equation 25.













0.75R

-IN

-------

(EQ. 25)

= –G

VFB

Most applications set R = R , hence the device 2-wire to

4-wire equals the transmit gain. Typically R is greater than

R/2

20kΩ to prevent loading of the device transmit output.

The resistor ratio, R /R , is determined by the transhybrid

FIGURE 6. AC SIGNAL TRANSMISSION MODEL

gain of the device, G . R is previously defined by the

transmit gain requirement and R is calculated using

Equation 26.

The gain of the transmit amplifier, set by R , determines the

programmed impedance of the device. The capacitor C

blocks the DC component of the loop current. The ground

symbols in the model represent AC grounds, not actual DC

potentials.

= ----------

(EQ. 26)

Power Dis s ipation

The sense amp output voltage, V , as a function of Tip and

Ring voltage and load is calculated using Equation 23.

The power dissipated by the device during on hook

transmission is strictly a function of the quiescent currents

for each supply voltage during Forward Active operation.

(EQ. 23)

------

= –(V – V )

T R

= V

× I

+ V × I

+ V

× I

CC CCQ

(EQ. 27)

FAQ

BLQ

BHQ

The transmit amplifier provides the programmable gain

required for impedance synthesis. In addition, the output of

this amplifier interfaces to the CODEC transmit input. The

output voltage is calculated using Equation 24.

Off hook power dissipation is increased above the quiescent

power dissipation by the DC load. If the loop length is less

than or equal to R

, the device is providing constant

KNEE

current, I , and the power dissipation is calculated using









(EQ. 24)

Equation 28.

-------

= –V

VTX

(EQ. 28)

= P

+ (V xI ) – (R

LOOP

)

FA(IA)

FA(Q)

Once the impedance matching components have been

selected using the design equations, the above equations

provide additional insight as to the expected AC node

voltages for a specific Tip and Ring load.

If the loop length is greater than R

, the device is

KNEE

operating in the constant voltage, resistive feed region. The

power dissipated in this region is calculated using Equation 29.

Trans hybrid Balance

(EQ. 29)

= P

+ (V xI ) – (R xI

LOOP

)

FA(IB)

FA(Q)

The final step in completing the impedance synthesis design

is calculating the necessary gains for transhybrid balance.

HC55180, HC55181, HC55183, HC55184

Since the current relationships are different for constant

Power Dis s ipation

current versus constant voltage, the region of device

operation is critical to valid power dissipation calculations.

The power dissipation equations for forward active operation

also apply to the reverse active mode.

Revers e Active

Ringing

Overview

The reverse active mode (RA, 011) provides the same

functionality as the forward active mode. On hook

transmission, DC loop feed and voice transmission are

supported. Loop supervision is provided by either the switch

hook detector (E0 = 1) or the ground key detector (E0 = 0).

The device may be operated from either high or low battery.

The ringing mode (RNG, 100) provides linear amplification to

support a variety of ringing waveforms. A programmable ring

trip function provides loop supervision and auto disconnect

upon ring trip. The device is designed to operate from the

high battery during this mode.

Architecture

During reverse active the Tip and Ring DC voltage

characteristics exchange roles. That is, Ring is typically 4V

below ground and Tip is typically 4V more positive than

battery. Otherwise, all feed and voice transmission

characteristics are identical to forward active.

The device provides linear amplification to the signal applied

to the ringing input, V . The differential ringing gain of the

device is 80V/V. The circuit model for the ringing path is

shown in the following figure.

Silent Polarity Revers al

R/8

VRS

Changing from forward active to reverse active or vice versa

is referred to as polarity reversal. Many applications require

slew rate control of the polarity reversal event. Requirements

range from minimizing cross talk to protocol signalling.

TIP

800K

5:1

RING

The device uses an external low voltage capacitor, C

, to

POL

set the reversal time. Once programmed, the reversal time

will remain nearly constant over various load conditions. In

addition, the reversal timing capacitor is isolated from the AC

loop, therefore loop stability is not impacted.

FIGURE 9. LINEAR RINGING MODEL

The voltage gain from the VRS input to the Tip output is

40V/V. The resistor ratio provides a gain of 8 and the current

mirror provides a gain of 5. The voltage gain from the VRS

input to the Ring output is -40V/V. The equations for the Tip

and Ring outputs during ringing are provided below.

The internal circuitry used to set the polarity reversal time is

shown below.

POL

(EQ. 31)

V = ----------- + (40 × VRS)

75kΩ

POL

(EQ. 32)

= ----------- – (40 × VRS)

When the input signal at VRS is zero, the Tip and Ring

amplifier outputs are centered at half battery. The device

provides auto centering for easy implementation of

FIGURE 8. REVERSAL TIMING CONTROL

During forward active, the current from source I1 charges

sinusoidal ringing waveforms. Both AC and DC control of the

Tip and Ring outputs is available during ringing. This feature

allows for DC offsets as part of the ringing waveform.

the external timing capacitor C

and the switch is open.

POL

The internal resistor provides a clamping function for

voltages on the POL node. During reverse active, the switch

closes and I2 (roughly twice I1) pulls current from I1 and the

timing capacitor. The current at the POL node provides the

drive to a differential pair which controls the reversal time of

the Tip and Ring DC voltages.

Ringing Input

The ringing input, V , is a high impedance input. The high

impedance allows the use of low value capacitors for AC

coupling the ring signal. The V

input is enabled only

∆time

75000

(EQ. 30)

= ----------------

POL

during the ringing mode, therefore a free running oscillator

may be connected to VRS at all times.

Where ∆time is the required reversal time. Polarized

capacitors may be used for C . The low voltage at the

POL pin and minimal voltage excursion ±0.75V, are well

When operating from a battery of -100V, each amplifier, Tip

POL

and Ring, will swing a maximum of 95V

. Hence, the

P-P

maximum signal swing at VRS to achieve full scale ringing is

suited to polarized capacitors.

HC55180, HC55181, HC55183, HC55184

approximately 2.4V

. The low signal levels are compatible

For sinusoidal waveforms, the average current, I

, is

AVG

P-P

with the output voltage range of the CODEC. The digital

nature of the CODEC ideally suits it for the function of

programmable ringing generator. See Applications.

defined in Equation 36.

× 2

RMS

 

-- -----------------------------------------

 

π Z

(EQ. 36)

AVG

+ R

REN

LOOP

Logic Control

The silent interval power dissipation will be determined by

the quiescent power of the selected operating mode.

Ringing patterns consist of silent intervals. The ringing to

silent pattern is called the ringing cadence. During the silent

portion of ringing, the device can be programmed to any

other operating mode. The most likely candidates are low

power standby or forward active. Depending on system

requirements, the low or high battery may be selected.

Forward Loop Back

Overview

The forward loop back mode (FLB, 101) provides test

capability for the device. An internal signal path is enabled

allowing for both DC and AC verification. The internal 600Ω

terminating resistor has a tolerance of ±20%. The device is

intended to operate from only the low battery during this

mode.

Loop supervision is provided with the ring trip detector. The ring

trip detector senses the change in loop current when the phone

is taken off hook. The loop detector full wave rectifies the

ringing current, which is then filtered with external components

and C . The resistor R sets the trip threshold and the

RT RT

capacitor C sets the trip response time. Most applications will

require a trip response time less than 150ms.

Architecture

When the forward loop back mode is initiated internal

switches connect a 600Ω load across the outputs of the Tip

and Ring amplifiers.

Three very distinct actions occur when the devices detects a

ring trip. First, the DET output is latched low. The latching

mechanism eliminates the need for software filtering of the

detector output. The latch is cleared when the operating

mode is changed externally. Second, the VRS input is

disabled, removing the ring signal from the line. Third, the

device is internally forced to the forward active mode.

TIP

TIP AMP

600Ω

RING AMP

Power Dis s ipation

RING

The power dissipation during ringing is dictated by the load

driving requirements and the ringing waveform. The key to valid

power calculations is the correct definition of average and RMS

currents. The average current defines the high battery supply

current. The RMS current defines the load current.

FIGURE 10. FORWARD LOOP BACK INTERNAL TERMINATION

DC Verification

When the internal signal path is provided, DC current will

flow from Tip to Ring. The DC current will force DET low,

indicating the presence of loop current. In addition, the ALM

output will also go low. This does not indicate a thermal

alarm condition. Rather, proper logic operation is verified in

the event of a thermal shutdown. In addition to verifying

device functionality, toggling the logic outputs verifies the

interface to the system controller.

The cadence provides a time averaging reduction in the

peak power. The total power dissipation consists of ringing

power, P , and the silent interval power, P .

t + t

(EQ. 33)

------------- -------------

+ P ×

= P ×

RNG

t + t

The terms t and t represent the cadence. The ringing

AC Verification

interval is t and the silent interval is t . The typical cadence

The entire AC loop of the device is active during the forward

loop back mode. Therefore a 4-wire to 4-wire level test

capability is provided. Depending on the transhybrid balance

implementation, test coverage is provided by a one or two

step process.

ratio t :t is 1:2.

R S

The quiescent power of the device in the ringing mode is

defined in Equation 34.

= V

× I

+ V × I

+ V

× I

CC CCQ

(EQ. 34)

r(Q)

BHQ

BLQ

System architectures which cannot disable the transhybrid

function would require a two step process. The first step

would be to send a test tone to the device while on hook and

not in forward loop back mode. The return signal would be

The total power during the ringing interval is the sum of the

quiescent power and loading power:

RMS

(EQ. 35)

= P

+ V

× I

– -----------------------------------------

r(Q)

AVG

+ R

LOOP

the test level times the gain R /R of the transhybrid

REN

amplifier. Since the device would not be terminated,

cancellation would not occur. The second step would be to

program the device to FLB and resend the test tone. The

HC55180, HC55181, HC55183, HC55184

return signal would be much lower in amplitude than the first

Thermal Shutdown

step, indicating the device was active and the internal

termination attenuated the return signal.

In the event the safe die temperature is exceeded, the ALM

output will go low and DET will go high and the part will

automatically shut down. When the device cools, ALM will

go high and DET will reflect the loop status. If the thermal

fault persists, ALM will go low again and the part will shut

down. Programming power denial will permanently

System architectures which disable the transhybrid function

would achieve test coverage with a signal step. Once the

transhybrid function is disable, program the device for FLB

and send the test tone. The return signal level is determined

by the 4-wire to 4-wire gain of the device.

shutdown the device and stop the self cooling cycling.

Battery Switching

Tip Open

Overview

The integrated battery switch selects between the high

battery and low battery. The battery switch is controlled

with the logic input BSEL. When BSEL is a logic high, the

high battery is selected and when a logic low, the low

battery is selected. All operating modes of the device will

operate from high or low battery except forward loop back.

The tip open mode (110) is intended for compatibility for

PBX type interfaces. Used during idle line conditions, the

device does not provide transmission. Loop supervision is

provided by either the switch hook detector (E0 = 1) or the

ground key detector (E0 = 0). The ground key detector will

be used in most applications. The device may be operated

from either high or low battery.

Functionality

The logic control is independent of the operating mode

decode. Independent logic control provides the most

flexibility and will support all application configurations.

Functionality

During tip open operation, the Tip amplifier is disabled and

the Ring amplifier is enabled. The minimum Tip impedance

is 30kΩ. The only active path through the device will be the

Ring amplifier.

When changing device operating states, battery switching

should occur simultaneously with or prior to changing the

operating mode. In most cases, this will minimize overall

power dissipation and prevent glitches on the DET output.

In keeping with the MTU characteristics of the device, Ring

will not exceed -56.5V when operating from the high battery.

Though MTU does not apply to tip open, safety requirements

are satisfied.

The only external component required to support the battery

switch is a diode in series with the V

supply lead. In the

event that high battery is removed, the diode allows the

device to transition to low battery operation.

On Hook Power Dis s ipation

The on hook power dissipation of the device during tip open

is determined by the operating voltages and quiescent

currents and is calculated using Equation 37.

Low Battery Operation

All off hook operating conditions should use the low battery.

The prime benefit will be reduced power dissipation. The

typical low battery for the device is -24V. However this may

be increased to support longer loop lengths or high loop

current requirements. Standby conditions may also operate

from the low battery if MTU compliance is not required,

further reducing standby power dissipation.

= V

× I

+ V × I

+ V

× I

CC CCQ

(EQ. 37)

BHQ

BLQ

The quiescent current terms are specified in the electrical

tables for each operating mode. Load power dissipation is

not a factor since this is an on hook mode.

Power Denial

High Battery Operation

Other than ringing, the high battery should be used for

standby conditions which must provide MTU compliance.

During standby operation the power consumption is typically

50mW with -100V battery. If ringing requirements do not

require full 100V operation, then a lower battery will result in

lower standby power.

Overview

The power denial mode (111) will shutdown the entire device

except for the logic interface. Loop supervision is not

provided. This mode may be used as a sleep mode or to

shut down in the presence of a persistent thermal alarm.

Switching between high and low battery will have no effect

during power denial.

High Voltage Decoupling

The 100V rating of the device will require a capacitor of

higher voltage rating for decoupling. Suggested decoupling

values for all device pins are 0.1µF. Standard surface mount

ceramic capacitors are rated at 100V. For applications

driven at low cost and small size, the decoupling scheme

shown below could be implemented.

Functionality

During power denial, both the Tip and Ring amplifiers are

disabled, representing high impedances. The voltages at

both outputs are near ground.

HC55180, HC55181, HC55183, HC55184

TIP

0.22µ

RING

VBL

VBH

HC5518X

TEST

LOAD

FIGURE 11. ALTERNATE DECOUPLING SCHEME

SW+

As with all decoupling schemes, the capacitors should be as

close to the device pins as physically possible.

SWC

SW-

Uncommitted Switch

FIGURE 13. TEST LOAD SWITCHING

Overview

The diode in series with the test load blocks current from

flowing through the uncommitted switch when the polarity of

the Tip and Ring terminals are reversed. In addition to the

reverse active state, the polarity of Tip and Ring are

reversed for half of the ringing cycle. With independent logic

control and the blocking diode, the uncommitted switch may

be continuously connected to the Tip and Ring terminals.

The uncommitted switch is a three terminal device designed

for flexibility. The independent logic control input, SWC,

allows switch operation regardless of device operating

mode. The switch is activated by a logic low. The positive

and negative terminals of the device are labeled SW+ and

SW- respectively.

Relay Driver

The uncommitted switch may be used as a relay driver by

connecting SW+ to the relay coil and SW- to ground. The

switch is designed to have a maximum on voltage of 0.6V

with a load current of 45mA.

+5V

RELAY

SW+

SWC

SW-

FIGURE 12. EXTERNAL RELAY SWITCHING

Since the device provides the ringing waveform, the relay

functions which may be supported include subscriber

disconnect, test access or line interface bypass. An external

snubber diode is not required when using the uncommitted

switch as a relay driver.

Tes t Load

The switch may be used to connect test loads across Tip

and Ring. The test loads can provide external test

termination for the device. Proper connection of the

uncommitted switch to Tip and Ring is shown below.

HC55180, HC55181, HC55183, HC55184

Bas ic Application Circuits

PS1

PS3

VCC VBL

VBH

VRX

VRS

TIP

HC55180

RING

VTX

-IN

RTD

VFB

ILIM

CDC

POL

DET

ALM

AGND

BGND

FIGURE 14. HC55180 BASIC APPLICATION CIRCUIT

TABLE 2. BASIC APPLICATION CIRCUIT COMPONENT LIST

COMPONENT

VALUE

TOLERANCE

N/A

RATING

N/A

U1 - Ringing SLIC

HC5518x

20kΩ

0.1W

10V

49.9kΩ

71.5kΩ

210kΩ

0.47µF

4.7µF

, C , C , C , C

RS TX RT POL

, C

20%

PS1

PS2

10V

0.1µF

>100V

100V

, C

PS3

0.1µF

1N400X type with breakdown > 100V.

, R

Protection resistor values are application dependent and will be determined by protection

requirements. Standard applications will use ≥ 35Ω per side.

Design Parameters: Ring Trip Threshold = 90mA

, Switch Hook Threshold = 12mA, Loop Current Limit = 24.6mA, Synthesize Device

PEAK

Impedance = 210kΩ/400 = 525Ω, with 39Ω protection resistors, impedance across Tip and Ring terminals = 603Ω. Where applicable, these

component values apply to the Basic Application Circuits for the HC55180, HC55181, HC55183 and HC55184. Pins not shown in the Basic

Application Circuit are no connect (NC) pins.

HC55180, HC55181, HC55183, HC55184

PS1

PS2

PS3

VCC VBL

VBH

VCC VBL

VBH

VRX

VRS

VRX

VRS

TIP

HC55181

HC55183

RING

VTX

-IN

VTX

-IN

SW+

SW-

RTD

VFB

RTD

BSEL

SWC

BSEL

ILIM

CDC

ILIM

DET

ALM

BGND

CDC

POL

DET

ALM

BGND

AGND

FIGURE 15. HC55181 BASIC APPLICATION CIRCUIT

FIGURE 16. HC55182 BASIC APPLICATION CIRCUIT

PS1

PS2

PS3

VCC VBL

VBH

VRX

VRS

TIP

HC55184

RING

VTX

-IN

RTD

VFB

BSEL

ILIM

CDC

POL

DET

ALM

BGND

AGND

FIGURE 17. HC55184 BASIC APPLICATION CIRCUIT

HC55180, HC55181, HC55183, HC55184

applications the synthesized device impedance (i.e., 600Ω)

will not match the 200Ω teletax impedance. The gain set by

Additional Application Diagrams

Reducing Overhead Voltages

R cancels the impedance matching feedback with respect

The transmission overhead voltage of the device is

internally set to 4V per side. The overhead voltage may be

reduced by injecting a negative DC voltage on the receive

input using a voltage divider (Figure 18). Accordingly, the

2-wire port overload level will decrease the same amount

as the injected offset.

to the teletax injection point. Therefore the device appears

as a low impedance source for teletax. The resistor R is

calculated using the following equation.

200

(EQ. 39)

------------------------------------------------------------------

× R

200 + 2 × R + (R ⁄ 400)

The signal level across a 200Ω load will be twice the injected

teletax signal level. As the teletax level at VTX will equal the

160kΩ

injection level, set R = R for cancellation. The value of R

FROM

CODEC

is based on the voice band transhybrid balance

VRX

requirements. The connection of the teletax source to the

transhybrid amplifier should be AC coupled to allow proper

biasing of the transhybrid amplifier input

1:1

HC5518X

VBL

FIGURE 18. EXTERNAL OVERHEAD CONTROL

The divider shunt resistance is the parallel combination of

CFB

VFB

the internal 160kΩ resistor and the external R . The sum of

-IN

VTX

TX IN

+2.4V

CODEC

R and R should be greater than 500kΩ to minimize the

additional power dissipation of the divider. The DC gain

TELETAX

SOURCE

relationship from the divider voltage, V , to the Tip and Ring

outputs is shown below.

= V

– 8 – (2 × V )

BL D

FIGURE 20. TELETAX SIGNALLING

(EQ. 38)

T – R

Ringing With DC Offs ets

With a low battery voltage -24V and a divider voltage of

-0.5V, the Tip to Ring voltage is 17V. As a result, the

overhead voltage is reduced from 8V to 7V and the overload

The balanced ringing waveform consists of zero DC offset

between the Tip and Ring terminals. However, the linear

amplifier architecture provides control of the DC offset during

ringing. The DC gain is the same as the AC gain, 40V/V per

amplifier. Positive DC offsets applied directly to the ringing

input will shift both Tip and Ring away from half battery

towards ground and battery respectively. A voltage divider

on the ringing input may be used to generate the offset

level will decrease from 3.5V

PEAK

to 3.0V

PEAK

CODEC Ringing Generation

Maximum ringing amplitudes of the device are achieved with

signal levels approximately 2.4V . Therefore the low pass

P-P

receive output of the CODEC may serve as the low level ring

generator. The ringing input impedance of 480kΩ minimum

should not interfere with CODEC drive capability. A single

external capacitor is required to AC coupled the ringing

signal from the CODEC. The circuit diagram for CODEC

ringing is shown below.

(Figure 21). The reference voltage, V

, can be either the

REF

CODEC 2.4V reference voltage or the 5V supply.

FROM

RING GEN.

160kΩ

VRS

480K

VRX

RX OUT

HC5518X

1:1

REF

FIGURE 21. EXTERNAL OVERHEAD CONTROL

VRS

480K

CODEC

An offset during ringing of 30V, would require a DC shift of

15V at Tip and 15V at Ring. The DC offset would be created

HC5518X

by a +0.375V (V ) at the VRS input. The divider resistors

FIGURE 19. CODEC RINGING INTERFACE

should be selected to minimize the value of the AC coupling

capacitor C

and the loading of the ring generator and

Implementing Teletax Signalling

voltage reference. The ringing input impedance should also

be accounted for in divider resistor calculations.

A resistor, R , is required at the -IN input of the device for

injecting the teletax signal (Figure 19). For most

HC55180, HC55181, HC55183, HC55184

Pin Des criptions

PLCC

SYMBOL

DESCRIPTION

TIP

TIP power amplifier output.

BGND

Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.

Internally separate from AGND but it is recommended that it is connected to the same potential as AGND.

VBL

VBH

SW+

SW-

SWC

Low battery supply connection.

High battery supply connection for the most negative battery.

Uncommitted switch positive terminal. This pin is a no connect (NC) on the HC55180, HC55183 and HC55184.

Uncommitted switch negative terminal. This pin is a no connect (NC) on the HC55180, HC55183 and HC55184.

Switch control input. This TTL compatible input controls the uncommitted switch, with a logic “0” enabling the switch and

logic “1” disabling the switch. This pin is a no connect (NC) on the HC55180, HC55183 and HC55184.

Mode control input - MSB. F2-F0 for the TTL compatible parallel control interface for controlling the various modes of

operation of the device.

Mode control input.

Detector Output Selection Input. This TTL input controls the multiplexing of the SHD (E0 = 1) and GKD (E0 = 0)

comparator outputs to the DET output based upon the state at the F2-F0 pins (see the Device Operating Modes table

shown on page page 2).

DET

ALM

Detector Output - This TTL output provides on-hook/off-hook status of the loop based upon the selected operating mode.

The detected output will either be switch hook, ground key or ring trip (see the Device Operating Modes table shown on

page page 2).

Thermal Shutdown Alarm. This pin signals the internal die temperature has exceeded safe operating temperature

(approximately 175°C) and the device has been powered down automatically.

AGND

BSEL

Analog ground reference. This pin should be externally connected to BGND.

Selects between high and low battery, with a logic “1” selecting the high battery and logic “0” the low battery. This pin is

a no connect (NC) on the HC55180.

POL

VRS

VRX

VTX

VFB

-IN

This pin is a no connect (NC) for all the devices.

External capacitor on this pin sets the polarity reversal time. This pin is a no connect on the HC55183.

Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode.

Analog Receive Voltage - 4-wire analog audio input voltage. AC couples to CODEC.

Transmit output voltage - Output of impedance matching amplifier, AC couples to CODEC.

Feedback voltage for impedance matching. This voltage is scaled to accomplish impedance matching.

Impedance matching amplifier summing node.

VCC

CDC

RTD

ILIM

Positive voltage power supply, usually +5V.

DC Biasing Filter Capacitor - Connects between this pin and V

Ring trip filter network.

Loop Current Limit programming resistor.

Switch hook detection threshold programming resistor.

RING power amplifier output.

RING

HC55180, HC55181, HC55183, HC55184

Plas tic Leaded Chip Carrier Packages (PLCC)

0.042 (1.07)

0.048 (1.22)

N28.45 (JEDEC MS-018AB ISSUE A)

0.042 (1.07)

0.056 (1.42)

0.004 (0.10)

28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

PIN (1) IDENTIFIER

0.025 (0.64)

0.045 (1.14)

0.050 (1.27) TP

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

4.20

MAX

4.57

NOTES

0.165

0.090

0.485

0.450

0.191

0.485

0.450

0.191

0.180

0.120

0.495

0.456

0.219

0.495

0.456

0.219

2.29

3.04

D2/E2

12.32

11.43

4.86

12.57

11.58

5.56

E1 E

4, 5

12.32

11.43

4.86

12.57

11.58

5.56

VIEW “A”

4, 5

0.020 (0.51)

MIN

Rev. 2 11/97

SEATING

PLANE

0.020 (0.51) MAX

3 PLCS

-C-

0.026 (0.66)

0.032 (0.81)

0.013 (0.33)

0.021 (0.53)

0.025 (0.64)

MIN

0.045 (1.14)

MIN

VIEW “A” TYP.

NOTES:

1. Controlling dimension: INCH. Converted millimeter dimensions are

not necessarily exact.

2. Dimensions and tolerancing per ANSI Y14.5M-1982.

3. Dimensions D1 and E1 do not include mold protrusions. Allowable

mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1

and E1 include mold mismatch and are measured at the extreme

material condition at the body parting line.

-C-

4. To be measured at seating plane

contact point.

5. Centerline to be determined where center leads exit plastic body.

6. “N” is the number of terminal positions.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

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