HD-15530 [INTERSIL]
CMOS Manchester Encoder-Decoder; CMOS曼彻斯特编码器，解码器
| 型号： | HD-15530 |
| 厂家： | 
Intersil |
| 描述： | CMOS Manchester Encoder-Decoder |
| 文件： | 总12页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD-15530
CMOS Manchester Encoder-Decoder
March 1997
Features
Description
• Support of MlL-STD-1553
The Intersil HD-15530 is a high performance CMOS device
intended to service the requirements of MlL-STD-1553 and
similar Manchester II encoded, time division multiplexed
serial data protocols. This LSI chip is divided into two
sections, an Encoder and a Decoder. These sections
operate completely independent of each other, except for the
Master Reset functions.
• Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 MBit/s
• Sync Identification and Lock-In
• Clock Recovery
• Manchester II Encode, Decode
This circuit meets many of the requirements of MIL-STD-
1553. The Encoder produces the sync pulse and the parity
bit as well as the encoding of the data bits. The Decoder
recognizes the sync pulse and identifies it as well as decod-
ing the data bits and checking parity.
• Separate Encode and Decode
• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE
TEMP. RANGE
1.25 MEGABIT/s PKG. NO.
This integrated circuit is fully guaranteed to support the
1MHz data rate of MlL-STD-1553 over both temperature and
voltage. It interfaces with CMOS, TTL or N channel support
circuitry, and uses a standard 5V supply.
o
o
CERDIP
-40 C to +85 C HD1-15530-9
F24.6
J28.A
E24.6
o
o
-55 C to +125 C HD1-15530-8
SMD#
CLCC
7802901JA
o
o
The HD-15530 can also be used in many party line digital
data communications applications, such as an environmen-
tal control system driven from a single twisted pair cable of
fiber optic cable throughout the building.
-40 C to +85 C HD4-15530-9
o
o
-55 C to +125 C HD4-15530-8
SMD#
PDIP
78029013A
o
o
-40 C to +85 C HD3-15530-9
Pinouts
HD-15530 (CERDIP, PDIP)
HD-15530 (CLCC)
TOP VIEW
TOP VIEW
VALID WORD
ENCODER
SHIFT CLK
1
2
24
V
CC
23 ENCODER CLK
22
TAKE DATA
SERIAL DATA OUT
DECODER CLK
3
SEND CLK IN
21 SEND DATA
4
4
3
2
1
28 27 26
SEND
DATA
DECODER
CLK
25
5
6
5
20 SYNC SELECT
19 ENCODER ENABLE
18 SERIAL DATA IN
17 BIPOLAR ONE OUT
16 OUTPUT INHIBIT
BIPOLAR ZERO IN
BIPOLAR ONE IN
6
24 NC
23 NC
NC
NC
7
7
UNIPOLAR DATA IN
8
SYNC
BIPOLAR
ZERO IN
22
21
20
19
8
DECODER SHIFT CLK
9
SELECT
COMMAND/
DATA SYNC
BIPOLAR
ZERO OUT
ENCODER
ENABLE
BIPOLAR
ONE IN
10
15
9
DECODER RESET 11
14 ÷ 6 OUT
UNIPOLAR
DATA IN
SERIAL
DATA IN
10
11
GND 12
13 MASTER RESET
DECODER
SHIFT CLK
BIPOLAR
ONE OUT
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2960.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19959-142
HD-15530
Block Diagrams
ENCODER
DECODER
GND
12
V
CC
8
7
24
16
3
UNIPOLAR
DATA IN
BIPOLAR
ONE IN
BIPOLAR
ZERO IN
TAKE
DATA
MASTER RESET
13
OUTPUT
INHIBIT
TRANSITION
FINDER
CHARACTER
IDENTIFIER
SEND CLK IN
22
17
15
10
4
÷ 6 OUT
BIPOLAR
ONE OUT
BIPOLAR
ZERO OUT
6
COMMAND/
DATA SYNC
SERIAL
DATA OUT
÷ 2
14
CHARACTER
FORMER
÷ 6
ENCODER
CLK
BIT
RATE
CLK
1
5
PARITY
CHECK
VALID
WORD
DECODER
CLK
SYNCHRONIZER
23
BIT
COUNTER
9
DECODER
SHIFT
CLK
13
MASTER
RESET
18
19
20
2
21
SERIAL
DATA IN
SYNC
SELECT
11
DECODER
RESET
BIT
COUNTER
SEND
DATA
ENCODER
ENABLE
ENCODER
SHIFT CLK
Pin Description
PIN
NUMBER
TYPE
NAME
SECTION
DESCRIPTION
1
O
VALID WORD
Decoder
Output high indicates receipt of a valid word, (valid parity and no Manches-
ter errors).
2
3
O
O
ENCODER SHIFT
CLOCK
Encoder
Decoder
Output for shifting data into the Encoder. The Encoder samples SDI on the
low-to-high transition of Encoder Shift Clock.
TAKE DATA
Output is high during receipt of data after identification of a sync pulse and
two valid Manchester data bits.
4
5
O
I
SERIAL DATA OUT
DECODER CLOCK
Decoder
Decoder
Delivers received data in correct NRZ format.
Input drives the transition finder, and the synchronizer which in turn
supplies the clock to the balance of the decoder, input a frequency equal to
12X the data rate.
6
7
I
I
BIPOLAR ZERO IN
BIPOLAR ONE IN
UNLPOLAR DATA IN
Decoder
Decoder
Decoder
Decoder
Decoder
A high input should be applied when the bus is in its negative state. This pin
must be held high when the Unipolar input is used.
A high input should be applied when the bus is in its positive state. This pin
must be held low when the Unipolar input is used.
8
I
With pin 6 high and pin 7 low, this pin enters unipolar data into the transition
finder circuit. If not used this input must be held low.
9
O
O
DECODER SHIFT
CLOCK
Output which delivers a frequency (DECODER CLOCK ÷ 12), synchro-
nized by the recovered serial data stream.
10
COMMAND SYNC
Output of a high from this pin occurs during output of decoded data which
was preceded by a Command (or Status) synchronizing character. A low
output indicates a Data synchronizing character.
11
I
DECODER RESET
Decoder
A high input to this pin during a rising edge of DECODER SHIFT CLOCK
resets the decoder bit counting logic to a condition ready for a new word.
12
13
I
I
GROUND
Both
Both
Ground Supply pin.
MASTER RESET
A high on this pin clears 2:1 counters in both Encoder and Decoder, and
resets the ÷ 6 circuit.
14
15
O
O
÷ 6 OUT
Encoder
Encoder
Output from 6:1 divider which is driven by the ENCODER CLOCK.
BIPOLAR ZERO OUT
An active low output designed to drive the zero or negative sense of a
bipolar line driver.
16
17
I
OUTPUT INHIBIT
Encoder
Encoder
A low on this pin forces pin 15 and 17 high, the inactive states.
O
BIPOLAR ONE OUT
An active low output designed to drive the one or positive sense of a bipolar
line driver.
5-143
HD-15530
Pin Description (Continued)
PIN
NUMBER
TYPE
NAME
SECTION
DESCRIPTION
18
I
SERIAL DATA IN
Encoder
Accepts a serial data stream at a data rate equal to ENCODER SHIFT
CLOCK.
19
I
ENCODER ENABLE
Encoder
A high on this pin initiates the encode cycle. (Subject to the preceeding
cycle being complete.)
20
21
22
I
O
I
SYNC SELECT
SEND DATA
Encoder
Encoder
Encoder
Actuates a Command sync for an input high and Data sync for an input low.
An active high output which enables the external source of serial data.
SEND CLOCK IN
Clock input at a frequency equal to the data rate X2, usually driven by ÷ 6
output.
23
24
I
I
ENCODER CLOCK
Encoder
Both
Input to the 6:1 divider, a frequency equal to the data rate X12 is usually
input here.
V
V
is the +5V power supply pin. A 0.1µF decoupling capacitor from V
CC
CC
CC
(pin 24) to GROUND (pin 12) is recommended.
I = Input
O = Output
Encoder Operation
The Encoder requires a single clock with a frequency of ENCODER SHIFT CLOCK so it can be sampled on the low-
twice the desired data rate applied at the SEND CLOCK to-high transition 3 - 4 . After the sync and Manchester II
input. An auxiliary divide by six counter is provided on chip coded data are transmitted through the BIPOLAR ONE and
which can be utilized to produce the SEND CLOCK by divid- BIPOLAR ZERO outputs, the Encoder adds on an additional
ing the DECODER CLOCK.
bit which is the parity for that word 5 . If ENCODER
ENABLE is held high continuously, consecutive words will be
encoded without an interframe gap. ENCODER ENABLE
must go low by time 5 as shown to prevent a consecutive
word from being encoded. At any time a low on OUTPUT
INHIBIT input will force both bipolar outputs to a high state
but will not affect the Encoder in any other way.
The Encoder’s cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK 1 .
This cycle lasts for one word length or twenty ENCODER
SHIFT CLOCK periods. At the next low-to-high transition of
the ENCODER SHIFT CLOCK, a high SYNC SELECT input
actuates a command sync or a low will produce a data sync
for the word 2 . When the Encoder is ready to accept data, To abort the Encoder transmission a positive pulse must be
the SEND DATA output will go high and remain high for six- applied at MASTER RESET. Anytime after or during this
teen ENCODER SHIFT CLOCK periods 3 . During these pulse, a low-to-high transition on SEND CLOCK clears the
sixteen periods the data should be clocked into the SERIAL internal counters and initializes the Encoder for a new word.
DATA input with every high-to-low transition of the
TIMING
0
1
2
3
4
5
6
7
15
16
17
18
19
SEND CLK
ENCODER
SHIFT CLK
ENCODER
ENABLE
DON’T CARE
DON’T CARE
SYNC SELECT
SEND DATA
VALID
SERIAL
DATA IN
15
14
13
12
11
10
3
2
1
0
BIPOLAR
ONE OUT
3
3
2
2
1
1
0
0
P
P
1ST HALF 2ND HALF 15
14
14
13
13
12
12
11
11
BIPOLAR
ZERO OUT
SYNC
SYNC
3
15
1
2
4
5
FIGURE 1.
5-144
HD-15530
Decoder Operation
The Decoder requires a single clock with a frequency of 12 data available at SERIAL DATA OUT is in NRZ format. The
times the desired data rate applied at the DECODER DECODER SHIFT CLOCK is provided so that the decoded
CLOCK input. The Manchester II coded data can be bits can be shifted into an external register on every low-to-
presented to the Decoder in one of two ways. The BIPOLAR high transition of this clock
-
2 3 . Note that DECODER
ONE and BIPOLAR ZERO inputs will accept data from a SHIFT CLOCK may adjust its phase up until the time that
comparator sensed transformer coupled bus as specified in TAKE DATA goes high.
Military Spec 1553. The UNIPOLAR DATA input can only
After all sixteen decoded bits have been transmitted 3 the
accept non-inverted Manchester II coded data. (e.g. from
data is checked for odd parity. A high on VALID WORD
BIPOLAR ONE OUT of an Encoder through an inverter to
output 4 indicates a successful reception of a word without
Unipolar Data Input).
any Manchester or parity errors. At this time the Decoder is
The Decoder is free running and continuously monitors its looking for a new sync character to start another output
data input lines for a valid sync character and two valid sequence. VALID WORD will go low approximately 20
Manchester data bits to start an output cycle. When a valid DECODER SHIFT CLOCK periods after it goes high if not
sync is recognized 1 , the type of sync is indicated on reset low sooner by a valid sync and two valid Manchester
COMMAND/DATA SYNC output. If the sync character was a bits as shown 1 .
command sync, this output will go high 2 and remain high
At any time in the above sequence a high input on
for sixteen DECODER SHIFT CLOCK periods 3 , otherwise
DECODER RESET during a low-to-high transition of
it will remain low. The TAKE DATA output will go high and
DECODER SHIFT CLOCK will abort transmission and ini-
remain high
- while the Decoder is transmitting the
2 3
tialize the Decoder to start looking for a new sync character.
decoded data through SERIAL DATA OUT. The decoded
TIMING
0
1
2
3
4
5
6
7
8
16
17
18
19
DECODER
SHIFT CLK
BIPOLAR
ONE IN
1ST HALF 2ND HALF
15
15
14
14
13
13
12
12
11
11
10
10
2
2
1
1
0
0
P
P
BIPOLAR
ZERO IN
SYNC
SYNC
TAKE DATA
COMMAND/
DATA SYNC
SERIAL
DATA OUT
15
14
13
12
4
3
2
1
0
UNDEFINED
VALID WORD
(FROM PREVIOUS RECEPTION)
1
3
4
2
FIGURE 2.
5-145
HD-15530
How to Make Our MTU Look Like a Manchester Encoded UART
V
VALID WORD
CC
DECODER
ENCODER CLK
SYNC
SELECT
1
2
24
23
22
21
20
19
18
17
16
15
14
13
ENCODER
ENABLE
BIPOLAR
ZERO IN
3
BIPOLAR
ONE IN
BIPOLAR
ONE OUT
4
5
6
UNIPOLAR
DATA IN
INHIBIT
OUTPUT
7
8
COMMAND
SYNC
BIPOLAR
ZERO OUT
9
10
11
12
DECODER
RESET
MASTER
RESET
A
B
CK
H
A
B
CK
O
SH/LD CK SI O SH/LD CK
H H
74LS164
74LS164
74165
74165
PARALLEL OUT
PARALLEL IN
FIGURE 3.
Typical Timing Diagrams for a Manchester Encoded UART
VALID
VALID
ENCODER ENABLE
SYNC SELECT
PARALLEL IN
BIPOLAR ONE OUT
BIPOLAR ZERO OUT
P
P
SYNC
MSB
LSB
PARITY
FIGURE 4. ENCODER TIMING
SYNC
MSB
LSB PARITY
BIPOLAR ONE IN
BIPOLAR ZERO IN
COMMAND SYNC
PARALLEL OUT
VALID WORD
P
P
VALID
VALID
FROM
PREVIOUS
RECEPTION
FIGURE 5. DECODER TIMING
5-146
HD-15530
Words. Terminals respond with Status Words. Each word is
MIL-STD-1553
preceded by a synchronizing pulse, and followed by parity
bit, occupying a total of 20µs. The word formats are shown in
Figure 4. The special abbreviations are as follows:
The 1553 standard defines a time division multiplexed data
bus for application within aircraft. The bus is defined to be
bipolar, and encoded in a Manchester II format, so no DC
component appears on the bus. This allows transformer
coupling and excellent isolation among systems and their
environment.
P
Parity, which is defined to be odd, taken across all 17
bits.
R/T
ME
TF
Receive on logical zero, transmit on ONE.
Message Error if logical 1.
The HD-15530 supports the full bipolar configuration,
assuming a bus driver configuration similar to that in Figure
1. Bipolar inputs from the bus, like Figure 2, are also accom-
modated.
Terminal Flat, if set, calls for controller to request
self-test data.
The paragraphs above are intended only to suggest the
content of MlL-STD-1553, and do not completely describe its
bus requirements, timing or protocols.
The signaling format in MlL-STD-1553 is specified on the
assumption that the network of 32 or fewer terminals are
controlled by a central control unit by means of Command
BUS
+
-
“1”
“1”
“1” REF
“0” REF
-
+
“0”
“0”
BUS
FIGURE 6. SIMPLIFIED MIL-STD-1553 DRIVER
FIGURE 7. SIMPLIFIED MIL-STD-1553 RECEIVER
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
COMMAND
SYNC
COMMAND WORD (FROM CONTROLLER TO TERMINAL)
5
1
5
5
1
DATA
SYNC
TERMINAL
ADDRESS
SUB ADDRESS
/MODE
DATA WORD
COUNT
SYNC
P
R/T
BIT
PERIOD
BIT
PERIOD
BIT
PERIOD
DATA WORD (SENT EITHER DIRECTION)
16
1
P
LOGICAL ONE DATA
LOGICAL ZERO DATA
SYNC
CONTROL WORD
STATUS WORD (FROM TERMINAL TO CONTROLLER)
5
1
9
1
1
TERMINAL
ADDRESS
SYNC
CODE FOR FAILURE MODES TF
P
ME
FIGURE 8. MIL-STD-1553 CHARACTER FORMATS
FIGURE 9. MIL-STD-1553 WORD FORMATS
NOTE: This page is a summary of MIL-STD-1553 and is not intended to describe the operation of the HD-15530.
5-147
HD-15530
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V Thermal Resistance (Typical)
θJA ( C/W) θJC ( C/W)
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
+0.3V
CC
CERDIP Package . . . . . . . . . . . . . . . .
CLCC Package . . . . . . . . . . . . . . . . . .
Plastic DIP Package . . . . . . . . . . . . . .
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
55
65
60
12
14
N/A
Operating Conditions
o
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
o
Temperature Range (T )
HD-15530-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
A
o
o
Maximum Storage Temperature Range . . . . . . . . .-65 C to +150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300 C
o
o
o
o
o
HD-15530-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
Encoder/Decoder Clock Rise Time . . . . . . . . . . . . . . . . . . .8ns Max
Encoder/Decoder Clock Fall Time . . . . . . . . . . . . . . . . . . . .8ns Max
Sync Transition Span (TD2) . . . . . . . . . . . . . . . 18 TDC Typ (Note 1)
Short Data Transition Span (TD4) . . . . . . . . . . . 6 TDC Typ (Note 1)
Long Data Transition Span (TD5). . . . . . . . . . . 12 TDC Typ (Note 1)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
o
DC Electrical Specifications V = 5V ±10%, T = -40 C to +85 C (HD-15530-9)
CC
A
o
o
T = -55 C to +125 C (HD-15530-8)
A
LIMITS
PARAMETER
Input LOW Voltage
SYMBOL
MIN
MAX
TEST CONDITIONS
UNITS
V
-
0.7 V
-
0.2 V
CC
V
V
V
V
= 4.5V and 5.5V
= 4.5V and 5.5V
= 4.5V and 5.5V
= 4.5V and 5.5V
V
V
IL
CC
CC
CC
CC
Input HIGH Voltage
Input LOW Clock Voltage
Input HIGH Clock Voltage
Output LOW Voltage
Output HIGH Voltage
Input Leakage Current
Standby Supply Current
Operating Power Supply Current
Function Test
V
-
lH
CC
V
GND +0.5
V
ILC
V
V
-0.5
CC
-
0.4
-
V
IHC
V
-
I
I
= 1.8mA (Note 2), V
= 4.5V
= 4.5V
V
OL
OL
CC
V
2.4
= -3mA (Note 2), V
CC
V
OH
OH
I
-1.0
+1.0
2
V = GND or V , V
= 5.5V
µA
mA
mA
-
I
I
CC CC
I
-
-
-
V
V
= V
CC
= 5.5V Output Open
CCSB
IN
I
10
-
= 5.5V, V = V , f =15MHz, Outputs Open
IN CC
CCOP
CC
F
(Note 3)
T
NOTES:
1. TDC = Decoder clock period = 1/FDC
2. Interchanging of force and sense conditions is permitted.
3. Tested as follows: = f = 15MHz, V = 70% V , V = 20% V , C = 50pF, V ≥ 1.5V and V ≤ 1.5V.
OH OL
IH
CC IL
CC
L
o
Capacitance T = +25 C; Frequency = 1MHz
A
SYMBOL
PARAMETER
Input Capacitance
Output Capacitance
TYPICAL
UNITS
CONDITIONS
All measurements are referenced to device GND
C
15
15
pF
pF
IN
C
O
5-148
HD-15530
o
o
AC Electrical Specifications V = 5V ±10%, T = -40 C to +85 C (HD-15530-9)
CC
A
o
o
T = -55 C to +125 C (HD-15530-8)
A
LIMITS
(NOTE 2)
PARAMETER
ENCODER TIMING
Encoder Clock Frequency
Send Clock Frequency
Encoder Data Rate
Master Reset Pulse Width
Shift Clock Delay
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
FEC
FESC
FED
TMR
TE1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 4.5V and 5.5V, C = 50pF
-
-
15
MHz
MHz
MHz
ns
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
L
= 4.5V and 5.5V, C = 50pF
2.5
L
= 4.5V and 5.5V, C = 50pF
-
1.25
L
= 4.5V and 5.5V, C = 50pF
150
-
-
L
= 4.5V and 5.5V, C = 50pF
125
ns
L
Serial Data Setup
TE2
= 4.5V and 5.5V, C = 50pF
75
75
90
100
55
150
0
-
ns
L
Serial Data Hold
TE3
= 4.5V and 5.5V, C = 50pF
-
ns
L
Enable Setup
TE4
= 4.5V and 5.5V, C = 50pF
-
ns
L
Enable Pulse Width
Sync Setup
TE5
= 4.5V and 5.5V, C = 50pF
-
ns
L
TE6
= 4.5V and 5.5V, C = 50pF
-
-
ns
L
Sync Pulse Width
TE7
= 4.5V and 5.5V, C = 50pF
ns
L
Send Data Delay
TE8
= 4.5V and 5.5V, C = 50pF
50
130
-
ns
L
Bipolar Output Delay
Enable Hold
TE9
= 4.5V and 5.5V, C = 50pF
-
ns
L
TE10
TE11
= 4.5V and 5.5V, C = 50pF
10
95
ns
L
Sync Hold
= 4.5V and 5.5V, C = 50pF
-
ns
L
DECODER TIMING
Decoder Clock Frequency
Decoder Data Rate
Decoder Reset Pulse Width
Decoder Reset Setup Time
Decoder Reset Hold Time
Master Reset Pulse
Bipolar Data Pulse Width
FDC
FDD
V
V
V
V
V
V
V
= 4.5V and 5.5V, C = 50pF
-
15
MHz
MHz
ns
CC
CC
CC
CC
CC
CC
CC
L
= 4.5V and 5.5V, C = 50pF
-
1.25
L
TDR
= 4.5V and 5.5V, C = 50pF
150
75
10
150
-
-
-
-
-
L
TDRS
TDRH
TMR
TD1
= 4.5V and 5.5V, C = 50pF
ns
L
= 4.5V and 5.5V, C = 50pF
ns
L
= 4.5V and 5.5V, C = 50pF
ns
L
= 4.5V and 5.5V, C = 50pF
TDC + 10
(Note 1)
ns
L
One Zero Overlap
TD3
V
= 4.5V and 5.5V, C = 50pF
-
TDC - 10
(Note 1)
ns
CC
L
Sync Delay (ON)
Take Data Delay (ON)
Serial Data Out Delay
Sync Delay (OFF)
Take Data Delay (OFF)
Valid Word Delay
NOTES:
TD6
TD7
V
V
V
V
V
V
= 4.5V and 5.5V, C = 50pF
-20
0
110
110
80
ns
ns
ns
ns
ns
ns
CC
CC
CC
CC
CC
CC
L
= 4.5V and 5.5V, C = 50pF
L
TD8
= 4.5V and 5.5V, C = 50pF
-
L
TD9
= 4.5V and 5.5V, C = 50pF
0
110
110
110
L
TD10
TD11
= 4.5V and 5.5V, C = 50pF
0
L
= 4.5V and 5.5V, C = 50pF
0
L
1. TDC = Decoder clock period = 1/FDC
2. AC Testing as follows: Input levels: V = 70% V , V = 20% V ; Input rise/fall times driven at 1ns/V; Timing Reference levels: 1.5V;
IH
CC IL
CC
Output load: C = 50pF.
L
5-149
HD-15530
Timing Waveforms
SEND CLOCK
T
E1
ENCODER SHIFT CLOCK
T
T
E2
E3
VALID
VALID
SERIAL DATA IN
SEND CLOCK
T
E1
ENCODER SHIFT CLOCK
ENCODER ENABLE
T
E4
T
E5
T
E6
VALID
SYNC SELECT
T
E7
ENCODER SHIFT CLOCK
SEND DATA
T
E8
SEND CLOCK
T
E9
BIPOLAR ONE OUT OR
BIPOLAR ZERO OUT
FIGURE 10. ENCODER TIMING
DECODER SHIFT CLOCK
COMMAND/DATA SYNC
TAKE DATA
T
T
D6
D7
DECODER SHIFT CLOCK
SERIAL DATA OUT
T
T
D8
D9
DATA BIT
DECODER SHIFT CLOCK
COMMAND/DATA SYNC
T
D10
TAKE DATA
T
VALID WORD
D11
DECODER SHIFT CLOCK
DECODER RESET
T
DRS
T
DR
T
DRH
FIGURE 11. DECODER TIMING
5-150
HD-15530
Timing Waveforms (Continued)
NOTE: UNIPOLAR IN = 0, FOR NEXT DIAGRAMS.
BIT PERIOD
BIT PERIOD
BIT PERIOD
BIPOLAR ONE IN
T
D3
T
D1
BIPOLAR ZERO IN
T
D2
T
D1
T
T
T
D2
D3
COMMAND SYNC
BIPOLAR ONE IN
BIPOLAR ZERO IN
T
D1
T
D3
T
T
D1
D1
T
T
D3
D2
D2
DATA SYNC
T
D1
BIPOLAR ONE IN
BIPOLAR ZERO IN
T
T
D3
T
T
T
D3
D3
D3
D3
T
T
D1
D1
T
T
T
T
D4
D4
D5
D5
ONE
ZERO
ONE
NOTE: BIPOLAR ONE IN = 0; BIPOLAR ZERO IN = 1, FOR NEXT DIAGRAMS.
T
D2
UNIPOLAR IN
UNIPOLAR IN
UNIPOLAR IN
T
D2
COMMAND SYNC
T
D2
T
D2
DATA SYNC
ONE
T
T
D4
D5
T
T
D5
T
D4
D4
ONE
ZERO
ONE
FIGURE 12. DECODER TIMING
Test Load Circuit
AC Testing Input, Output Waveform
INPUT
OUTPUT
V
V
DUT
IH
OH
50%
50%
CL9
(NOTE)
V
V
OL
IL
AC Testing: All input signals must switch between V and V . Input
IL IH
rise and fall times are driven at 1ns per volt.
NOTE: Includes stray and jig capacitance.
5-151
HD-15530
Burn-In Circuits
HD1-15530 CERDIP
V
CC
C1
GND
V
1
24
23
22
21
20
19
18
17
16
15
14
13
A
A
CC
R1
2
3
F0
A
A
A
4
R1
R1
R1
R1
R1
R1
5
GND
F0
6
V
CC
V
CC
7
GND
8
GND
A
R1
R1
R1
R1
9
V
CC
A
A
10
11
12
GND
GND
GND
GND
R1
R1
HD4-15530 CLCC
V
CC
C1
GND GND GND GND
F0
R2 R2 R2 R2
4
3
2
1
28 27 26
R2
GND
NC
F0
NC
NC
25
5
24
23
22
21
20
19
6
7
NC
GND
8
V
9
CC
GND
GND
GND
10
11
R2
12 13 14 15 16 17 18
R2
R2
V
CC
R2
GND GND GND GND
NOTES:
1. V
= 5.5V ± 0.5V
CC
2. V = 4.5V ± 10%
IH
3. V = -0.2V +0.4V
IL
4. R1 = 47KΩ ± 5%
5. R2 = 1.8KΩ ± 5%
6. F0 = 100KHz ± 10%
7. C1 = 0.01µF Min.
5-152
HD-15530
Die Characteristics
DIE DIMENSIONS:
155 x 195 x 19mils
GLASSIVATION:
Type: SiO
2
Thickness: 8kA ±1kÅ
METALLIZATION:
Type: Si-Al
Thickness: 11kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
5
2
1.8 x 10 A/cm
Metallization Mask Layout
HD-15530
V
CC
ENCODER
SHIFT CLK
VALID
WORD
ENCODER CLK
TAKE DATA
SEND CLK IN
SERIAL DATA OUT
SEND DATA
DECODER CLK
SYNC SELECT
BIPOLAR ZERO IN
BIPOLAR ONE IN
ENCODER ENABLE
SERIAL DATA IN
UNIPOLAR DATA IN
BIPOLAR ONE OUT
DECODER SHIFT CLK
OUTPUT INHIBIT
BIPOLAR ZERO OUT
COMMAND/DATA SYNC
DECODER
RESET
GND MASTER
RESET
÷ 6 OUT
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5-153
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