HI5728INZ [INTERSIL]
10-Bit, 125/60MSPS, Dual High Speed CMOS D/A Converter;
| 型号： | HI5728INZ |
| 厂家： | 
Intersil |
| 描述： | 10-Bit, 125/60MSPS, Dual High Speed CMOS D/A Converter 转换器 |
| 文件： | 总19页 (文件大小：458K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI5728
®
Data Sheet
January 22, 2010
FN4321.5
10-Bit, 125/60MSPS, Dual High Speed
CMOS D/A Converter
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .125MSPS
• Low Power . . . . . . . . . . . . . . . 330mW at 5V, 54mW at 3V
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . ±1 LSB
• Differential Linearity . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB
• Gain Matching (Typ). . . . . . . . . . . . . . . . . . . . . . . . . .0.5%
• SFDR at 5MHz Output . . . . . . . . . . . . . . . . . . . . . . . 68dBc
• Single Power Supply from +5V to +3V
The HI5728 is a 10-bit, dual 125MSPS D/A converter which
is implemented in an advanced CMOS process. It is
designed for high speed applications where integration,
bandwidth and accuracy are essential. Operating from a
single +5V or +3V supply, the converter provides 20.48mA of
full scale output current and includes an input data register.
Low glitch energy and excellent frequency domain
performance are achieved using a segmented architecture.
A 60MSPS version and an 8-bit (HI5628) version are also
available. Comparable single DAC solutions are the HI5760
(10-bit) and the HI5660 (8-bit).
• CMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
• Internal Voltage Reference
Ordering Information
• Dual 10-Bit D/A Converters on a Monolithic Chip
• Pb-Free Available (RoHS Compliant)
MAX
TEMP.
RANGE
(°C) PACKAGE DWG. # (MHz)
CLOCK
PART
NUMBER
PART
MARKING
PKG.
SPEED
Applications
HI5728IN*
HI5728IN
-40 to +85 48 Ld LQFP Q48.7x7A 125
• Wireless Local Loop
HI5728INZ*
(Note)
HI5728INZ
-40 to +85 48 Ld LQFP Q48.7x7A 125
(Pb-free)
• Direct Digital Frequency Synthesis
• Wireless Communications
• Signal Reconstruction
HI5728/6IN
HI5728/6IN -40 to +85 48 Ld LQFP Q48.7x7A
60
60
HI5728/6INZ HI5728 /6INZ -40 to +85 48 Ld LQFP Q48.7x7A
(Note)
(Pb-free)
• Arbitrary Waveform Generators
• Test Equipment/Instrumentation
• High Resolution Imaging Systems
HI5728EVAL1
+25
Evaluation Platform
125
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel
specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1999, 2010. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
HI5728
Pinout
HI5728
(48 LD LQFP)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
QD6
QD5
QD4
36
1
ID6
35
34
33
32
31
30
29
28
27
26
25
ID5
ID4
ID3
2
3
QD3
QD2
QD1
4
5
ID2
ID1
6
QD0 (LSB)
ID0 (LSB)
7
DV
DD
DGND
SLEEP
8
DV
DD
9
NC
DGND
10
AV
DD
AGND
NC
11
AV
DD
12
13 14 15 16 17 18 19 20 21 22 23 24
FN4321.5
January 22, 2010
2
HI5728
Functional Block Diagram
IOUTA IOUTB
(LSB) ID0
ID1
CASCODE
CURRENT
SOURCE
ID2
ID3
5 LSBs
+
36
36
ID4
SWITCH
MATRIX
LATCH
LATCH
31 MSB
ID5
ID6
SEGMENTS
UPPER
5-BIT
31
ID7
DECODER
ID8
(MSB) ID9
ICLK
ICOMP1
INT/EXT
BIAS
GENERATION
INT/EXT
REFERENCE
SELECT
VOLTAGE
REFERENCE
REFLO
REFIO
FSADJ
SLEEP
QCOMP1
(LSB) QD0
QD1
CASCODE
CURRENT
SOURCE
QD2
QD3
5 LSBs
+
36
36
QD4
SWITCH
MATRIX
LATCH
LATCH
31 MSB
SEGMENTS
QD5
QD6
UPPER
5-BIT
31
QD7
DECODER
QD8
QCLK
AV
AGND DV
DD
DGND
QOUTA QOUTB
DD
FN4321.5
January 22, 2010
3
HI5728
Typical Applications Circuit
I
/Q
CLK CLK
DIGITAL
GROUND
PLANE
50Ω
DV
DD
DV
DD
ANALOG
GROUND
PLANE
0.1µF
0.1µF
48 47 46 45 44 43 42 41 40 39 3837
36
QD6
QD5
QD4
QD3
QD2
QD1
QD0 (LSB)
1
2
3
4
5
6
7
ID6
ID5
ID4
ID3
ID2
ID1
35
34
33
32
31
30
29
28
27
26
25
ID0 (LSB)
SLEEP
DV
DGND
NC (GROUND)
DV
DD
8
9
DD
DV
DD
DV
DD
DGND
0.1µF
10
AV
AV
11 NC (GROUND)
DD
DD
12
0.1µF
13 14 15 16 17 18 19 20 21 22 23 24
0.1µF
AGND
AV
DD
0.1µF
AGND
QCOMP1
AV
DD
0.1µF
REFIO
ICOMP1
0.1µF
0.1µF
R
NOTE: ICOMP1 AND QCOMP1
PINS (24, 14) MUST BE TIED
TOGETHER EXTERNALLY
SET
2kΩ
AV
DD
50Ω 50Ω
50Ω 50Ω
QOUTB
QOUTA
IOUTA
IOUTB
FERRITE
BEAD
FERRITE
BEAD
+5V OR +3V SUPPLY
+5V OR +3V SUPPLY
+
+
10µH
DV
(POWER PLANE)
AV
(POWER PLANE)
DD
10µH
DD
10µF
0.1µF
0.1µF
10µF
FN4321.5
January 22, 2010
4
HI5728
Pin Descriptions
PIN NO.
PIN NAME
PIN DESCRIPTION
39, 38, 37, 36, QD9 (MSB) Through Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the Q
35, 34, 33, 32,
31, 30
QD0 (LSB)
channel.
1, 2, 3, 4, 5, 6, 7, ID9 (MSB) Through Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the I
46, 47, 48
ID0 (LSB)
channel.
8
SLEEP
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep
pin has internal 20µA active pull-down current.
15
23
REFLO
REFIO
Connect to analog ground to enable internal 1.2V reference or connect to AV
to disable.
DD
Reference voltage input if internal reference is disabled and reference voltage output if internal reference is
enabled. Use 0.1µF cap to ground when internal reference is enabled.
22
FSADJ
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current Per Channel = 32 x I
.
FSADJ
14, 24
ICOMP1, QCOMP1 Reduces noise. Connect each to AV
with 0.1µF capacitor near each pin. The ICOMP1 and QCOMP1
DD
pins MUST be tied together externally.
13, 18, 19, 25
AGND
IOUTB
IOUTA
QOUTB
QOUTA
NC
Analog Ground Connections.
17
The complimentary current output of the I channel. Bits set to all 0s gives full scale current.
Current output of the I channel. Bits set to all 1s gives full scale current.
The complimentary current output of the Q channel. Bits set to all 0s gives full scale current.
Current output of the Q channel. Bits set to all 1s gives full scale current.
No Connect. Recommended: connect to ground.
16
20
21
11, 27
12, 26
10, 28, 41, 44
9, 29, 40, 45
43
AV
Analog Supply (+2.7V to +5.5V).
DD
DGND
DV
Digital Ground.
Supply voltage for digital circuitry (+2.7V to +5.5V).
DD
ICLK
Clock input for I channel. Positive edge of clock latches data.
Clock input for Q channel. Positive edge of clock latches data.
42
QCLK
FN4321.5
January 22, 2010
5
HI5728
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DV
to DCOM . . . . . . . . . . . . . . . . . +5.5V
to ACOM. . . . . . . . . . . . . . . . . . +5.5V
Thermal Resistance (Typical, Note 1)
θ
(°C/W)
55
DD
Analog Supply Voltage AV
JA
DD
48 Ld TQFP Package. . . . . . . . . . . . . . . . . . . . . . . .
Maximum Power Dissipation
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . .DV +0.3V
DD
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . . ±50µA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV +0.3V
48 Ld TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .930mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Analog Output Current (I
OUT
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications AV = DV = +5V, V
= Internal 1.2V, IOUTFS = 20mA, T = +25°C for All Typical Values. Data given is
A
per channel except for “POWER SUPPLY CHARACTERISTICS” on page 8
DD
DD
REF
HI5728IN
T
= -40°C TO +85°C
A
MIN
MAX
PARAMETER
SYSTEM PERFORMANCE (Per Channel)
Resolution
TEST CONDITIONS
(Note 11) TYP (Note 11)
UNITS
10
-1
-
-
+1
Bits
LSB
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 7)
±0.5
±0.25
Differential Linearity Error, DNL
(Note 7)
(Note 7)
(Note 7)
-0.5
-0.025
-
+0.5
+0.025
-
LSB
Offset Error, I
OS
% FSR
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
ppm FSR/°C
dB
Offset Drift Coefficient
0.1
±2
Full Scale Gain Error, FSE
With External Reference (Notes 2, 7)
With Internal Reference (Notes 2, 7)
With External Reference (Note 7)
With Internal Reference (Note 7)
-10
-10
-
+10
+10
-
±1
Full Scale Gain Drift
±50
±100
0.1
80
-
-
Gain Matching Between Channels
I/Q Channel Isolation
-0.5
-
0.5
-
F
= 10MHz
dB
OUT
(Note 3)
Output Voltage Compliance Range
-0.3
2
-
1.25
20
V
Full Scale Output Current, I
-
mA
FS
DYNAMIC CHARACTERISTICS (Per Channel)
Maximum Clock Rate, f
Output Settling Time, (t
(Note 3)
125
-
-
-
-
-
-
-
-
-
-
MHz
ns
CLK
)
0.1% (±1 LSB, equivalent to 9 Bits) (Note 7)
0.05% (±1/2 LSB, equivalent to 10 Bits) (Note 7)
-
-
-
-
-
-
-
-
20
35
35
1.5
1.5
10
50
30
SETT
ns
Singlet Glitch Area (Peak Glitch)
Output Rise Time
R
= 25Ω (Note 7)
pV•s
ns
L
Full Scale Step
Full Scale Step
Output Fall Time
ns
Output Capacitance
Output Noise
pF
IOUTFS = 20mA
IOUTFS = 2mA
pA/√Hz
pA/√Hz
FN4321.5
January 22, 2010
6
HI5728
Electrical Specifications AV = DV = +5V, V = Internal 1.2V, IOUTFS = 20mA, T = +25°C for All Typical Values. Data given is
REF A
DD
DD
per channel except for “POWER SUPPLY CHARACTERISTICS” on page 8 (Continued)
HI5728IN
T
= -40°C TO +85°C
A
MIN
MAX
PARAMETER
TEST CONDITIONS
(Note 11) TYP (Note 11)
UNITS
AC CHARACTERISTICS (Per Channel) - HI5728IN - 125MHz
Spurious Free Dynamic Range,
SFDR Within a Window
f
= 125MSPS, f
= 100MSPS, f
= 32.9MHz, 10MHz Span (Notes 4, 7)
= 5.04MHz, 4MHz Span (Notes 4, 7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
75
76
75
76
78
71
71
76
54
64
52
60
68
74
63
55
68
73
73
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
CLK
OUT
f
CLK
OUT
f
= 60MSPS, f
= 50MSPS, f
= 50MSPS, f
= 10.1MHz, 10MHz Span (Notes 4, 7)
= 5.02MHz, 2MHz Span (Notes 4, 7)
= 1.00MHz, 2MHz Span (Notes 4, 7)
CLK
OUT
OUT
OUT
f
CLK
f
CLK
Total Harmonic Distortion (THD) to
Nyquist
f
f
f
= 100MSPS, f
= 2.00MHz (Notes 4, 7)
OUT
CLK
CLK
CLK
= 50MSPS, f
= 50MSPS, f
= 2.00MHz (Notes 4, 7)
OUT
OUT
= 1.00MHz (Notes 4, 7)
Spurious Free Dynamic Range,
SFDR to Nyquist
f
= 125MSPS, f
= 125MSPS, f
= 100MSPS, f
= 100MSPS, f
= 100MSPS, f
= 100MSPS, f
= 32.9MHz, 62.5MHz Span (Notes 4, 7)
= 10.1MHz, 62.5MHz Span (Notes 4, 7)
= 40.4MHz, 50MHz Span (Notes 4, 7)
= 20.2MHz, 50MHz Span (Notes 4, 7)
= 5.04MHz, 50MHz Span (Notes 4, 7)
= 2.51MHz, 50MHz Span (Notes 4, 7)
CLK
OUT
OUT
OUT
OUT
OUT
OUT
f
CLK
f
CLK
f
CLK
f
CLK
f
CLK
f
= 60MSPS, f
= 50MSPS, f
= 50MSPS, f
= 50MSPS, f
= 50MSPS, f
= 10.1MHz, 30MHz Span (Notes 4, 7)
= 20.2MHz, 25MHz Span (Notes 4, 7)
= 5.02MHz, 25MHz Span (Notes 4, 7)
= 2.51MHz, 25MHz Span (Notes 4, 7)
= 1.00MHz, 25MHz Span (Notes 4, 7)
CLK
OUT
OUT
OUT
OUT
OUT
f
CLK
f
CLK
f
CLK
f
CLK
AC CHARACTERISTICS (Per Channel) - HI5728/6IN - 60MHz
Spurious Free Dynamic Range,
SFDR Within a Window
f
= 60MSPS, f
= 50MSPS, f
= 50MSPS, f
= 10.1MHz, 10MHz Span (Notes 4, 7)
= 5.02MHz, 2MHz Span (Notes 4, 7)
= 1.00MHz, 2MHz Span (Notes 4, 7)
-
-
-
-
-
-
-
-
-
-
-
-
75
76
78
71
76
56
63
55
68
73
73
71
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
CLK
OUT
OUT
OUT
f
CLK
f
CLK
Total Harmonic Distortion (THD) to
Nyquist
f
f
= 50MSPS, f
= 50MSPS, f
= 2.00MHz (Notes 4, 7)
= 1.00MHz (Notes 4, 7)
CLK
CLK
OUT
OUT
Spurious Free Dynamic Range,
SFDR to Nyquist
f
= 60MSPS, f
= 60MSPS, f
= 50MSPS, f
= 50MSPS, f
= 50MSPS, f
= 50MSPS, f
= 25MSPS, f
= 20.2MHz, 30MHz Span (Notes 4, 7)
= 10.1MHz, 30MHz Span (Notes 4, 7)
= 20.2MHz, 25MHz Span (Notes 4, 7)
= 5.02MHz, 25MHz Span (Notes 4, 7)
= 2.51MHz, 25MHz Span (Notes 4, 7)
= 1.00MHz, 25MHz Span (Notes 4, 7)
= 5.02MHz, 25MHz Span (Notes 4, 7)
CLK
OUT
OUT
OUT
OUT
OUT
OUT
OUT
f
CLK
f
CLK
f
CLK
f
CLK
f
CLK
f
CLK
VOLTAGE REFERENCE
Internal Reference Voltage, V
Voltage at Pin 22 with Internal Reference
1.04
1.16
±60
0.1
1.28
V
ppm/°C
µA
FSADJ
Internal Reference Voltage Drift
-
-
-
-
Internal Reference Output Current
Sink/Source Capability
Reference Input Impedance
-
-
1
-
-
MΩ
Reference Input Multiplying
Bandwidth
(Note 7)
1.4
MHz
DIGITAL INPUTS D9-D0, CLK (Per Channel)
Input Logic High Voltage with (Note 3)
5V Supply, V
3.5
5
-
V
IH
FN4321.5
January 22, 2010
7
HI5728
Electrical Specifications AV = DV = +5V, V = Internal 1.2V, IOUTFS = 20mA, T = +25°C for All Typical Values. Data given is
REF A
DD
DD
per channel except for “POWER SUPPLY CHARACTERISTICS” on page 8 (Continued)
HI5728IN
T
= -40°C TO +85°C
A
MIN
MAX
PARAMETER
TEST CONDITIONS
(Note 11) TYP (Note 11)
UNITS
Input Logic High Voltage with
(Note 3)
(Note 3)
(Note 3)
2.1
3
0
0
-
V
3V Supply, V
IH
Input Logic Low Voltage with
5V Supply, V
-
-
1.3
0.9
V
V
IL
Input Logic Low Voltage with
3V Supply, V
IL
Input Logic Current, I
Input Logic Current, I
-10
-10
-
-
-
+10
+10
-
µA
µA
pF
IH
IL
Digital Input Capacitance, C
5
IN
TIMING CHARACTERISTICS (Per Channel)
Data Setup Time, t
See Figure 41 (Note 3)
3
3
-
-
-
-
-
-
-
ns
ns
ns
ns
SU
Data Hold Time, t
See Figure 41 (Note 3)
See Figure 41
HLD
Propagation Delay Time, t
1
-
PD
CLK Pulse Width, t
, t
PW1 PW2
See Figure 41 (Note 3)
4
POWER SUPPLY CHARACTERISTICS
AVDD Power Supply
(Notes 8, 9)
2.7
5.0
5.0
46
5.5
V
V
DVDD Power Supply
(Notes 8, 9)
2.7
5.5
Analog Supply Current (I
)
(5V or 3V, IOUTFS = 20mA)
(5V or 3V, IOUTFS = 2mA)
(5V, IOUTFS = Don’t Care) (Note 5)
(3V, IOUTFS = Don’t Care) (Note 5)
-
60
mA
AVDD
-
8
-
mA
Digital Supply Current (I
)
-
6
10
mA
DVDD
-
3
-
mA
Supply Current (I
) Sleep Mode (5V or 3V, IOUTFS = Don’t Care)
(5V, IOUTFS = 20mA) (Note 6)
(5V, IOUTFS = 2mA) (Note 6)
-
3.2
330
140
170
54
6
mA
AVDD
Power Dissipation
-
-
mW
mW
mW
mW
mW
mW
mW
% FSR/V
-
-
(3V, IOUTFS = 20mA) (Note 6)
(3V, IOUTFS = 2mA) (Note 6)
-
-
-
-
(5V, IOUTFS = 20mA) (Note 10)
(3.3V, IOUTFS = 20mA) (Note 10)
(3V, IOUTFS = 20mA) (Note 10)
-
300
150
135
-
-
-
-
-
-
Power Supply Rejection
NOTES:
Single Supply (Note 7)
-0.2
+0.2
2. Gain Error measured as the error in the ratio between the full scale output current and the current through R
should be 32.
(typically 625μA). Ideally the ratio
SET
3. Limits established by characterization and are not production tested.
4. Spectral measurements made with differential coupled transformer and 100% amplitude.
5. Measured with the clock at 50MSPS and the output frequency at 1MHz, both channels.
6. Measured with the clock at 100MSPS and the output frequency at 40MHz, both channels.
7. See “Definition of Specifications” on page 16.
8. For operation below 3V, it is recommended that the output current be reduced to 12mA or less to maintain optimum performance. DV and AV
DD
DD
do not have to be equal.
9. For operation above 125MHz, it is recommended that the power supply be 3.3V or greater. The part is functional with the clock above 125MSPS
and the power supply below 3.3V, but performance is degraded.
10. Measured with the clock at 60MSPS and the output frequency at 10MHz, both channels.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN4321.5
January 22, 2010
8
HI5728
Typical Performance Curves, 5V Power Supply
80
75
70
65
60
55
50
76
74
72
70
-6dBFS
-6dBFS
0dBFS
-12dBFS
68
66
64
62
60
-12dBFS
0dBFS
1
2
3
4
5
6
7
8
9
10
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
FIGURE 1. SFDR vs f
, CLOCK = 5MSPS
OUT
FIGURE 2. SFDR vs f
, CLOCK = 25MSPS
OUT
80
75
70
65
60
55
0dBFS
-6dBFS
75
70
-12dBFS
-6dBFS
65
60
55
-12dBFS
0dBFS
25
50
45
0
5
10
15
20
30
35
40
45
0
2
4
6
8
10
12
14
16
18
20
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
FIGURE 3. SFDR vs f
, CLOCK = 50MSPS
OUT
FIGURE 4. SFDR vs f
, CLOCK = 100MSPS
OUT
75
80
75
70
65
60
55
50
45
25MSPS
70
65
60
55
50
45
50MSPS
100MSPS
6dBFS
-12dBFS
125MSPS
0dBFS
30
-25
-20
-15
-10
-5
0
0
5
10
15
20
25
35
40
45
50
AMPLITUDE (dBFS)
OUTPUT FREQUENCY (MHz)
FIGURE 5. SFDR vs f
, CLOCK = 125MSPS
OUT
FIGURE 6. SFDR vs AMPLITUDE, f
/f = 10
CLK OUT
FN4321.5
January 22, 2010
9
HI5728
Typical Performance Curves, 5V Power Supply (Continued)
75
70
65
60
55
50
45
40
80
75
70
65
60
55
50
45
40
25MSPS
50MSPS
25MSPS
(3.38/3.63MHz)
100MSPS
50MSPS
(6.75/7.25MHz)
125MSPS
100MSPS
(13.5/14.5MHz)
125MSPS
(16.9/18.1MHz)
-25
-20
-15
-10
-5
0
-25
-20
-15
-10
-5
0
AMPLITUDE (dBFS)
AMPLITUDE (TOTAL PEAK POWER OF COMBINED TONES) (dBFS)
FIGURE 7. SFDR vs AMPLITUDE, f
/f
CLK OUT
= 5
FIGURE 8. SFDR vs AMPLITUDE OF TWO TONES, f
/f = 7
CLK OUT
75
75
2.5MHz
10MHz
70
65
60
55
50
45
40
70
-6dBFS DIFF
0dBFS DIFF
65
20MHz
60
40MHz
55
-6dBFS SINGLE
50
0dBFS SINGLE
45
2
4
6
8
10
12
14
16
18
20
0
5
10
15
20
25
30
35
40
I
(mA)
OUTPUT FREQUENCY (MHz)
OUT
FIGURE 9. SFDR vs I
, CLOCK = 100MSPS
OUT
FIGURE 10. DIFFERENTIAL vs SINGLE-ENDED,
CLOCK = 100MSPS
80
75
70
65
60
55
50
45
40
-10
2.5MHz
f
= 100MSPS
-20
CLK
f
=9.95MHz
OUT
AMPLITUDE = 0dBFS
SFDR = 64dBc
-30
10.1MHz
-40
14dB EXTERNAL ANALYZER ATTENUATION
-50
-60
-70
-80
-90
40.4MHz
60
-100
-110
0
50
5MHz/DIV.
FREQUENCY (MHz)
-40
-20
0
20
40
80
5MHz/DIV.
TEMPERATURE (°C)
FIGURE 11. SFDR vs TEMPERATURE, CLOCK = 100MSPS
FIGURE 12. SINGLE TONE SFDR
FN4321.5
January 22, 2010
10
HI5728
Typical Performance Curves, 5V Power Supply (Continued)
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-20
f
= 100MSPS
CLK
l=
= 100MSPS
f
CLK
-30
f
= 3.8, 4.4, 5.6, 6.2MHz
COMBINED PEAK
AMPLITUDE = 0dBFS
SFDR = 71.4dBc
OUT
f
= 13.5/14.5MHZ
OUT
COMBINED PEAK
-40
AMPLITUDE = 0dBFS
SFDR = 62.9dBc
-50
14dB EXTERNAL
ANALYZER ATTENUATION
(IN A WINDOW)
-60
-70
-80
-90
-100
-110
0
5MHz/DIV.
5MHz/DIV.
50
0.5
15
FREQUENCY (MHz)
1.45MHz/ DIV.
FIGURE 13. TWO TONE, CLOCK = 100MSPS
FIGURE 14. FOUR-TONE, CLOCK = 100MSPS
-20
-30
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
= 50MSPS
CLK
f
= 100MSPS
CLK
= 2.6, 3.2, 3.8, 4.4, 5.6, 6.2, 6.8MHZ
f
= 1.9, 2.2, 2.8, 3.1MHZ
COMBINED PEAK
AMPLITUDE = 0dBFS
SFDR = 73.6dBc
OUT
f
OUT
COMBINED PEAK AMPLITUDE = 0dBFS
SFDR = 67dBc (IN A WINDOW)
-40
-50
(IN A WINDOW)
-60
-70
-80
-90
-100
-110
0.5
950kHz/DIV.
10
1.95MHz/DIV.
20
0.5
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 15. EIGHT-TONE, CLOCK = 100MSPS
FIGURE 16. FOUR-TONE, CLOCK = 50MSPS
0.4
0.2
0
0.4
0.2
0
-0.2
-0.4
-0.2
-0.4
0
200
400
600
800
1000
0
200
400
600
800
1000
CODE
CODE
FIGURE 17. DIFFERENTIAL NONLINEARITY
FIGURE 18. INTEGRAL NONLINEARITY
FN4321.5
January 22, 2010
11
HI5728
Typical Performance Curves, 5V Power Supply (Continued)
320
310
300
290
280
270
260
250
240
230
220
210
0
20
40
60
80
100
120
CLOCK RATE (MSPS)
FIGURE 19. POWER vs CLOCK RATE, f
/f
= 10, I
= 20mA
CLK OUT
OUT
Typical Performance Curves, 3V Power Supply
80
75
70
65
80
0dBFS
-6dBFS
75
-6dBFS
70
0dBFS
65
-12dBFS
60
-12dBFS
55
60
1
50
2
3
4
5
6
7
8
9
10
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
FIGURE 20. SFDR vs f
, CLOCK = 5MSPS
FIGURE 21. SFDR vs f
, CLOCK = 25MSPS
OUT
OUT
80
75
70
65
60
55
50
80
75
70
65
60
55
50
45
0dBFS
-6dBFS
-6dBFS
-12dBFS
-12dBFS
0dBFS
10
0
5
10
15
20
25
30
35
40
45
0
2
4
6
8
12
14
16
18
20
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
FIGURE 22. SFDR vs f
, CLOCK = 50MSPS
FIGURE 23. SFDR vs f
, CLOCK = 100MSPS
OUT
OUT
FN4321.5
January 22, 2010
12
HI5728
Typical Performance Curves, 3V Power Supply (Continued)
80
75
70
65
60
55
50
45
80
75
70
65
60
55
50
45
0dBFS
25MSPS
50MSPS
100MSPS
125MSPS
-6dBFS
-12dBFS
0
5
10
15
20
25
30
35
40
45
50
-25
-20
-15
-10
-5
0
OUTPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
FIGURE 24. SFDR vs f
, CLOCK = 125MSPS
OUT
FIGURE 25. SFDR vs AMPLITUDE, f
/f = 10
CLK OUT
75
70
80
75
70
65
60
55
50
45
40
25MSPS
25MSPS
65
(3.38/3.63MHz)
50MSPS
100MSPS
60
50MSPS
(6.75/7.25MHz)
5MSPS
55
100MSPS
(13.5/14.5MHz)
125MSPS
50
45
40
125MSPS
(16.9/18.1MHz)
-25
-20
-15
-10
-5
0
-25
-20
-15
-10
-5
0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
FIGURE 26. SFDR vs AMPLITUDE, f
/f
CLK OUT
= 5
FIGURE 27. SFDR vs AMPLITUDE OF TWO TONES, f
/f
= 7
CLK OUT
80
80
2.5MHz
75
70
65
60
55
50
45
75
70
65
60
55
50
45
0dBFS DIFF
10MHz
20MHz
-6dBFS SINGLE
-6dBFS DIFF
40MHz
0dBFS SINGLE
0
5
10
15
20
25
30
35
40
2
4
6
8
10
12
14
16
18
20
I
(mA)
OUT
OUTPUT FREQUENCY (MHz)
FIGURE 28. SFDR vs I
, CLOCK = 100MSPS
OUT
FIGURE 29. DIFFERENTIAL vs SINGLE-ENDED,
CLOCK = 100MSPS
FN4321.5
January 22, 2010
13
HI5728
Typical Performance Curves, 3V Power Supply (Continued)
80
75
70
65
60
55
50
45
40
-10
-20
f
= 100MSPS
CLK
f
2.5MHz
= 9.95MHz
OUT
AMPLITUDE = 0dBFS
SFDR = 63dBc
14dB EXTERNAL
ANALYZER ATTENUATION
-30
10.1MHz
-40
-50
-60
-70
-80
40.4MHz
60
-90
-100
-110
-40
-20
0
20
40
80
0
5MHz/DIV.
50
o
TEMPERATURE ( C)
FREQUENCY (MHz)
FIGURE 30. SFDR vs TEMPERATURE, CLOCK = 100MSPS
FIGURE 31. SINGLE TONE SFDR
-20
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
= 100MSPS
CLK
f
= 100MSPS
CLK
= 13.5/14.5MHz
-30
-40
f
= 3.8, 4.4, 5.6, 6.2MHz
COMBINED PEAK
AMPLITUDE = 0dBFS
SFDR = 70.6dBc
OUT
f
OUT
COMBINED PEAK
AMPLITUDE = 0dBFS
SFDR = 61.5dBc
-50
(IN A WINDOW)
14dB EXTERNAL
ANALYZER ATTENUATION
-60
-70
-80
-90
-100
-110
0.5
1.45MHz/DIV.
15
0
5MHz/DIV.
50
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 32. TWO-TONE, CLOCK = 100MSPS
FIGURE 33. FOUR-TONE, CLOCK = 100MSPS
-20
-30
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
= 100MSPS
CLK
f
= 50MSPS
CLK
f
= 2.6, 3.2, 3.8, 4.4,
OUT
f
= 1.9, 2.2, 2.8, 3.1MHz
COMBINED PEAK
AMPLITUDE = 0dBFS
SFDR = 74.2dBc
OUT
5.6, 6.2, 6.8MHz
-40
COMBINED PEAK
-50
AMPLITUDE = 0dBFS
SFDR = 67.4dBc
(IN A WINDOW)
(IN A WINDOW)
-60
-70
-80
-90
-100
-110
0.5
1.95MHz/DIV.
20
0
950kHz/DIV.
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 34. EIGHT-TONE, CLOCK = 100MSPS
FIGURE 35. FOUR-TONE, CLOCK = 50MSPS
FN4321.5
January 22, 2010
14
HI5728
Typical Performance Curves, 3V Power Supply (Continued)
0.4
0.2
0
0.4
0.2
0
-0.2
-0.4
-0.2
-0.4
0
200
400
600
800
1000
0
200
400
600
800
1000
CODE
CODE
FIGURE 36. DIFFERENTIAL NONLINEARITY
FIGURE 37. INTEGRAL NONLINEARITY
152
148
144
140
136
132
128
124
120
0
20
40
60
80
100
120
CLOCK RATE (MSPS)
FIGURE 38. POWER vs CLOCK RATE, f
/f
CLK OUT
= 10, I
= 20mA
OUT
FN4321.5
January 22, 2010
15
HI5728
Timing Diagrams
50%
CLK
D9-D0
1
GLITCH AREA =
/ (H x W)
2
V
HEIGHT (H)
1 LSB ERROR BAND
I
OUT
t(ps)
WIDTH (W)
t
SETT
t
PD
FIGURE 40. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
FIGURE 39. OUTPUT SETTLING TIME DIAGRAM
t
t
PW2
PW1
50%
CLK
t
t
t
SU
SU
SU
t
t
t
HLD
HLD
HLD
D9-D0
t
SETT
t
PD
I
OUT
t
t
SETT
SETT
t
t
PD
PD
FIGURE 41. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
measurement was done by switching from code 0 to 256, or
quarter scale. Termination impedance was 25Ω due to the
parallel resistance of the output 50Ω and the oscilloscope’s
50Ω input. This also aids the ability to resolve the specified
error band without overdriving the oscilloscope.
Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Singlet Glitch Area, is the switching transient appearing on
the output during a code transition. It is measured as the
area under the overshoot portion of the curve and is
expressed as a Volt-Time specification. This is tested under
the same conditions as “Output Settling Time, (tSETT)” on
page 6
Output Settling Time, is the time required for the output
voltage to settle to within a specified error band measured
from the beginning of the output transition. The
FN4321.5
January 22, 2010
16
HI5728
Full Scale Gain Error, is the error from an ideal ratio of 32
between the output current and the full scale adjust current
The five MSBs are represented by 31 major current sources
of equivalent current. The five LSBs are comprised of binary
weighted current sources. Consider an input waveform to
the converter which is ramped through all the codes from 0
to 1023. The five LSB current sources would begin to count
up. When they reached the all high state (decimal value of
31) and needed to count to the next code, they would all turn
off and the first major current source would turn on. To
continue counting upward, the 5 LSBs would count up
another 31 codes, and then the next major current source
would turn on and the five LSBs would all turn off. The
process of the single, equivalent, major current source
turning on and the five LSBs turning off each time the
converter reaches another 31 codes greatly reduces the
glitch at any one switching point. In previous architectures
that contained all binary weighted current sources or a
binary weighted resistor ladder, the converter might have a
substantially larger amount of current turning on and off at
certain, worst-case transition points such as mid-scale and
quarter scale transitions. By greatly reducing the amount of
current switching at certain ‘major’ transitions, the overall
glitch of the converter is dramatically reduced, improving
settling times and transient problems.
(through R
SET
).
Full Scale Gain Drift, is measured by setting the data inputs to
all ones and measuring the output voltage through a known
resistance as the temperature is varied from T
to T . It is
MIN
MAX
defined as the maximum deviation from the value measured at
room temperature to the value measured at either T or
MIN
. The units are ppm of FSR (full scale range) per °C.
T
MAX
Total Harmonic Distortion, THD, is the ratio of the DAC output
fundamental to the RMS sum of the first five harmonics.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental to the largest harmonically or
non-harmonically related spur within the specified window.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedance load should
be chosen such that the voltage developed does not violate
the compliance range.
Offset Error, is measured by setting the data inputs to all
zeros and measuring the output voltage through a known
resistance. Offset error is defined as the maximum deviation
of the output current from a value of 0mA.
Digital Inputs And Termination
The HI5728 digital inputs are guaranteed to CMOS levels.
However, TTL compatibility can be achieved by lowering the
supply voltage to 3V due to the digital threshold of the input
buffer being approximately half of the supply voltage. The
internal register is updated on the rising edge of the clock. To
minimize reflections, proper termination should be
Offset Drift, is measured by setting the data inputs to all zeros
and measuring the output voltage through a known resistance
as the temperature is varied from T
to T . It is defined as
MIN
MAX
the maximum deviation from the value measured at room
temperature to the value measured at either T or T
.
MIN MAX
The units are ppm of FSR (Full Scale Range) per °C.
implemented. If the lines driving the clock(s) and digital
inputs are 50Ω lines, then 50Ω termination resistors should
be placed as close to the converter inputs as possible.
Power Supply Rejection, is measured using a single power
supply. Its nominal +5V is varied ±10% and the change in the
DAC full scale output is noted.
Ground Plane(s)
Reference Input Multiplying Bandwidth, is defined as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference
with the digital inputs set to all 1s. The frequency is
increased until the amplitude of the output waveform is
0.707 of its original value.
If separate digital and analog ground planes are used, then all
of the digital functions of the device and their corresponding
components should be over the digital ground plane and
terminated to the digital ground plane. The same is true for the
analog components and the analog ground plane. Refer to the
Application Note on the HI5728 Evaluation Board for further
discussion of the ground plane(s) upon availability.
Internal Reference Voltage Drift, is defined as the
maximum deviation from the value measured at room
Noise Reduction
temperature to the value measured at either T
or T .
MAX
MIN
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the converter’s power supply
The units are ppm per °C.
pins, AV
and DV . Also, should the layout be designed
Detailed Description
The HI5728 is a dual, 10-bit, current out, CMOS, digital to
DD
DD
using separate digital and analog ground planes, these
capacitors should be terminated to the digital ground for
analog converter. Its maximum update rate is 125MSPS and
can be powered by either single or dual power supplies in
the recommended range of +3V to +5V. It consumes less
than 330mW of power when using a +5V supply with the
data switching at 100MSPS. The architecture is based on a
segmented current source arrangement that reduces glitch
by reducing the amount of current switching at any one time.
DV
DD
and to the analog ground for AV . Additional filtering
DD
of the power supplies on the board is recommended. See
the Application Note on the HI5728 Evaluation Board for
more information upon availability.
FN4321.5
January 22, 2010
17
HI5728
recommended that the unused output be either grounded or
equally terminated. The voltage developed at the output
must not violate the output voltage compliance range of
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.2V with a ±60 ppm/°C drift coefficient over the full
temperature range of the converter. It is recommended that a
0.1μF capacitor be placed as close as possible to the REFIO
pin, connected to the analog ground. The REFLO pin (15)
selects the reference. The internal reference can be selected if
pin 15 is tied low (ground). If an external reference is desired,
then pin 15 should be tied high (to the analog supply voltage)
and the external reference driven into REFIO, pin 23. The full
scale output current of the converter is a function of the voltage
-0.3V to 1.25V. R
should be chosen so that the desired
LOAD
output voltage is produced in conjunction with the output full
scale current, which is described above in the ‘Reference’
section. If a known line impedance is to be driven, then the
output load resistor should be chosen to match this
impedance. The output voltage equation is:
(EQ. 2)
V
= I
× R
OUT LOAD
OUT
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 16
and 17 will be biased at zero volts. It is important to note
here that the negative voltage output compliance range limit
reference used and the value of R should be within
the 2mA to 20mA range, through operation below 2mA is
possible, with performance degradation.
. I
SET OUT
If the internal reference is used, V
FSADJ
will equal
approximately 1.16V (pin 22). If an external reference is used,
will equal the external reference. The calculation for
V
FSADJ
(Full Scale) is:
I
OUT
is -300mV, imposing a maximum of 600mV
amplitude
P-P
(EQ. 1)
I
(Full Scale)= V
⁄ R
× 32
SET
OUT
FSADJ
with this configuration. The loading as shown in Figure 1 will
result in a 500mV signal at the output of the transformer if
the full scale output current of the DAC is set to 20mA.
If the full scale output current is set to 20mA by using the
internal voltage reference (1.16V) and a 1.86kΩ R
SET
resistor, then the input coding to output current will resemble
the following:
V
= (2 x I
x R )V
OUT EQ
OUT
50Ω
TABLE 1. INPUT CODING vs OUTPUT CURRENT (Per DAC)
IOUTB (QOUTB)
PIN 17 (20)
PIN 16 (21)
IOUTA
(mA)
IOUTB
(mA)
100Ω
50Ω
INPUT CODE (D9-D0)
11111 11111
IOUTA (QOUTA)
50Ω
20
10
0
0
10000 00000
10
20
00000 00000
FIGURE 42.
V
= 2 x I
x R
EQ ,
where R is ~12.5Ω.
EQ
Outputs
OUT
OUT
IOUTA and IOUTB (or QOUTA and QOUTB) are
Allowing the center tap to float will result in identical
complementary current outputs. The sum of the two currents
is always equal to the full scale output current minus one
LSB. If single ended use is desired, a load resistor can be
used to convert the output current to a voltage. It is
transformer output, however the output pins of the DAC will
have positive DC offset. The 50Ω load on the output of the
transformer represents the spectrum analyzer’s input
impedance.
FN4321.5
January 22, 2010
18
HI5728
Thin Plastic Quad Flatpack Packages (LQFP)
D
Q48.7x7A (JEDEC MS-026BBC ISSUE B)
48 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE
D1
-D-
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
-
MAX
1.60
0.15
1.45
0.27
0.23
9.10
7.10
9.10
7.10
0.75
NOTES
A
A1
A2
b
-
0.062
0.005
0.057
0.010
0.009
0.358
0.280
0.358
0.280
0.029
-
0.002
0.054
0.007
0.007
0.350
0.272
0.350
0.272
0.018
0.05
1.35
0.17
0.17
8.90
6.90
8.90
6.90
0.45
-
-
-A-
-B-
6
E
b1
D
-
E1
3
D1
E
4, 5
3
E1
L
4, 5
e
-
N
48
0.020 BSC
48
0.50 BSC
7
PIN 1
e
-
SEATING
PLANE
Rev. 2 1/99
-H-
A
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
0.08
0.003
-C-
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane -C- .
4. Dimensions D1 and E1 to be determined at datum plane
0.08
0.003
D
A-B
C
S
M
S
-H-
.
b
o
o
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
11 -13
0.020
b1
MIN
0.008
o
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed
the maximum b dimension by more than 0.08mm (0.003
inch).
0
MIN
0.09/0.16
0.004/0.006
A2
A1
GAGE
PLANE
BASE METAL
WITH PLATING
7. “N” is the number of terminal positions.
L
0.09/0.20
o
o
11 -13
0.25
0.010
0.004/0.008
o
o
0 -7
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4321.5
January 22, 2010
19
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HI5728INZ-T
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