HI5810JIB-T_技术文档

HI5810

TM

Data Sheet

May 2001

File Number 3633.3

CMOS 10 Microsecond, 12-Bit, Sampling

A/D Converter with Internal Track and

Hold

Features

• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µs

• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 100kSPS

• Built-In Track and Hold

The HI5810 is a fast, low power, 12-bit, successive-

approximation, analog-to-digital converter. It can operate

from a single 3V to 6V supply and typically draws just 1.9mA

when operating at 5V. The HI5810 features a built-in track

and hold. The conversion time is as low as 10µs with a 5V

supply.

itle

I581

• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .+5V

• Maximum Power Consumption . . . . . . . . . . . . . . . 40mW

• Internal or External Clock

b-

t

MO

0

cro-

-

• 1MHz Input Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . -3dB

The twelve data outputs feature full high speed CMOS

three-state bus driver capability, and are latched and held

through a full conversion cycle. The output is user

selectable: [i.e., 12-bit, 8-bit (MSBs), and/or 4-bit (LSBs)]. A

data ready flag, and conversion-start input complete the

digital interface.

Applications

• Remote Low Power Data Acquisition Systems

• Digital Audio

d,

-Bit,

m-

ng

D

n-

rter

th

• DSP Modems

An internal clock is provided and is available as an output.

The clock may also be over-driven by an external source.

• General Purpose DSP Front End

• µP Controlled Measurement Systems

• Process Controls

Part Number Information

INL (LSB)

(MAX OVER

TEMP.)

TEMP.

• Industrial Controls

PART

NUMBER

RANGE

PKG.

NO.

o

( C)

PACKAGE

er-

l

ck

d

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

HI5810JIB-T

2.5

-40 to 85 24 Ld SOIC

Tape and Reel

M24.3

ld)

utho

)

ey-

rds

ter-

Pinout

HI5810

(SOIC)

TOP VIEW

DRDY

(LSB) D0

D1

1

2

3

4

5

6

7

8

9

24

V

DD

23 OEL

22 CLK

21 STRT

rpo-

ion,

mi-

n-

ctor,

D,

D2

20

19

18

17

16

V

-

REF

D3

+

D4

REF

D5

V

IN

D6

V

+

AA

D7

V

-

AA

D8 10

D9 11

15 OEM

C,

14 D11 (MSB)

13 D10

sh,

V

12

SS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

HI5810

Functional Block Diagram

STRT

V

DD

TO INTERNAL LOGIC

V

SS

V

IN

CLK

CLOCK

CONTROL

AND

TIMING

DRDY

32C

OEM

V

+

REF

16C

8C

D11 (MSB)

50Ω

SUBSTRATE

D10

D9

4C

2C

V

+

AA

C

D8

V

-

32C

AA

64C

63

D7

16C

12-BIT

12-BIT EDGE

SUCCESSIVE

APPROXIMATION

REGISTER

D6

D5

D4

D3

TRIGGERED

“D” LATCHES

8C

4C

2C

C

P1

D2

D1

V

-

REF

D0 (LSB)

OEL

2

HI5810

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage

Thermal Resistance (Typical, Note 1)

θ

( C/W)

JA

V

to V

. . . . . . . . . . . . . . . . . . . . (V

-0.5V) < V

DD

< +6.5V

+6.5V)

DD

SS

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature

Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . .300 C

75

V

+ to V - . . . . . . . . . . . . . . . . . . . (V -0.5V) to (V

+ to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V

AA AA SS

SS

o

V

AA DD

o

Analog and Reference Inputs

+ V - . . . . . . . . (V -0.3V) < V

o

V

< (V

+0.3V)

IN, REF

,

REF SS

INA

DD

Digital I/O Pins . . . . . . . . . . . . . . . (V -0.3V) < V < (V

SS I/O

(SOIC - Lead Tips Only)

Operating Conditions

o

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Electrical Specifications

V

= V + = 5V, V

+ = +4.608V, V = V - = V

SS AA

- = GND, CLK = External 1.5MHz,

REF

DD

Unless Otherwise Specified

AA REF

o

25 C

-40 C TO 85 C

PARAMETER

MIN

TYP

MAX

MIN

MAX

TEST CONDITIONS

UNITS

ACCURACY

Resolution

12

-

12

-

Bits

LSB

Integral Linearity Error, INL (End Point)

Differential Linearity Error, DNL

2.5

2.0

3.5

2.5

2.0

3.5

2.5

-

Gain Error, FSE (Adjustable to Zero)

-

Offset Error, V

(Adjustable to Zero)

-

OS

DYNAMIC CHARACTERISTICS

Signal to Noise Ratio, SINAD

RMS Signal

f

= Internal Clock, f = 1kHz

IN

-

68.8

62.1

-

dB

S

= 1.5MHz, f = 1kHz

IN

RMS Noise + Distortion

Signal to Noise Ratio, SNR

RMS Signal

f

= Internal Clock, f = 1kHz

IN

70.5

63.2

dB

S

= 1.5MHz, f = 1kHz

IN

RMS Noise

Total Harmonic Distortion, THD

f

= Internal Clock, f = 1kHz

IN

-

-73.9

-68.4

-

dBc

S

= 1.5MHz, f = 1kHz

IN

Spurious Free Dynamic Range, SFDR

f

= Internal Clock, f = 1kHz

IN

75.4

69.2

dB

S

= 1.5MHz, f = 1kHz

IN

ANALOG INPUT

Input Current, Dynamic

Input Current, Static

Input Bandwidth -3dB

Reference Input Current

At V = V

+, 0V

-

125

0.6

1

150

-

150

µA

MHz

µA

W

IN REF

Conversion Stopped

10

-

10

-

160

420

380

20

-

Input Series Resistance, R

In Series with Input C

During Sample State

During Hold State

-

S

SAMPLE

HOLD

SAMPLE

Input Capacitance, C

-

pF

-

pF

3

HI5810

Electrical Specifications

V

= V + = 5V, V

+ = +4.608V, V = V - = V

- = GND, CLK = External 1.5MHz,

REF

DD

AA REF

SS

AA

Unless Otherwise Specified (Continued)

o

25 C

-40 C TO 85 C

PARAMETER

MIN

TYP

MAX

MIN

MAX

TEST CONDITIONS

UNITS

DIGITAL INPUTS OEL, OEM, STRT

High-Level Input Voltage, V

2.4

-

0.8

10

-

2.4

-

0.8

10

-

V

IH

Low-Level Input Voltage, V

-

IL

Input Leakage Current, I

Except CLK, V = 0V, 5V

IN

-

µA

pF

IL

Input Capacitance, C

10

IN

DIGITAL OUTPUTS

High-Level Output Voltage, V

I

= -400µA

4.6

-

0.4

10

-

4.6

-

0.4

10

-

V

OH

SOURCE

Low-Level Output Voltage, V

= 1.6mA

-

OL

SINK

Three-State Leakage, I

Except DRDY, V

Except DRDY

= 0V, 5V

OUT

-

µA

pF

OZ

Output Capacitance, C

20

OUT

CLOCK

High-Level Output Voltage, V

I

= -100µA (Note 2)

4

-

4

-

V

OH

SOURCE

Low-Level Output Voltage, V

Input Current

= 100µA (Note 2)

1

5

1

5

OL

SINK

CLK Only, V = 0V, 5V

IN

-

mA

TIMING

Conversion Time (t

(Includes Acquisition Time)

+ t

)

10

-

10

-

µs

CONV

ACQ

Clock Frequency

Internal Clock, (CLK = Open)

External CLK (Note 2)

(Note 2)

200

300

-

400

2.0

-

150

500

-

kHz

MHz

ns

0.05

-

Clock Pulse Width, t

, t

LOW HIGH

100

-

100

-

Aperture Delay, t APR

-

35

105

100

30

60

4

50

150

160

-

70

180

195

-

ns

D

Clock to Data Ready Delay, t DRDY

D1

(Note 2)

-

ns

Clock to Data Ready Delay, t DRDY

D2

(Note 2)

-

75

100

15

-

ns

Start Removal Time, t STRT

(Note 2)

75

85

10

-

ns

R

Start Setup Time, t STRT

SU

(Note 2)

-

ns

Start Pulse Width, t STRT

(Note 2)

-

ns

W

Start to Data Ready Delay, t DRDY

D3

(Note 2)

65

60

20

80

105

-

120

-

ns

Clock Delay from Start, t STRT

(Note 2)

-

ns

D

Output Enable Delay, t

(Note 2)

-

30

95

-

50

120

ns

EN

Output Disabled Delay, t

(Note 2)

-

ns

DIS

POWER SUPPLY CHARACTERISTICS

Supply Current, I

+ I

AA

-

2.6

8

-

8.5

mA

DD

NOTE:

2. Parameter guaranteed by design or characterization, not production tested.

4

HI5810

Timing Diagrams

5 - 14

4

15

1

3

1

2

3

CLK

(EXTERNAL

OR INTERNAL)

t

LOW

t

DRDY

D1

t

HIGH

STRT

DRDY

t

DRDY

D2

DATA N - 1

D0 - D11

DATA N

HOLD N

V

TRACK N

TRACK N + 1

IN

OEL = OEM = V

SS

FIGURE 1. CONTINUOUS CONVERSION MODE

2

3

15

2

4

1

5

CLK

(EXTERNAL)

t STRT

SU

t

STRT

R

t

STRT

W

STRT

t

DRDY

D3

DRDY

HOLD

TRACK

V

IN

FIGURE 2. SINGLE SHOT MODE EXTERNAL CLOCK

15

1

3

4

5

CLK

(INTERNAL)

2

t

STRT

D

t

STRT

R

t

STRT

W

STRT

DRDY

DON’T CARE

t

DRDY

D3

HOLD

TRACK

V

IN

FIGURE 3. SINGLE SHOT MODE INTERNAL CLOCK

5

HI5810

Timing Diagrams (Continued)

OEL OR OEM

t

DIS

EN

D0 - D3 OR

90%

10%

D4 - D11

50%

HIGH

IMPEDANCE

TO HIGH

TO

OUTPUT

HIGH

IMPEDANCE

50%

TO LOW

1.6mA

+2.1V

50pF

+2.1V

50pF

-400µA

-1.6mA

FIGURE 4. OUTPUT ENABLE/DISABLE TIMING DIAGRAM

FIGURE 5. TIMING LOAD CIRCUIT

Typical Performance Curves

1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.40

0.35

0.30

2.0

V

= V + = 5V, V

AA

+ = 4.608V, CLK = 1.5MHz

REF

DD

V

= V + = 5V, V

AA REF

+ = 4.608V, CLK = 1.5MHz

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

DD

0

-50 -40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90

o

-50 -40 -30 -20 -10

10 20 30 40 50 60 70 80 90

o

TEMPERATURE ( C)

FIGURE 6. NL vs TEMPERATURE

FIGURE 7. OFFSET ERROR vs TEMPERATURE

-1.0

-1.1

-1.2

-1.3

-1.4

-1.5

-1.6

-1.7

-1.8

-1.9

-2.0

-2.1

-2.2

-2.3

-2.4

-2.5

1.75

1.70

1.65

1.60

1.55

1.50

1.45

1.40

1.35

1.30

1.25

1.20

1.15

1.10

1.05

1.00

V

= V + = 5V, V

AA

+ = 4.608V, CLK = 1.5MHz

REF

V

= V + = 5V, V

AA

+ = 4.608V, CLK = 1.5MHz

REF

DD

-50 -40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90

o

-50 -40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90

o

TEMPERATURE ( C)

FIGURE 8. DNL vs TEMPERATURE

FIGURE 9. FULL SCALE ERROR vs TEMPERATURE

6

HI5810

Typical Performance Curves (Continued)

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

INPUT FREQUENCY = 1kHz

SAMPLING RATE = 100kHz

SNR = 64.92dB

SINAD = 63.82dB

EFFECTIVE BITS = 10.30

THD = -69.44dBc

PEAK NOISE = -70.1dB

SFDR = 70.1dB

-50 -40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90

o

FREQUENCY

TEMPERATURE ( C)

FIGURE 10. SUPPLY CURRENT vs TEMPERATURE

FIGURE 11. FFT SPECTRUM

500

V

= V + = 5V, V + = 4.608V

AA REF

DD

450

400

350

300

250

200

150

-60 -40 -20

0

20

40

60

80 100 120 140

o

TEMPERATURE ( C)

FIGURE 12. INTERNAL CLOCK FREQUENCY vs TEMPERATURE

7

HI5810

capacitors to V

-. The capacitor common node, after the

REF

TABLE 1. PIN DESCRIPTIONS

charges balance out, will indicate whether the input was

1

above

/

of (V

+ - V

-). At the end of the fourth

REF

PIN NO. NAME

DESCRIPTION

2

REF

period, the comparator output is stored and the MSB

capacitor is either left connected to V + (if the comparator

1

DRDY Output flag signifying new data is available.

Goes high at end of clock period 15. Goes low

when new conversion is started.

REF

was high) or returned to V

comparison to be at either / or / of (V

-. This allows the next

1

REF

3

+ - V

-).

2

3

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

Bit 0 (Least Significant Bit, LSB).

4

REF

Bit 1.

At the end of periods 5 through 14, capacitors representing

D10 through D1 are tested, the result stored, and each

4

Bit 2.

5

Bit 3.

capacitor either left at V

+ or at V

-.

REF

6

Bit 4.

At the end of the 15th period, when the LSB (D0) capacitor is

tested, (D0) and all the previous results are shifted to the

output registers and drivers. The capacitors are reconnected

to the input, the comparator returns to the balance state, and

the data ready output goes active. The conversion cycle is

now complete.

7

Bit 5.

8

Bit 6.

9

Bit 7.

10

11

12

13

14

15

Bit 8.

Bit 9.

V

Digital Ground, (0V).

Analog Input

SS

D10 Bit 10.

The analog input pin is a predominately capacitive load that

changes between the track and hold periods of the

conversion cycle. During hold, clock period 4 through 15, the

input loading is leakage and stray capacitance, typically less

than 5µA and 20pF.

D11 Bit 11 (Most Significant Bit, MSB)

OEM Three-State Enable for D4-D11. Active low

input.

16

17

18

19

V

-

Analog Ground, (0V).

AA

+

Analog Positive Supply. (+5V) (See text.)

Analog Input.

At the start of input tracking, clock period 1, some charge is

dumped back to the input pin. The input source must have low

enough impedance to dissipate the current spike by the end of

the tracking period as shown in Figure 13. The amount of

charge is dependent on supply and input voltages. The

average current is also proportional to clock frequency.

AA

V

IN

V

+

Reference Voltage Positive Input, sets 4095

code end of input range.

REF

20

21

22

V

-

Reference Voltage Negative Input, sets 0

code end of input range.

REF

STRT Start Conversion Input active low, recognized

after end of clock period 15.

CLK CLK Input or Output. Conversion functions are

synchronized to positive going edge (see text).

20mA

I

IN

10mA

0mA

23

24

OEL Three-State Enable for D0 D3. Active low input.

V

Digital Positive Supply (+5V).

DD

Theory of Operation

5V

The HI5810 is a CMOS 12-bit, Analog-to-Digital Converter

that uses capacitor charge balancing to successively

approximate the analog input. A binarily weighted capacitor

network forms the A/D heart of the device. See the block

diagram for the HI5810.

CLK

0V

5V

DRDY

0V

200ns/DIV.

The capacitor network has a common node which is

connected to a comparator. The second terminal of each

CONDITIONS: V

V

= V + = 5.0V, V + = 4.608V,

REF

DD

AA

= 4.608V, CLK = 750kHz, T = 25 C

o

IN

A

capacitor is individually switchable to the input, V

+ or

REF

FIGURE 13. TYPICAL ANALOG INPUT CURRENT

V

-.

REF

During the first three clock periods of a conversion cycle, the

switchable end of every capacitor is connected to the input

and the comparator is being auto balanced at the capacitor

common node.

As long as these current spikes settle completely by end of

the signal acquisition period, converter accuracy will be

preserved. The analog input is tracked for 3 clock cycles.

With an external clock of 1.5MHz the track period is 2µs.

During the fourth period, all capacitors are disconnected

from the input; the one representing the MSB (D11) is

A simplified analog input model is presented in Figure 14.

During tracking, the A/D input (V ) typically appears as a

IN

connected to the V

+ terminal; and the remaining

380pF capacitor being charged through a 420Ω internal

REF

8

HI5810

switch resistance. The time constant is 160ns. To charge this

capacitor from an external “zero Ω” source to 0.5 LSB

(1/8192), the charging time must be at least 9 time constants

accuracy is of utmost importance full scale and offset errors

may be adjusted to zero.

The V

REF

+ and V - pins reference the two ends of the

REF

or 1.4µs. The maximum source impedance (R

Max)

SOURCE

analog input range and may be used for offset and full scale

for a 2µs acquisition time settling to within 0.5 LSB is 164Ω.

adjustments. In a typical system the V - might be returned

REF

to a clean ground, and the offset adjustment done on an input

amplifier. V + would then be adjusted to null out the full

If the clock frequency was slower, or the converter was not

restarted immediately (causing a longer sample time), a

higher source impedance could be tolerated.

REF

scale error. When this is not possible, the V

- input can be

REF

- must be well

adjusted to null the offset error, however, V

decoupled.

REF

V

IN

R

_SW≈ 420Ω

C

_SAMPLE≈ 380pF

Full scale and offset error can also be adjusted to zero in the

R

SOURCE

signal conditioning amplifier driving the analog input (V ).

IN

-t

ACQ

ln [2

- R

R

=

C

SW

SOURCE (MAX)

-(N + 1)

Control Signal

]

SAMPLE

The HI5810 may be synchronized from an external source

by using the STRT (Start Conversion) input to initiate

conversion, or if STRT is tied low, may be allowed to free

run. Each conversion cycle takes 15 clock periods.

FIGURE 14. ANALOG INPUT MODEL IN TRACK MODE

Reference Input

The reference input V

+ should be driven from a low

REF

impedance source and be well decoupled.

The input is tracked from clock period 1 through period 3,

then disconnected as the successive approximation takes

As shown in Figure 15, current spikes are generated on the

reference pin during each bit test of the successive

approximation part of the conversion cycle as the charge

place. After the start of the next period 1 (specified by t

D

data), the output is updated.

balancing capacitors are switched between V

- and

REF

The DRDY (Data Ready) status output goes high (specified

V

+ (clock periods 5 - 14). These current spikes must

REF

settle completely during each bit test of the conversion to not

degrade the accuracy of the converter. Therefore V

by t DRDY) after the start of clock period 1, and returns

D1

low (specified by t DRDY) after the start of clock period 2.

D2

+

-

REF

- should be well bypassed. Reference input V

The 12 data bits are available in parallel on three-state bus

driver outputs. When low, the OEM input enables the most

significant byte (D4 through D11) while the OEL input

and V

REF

is normally connected directly to the analog ground plane. If

- is biased for nulling the converters offset it must be

V

REF

enables the four least significant bits (D0 - D3). t

specify the output enable and disable times.

and t

DIS

stable during the conversion cycle.

EN

If the output data is to be latched externally, either the trailing

edge of data ready or the next falling edge of the clock after

data ready goes high can be used.

20mA

I

+

10mA

0mA

REF

When STRT input is used to initiate conversions, operation is

slightly different depending on whether an internal or

external clock is used.

Figure 3 illustrates operation with an internal clock. If the

5V

0V

CLK

STRT signal is removed (at least t STRT) before clock

R

period 1, and is not reapplied during that period, the clock

will shut off after entering period 2. The input will continue to

track and the DRDY output will remain high during this time.

5V

0V

DRDY

2µs/DIV.

A low signal applied to STRT (at least t STRT wide) can

W

now initiate a new conversion. The STRT signal (after a

delay of (t STRT)) causes the clock to restart.

D

CONDITIONS: V

= V + = 5.0V, V

+ = 4.608V,

o

DD

AA REF

V

= 2.3V, CLK = 750kHz, T = 25 C

A

IN

FIGURE 15. TYPICAL REFERENCE INPUT CURRENT

Depending on how long the clock was shut off, the low

portion of clock period 2 may be longer than during the

remaining cycles.

The HI5810 is specified with a 4.608V reference, however, it

will operate with a reference down to 3V having a slight

degradation in performance.

The input will continue to track until the end of period 3, the

same as when free running.

Full Scale and Offset Adjustment

In many applications the accuracy of the HI5810 would be

sufficient without any adjustments. In applications where

9

HI5810

Figure 2 illustrates the same operation as above but with an

Except for V +, which is a substrate connection to V , all

AA DD

external clock. If STRT is removed (at least t STRT) before

pins have protection diodes connected to V

and V

.

R

DD

SS

clock period 2, a low signal applied to STRT will drop the

DRDY flag as before, and with the first positive going clock

Input transients above V

the digital supplies.

or below V will get steered to

SS

DD

edge that meets the (t STRT) setup time, the converter will

continue with clock period 3.

SU

The V + and V - terminals supply the charge balancing

AA AA

comparator only. Because the comparator is autobalanced

between conversions, it has good low frequency supply

rejection. It does not reject well at high frequencies however;

Clock

The HI5810 can operate either from its internal clock or from

one externally supplied. The CLK pin functions either as the

clock output or input. All converter functions are

V

- should be returned to a clean analog ground and V +

AA AA

should be RC decoupled from the digital supply as shown in

Figure 17.

synchronized with the rising edge of the clock signal.

There is approximately 50Ω of substrate impedance

Figure 16 shows the configuration of the internal clock. The

clock output drive is low power: if used as an output, it

should not have more than 1 CMOS gate load applied, and

stray wiring capacitance should be kept to a minimum.

between V

and V +. This can be used, for example, as

DD

part of a low pass RC filter to attenuate switching supply

AA

noise. A 10µF capacitor from V + to ground would

AA

attenuate 30kHz noise by approximately 40dB. Note that

The internal clock will shut down if the A/D is not restarted

after a conversion. The clock could also be shut down with

an open collector driver applied to the CLK pin. This should

only be done during the sample portion (the first three clock

periods) of a conversion cycle, and might be useful for using

the device as a digital sample and hold.

back-to-back diodes should be placed from V

handle supply to capacitor turn-on or turn-off current spikes.

to V + to

DD

AA

Dynamic Performance

Fast Fourier Transform (FFT) techniques are used to

evaluate the dynamic performance of the A/D. A low

distortion sine wave is applied to the input of the A/D

converter. The input is sampled by the A/D and its output

stored in RAM. The data is than transformed into the

frequency domain with a 4096 point FFT and analyzed to

evaluate the converters dynamic performance such as SNR

and THD. See Typical Performance Characteristics.

If an external clock is supplied to the CLK pin, it must have

sufficient drive to overcome the internal clock source. The

external clock can be shut off, but again, only during the

sample portion of a conversion cycle. At other times, it must

be above the minimum frequency shown in the

specifications. In the above two cases, a further restriction

applies in that the clock should not be shut off during the

third sample period for more than 1ms. This might cause an

internal charge pump voltage to decay.

Signal-To-Noise Ratio

The signal to noise ratio (SNR) is the measured RMS signal to

RMS sum of noise at a specified input and sampling frequency.

The noise is the RMS sum of all except the fundamental and

the first five harmonic signals. The SNR is dependent on the

number of quantization levels used in the converter. The

theoretical SNR for an N-bit converter with no differential or

integral linearity error is: SNR = (6.02N + 1.76)dB. For an ideal

12-bit converter the SNR is 74dB. Differential and integral

linearity errors will degrade SNR.

If the internal or external clock was shut off during the

conversion time (clock cycles 4 through 15) of the A/D, the

output might be invalid due to balancing capacitor droop.

An external clock must also meet the minimum t

and

LOW

times shown in the specifications. A violation may

t

HIGH

cause an internal miscount and invalidate the results.

Sinewave Signal Power

SNR = 10 Log

INTERNAL

ENABLE

Total Noise Power

CLOCK

CLK

Signal-To-Noise + Distortion Ratio

OPTIONAL

EXTERNAL

CLOCK

SINAD is the measured RMS signal to RMS sum of noise

plus harmonic power and is expressed by the following.

100kΩ

18pF

Sinewave Signal Power

SINAD = 10 Log

FIGURE 16. INTERNAL CLOCK CIRCUITRY

Noise + Harmonic Power (2nd - 6th)

Power Supplies and Grounding

Effective Number of Bits

V

and V are the digital supply pins: they power all

DD

SS

internal logic and the output drivers. Because the output

drivers can cause fast current spikes in the V and V

The effective number of bits (ENOB) is derived from the

SINAD data;

DD

SS

lines, V should have a low impedance path to digital

SS

ground and V

SINAD - 1.76

should be well bypassed.

DD

ENOB =

6.02

10

HI5810

Total Harmonic Distortion

Spurious-Free Dynamic Range

The total harmonic distortion (THD) is the ratio of the RMS

sum of the second through sixth harmonic components to

the fundamental RMS signal for a specified input and

sampling frequency.

The spurious-free dynamic range (SFDR) is the ratio of the

fundamental RMS amplitude to the RMS amplitude of the

next largest spur or spectral component. If the harmonics

are buried in the noise floor it is the largest peak.

Total Harmonic Power (2nd - 6th Harmonic)

THD = 10Log

Sinewave Signal Power

SFDR = 10Log

Sinewave Signal Power

Highest Spurious Signal Power

TABLE 2. CODE TABLE

BINARY OUTPUT CODE

INPUT VOLTAGE†

+ = 4.608V

MSB

LSB

D0

1

CODE

DESCRIPTION

V

DECIMAL

COUNT

REF

V

- = 0V (V)

D11

1

D10

1

D9

1

D8

1

D7

1

D6

1

D5

1

D4

1

D3

1

D2

1

D1

1

REF

Full Scale (FS)

4.6069

4.6058

3.4560

2.3040

1.1520

0.001125

0

4095

4094

3072

2048

1024

1

FS - 1 LSB

3

1

0

/

FS

1

0

4

2

4

1

0

1

0

1 LSB

Zero

0

1

0

†The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage.

+5V

0.1µF

4.7µF

10µF

0.1µF

0.01µF

V

+

V

DD

AA

D11

.

OUTPUT

DATA

D0

V

REF

V

+

REF

0.001µF

4.7µF

DRDY

OEM

OEL

ANALOG

INPUT

V

IN

STRT

CLK

1.5MHz CLOCK

-

V

-

V

SS

REF

AA

FIGURE 17. GROUND AND SUPPLY DECOUPLING

11

HI5810

Die Characteristics

DIE DIMENSIONS

PASSIVATION

3200µm x 3940µm

Type: PSG

Thickness: 13kÅ 2.5kÅ

METALLIZATION

WORST CASE CURRENT DENSITY

Type: AlSi

Thickness: 11kÅ 1kÅ

5

2

1.84 x 10 A/cm

Metallization Mask Layout

HI5810

DRDY

D0

(LSB)

D1

V

OEL

DD

CLK

D2

D3

STRT

V

-

REF

D4

D5

D6

V

+

REF

D7

D8

V

IN

V

+

-

AA

V

AA

D9

V

D10

D11

(MSB)

OEM

SS

12

HI5810

Small Outline Plastic Packages (SOIC)

M24.3 (JEDEC MS-013-AD ISSUE C)

N

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES

MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

2.35

0.10

0.33

0.23

MAX

2.65

0.30

0.51

0.32

15.60

7.60

NOTES

-B-

A

A1

B

C

D

E

e

0.0926

0.0040

0.013

0.1043

0.0118

0.020

-

1

2

3

L

9

SEATING PLANE

A

0.0091

0.5985

0.2914

0.0125

-

-A-

o

0.6141 15.20

3

h x 45

D

0.2992

7.40

4

-C-

0.05 BSC

1.27 BSC

-

α

µ

H

h

0.394

0.010

0.016

0.419

0.029

0.050

10.00

0.25

0.40

10.65

0.75

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C A M B S

N

α

24

7

o

0

8

0

8

-

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 0 12/93

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality/iso.asp.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.

Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-

ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.

No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation

2401 Palm Bay Rd.

Palm Bay, FL 32905

TEL: (321) 724-7000

FAX: (321) 724-7240

EUROPE

Intersil SA

Mercure Center

100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111

FAX: (32) 2.724.22.05

ASIA

Intersil Ltd.

8F-2, 96, Sec. 1, Chien-kuo North,

Taipei, Taiwan 104

Republic of China

TEL: 886-2-2515-8508

FAX: 886-2-2515-8369

13


型号：	HI5810JIB-T
厂家：	Intersil
描述：	CMOS 10 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold CMOS 10微秒， 12位，采样A / D转换器，内置跟踪保持转换器
文件：	总13页 (文件大小：763K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HI5810JIB-T [INTERSIL]

相关型号：

HI5810JIJ

HI5810JIP

HI5810KIB

HI5810KIJ

HI5810KIP

HI5810_01

HI5812

HI5812JIB

HI5812JIBZ

HI5812JIJ

HI5812JIP

HI5812JIPZ