HS-139EH [INTERSIL]
Radiation Hardened Quad Voltage Comparator; 抗辐射四路电压比较器
| 型号： | HS-139EH |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened Quad Voltage Comparator |
| 文件： | 总3页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Radiation Hardened Quad Voltage Comparator
HS-139RH, HS-139EH
Features
The Radiation Hardened HS-139RH, HS-139EH consists of four
independent single or dual supply voltage comparators on a
single monolithic substrate. The common mode input voltage
range includes ground, even when operated from a single
supply and the low supply current makes these comparators
suitable for low power applications. These types were designed
to directly interface with TTL and CMOS.
• QML Qualified Per MIL-PRF-38535 Requirements
• Radiation Environment
- Latch-up Free Under any Conditions
5
- Total Dose (Max). . . . . . . . . . . . . . . . . . . . . . 3 x 10 RAD(Si)
2
- SEU LET Threshold . . . . . . . . . . . . . . . . . . . 20MeV/cm /mg
- Low Dose Rate Effects Immunity
The HS-139RH, HS-139EH is fabricated on our dielectrically
isolated Rad Hard Silicon Gate (RSG) process, which provides
an immunity to Single Event Latch-up and the capability of
highly reliable performance in any radiation environment.
• 100V Output Voltage Withstand Capability
• ESD Protection to >3000V
• Differential Input Voltage Range Equal to the Supply Voltage
• Input Offset Voltage (V ) . . . . . . . . . . . . . . . . . . . . 2mV (Max)
IO
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed below must be used when ordering.
• Quiescent Supply Current . . . . . . . . . . . . . . . . . . . . 2mA (Max)
• Pb-Free (RoHS Compliant)
Detailed Electrical Specifications for the HS-139RH, HS-139EH
are contained in SMD 5962-98613. A “hot-link” is provided on
our homepage with instructions for downloading.
Applications
• Pulse Generators
www.intersil.com/spacedefense/newsafclasst.asp
• Timing Circuitry
• Level Shifting
• Analog-to-Digital Conversion
Ordering Information
ORDERING NUMBER
INTERNAL
MKT. NUMBER
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PACKAGE
DRAWING NUMBER
(Note)
5962F9861303VCC
5962F9861301VCC
5962F9861301QCC
HS1-139RH/PROTO
5962F9861301VXC
5962F9861301QXC
5962F9861302VXC
HS9-139RH/PROTO
HS1-139EH-Q
Q 5962F98 61303VCC
Q 5962F98 61301VCC
Q 5962F98 61301QCC
HS1-139RH/PROTO
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
14 Ld SBDIP
D14.3
HS1-139RH-Q
14 Ld SBDIP
D14.3
D14.3
D14.3
K14.A
K14.A
K14.A
K14.A
HS1-139RH-8
14 Ld SBDIP
HS1-139RH/PROTO
HS9-139RH-Q
14 Ld SBDIP
Q 5962F98 61301VXC
Q 5962F98 61301QXC
Q 5962F98 61302VXC
HS9-139RH /PROTO
14 Ld FLATPACK
14 Ld FLATPACK
14 Ld FLATPACK
14 Ld FLATPACK
HS9-139RH-8
HS9-139EH-Q
HS9-139RH/PROTO
NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
July 12, 2012
FN3573.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 1999, 2004, 2008, 2009, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
1
All other trademarks mentioned are the property of their respective owners.
HS-139RH, HS-139EH
Pin Configurations
s
HS-139RH, HS-139EH
HS-139RH, HS-139EH
(FLATPACK CDFP3-F14)
TOP VIEW
(SBDIP CDIP2-T14)
TOP VIEW
OUT 2
OUT 1
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT 3
OUT 4
GND
OUT 2
OUT 1
V+
1
2
3
4
5
6
7
14 OUT 3
13 OUT 4
V+
- IN 1
+ IN 1
- IN 2
+IN 2
12 GND
11 + IN 4
10 - IN 4
+ IN 4
- IN 4
+ IN 3
- IN 3
- IN 1
+ IN 1
- IN 2
+ IN 2
8
9
8
+ IN 3
- IN 3
Die Characteristics
DIE DIMENSIONS:
Backside Finish:
3750µm x 2820µm (148 mils x 111 mils)
Silicon
483µm ±25.4µm (19 mils ±1 mil)
ASSEMBLY RELATED INFORMATION:
INTERFACE MATERIALS:
Glassivation:
Substrate Potential:
Unbiased (DI)
Type: Silox (SiO )
2
Thickness: 8.0kÅ ±1.0kÅ
ADDITIONAL INFORMATION:
Worst Case Current Density:
Top Metallization:
5
2
<2.0 x 10 A/cm
Type: AlSiCu
Transistor Count:
Thickness: 16.0kÅ ±2kÅ
49
Substrate:
Radiation Hardened Silicon Gate, Dielectric Isolation
FN3573.5
July 12, 2012
2
HS-139RH, HS-139EH
Metallization Mask Layout
HS-139RH, HS-139EH
GND
+IN4
-IN4
(10)
(12)
(11)
OUT4
(13)
+IN3
(9)
OUT3
(14)
-IN3
(8)
+IN2
(7)
OUT2
(1)
-IN2
(6)
OUT1
(2)
V+
(3)
-IN1
(4)
+IN1
(5)
TABLE 1. HS-139RH, HS-139EH PAD COORDINATES
RELATIVE TO PIN 1
X
Y
PIN NUMBER
PAD NAME
OUT 2
OUT 1
V+
COORDINATES
COORDINATES
1
2
0
0
0
-535
3
1323
1862
2439
3084
3084
3084
3084
2439
1862
1550
0
-688
4
-IN 1
-670
5
+IN 1
-IN 2
-670
6
-299
7
+IN 2
-IN 3
278
8
518
9
+IN 3
-IN 4
1095
1466
1466
1503
1331
796
10
11
12
13
14
+IN 4
GND
OUT 4
OUT 3
0
NOTE: Dimensions in microns
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3573.5
July 12, 2012
3
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