HS-3282 [INTERSIL]
CMOS ARINC Bus Interface Circuit; CMOS ARINC总线接口电路型号: | HS-3282 |
厂家: | Intersil |
描述: | CMOS ARINC Bus Interface Circuit |
文件: | 总15页 (文件大小:179K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HS-3282
REFERENCE AN400
March 1997
CMOS ARINC Bus Interface Circuit
Features
Description
• ARlNC Specification 429 Compatible
• Data Rates of 100 Kilobits or 12.5 Kilobits
• Separate Receiver and Transmitter Section
The HS-3282 is a high performance CMOS bus interface
circuit that is intended to meet the requirements of ARINC
Specification 429, and similar encoded, time multiplexed
serial data protocols. This device is intended to be used with
the HS-3182, a monolithic Dl bipolar differential line driver
designed to meet the specifications of ARINC 429. The
ARINC 429 bus interface circuit consists of two (2) receivers
and a transmitter operating independently as shown in
Figure 1. The two receivers operate at a frequency that is ten
(10) times the receiver data rate, which can be the same or
different from the transmitter data rate. Although the two
receivers operate at the same frequency, they are
functionally independent and each receives serial data asyn-
chronously. The transmitter section of the ARINC bus
interface circuit consists mainly of a First-In First-Out (FIFO)
memory and timing circuit. The FIFO memory is used to hold
up to eight (8) ARINC data words for transmission serially.
The timing circuit is used to correctly separate each ARINC
word as required by ARINC Specification 429. Even though
ARINC Specification 429 specifies a 32-bit word, including
parity, the HS-3282 can be programmed to also operate with
a word length of 25 bits. The incoming receiver data word
parity is checked, and a parity status is stored in the receiver
latch and output on Pin BD08 during the 1st word. [A logic
“0” indicates that an odd number of logic “1” s were received
and stored; a logic “1” indicates that an even number of logic
“1”s were received and stored]. In the transmitter the parity
generator will generate either odd or even parity depending
upon the status of PARCK control signal. A logic “0” on BD12
will cause odd parity to be used in the output data stream.
• Dual and Independent Receivers, Connecting Directly
to ARINC Bus
• Serial to Parallel Receiver Data Conversion
• Parallel to Serial Transmitter Data Conversion
• Word Lengths of 25 or 32 Bits
• Parity Status of Received Data
• Generate Parity of Transmitter Data
• Automatic Word Gap Timer
• Single 5V Supply
• Low Power Dissipation
• Full Military Temperature Range
Ordering Information
PKG.
NO.
PACKAGE
CERDIP
SMD#
TEMP. RANGE
PART NUMBER
o
o
-55 C to +125 C HS1-3282-8
F40.6
5962-8688001QA F40.6
o
o
CLCC
-40 C to +85 C HS4-3282-9+
J44.A
J44.A
o
o
-55 C to +125 C HS4-3282-8
SMD#
5962-8688001XA J44.A
Versatility is provided in both the transmitter and receiver by
the external clock input which allows the bus interface circuit
to operate at data rates from 0 to 100 kilobits. The external
clock must be ten (10) times the data rate to insure no data
ambiguity.
The ARINC bus interface circuit is fully guaranteed to
support the data rates of ARINC specification 429 over both
the voltage (±5%) and full military temperature range. It
interfaces with UL, CMOS or NMOS support circuitry, and
uses the standard 5-volt V
supply.
CC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2964.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19959-183
HS-3282
Pinouts
HS-3282 (CERDIP)
TOP VIEW
V
1
2
3
4
5
6
7
8
9
40 NC
DD
429DI1(A)
429DI1(B)
429DI2(A)
429DI2(B)
D/R1
39 MR
38 TX CLK
37 CLK
36 NC
35 NC
D/R2
34 CWSTR
33 ENTX
32 429D0
31 429D0
30 TX/R
29 PL2
SEL
EN1
EN2 10
BD15 11
BD14 12
BD13 13
BD12 14
BD11 15
BD10 16
BD09 17
BD08 18
BD07 19
BD06 20
28 PL1
27 BD00
26 BD01
25 BD02
24 BD03
23 BD04
22 BD05
21 GND
HS-3282 (CLCC)
TOP VIEW
44
43 42 41 40
6
5
4
3
2
1
7
39
38
NC
D/R1
D/R2
NC
NC
8
9
37 CWSTR
10
11
12
ENTX
429D0
429D0
TX/R
PL2
SEL
EN1
36
35
34
33
32
31
30
29
EN2
BD15 13
14
BD14
15
PL1
BD13
BD12 16
BD11
BD00
BD01
17
18 19 20 21 22 23 24 25 26 27 28
5-184
HS-3282
Pin Description
PIN
1
SYMBOL
SECTION
Recs/Trans
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Recs/Trans
DESCRIPTION
V
Supply pin 5 volts ±5%.
CC
2
429 DI1 (A)
429 DI1 (B)
429 Dl2 (A)
429 DI2 (B)
D/R1
ARlNC 429 data input to Receiver 1.
ARlNC 429 data input to Receiver 1.
ARINC 429 data input to Receiver 2.
ARINC 429 data input to Receiver 2.
3
4
5
6
Device ready flag output from Receiver 1 indicating a valid data word is ready to be fetched.
Device ready flag output from Receiver 2 indicating a valid data word is ready to be fetched.
Bus Data Selector - Input signal to select one of two 16-bit words from either Receiver 1 or 2.
Input signal to enable data from Receiver 1 onto the data bus.
7
D/R2
8
SEL
9
EN1
10
11
EN2
Input signal to enable data from Receiver 2 onto the data bus.
BD15
Bi-directional data bus for fetching data from either of the Receivers, or for loading data into
the Transmitter memory or control word register. See Control Word Table for description of
Control Word bits.
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
GND
BD05
BD04
BD03
BD02
BD01
BD00
PL1
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Transmitter
Transmitter
See Pin 11.
See Pin 11.
See Pin 11.
See Pin 11.
See Pin 11.
See Pin 11.
See Pin 11.
See Pin 11.
See Pin 11.
Circuit Ground.
See Pin 11.
See Pin 11. Control Word function not applicable.
See Pin 11. Control Word function not applicable.
See Pin 11. Control Word function not applicable.
See Pin 11. Control Word function not applicable.
See Pin 11. Control Word function not applicable.
Parallel load input signal loading the first 16-bit word into the Transmitter memory.
PL2
Parallel load input signal loading the first 16-bit word into the Transmitter memory and initiates
data transfer into the memory stack.
30
TX/R
Transmitter
Transmitter flag output to indicate the memory is empty.
5-185
HS-3282
Pin Description (Continued)
PIN
31
32
33
34
SYMBOL
429D0
SECTION
Transmitter
Transmitter
Transmitter
Recs/Trans
DESCRIPTION
Data output from Transmitter
Data output from Transmitter.
429D0
ENTX
Transmitter Enable input signal to initiate data transmission from FIFO memory.
CWSTR
Control word input strobe signal to latch the control word from the databus into the control
word register.
35
36
37
-
-
-
No connection. Must be left open.
-
No connection. Must be left open or tied low but never tied high.
CLK
Recs/Trans
External clock input. May be either ten (10) or eighty (80) times the data rate. If using both
ARINC data rates it must be ten (10) times the highest data rate, (typically 1MHz).
38
39
TXCLK
MR
Transmitter
Recs/Trans
Transmitter Clock output. Delivers a clock frequency equal to the transmitter data rate.
Master Reset. Active low pulse used to reset FIFO, bit counters, gap timer, word count signal,
TX/R and various other flags and controls. Master reset does not reset the control word
register. Usually only used on Power-Up or System Reset.
40
-
-
No Connection.
Pinout
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC NC NC
5-186
HS-3282
Operational Description
The HS-3282 is designed to support ARINC Specification Provisions have been made through the external clock input
429 and other serial data protocols that use a similar format to provide data rate flexibility. This requires an external clock
by collecting the receiving, transmitting, synchronizing, that is 10 times the data rate.
timing and parity functions on a single, low power LSl circuit.
To obtain the flexibility discussed above, a number of
It goes beyond the ARlNC requirements by providing for
external control signals are required, To reduce the pin count
either odd or even parity, and giving the user a choice of
requirements, an internal control word register is used. The
either 25 or 32-bit word lengths. The receiver and transmitter
control word is latched from the data bus into the register by
sections operate independently of each other. The serial-to-
the Control Word Strobe (CWSTR) signal going to a logic
parallel conversion required of the receiver and the parallel-
“1”. Eleven (11) control functions are used, and along with
to-serial conversion requirements of the transmitter have
the Bus Data (BD) line are listed below:
been incorporated into the bus interface circuit.
Control Word
PIN NAME SYMBOL
FUNCTION
BD05
SLFTST
Connects the self test signal from the transmitter directly to the receiver shift registers, bypassing the input
receivers. Receiver 1 receives Data True and Receiver 2 receives Data Not. Note that the transmitter output
remains active. (Logic “0” on SLFTST Enables Self Test).
BD06
BD07
SDENB1 Signal to Activate the Source/Destination (S/D) Decoder for Receiver 1. (Logic “1” activates S/D Decoder).
X1
If SDENB1 = “1” then this bit is compared with ARlNC Data Bit #9. If Y1 also matches (see Y1), the word will be
accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care.
BD08
Y1
If SDENBI = “1” then this bit is compared with ARINC Data Bit #10. If X1 also matches (see X1), the word will
be accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care.
BD09
BD10
SDENB2 Signal to activate the Source/Destination (S/D) Decoder for Receiver 2. (Logic “1” activates S/D Decoder).
X2
If SDENB2 = “1” then this bit is compared with ARlNC Data Bit #9. If Y2 also matches (see Y2), the word will be
accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care.
BD11
BD12
BD13
BD14
Y2
If SDENB2 = “1” then this bit is compared with ARINC Data Bit #10. If X2 also matches (see X2), the word will
be accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care.
PARCK
TXSEL
Signal used to invert the transmitter parity bit for test of parity circuits. Logic “0” selects normal odd parity. Logic
“I” selects even parity.
Selects high or low Transmitter data rate. If TXSEL = “0” then transmitter data rate is equal to the clock rate
divided by ten (10). If TXSEL = “1” then transmitter data rate is equal to the clock rate divided by eighty (80).
RCVSEL Selects high or low Receiver data rate. If RCVSEL = “0” then the received data rate should be equal to the clock
rate divided by ten (10), if RCVSEL = “1 “then the received data rate should be equal to the clock rate divided
by eighty (80).
BD15
WLSEL
Selects word length. If WLSEL = “0” a 32-bit word format will be selected. If WLSEL = “1” a 25-Bit word format
will be selected.
ARlNC 429 DATA FORMAT as input to the Receiver and out- This format is shuffled when seen on the sixteen bidirec-
put from the Transmitter is as follows:
tional input/outputs. The format shown below is used from
the receivers and input to the transmitter:
TABLE 1. ARINC 429 32-BIT DATA FORMAT
TABLE 2A. WORD 1 FORMAT
ARINC BIT #
1 - 8
FUNCTION
Label
BI-DIRECTIONAL
BIT #
15, 14
13
FUNCTION
Data
ARINC BlT #
13, 12
11
9 - 10
11
SDl or Data
LSB
LSB
12 - 27
28
Data
12, 11
10, 9
8
SDl or Data
SSM Status
Parity Status
Label
10, 9
MSB
31, 30
32
29
Sign
30, 31
32
SSM
7 - 00
1 - 8
Parity Status
5-187
HS-3282
• The Line Receiver functions as a voltage level translator.
It transforms the 10 volt differential line voltage, ARINC
429 format, into 5 volt internal logic level.
TABLE 2B. WORD 2 FORMAT
BI-DIRECTIONAL
BlT#
FUNCTION
ARINC BIT#
• The output of the Line Receiver is one of two inputs to the
Self-Test Data Selector (SEL). The other input to the
Data Selector is the Self-Test Signal from the Transmitter
section.
15
Sign
29
28
14
MSB
13 - 00
Data
27 - 14
• The incoming data, either Self-Test or ARlNC 429, is
double sampled by the Word Gap Timer to generate a
Data Clock. The Receiver sample frequency (RCVCLK),
1MHz, or 125kHz, is generated by the Receiver/Transmit-
ter Timing Circuit. This sampling frequency is ten times the
Data Rate to ensure no data ambiguity.
Receiver Parity Status:
0 = Odd Parity
1 = Even Parity
If the receiver input data word string is broken before the
entire data word is received, the receiver will reset and
ignore the partially received data word.
• The derived data clock then shifts the data down a 32-Bit
long Data Shift Register (Data S/RI). The Data Word
Length is selectable for either 25 Bits or 32 Bits long by the
Control Signal (WLSEL). As soon as the data word is
completely received, an internal signal (WDCNT1) is gen-
erated by the Word Gap Timer Circuit.
If the transmitter is used to transmit consecutive data words,
each word will be separated by a four (4) bit “null” state (both
positive and negative outputs will maintain a zero (0) volt
level.)
• The Source/Destination (S/D) Decoder compares the user
set code (X and Y) with Bits 9 and 10 of the Data Word. If
the two codes are matched, a positive signal is generated
to enable the WDCNT1 signal to latch in the received data.
Otherwise, the data word is ignored and no latching action
takes place. The S/D Decoder can be Enabled and
Disabled by the control signal S/D ENB. If the data word is
latched, an indicator flag (D/R1) is set. This indicates a
valid data word is ready to be fetched by the user.
TABLE 3. ARINC 25-BIT DATA FORMAT
ARINC BIT #
FUNCTION
Label
1 - 8
9
LSB
11 - 23
24
Data
MSB
25
Parity Status
• After the receiver data has been shifted down the shift
register, it is placed in a holding register. The device ready
flag will then be set indicating that data is ready to be
fetched. If the data is ignored and left in the holding regis-
ter, it will be written over when the next data word is
received.
TABLE 4A. WORD 1 FORMAT
BI-DIRECTIONAL
BIT#
FUNCTION
Don’t Care
Parity Status
Label
ARINC BIT#
15 - 9
8
XXX
25
• The received data in the 32-bit holding register is placed
on the bus in the form of two (2)16-bit words regardless of
whether the format is for 32 or 25-bit data words. Either
word can be accessed first or repeatedly until the next
received data word falls into the holding register.
7 - 0
1 - 8
TABLE 4B. WORD 2 FORMAT
BI-DIRECTIONAL
• The parity of the incoming word is checked and the status
(i.e., logic “0” for odd parity and logic “1” for even parity)
stored in the receiver latch and output on BD08 during the
Word No. 1.
BIT#
FUNCTION
ARINC BlT#
15
MSB
24
23 -10
9
14 - 1
0
Data
LSB
• Assuming the user desires to access the data, he first sets
the Data Select Line (SEL) to a Logic “0” level and pulses
the Enable (EN1) line. This action causes the Data
Selector (SELl) to select the first-data word, which con-
tains the label field and Enable it onto the Data Bus. To
obtain the second data word, the user sets the SEL line to
a Logic “1” level and pulse the Enable (EN1) line again.
The Enable pulse duration is matched to the user circuit
requirement needed to read the Data Word from the Data
Bus. The second Enable pulse is also used to reset the
Device Ready (D/R1) flip-flop. This completes a receiving
cycle.
Receiver Parity Status:
0 = Odd Parity
1 = Even Parity
No Source/Destination (S/D) in 25-Bit format.
Receiver Operation
Since the two receivers are functionally identical, only one
will be discussed in detail, and the block diagram will be
used for reference in this discussion. The receiver consists
of the following circuits:
5-188
HS-3282
Transmitter Operation
Sample Interface Technique
The Transmitter section consists of an 8-word deep by 31- From Figure 1, one can see that the Data Bus is time shared
Bit long FIFO Memory, Parity Generator, Transmitter Word between the Receiver and Transmitter. Therefore, bus
Gap Timing Circuit and Driver Circuit.
controlling must be synchronously shared between the
Receiver and the Transmitter.
• The FlFO Memory is organized in such a way that data
loaded in the input register is automatically transferred to Figure 2 shows the typical interface timing control of the
the output register for Serial Data Transmission. This ARlNC Chip for Receiving function and for Transmitting
eliminates a large amount of data managing time since the function. Timing sequence for loading the Transmitter FIFO
data need not be clocked from the input register to the Memory is shown in Timing Interval A. A transmitter Ready
output register. The FIFO input register is made up of two (TX/R) Flag signals the user that the Transmitter Memory is
sets of 16 D-type flip-flops, which are clocked by the two empty. The user then Enables the Transmitter Data, a 16-Bit
parallel load signals (PL1 and PL2). PL1 must always word, on the Data Bus and strobes the Transmitter with a
precede PL2. Multiple PL1’s may occur and data will be Parallel Load (PL1) Signal. The second part of the 32-Bit
written over. As soon as PL2 is received, data is word is similarly loaded into the Transmitter with PL2, which
transferred to the FIFO. The data from the Data Bus is also initiates data transfer to stack. This is continuous until
clocked into the D-type flip-flop on the positive going edge the Memory is full, which is eight 31-Bit words. The user
of the PL signals. If the FIFO memory is initially empty, or must keep track of the number of words loaded into the
the stack is not full, the data will be automatically Memory to ensure no data is written over by other data.
transferred down the Memory Stack and into the output During the time the user is loading the Transmitter, he does
register or to the last empty FIFO storage register. If the not have to service the Receiver, even if the Receiver flags
Transmitter Enable signal (ENTX) is not active, a Logic “0”, the user with the signal D/R1 that a valid received word is
the data remains at the output register. The FIFO Memory ready to be fetched. This is shown by the Timing interval B. If
has storage locations to hold eight 31-bit words. If the the user decides to obtain the received data before the
memory is full and the new data is again strobed with PL, Transmitter is completely loaded, he sets the two parallel
the old data at the input register is written over by the new load signals (PL1 and PL2) at a Logic “1” state, and strobes
data. Data will remain in the Memory until ENTX goes to a EN1 while the signal SEL is at a Logic “0” state. After the
Logic “1”. This activates the FIFO Clock and data is shifted negative edge of EN1, the first 16-Bit segment of the
out serially to the Transmitter Driver. Data may be loaded received word becomes valid on the Data Bus. At the
into the FIFO only while ENTX is inactive (low). It is not positive edge of EN1, the user should toggle the signal SEL
possible to write data into the FIFO while transmitting. to ready the Receiver for the second 16-Bit word. Strobing
WARNING: If PL1 or PL2 is applied while ENTX is high, the Receiver with EN1, the second time, enables the second
i.e., while transmitting, the FlFO may be disrupted such 16-Bit word and resets the Receiver Ready Flag D/R1. The
that it would require a MR (Master Reset) signal to user should now reset the signal SEL to a Logic “0” state to
recover.
ready the Receiver for another Read Cycle. During the time
period that the user is fetching the received words, he can
load the transmitter. This is done by interlacing the PL
signals with the EN signals as shown in the Timing Interval
B. Servicing the Receiver 2 is similar and is illustrated by
Timing interval C. Timing interval D shows the rest of the
Transmitter loading sequence and the beginning of the
transmission by switching the signal TX Enable to a Logic “1”
state. Timing interval E is the time it takes to transmit all data
from the FlFO Memory, either 288 Bit times or 232 Bit times.
• The Output Register of the FIFO is designed such that it
can shift out a word of 24 Bits long or 31 Bits long. This
word length is again controlled by the WLSEL bit. The TX
word Gap Timer Circuit also automatically inserts a gap
equivalent to 4-Bit Times between each word. This gives a
minimum requirement of 29-Bit time or 36-Bit time for each
word transmission. Assuming the signal, ENTX, remains
at a Logic “1”, a transfer to stack signal is generated to
transfer the data down the Memory Stack one position.
This action is continued until the last word is shifted out of
the FIFO memory. At this time a Transmitter Ready (TX/R)
flag is generated to signal the user that the Transmitter is
ready to receive eight more data words. During transmis-
sion, if ENTX is taken low then high again, transmission
will cease leaving a portion of the word untransmitted, and
the data integrity of the FIFO will be destroyed.
Repeater Operation
This mode of operation allows a data word that has been
received to be placed directly in the FIFO for transmission. A
timing diagram is shown in Figure 7. A 32-bit word is used in
this example. The data word is shifted into the shift register
and the D/R flag goes low. A logic “0” is placed on the SEL
line and EN1 is strobed. This is the same as the normal
receiver operation and places half the data word (16 bits) on
the data bus. By strobing PL1 at the same time as EN1,
these 16 bits will be taken off the bus and placed in the
FIFO. SEL is brought back high and EN1 is strobed again for
the second 16 bits of the data word. Again by strobing PL2 at
the same time the second 16 bits will be placed in the FIFO.
The parity bit will have been stripped away leaving the 31-bit
data word in the FIFO ready for transmission as shown in
Figure 6.
• A Bit Counter is used to detect the last Bit shifted out of
the FIFO memory and appends the Parity Bit generated
by the Parity Generator. The Parity Generator has a
control signal, Parity Check (PARCK), which establishes
whether odd or even parity is used in the output data word.
PARCK set to a logic “0” will result in odd parity and when
set to a logic “1” will result in even parity.
5-189
HS-3282
CLK
37
TX CLK
38
V
GND
21
SLF TST
(BD05)
S/D ENB1
(BD06)
CC
1
RCV CLK
RCVSEL
WDCNT 1
TXSEL
RCV
TIMING
TX
WLSEL
SEL
WORD GAP
SELF
TEST
S/D ENB2
(BD09)
DATA CLOCK
429D11 (A)
429D11 (B)
X1 (BD07)
Y1 (BD06)
X2 (BD10)
2
CONTROL
WORD
REGISTER
DATA S/R 1
RCV
CLK
TX
LINE
RECEIV.
ER 1
CLK
Y2 (BD11)
PARCK
(BD12)
TXSEL
(BD13)
RCVSEL
(BD14)
WLSEL
(BD15)
3
32
LATCH 1
SEL EN1
SLF
TEST
11
S/DENB
16
16
SEL 1
16
S/D
WDCNT 1
WDCNT 2
34
DECODER
CWSTR
ENTX
16
16
TX CLK
WLSEL
16
SEL 2
D
D
TX WORD
GAP
F/F
F/F
S/D CODER
33
SEL EN2
LATCH 2
32
DATA S/R 2
DATA CLOCK
429D12 (A)
429D12 (B)
4
16
16
LINE
RECEIV.
ER 2
5
16
SEL
32
31
FIFO
8 x 31
TXC
DRVR
429D0
429D0
PARITY
PARCK
SELF
TEST
11 - 20
WORD GAP
8
WLSEL
WDCNT 2
22 - 27
RCV CLK
SELF
TEST
39
6
7
9
10
28 29
30
BD15-
BD00
DATA
BUS
MR D/R1 D/R2
SEL EN1 EN2
PL1 PL2
TX/R
FIGURE 1. SINGLE CHIP ARINC 429 INTERFACE FUNCTIONAL BLOCK DIAGRAM
5-190
HS-3282
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V Thermal Resistance
θJA ( C/W) θJC ( C/W)
Input, Output or I/O Voltage Applied
(Except Pins 2 - 5) . . . . . . . . . . . . . . . . GND -0.3V to V
Input Voltage Applied (Pins 2 - 5). . . . . . . . . . . . . . . . . -29V to +29V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
CDIP Package . . . . . . . . . . . . . . . . . . .
CLCC Package . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175 C
Maximum Storage Temperature Range . . . . . . . . .-65 C to +150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300 C
35
55
8
12
+0.3V
DD
o
o
o
o
Operating Conditions
Die Characteristics
Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V
Operating Temperature Range
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2632 Gates
o
o
HS-3282-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to +70 C
o
o
HS-3282-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
o
DC Electrical Performance Specifications V = 5V ±5%, T = 0 C to +70 C (HS-3282-5),
DD
A
o
o
T = -55 C to +125 C (HS-3282-8)
A
LIMITS
PARAMETER
ARlNC INPUTS Pins 2-3,4-5
Logic “1” Input Voltage
Logic “0” Input Voltage
Null Input Voltage
SYMBOL
CONDITIONS
MIN
MAX
UNITS
V
V
V
V
V
V
V
V
V
V
= 5.25V
6.7
-13.0
-2.5
-5.0
-
13.0
-6.7
+2.5
+5.0
200
-
V
V
lH
DD
DD
DD
DD
DD
DD
DD
DD
DD
V
= 5.25V
IL
V
= 4.75V, 5.25V
= 4.75V, 5.25V
V
NUL
Common Mode Voltage
Input Leakage
V
V
CH
I
= 5.25V, V = ±6.5V
IN
µA
µA
kΩ
kΩ
kΩ
lH
Input Leakage
I
= 5.25V, V = 0.0V
IN
-450
12
lL
Differential Input Impedance
RI
= 5.25V, V = +5V, -5V
IN
-
Input lmpedance to V
RH
RG
= 5.25V, V = 0V
lN
12
-
DD
Input lmpedance to GND
= Open, V = 5.0V
lN
12
-
BIDIRECTIONAL INPUTS Pins 11-20, 22-27
Logic “1” Input Voltage
Logic “0” Input Voltage
Input Leakage
V
V
V
V
V
= 5.25V
= 4.75V
2.1
-
V
V
IH
DD
DD
DD
DD
V
-
-
0.7
1.5
-
IL
l
= 5.25V,V = 5.25V
IN
µA
µA
IH
Input Leakage
I
= 5.25V, V = 0.0V
IN
-1.5
lL
ALL OTHER INPUTS Pins 8-10, 28, 29, 33, 34, 37, 39
Logic “1” Input Voltage
Logic “0” Input Voltage
Input Leakage
V
V
V
V
V
= 5.25V
= 4.75V
3.5
-
-
0.7
10
-
V
V
IH
DD
DD
DD
DD
V
IL
I
= 5.25V, V = 5.25V
IN
-
µA
µA
lH
Input Leakage
I
= 5.25V, V = 0.0V
IN
-75
lL
OUTPUTS Pins 6, 7, 11-20, 22-27, 30-32, 38, Supply Pin 1
Logic “1” Output Voltage
Logic “0” Output Voltage
Standby Supply Current
V
V
V
V
= 4.75V, I = -1.5mA
OH
2.7
-
V
V
OH
DD
DD
DD
V
= 4.75V l = 1.8mA
-
-
0.4
20
OL
OL
l
= 5.25V, V = 0V Except 9,10,
mA
CC1
IN
29 = 5.25V
Operating Supply Current
l
V
= 5.25V, V = 5.25V Except 8,
-
20
mA
CC2
DD
IN
33 = 0.0V, CLK = 1MHz
5-191
HS-3282
o
o
AC Electrical Performance Specifications V = 5V ±5%, T = 0 C to +70 C (HS-3282-5),
DD
A
o
o
T = -55 C to +125 C (HS-3282-8)
A
LIMITS
PARAMETER
SYMBOL
FC
CONDITIONS
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
MIN
MAX
1
UNITS
MHz
kHz
Clock Frequency
Data Rate 1/
V
V
V
V
-
DD
DD
DD
DD
FD
-
-
100
12.5
-
Data Rate 2/
FD
kHz
Master Reset Pulse Width
TMR
200
ns
RECEIVER TIMING
Receiver Ready Time From 32nd Bit 1/
Receiver Ready Time From 32nd Bit 2/
Device Ready to Enable Time
Data Enable Pulse Width
TD/R2
TD/R2
V
V
V
V
V
V
V
V
V
V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
-
-
16
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
128
TD/REN
TEN
0
-
200
50
-
-
-
Data Enable to Data Enable Time
Data Enable to Device Ready Reset Time
Output Data Valid to Enable Time
Data Enable to Data Select Time
Data Select to Data Enable Time
Output Data Disable Time
TENEN
TEND/R
TENDATA
TENSEL
TSELEN
TDATAEN
200
200
-
-
20
20
-
-
80
CONTROL WORD TIMING
Control Word Strobe Pulse Width
Control Word Setup Time
TCWSTR
TCWSET
TCWHLD
V
V
V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
130
130
0
-
-
-
ns
ns
ns
DD
DD
DD
Control Word Hold Time
TRANSMITTER FIFO Write Timing
Parallel Load Pulse Width
TPL
V
V
V
V
V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
200
0
-
ns
ns
ns
ns
ns
DD
DD
DD
DD
DD
Parallel Load to Parallel Load 2 Delay
Transmitter Ready Delay Time
Data Word Setup Time
TPL12
-
TTX/R
-
840
TDWSET
TDWHLD
110
0
-
-
Data Word Hold Time
TRANSMITTER Output Timing
Enable Transmit to Output Data Valid Time 1/
Enable Transmit to Output Data Valid Time 2/
Output Data Bit Time 1/
TENDAT
TENDAT
TBlT
V
V
V
V
V
V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
-
25
µs
µs
µs
µs
µs
µs
DD
DD
DD
DD
DD
DD
-
200
5.05
40.4
5.05
40.4
4.95
39.6
4.95
39.6
Output Data Bit Time 2/
TBlT
Output Data Null Time 1/
TNULL
TNULL
Output Data Null Time 2/
5-192
HS-3282
o
o
AC Electrical Performance Specifications V = 5V ±5%, T = 0 C to +70 C (HS-3282-5),
DD
A
o
o
T = -55 C to +125 C (HS-3282-8) (Continued)
A
LIMITS
PARAMETER
Data Word Gap Time 1/
SYMBOL
TGAP
CONDITIONS
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
MIN
39.6
316.8
-
MAX
40.4
323.2
400
-
UNITS
µs
V
V
V
V
DD
DD
DD
DD
Data Word Gap Time 2/
TGAP
µs
Data Transmission Word to TX/R Set Time
Enable Transmit Turnoff Time
TDTX/R
TENTX/R
ns
0
ns
REPEATER OPERATION TIMING
Data Enable to Parallel Load Delay Time
Data Enable Hold for Parallel Load Time
Enable Transmit Delay Time
TENPL
TPLEN
V
V
V
= 4.75V, 5.25V
= 4.75V, 5.25V
= 4.75V, 5.25V
0
0
0
-
-
-
ns
ns
ns
DD
DD
DD
TTX/REN
NOTES:
1. 100kHz Data Rate.
2. 12.5kHz Data Rate.
o
o
Electrical Performance Specifications V = 5V ±5%, T = 0 C to +70 C (HS-3282-5),
DD
A
o
o
T = -55 C to +125 C (HS-3282-8)
A
LIMITS
(NOTE 1)
PARAMETER
SYMBOL
CD
CONDITIONS
MIN
MAX
20
20
20
15
15
10
10
15
15
UNITS
pF
Differential Input Capacitance
V
= Open, f = 1MHz, Note 2, 3
= GND, f = 1MHz, Note 2, 3
= Open, f = 1MHz, Note 2, 3
= Open, f = 1MHz, Note 2, 4
= Open, f = 1MHz, Note 2, 5
-
-
-
-
-
-
-
-
-
DD
DD
DD
DD
DD
Input Capacitance to V
CH
V
V
V
V
pF
DD
lnput Capacitance to GND
Input Capacitance
Output Capacitance
Clock Rise Time
Clock Fall Time
CG
pF
Cl
pF
CO
pF
TLHC
THLC
TLHI
THLI
CLK = 1MHz, From 0.7V to 3.5V
CLK = 1MHz, From 3.5V to 0.7V
From 0.7V to 3.5V, Note 6
ns
ns
Input Rise Time
Input Fall Time
ns
From 3.5V to 0.7V, Note 6
ns
NOTES:
1. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design and after major process and/or design changes affecting these parameters.
2. All measurements are referenced to device GND.
3. Pins 2-3, 4-5.
4. Pins 8-10, 28, 29, 33, 34, 37, 39.
5. Pins 6, 7, 11-20, 22-27, 30-32, 38.
6. Pins 8-20, 22-29, 33, 34.
5-193
HS-3282
Timing Waveforms
TX/R
TX ENABLE
DATA BUS
PL1
PL2
D/R1
D/R2
EN1
EN2
SEL
TIME
INTERVAL A
TIME
INTERVAL B
TIME
INTERVAL C
TIME
INTERVAL D
TIME
INTERVAL E
BUS IS BEING USED AS AN OUTPUT
BUS IS BEING USED AS AN INPUT
FIGURE 2. TYPICAL INTERFACE TIMING SEQUENCE
429DI
D/R
BIT
32
t
t
END/R
D/R
t
t
ENEN
D/REN
EN
t
SELEN
t
t
t
ENSEL
SELEN
ENSEL
t
EN
t
EN
SEL
t
t
ENDATA
DATAEN
t
t
DATAEN
ENDATA
BD00-15
WORD
1
WORD
2
OR
SEL
WORD
2
WORD
1
BD00-15
FIGURE 3. RECEIVER TIMING
t
CWSTR
CWSTR
BD00-15
t
CWHLD
t
CWSET
CONTROL WORD
FIGURE 4. CONTROL WORD TIMING
5-194
HS-3282
Timing Waveforms (Continued)
PL1
t
PL12
t
PL
PL2
t
TX/R
t
PL
TX/R
t
t
DWSET
DWSET
t
DWHLD
t
DWHLD
BD00-15
WORD 1
WORD 2
FIGURE 5. TRANSMITTER FIFO WRITE TIMING
TX/R
t
ENTX/R
ENTX
t
BIT
t
t
NUL
NUL
t
NUL
t
t
GAP
ENDAT
BIT
1
BIT
2
BIT
32
BIT
1
BIT
32
42900
t
DTX/R
FIGURE 6. TRANSMITTER OUTPUT TIMING
BIT
32
t
429DI
D/R
t
D/R
END/R
t
t
ENEN
D/REN
t
t
EN
EN
EN
t
SELEN
t
t
SELEN
t
ENSEL
ENSEL
SEL
t
ENPL
t
PLEN
PL1
PL2
t
ENPL
t
PLEN
t
TX/R
TX/R
t
t
ENTX/R
TX/REN
ENTX
t
t
NUL
ENDAT
BIT
1
BIT
32
429D0
t
DTX/R
FIGURE 7. REPEATER OPERATION TIMING
5-195
HS-3282
Burn-In Circuits
HS-3282 CERDIP
V
C
DD
GND
1
2
3
4
5
6
7
8
9
V
NC 40
NC
DD
F4
GND
F4
F15
DI1(A)
MR 39
TX CLK 38
CLK 37
NC 36
DI1(B)
DI2(A)
DI2(B)
D/R1
D/R2
SEL
NC
F0
GND
NC
NC
NC
NC 35
NC
V
CWSTR 34
ENTX 33
429D0 32
429D0 31
TX/R 30
PL2 29
DD
F9
GND
NC
NC
NC
F8
V
EN1
DD
F8
F15
F14
F13
F12
F11
F10
F9
10 EN2
11 BD15
12 BD14
13 BD13
14 BD12
15 BD11
16 BD10
17 BD09
18 BD08
19 BD07
20 BD06
PL1 28
F8
BD00 27
BD01 26
BD02 25
BD03 24
BD04 23
BD05 22
21
F0
F1
F2
F3
F8
F4
F7
F5
F6
GND
HS-3282 CLCC
GND
C
44
43 42 41 40
6
5
4
3
2
1
7
39
38
NC
NC
NC
F9
NC
NC
NC
NC
NC
V
D/R1
D/R2
8
9
CWSTR 37
DD
GND
NC
10
11
12
ENTX
D0
SEL
EN1
36
35
34
33
32
31
30
29
V
DD
D0
F8
NC
NC
EN2
F15
13 BD15
TX/R
PL2
14
F14
F8
BD14
15
PL1
BD13
16 BD12
BD11
F13
F12
F8
F0
BD00
BD01
17
F11
F1
18 19 20 21 22 23 24 25 26 27 28
NOTES:
1. Resistors = 47kΩ, 5%, 1/4W (Min)
2. GND = Ground
3. V
= +5.5V, ±0.5V
DD
4. C = 0.01mF/Socket (Min)
5. F0 = 100kHz, F1 = F0/2, . . . F15 = F14/2
5-196
HS-3282
Die Characteristics
DIE DIMENSIONS:
246 x 224 x 19 mils)
(6250 x 5700 x 483µm)
GLASSIVATION:
Type: SiO
Thickness: 8kA ±1kÅ
2
METALLIZATION:
Type: Si-Al
WORST CASE CURRENT DENSITY:
2 x 10 A/cm
5
2
Thickness: 11kÅ ±2kÅ
Metallization Mask Layout
HS-3282
D/R2 (7)
SEL (8)
(36) N/C
EN1 (9)
(35) N/C
EN1 (10)
(34) CWSTR
BD15 (11)
BD14 (12)
(33) ENTX
(32) 429D0
(31) 429D0
(30) TX/R
BD13 (13)
BD12 (14)
BD11 (15)
(29) PL2
(28) PL1
BD10 (16)
(27) BD00
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
5-197
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