ISL55211IRTZ-EVAL1Z_技术文档

Wideband, Low Noise, Low Distortion, Fixed Gain,

Differential Amplifier

ISL55211

Features

The ISL55211 is a wideband, differential input to differential

output amplifier offering 3 possible internal gain settings.

Using fixed 500Ω internal feedback resistors, the amplifier

may be configured for a differential gain of 2, 4 or 5V/V

depending on which combination of input pins are connected

to the signal source. Internal feedback capacitors controls the

signal bandwidth to be a constant 1.4GHz in all gain settings.

• 3 Fixed Gain Options . . . . . . . . . . . . . . . . . . . . . . . 2, 4, or 5V/V

• Constant Bandwidth Over Gain . . . . . . . . . . . . . . . . . . 1.4GHz

• Differential Slew Rate . . . . . . . . . . . . . . . . . . . . . . . 5,600V/µs

• 2V , 2-tone IM3 (200Ω) 100MHz . . . . . . . . . . . . . . -103dBc

P-P

• Low Differential Output Noise (Gain 5V/V). . . . . .<12nV/√Hz

• Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . 3.0V to 4.2V

• Quiescent Power (3.3V Supply) . . . . . . . . . . . . . . . . . .115mW

Ideally suited for AC-coupled data acquisition applications, the

output DC common mode voltage is controlled through an

external V pin or left to default to 1.2V above the negative

CM

Applications

supply pin. Where the differential signal source is AC-coupled,

the input common mode voltage will equal the output

common mode voltage.

• Low Power, High Dynamic Range ADC Interface

• Differential Mixer Output Amplifier

• SAW Filter Pre/Post Driver

Intended for very high dynamic range ADC interface

applications, the ISL55211 offers 5600V/µs differential slew

rate, <12nV/√Hz output noise, and >100dBc SFDR to

• Fixed Gain Coax Receiver

>100MHz for 2V

2-tone 3rd order intermodulation. Its

P-P

Related Devices

balanced architecture effectively suppresses even order

distortion terms - an important issue for very wide band 1st

Nyquist zone ADC interface applications. Minimum gain

operation of 2V/V (6dB) with <1dB peaking ensures stable

performance over-temperature. It's ultra high differential slew

rate of 5600V/µs provides adequate performance margin for

large signal application through 500MHz.

• ISL55210 - External Gain Set Version

• ISLA112P50 - 12-bit, 500MSPS ADC (<500mW)

• ISLA214P50 - 14-bit, 500MSPS ADC (<850mW)

Related Literature

• AN1649 - “Designer’s guide to the ISL55210 and ISL55211

Evaluation Boards”

The ISL55211 requires only a single 3.3V (max. 4.2V) power

supply and 35mA quiescent current, providing a very low

power solution (115mW). Further power savings are possible

using the optional power shutdown control - where the

quiescent current can be reduced to <0.4mA. A companion

device, the ISL55210, offers similar performance where the

feedback and gain resistors are external. Both are available in

a 16 Ld TQFN (Pb-free) package and are specified for

operation over the -40°C to +85°C ambient temperature

range.

+3.3V

MEASURED FREQUENCY RESPONSE

23

ISLA214P50

(850mW)

35mA

(115mW)

20

17

14

11

8

5

2

-1

14Bit 500MSPS

50

ADT2-1T

1:1.4

10

+

120nH

V_ADC

V

i

1:2

ISL55211

22pF

300

V_CM

1.2V

8pF

50

G = 5V/V

ADT4-1T

120nH

-4

-7

-10

-13

-

10

50

180mV

For ADC -1dBFS

P-P

V_CM

V_ADC

20 log

= 20dB

V

1M

10M

100M

1G

i

HIGH GAIN, VERY LOWPOWER, ADC INTERFACE WITH 3^RDORDER OUTPUT FILTER

FREQUENCY (Hz)

FIGURE 1. TYPICAL APPLICATION CIRCUIT

June 21, 2011

FN7868.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

ISL55211

Pin Configuration

ISL55211

(3x3 16 LD TQFN)

TOP VIEW

V_CM

14

GND

16

V_S+

15

GND

13

348

500

V_IN2-

V_IN1-

V_IN1+

V_IN2+

1

12 V_O+

750

0.2pF

2

3

11

-

NC

140

V_CM

10

9

NC

V_O-

+

0.2pF

750

348

4

500

7

8

5

6

GND

Pd

GND

V_S+

GND

Pin Descriptions

PIN NUMBER

SYMBOL

DESCRIPTION

1

V

Balanced Differential Input for Av = 6dB, strapped to V for Av = 14dB

IN1-

IN2-

IN1-

2

Balanced Differential Input for Av = 12dB, strapped to V

for Av = 14dB

IN2-

3

V

Balanced Differential Input for Av = 12dB, strapped to V

IN1+

IN2+

4

Balanced Differential Input for Av = 6dB, strapped to V

Supply Ground (thermal pad electrically connected)

Positive Power Supply (3.0V~4.2V)

for Av = 14dB

IN1+

5, 8, 13, 16

GND

6, 15

7

V

S+

Pd

Power-down: Pd = logic low. Puts part into low power mode; Pd = logic high or open for normal operation

9

V

Inverting Amplifier Output

No Internal Connection

O-

10, 11

12

NC

V

Non-Inverting Amplifier Output

Common-mode Voltage Input

O+

14

V

CM

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

TEMP RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

PART MARKING

ISL55211IRTZ

ISL55211IRTZ-EVAL1Z

NOTES:

5211

-40 to +85

16 Ld 3x3 TQFN

L16.3x3D

Evaluation Board

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL55211. For more information on MSL please see techbrief TB363.

FN7868.0

June 21, 2011

2

ISL55211

Absolute Maximum Ratings (T = +25°C)

Thermal Information

A

Supply Voltage from V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V

Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V +0.3V to GND-0.3V

S+

Thermal Resistance (Typical)

16 Ld TQFN Package (Notes 4, 5) . . . . . . .

θ

_JA(°C/W)

63

θ

_JC(°C/W)

16.5

S+

Power Dissipation. . . . . . . . . . . . . . . . . . . . See Thermal Conditions Section

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . . . . 3500V

Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . . . . . . . 250V

Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1500V

Latch up (Per JESD-78; Class II; Level A) . . . . . . . . . . . . . . . . . . . . . . 100mA

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C

Max. Continuous Operating Junction Temperature . . . . . . . . . . . . .+135°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379.

5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications

V

= +3.3V Test Conditions: G = 12dB, V = open, V = 2V , R = 200Ω differential, T = +25°C,

S+

CM

O

P-P

L

A

differential input, differential output, input and output referenced to internal default V (1.2V nominal) unless otherwise specified.

MIN

MAX

PARAMETER

AC PERFORMANCE

CONDITIONS

(Note 6)

TYP

(Note 6)

UNIT

TESTED

Small-Signal Bandwidth (4-port S

parameter, Test Circuit 2)

G = 6dB, V = 100mV

1.6

1.4

GHz

MHz

GHz

V/V

O

P-P

G = 12dB, V = 100mV

O

P-P

G = 14dB, V = 100mV

1.4

O

P-P

Bandwidth for 0.1-dB Flatness

Large-Signal Bandwidth

Gain Accuracy

G = 12dB, V = 2V

(Figure 17)

150

1.2

O

P-P

G = 12dB, V = 2V

O

G = 6dB, R = Open

1.96

3.88

4.8

2

2.04

4.12

5.2

*

L

G = 12dB, R = Open

4

V/V

L

G = 14dB, R = Open

L

5

V/V

Slew Rate (Differential)

5,600

0.22

-110

-98

V/µs

ns

Differential Rise/Fall Time

2-V step (simulated)

2nd-order Harmonic Distortion,

Test Circuit 1, 15dB Gain

f = 20MHz, V = 2V

dBc

nV/√Hz

O

P-P

f = 50MHz, V = 2V

O

P-P

f = 100MHz, V = 2V

-85

O

P-P

3rd-order Harmonic Distortion,

Test Circuit 1, 15dB Gain

f = 20MHz, V = 2V

-120

-110

-100

-89

O

P-P

f = 50MHz, V = 2V

O

P-P

f = 100MHz, V = 2V

O

P-P

2nd-order Intermodulation Distortion,

Test Circuit 1, 15dB Gain

f = 70MHz, 200kHz spacing (2V

envelope)

c

P-P

f = 140MHz, 200kHz spacing (2V

envelope)

-78

c

P-P

3rd-order Intermodulation Distortion,

Test Circuit 1, 15dB Gain

f = 70MHz, 200kHz spacing (2V

envelope)

-104

-92

c

P-P

f = 140MHz, 200kHz spacing (2V

envelope)

c

P-P

Output Voltage Noise

Test Circuit 1, total gain 15dB, ADT2-1T

11.2

DC PERFORMANCE (Internal Nodes)

Input Offset Voltage

T

= +25°C

-1.4

-1.6

±0.1

+1.4

+1.6

mV

*

A

T

= -40°C to +85°C

A

FN7868.0

June 21, 2011

3

ISL55211

Electrical Specifications

V

= +3.3V Test Conditions: G = 12dB, V = open, V = 2V , R = 200Ω differential, T = +25°C,

S+

CM

O

P-P

L

A

differential input, differential output, input and output referenced to internal default V (1.2V nominal) unless otherwise specified. (Continued)

CM

MIN

MAX

PARAMETER

Average Offset Voltage Drift

Input Bias Current

CONDITIONS

= -40°C to +85°C

(Note 6)

TYP

±3

(Note 6)

UNIT

µV/°C

µA

TESTED

*

T

A

T

= +25°C, positive current into the pin

= -40°C to +85°C

= +25°C

+50

200

±1

+120

+140

A

T

µA

A

Average Bias Current Drift

Input Offset Current

T

nA/°C

µA

A

T

-5

-6

+5

+6

*

A

T

= -40°C to +85°C

µA

A

Average Offset Current Drift

INPUT

T

±8

nA/°C

A

Common-mode Input Range High

Common-mode Input Range Low

Common-mode Rejection Ratio

Internal Nodes

1.7

V

*

1.1

56

f < 10MHz, common mode to differential

output

75

dB

Differential Input Impedance

V

Connected to V

200

Ω

IN1-

IN2-

Connected to V

IN1+

IN2+

OUTPUT (Pins 9 AND 12)

Maximum Output Voltage

Minimum Output Voltage

Differential Output Voltage Swing

Each output (with 200Ω differential load)

Linear Operation

2.15

2.35

0.45

3.8

V

*

0.63

T

= +25°C

3.04

2.95

40

V

A

P-P

V

T

= -40°C to +85°C

A

Differential Output Current Drive

Closed-loop Output Impedance

R = 10Ω [sourcing or sinking]

45

mA

*

L

f < 10MHz, differential

0.6

Ω

OUTPUT COMMON-MODE VOLTAGE CONTROL (Pin 14)

Small-signal Bandwidth

Slew Rate

From V pin to Output V

CM

30

150

0.999

±1

MHz

V/µs

V/V

mV

CM

Rising/Falling

Gain

V

input pin 1.0V to 1.4V

0.995

-8

*

CM

Output Common-Mode Offset from CM Input

CM Default Voltage

CM Input Bias Current

CM Input Voltage Range

CM Input Impedance

POWER SUPPLY

+8

Output V with V pin floating

1.18

1.2

2

1.22

V

CM

At control pin

µA

At control pin

0.9

1.9

V

*

15 || 50

kΩ || pF

Specified Operation Voltage

Quiescent Current

3

33

3.3

35

67

4.2

37

V

*

T

= +25°, V = 3.3V, V = 0V

S+ S-

mA

dB

A

T

= -40°C to +85°C

30.5

50

39.5

A

Power-supply Rejection (PSRR) V

3.0V to 4.5V range

*

S+

f < 10MHz [PSRR to differential output]

Referenced to GND

POWER-DOWN (Pin 7)

Enable Voltage Threshold

Disable Voltage Threshold

Assured on above 1.55V

1.3

0.7

1.55

V

*

Assured off below 0.54V

0.54

FN7868.0

June 21, 2011

4

ISL55211

Electrical Specifications

V

= +3.3V Test Conditions: G = 12dB, V = open, V = 2V , R = 200Ω differential, T = +25°C,

S+

CM

O

P-P

L

A

differential input, differential output, input and output referenced to internal default V (1.2V nominal) unless otherwise specified. (Continued)

CM

MIN

MAX

PARAMETER

CONDITIONS

(Note 6)

TYP

0.3

(Note 6)

UNIT

mA

TESTED

*

Power-down Quiescent Current

T

= +25°C

0.2

0.15

-5

0.4

0.45

+5

A

T

= -40°C to +85°C

mA

A

Input Bias Current

Input Impedance

Turn-on Time Delay

Turn-off Time Delay

NOTE:

PD = 0V, current positive into pin

1

µA

2 || 5

200

400

MΩ || pF

ns

Measured to output on

Measured to output off

ns

6. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.

TABLE 1. ISL55211 INTENDED TRANSFORMER + INTERNAL GAIN

SETTINGS

ISL55211

500

INPUT

XFMR

TURNS

RATIO

INTERNAL

R VALUE (Ω)

TO GET 50Ω

MATCH

T

R

VALUE

GAIN (V/V)

V /V

GAIN (dB)

V /V

G

R_G

(Ω)

+

O

I

O

I

V

I

1:1.4

1:2

250

125

100

250

125

100

2.8

9

122

162

1:n

50

INPUT

5.6

7

15

17

12

18

20

V_O

R_T

192

4

333

-

R_G

1:2

8

1020

Open

1:2

10

500

FIGURE 2. INTENDED CONFIGURATION

FN7868.0

June 21, 2011

5

ISL55211

Typical Performance Curves

V

= 3.3V, T ≈ +25°C, unless otherwise noted.

s+

A

3

2

1

3

2

1

Av = 2

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

Av = 5

Av = 4

TEST CIRCUIT #1

= 500mV

TEST CIRCUIT #1

V = 500mV

O

V

O

P-P

10M

100M

1G

10M

100M

1G

FREQUENCY (Hz)

FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE WITH ADT2-1T

INPUT TRANSFORMER

FIGURE 4. SMALL SIGNAL FREQUENCY RESPONSE WITH

ADT4-1WT INPUT TRANSFORMER

3

2

1

3

2

1

Av = 2

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

0

-1

-2

-3

Av = 5

-4

-5

Av = 4

-6

Av = 4

-7

-8

-9

TEST CIRCUIT #1

= 3V

TEST CIRCUIT #1

= 3V

V

O(P-P)

P-P

O(P-P)

P-P

10M

100M

1G

10M

100M

FREQUENCY (Hz)

1G

FREQUENCY (Hz)

FIGURE 5. LARGE SIGNAL FREQUENCY RESPONSE WITH ADT2-1T

INPUT TRANSFORMER

FIGURE 6. LARGE SIGNAL FREQUENCY RESPONSE WITH

ADT4-1WT INPUT TRANSFORMER

25

20

GAIN = 12dB

18

GAIN = 9dB

20

16

14

12

10

8

15

10

GAIN = 17dB

GAIN = 20dB

6

GAIN = 15dB

GAIN = 18dB

5

4

2

TEST CIRCUIT #1

0

TEST CIRCUIT #1

0

50

100

150

200

250

300

350

400

450

500

50

100

150

200

250

300

350

400

450

500

FREQUENCY (MHz)

FIGURE 7. NOISE FIGURE WITH ADT2-1T INPUT TRANSFORMER

FIGURE 8. NOISE FIGURE WITH ADT4-1WT INPUT TRANSFORMER

FN7868.0

June 21, 2011

6

ISL55211

Typical Performance Curves

V

= 3.3V, T ≈ +25°C, unless otherwise noted. (Continued)

s+

A

-60

HD2 of 3V

P-P

TEST CIRCUIT 1

= 200Ω

TEST CIRCUIT 1

= 200Ω

GAIN = 15dB

IM2 of 3V

P-P

IM2 of 1V

P-P

-65

-70

R

L

-70

GAIN = 15dB

HD2 of 2V

P-P

IM2 of 2V

P-P

-75

-80

HD3 of 3V

P-P

-80

-90

-85

-90

-100

-110

-120

-95

IM3 of 2V

P-P

IM3 of 1V

P-P

-100

-105

-110

HD3 of 2V

P-P

IM3 of 3V

100

P-P

HD3 of 1V

P-P

HD2 of 1V

100M

FREQUENCY (Hz)

50M

150M

200M

50

150

200

FREQUENCY (MHz)

FIGURE 10. IM2 AND IM3 vs OUTPUT SWING

FIGURE 9. HD2, HD3 vs OUTPUT SWING

-60

-70

-60

-65

TEST CIRCUIT 1

= 1V EACH TONE

TEST CIRCUIT 1

R

= 200Ω

IM2 of 9dB

V

L

O

P-P

V

= 2V

IM2 of 17dB

O

P-P

-70

HD2 of 9dB

HD2 of 15dB

-75

IM2 of 15dB

-80

HD2 of 17dB

-80

-90

-85

-90

IM3 of 9dB

-100

-110

-120

HD3 of 17dB

-95

IM3 of 15dB

-100

-105

-110

HD3 of 15dB

150M

IM3 of 17dB

100M

HD3 of 9dB

100M

50M

200M

50M

150M

200M

FREQUENCY (Hz)

FREQUENCY (MHz)

FIGURE 12. IM2 AND IM3 vs GAIN

FIGURE 11. HD2, HD3 vs GAIN

-50

-60

HD2 of 50Ω

HD2 of 500Ω

TEST CIRCUIT 1

GAIN = 15dB

TEST CIRCUIT 1

IM2 of 100Ω

-60

-70

IM2 of 50Ω

HD2 of 100Ω

HD2 of 200Ω

IM2 of 200Ω

-70

-80

-90

-80

-100

-110

-120

-130

IM2 of 500Ω

-90

HD3 of 500Ω

HD3 of 200Ω

IM3 of 500Ω

IM3 of 100Ω

IM3 of 50Ω

-100

-110

HD3 of 100

Ω

IM3 of 200Ω

50M

HD3 of 50Ω

100M

FREQUENCY (Hz)

50M

150M

200M

100M

150M

200M

FREQUENCY (Hz)

FIGURE 14. IM2, IM3 vs DIFFERENTIAL LOAD

FIGURE 13. HD2, HD3 vs DIFFERENTIAL LOAD

FN7868.0

June 21, 2011

7

ISL55211

Typical Performance Curves

V

= 3.3V, T ≈ +25°C, unless otherwise noted. (Continued)

s+

A

200

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

15

14

13

12

11

10

9

PHASE OF 17dB

PHASE OF 15dB

PHASE OF 9dB

TEST CIRCUIT 1

WITH ADT2-1T INPUT

180

160

140

120

100

80

GAIN = 17dB

GAIN = 15dB

8

GROUP DELAY OF 17dB

7

TEST CIRCUIT 1 ADT2-1T

OUTPUT NOISE INCLUDING

50Ω SOURCE NOISE

GAIN = 9dB

GROUP DELAY OF 15dB

GROUP DELAY OF 9dB

6

5

1M

10

30

50

70

90

110 130 150 170 190

10M

FREQUENCY (Hz)

100M

FREQUENCY (MHz)

FIGURE 16. DIFFERENTIAL OUTPUT NOISE vs GAIN

FIGURE 15. PHASE AND GROUP DELAY vs GAIN

3

0

12

TEST CIRCUIT 2

SIMULATED

6dB

10

8

-3

6

12dB

14dB

GAIN = 2

-6

4

GAIN = 5

GAIN = 4

-9

2

TEST CIRCUIT 2

NO TRANSFORMERS

-12

0

10

100

1000

1M

10M

100M

1000M

5000

FREQUENCY (MHz)

FREQUENCY (Hz)

FIGURE 17. SMALL SIGNAL FREQUENCY RESPONSE

FIGURE 18. DIFFERENTIAL OUTPUT IMPEDANCE

-50

-55

-60

-65

-70

-75

-80

3

0

TEST CIRCUIT 3

V

DIFFERENTIAL IS 2V

O(P-P)

P-P

-3

-6

-9

9dB

10mV

P-P

200mV

P-P

15dB

-12

17dB

-15

-18

-21

TEST CIRCUIT 3

COMMON MODE AC OUTPUT

1

10

2M

20M

FREQUENCY (Hz)

200M

100

200

FREQUENCY (MHz)

FIGURE 19. V

PIN INPUT FREQUENCY RESPONSE TO OUTPUT

FIGURE 20. OUTPUT BALANCE ERROR

CM

COMMON MODE

FN7868.0

June 21, 2011

8

ISL55211

Typical Performance Curves

V

= 3.3V, T ≈ +25°C, unless otherwise noted. (Continued)

s+

A

0.15

1.5

1.0

0.5

0

TEST CIRCUIT #1 WITH ADT2-1T

100MHz SQUARE WAVE INPUT

TEST CIRCUIT #1 WITH ADT2-1T

100MHz SQUARE WAVE INPUT

OUTPUT

0.10

0.05

0

INPUT

-0.05

-0.10

-0.15

-0.5

-1

-1.5

0

2

4

6

8

10

12

14

16

18

20

0

2

4

6

8

10

12

14

16

18

20

TIMEBASE (ns)

FIGURE 21. SMALL SIGNAL STEP RESPONSE

FIGURE 22. LARGE SIGNAL RESPONSE

-14.4

-14.6

-14.8

-15.0

-15.2

-15.4

-15.6

-15.8

-16.0

110000MMHHzzOOUUTTPPUUTT

2V

P-P

EENNAABBLLEEDD

100mV

P-P

PD

DDIISSAABBLLEEDD

TEST CIRCUIT 1 WITH ADT2-1T INPUT

OUTPUT V

RELATIVE TO INPUT V

P-P

1M

10M

100M

TEST CIRCUIT 1

22µµss//DDIIVV

FREQUENCY (Hz)

FIGURE 23. ENABLE/DISABLE TIMES (2µs/DIV)

FIGURE 24. SHUTDOWN FEED-THROUGH

2.5

2.0

1.5

1.0

0.5

0

95

85

75

65

55

45

35

OUTPUT

PSRR TO V (DIFFERENTIAL)

O

INPUT

CMRR TO V (DIFFERENTIAL)

O

-0.5

-1.0

-1.5

-2.0

-2.5

TEST CIRCUIT 1 SIMULATED

EXACT EXTERNAL R’s

TEST CIRCUIT 1

1

10

100

1000

0

20

40

60

80

100 120 140 160 180 200

TIME (ns)

FREQUENCY (MHz)

FIGURE 25. OVERDRIVE RECOVERY

FIGURE 26. PSRR/CMRR TO DIFFERENTIAL V

O

FN7868.0

June 21, 2011

9

ISL55211

Typical Performance Curves

V

= 3.3V, T ≈ +25°C, unless otherwise noted. (Continued)

s+

A

6

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

TEST CIRCUIT 1

T

= +85°C

A

5

4

3

2

1

MAXIMUM DIFFERENTIAL V

OUTPUT USING DEFAULT V

P-P

CM

T

= +25°C

A

T

= -40°C

A

INTERNALLY SET V

CM

3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5

SINGLE SUPPLY VOLTAGE (V)

3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5

SUPPLY VOLTAGE (V)

FIGURE 27. DEFAULT V

AND MAX V

vs SUPPLY VOLTAGE

OPP

FIGURE 28. SUPPLY CURRENT vs SUPPLY VOLTAGE

CM

shown in Table 1, gives a 9dB to 20dB operating gain range in

approximately 3dB steps.

Applications

Basic Operation

The device can be powered down to < 400µA supply current

using the optional disable pin. To operate normally, this pin

The ISL55211 is a very wideband, voltage feedback based,

differential amplifier including an output common mode control

loop and optional power shutdown feature. Intended for very low

distortion differential signal driving, this internally fixed gain

device provides 3 possible gain settings by simply picking the

input side connections as shown in Table 1. Including internal

compensation, the ISL55211 holds a constant bandwidth over

gain settings. Most applications are intended for AC-coupled I/O

using a single 3.3V supply and an input transformer. The internal

resistor values have been scaled up slightly to require an external

termination element along with the two internal resistors where

a 50Ω differential input match is desired. This does increase the

output noise slightly but narrows up the input VSWR tolerance

and lowers the added loading of the feedback resistors

improving SFDR.

should be asserted high using a simple logic gate to +V or tied

CC

high through a 10kΩ resistor to +V . When disabled, the power

CC

dissipation drops to < 1mW but, due to the inverting op amp type

architecture, the input signal will feed-forward through the

feedback and gain resistors giving limited isolation.

Application and Characterization Circuits

Test Circuit 1 of Figure 29 forms a starting point for many of the

characterization curves for the ISL55211. Since most lab sources

and measurement devices are single-ended, this circuit converts

to differential at the input through a wideband transformer and

would also be a typical application circuit coming from a

single-ended source. Assuming the source is a 50Ω impedance,

the internal R resistors and external R are set to provide both

G

T

the input termination and the gain. Since the inverting summing

nodes act as virtual ground points for AC signal analysis, the total

Where DC-coupled differential I/O operation is desired, the

ISL55211 can be connected directly to the source as long as the

internal input common mode range limits are observed (1.1V to

1.7V for a 3.3V single supply operation). For a DC-coupled, single

to differential requirement, consider the ISL55210. This device is

an external resistor version of the ISL55211 where the flexibility

in the external resistors will enable single to differential

operation. For a ground referenced input signal, this will require a

negative supply when using the ISL55210.

termination impedance across the input transformer secondary

2

will be (2*R )||R . Setting this equal to n *R will give a

G

T

S

matched input impedance inside the bandwidth of the

transformer (where "n" is the turns ratio). The amplifier gain is

fixed by the selected input R element and the internal 500Ω

G

feedback resistors. While the ISL55211 is internally a Voltage

Feedback Design (VFA) to give the lowest possible noise, internal

compensation caps hold the bandwidth over gain setting

approximately constant at 1.4GHz. For wider small signal

bandwidth at lower gains, consider the ISL55210, which provides

>2.2GHz at a gain of 12dB.

Most applications behave as a differential inverting op amp

design. There is therefore an input gain resistor on each side of

the inputs that must be driven. The 3 possible connections to the

two pairs of input pins will give a 100Ω, 125Ω, or 250Ω input

resistor on each side. Combined with the two input turns ratio's

FN7868.0

June 21, 2011

10

ISL55211

Where just the amplifier is tested, a 4-port network analyzer is

used and the very simple test circuit of Figure 30 is

+3.3V

115mW 35mA

implemented. This is used to measure the differential S21 curves

vs gain of Figure 17 and as a simulation circuit for the differential

output impedance vs gain of Figure 18. Changing the gain is a

10k

PD

500

simple matter of adjusting the connections to the four input R

G

85

connections resistors, as shown in Table 1. This circuit depends

on the two AC-coupled source 50Ω of the 4 port network analyzer

and presents an AC-coupled differential 100Ω load to the

amplifier as the input impedance of the remaining two ports of

the network analyzer.

0.2pF

+

50

R_G

1µF

V_O

1:1.4

35

1:1

200

V_m

R_T

V

i

1µF

V_CM

0.1µF

ADT2-

1T

ADT1-

1WT

+3.3V

10k

or

-

0.2pF

500

ADT4-

1Wt

1µF

85

R_G

R_F

PD

ISL55211

R_G

50

+

FIGURE 29. TEST CIRCUIT 1

1/2 of a 4-port

S-parameter

V_CM

Working with a transformer coupled input as shown in Figure 29,

or with two DC blocking caps from a differential source, means

the output common mode voltage set by either the default

1/2 of a 4-port

S-parameter

R_T

internal V setting, or a voltage applied to the V control pin,

CM CM

-

50

will also appear as the input common mode voltage. This

provides a very easy way to control the ISL55211 I/O common

mode operating voltages for an AC-coupled signal path. The

50

R_G

internal common mode loop holds the output pins to V and,

CM

R_F

ISL55211

since there is no DC path for an I current back towards the

CM

input in Figure 29, that V setting will also appear as the input

common mode voltage. It is useful, for this reason, to leave any

input transformer secondary centertap unconnected. The

CM

FIGURE 30. TEST CIRCUIT 2 4-PORT S-PARAMETER

MEASUREMENTS

internally set V voltage is referenced from the negative supply

CM

Using this measurement allows the small single bandwidth of

just the ISL55211 to be exposed. Many of the other

measurements are using I/O transformers that are limiting the

apparent bandwidth to a reduced level. Figure 17 shows the 3

normalized differential S21 curves for the possible internal gains

of 9dB, 14dB and 15dB. The small signal bandwidth is remaining

nearly constant at 1.4GHz due to the internal capacitive

feedback network.

pin. With a single 3.3V supply, it is very close to 1.2V but will

change with total supply voltage across the device as shown in

Figure 27.

Most of the characterization curves starting with Figure 29 then

get different gains by changing the connections to the two pairs

of input R connections, as shown on the pin configuration

G

drawing on page 2. Two input turns ratios are intended for Test

Circuit 1; either a 1:1.4 turns ratio (ohms ratio of 2) or a 1:2 turns

ratio (ohm ratio of 4). The specific transformers shown in

Figure 29 are representative of broadband RF transformers but

alternate devices and manufacturers of these turns ratio devices

are certainly applicable. The output side of this test circuit

presents a differential 200Ω load while converting the

differential to single-ended through a resistive attenuator and a

1:1 transformer. This inserts approximately a 17dB insertion loss

that is removed to report the characteristic curves. For load tests

below the 200Ω shown in Figure 29, a simple added shunt

resistor is placed across the output pins. For loads > 200Ω, the

series and shunt load R's are adjusted to show that total load

(including the 50Ω measurement load reflected through the 1:1

output measurement port transformer) and provide an apparent

50Ω differential source to that transformer. This output side

transformer is for measurement purposes only and is not

necessary for final applications circuits. There are output

interface designs that do benefit from a transformer as part of

the signal path as shown in Figure 1. In that case, the 1:1:4

output side transformer becomes part of a filter design and

recovers the filter insertion loss from the amplifier output pins to

the ADC inputs.

The closed loop differential output impedance of Figure 18 is

simulated using Figure 30 in ADS. This shows a relatively low

output impedance (< 1Ω through 100MHz) constant with signal

gain setting. Typical FDA outputs show a closed loop output

impedance that increases with signal gain setting. The ISL55211

holds a more constant response due to internal design elements

unique to this device.

Common mode output measurements are made using the circuit

in Figure 31. Here, the outputs are summed together through two

100Ω resistors (still a 200Ω differential load) to a center point

where the average, or common mode, output voltage may be

sensed. This is coupled through a 1µF DC blocking capacitor and

measured using 50Ω test equipment. The common mode source

impedance for this circuit is the parallel combination of the

2-100Ω elements, or 50Ω. Figure 19 uses this circuit to measure

the small and large signal response from the V control pin to

CM

the output common mode. This pin includes an internal 50pF

capacitor on the default bias network (to filter supply noise when

there is no connection to this pin), which bandlimits the response

to approximately 30MHz. This is far lower than the actual

bandwidth of the common mode loop. Figure 20 uses this output

FN7868.0

June 21, 2011

11

ISL55211

CM measurement circuit with a large signal (2V ) differential

output voltage (generated through the Vi path of Figure 31) to

measure the differential to common mode conversion - often

called the "Output Balance Error" for an FDA.

P-P

ISL55211

500

R_S

R_G

+3.3V

10k

+

Vi

PD

75 INPUT

V_O

500

R_T

R_G

100

+

ADT2-1T

1:1.4

V_i

Output

V_CM

1:n

R_S

1µF

50

1µF

-

1µF

V_CM

50

1:1.4 -> CX2045NL

1:2 -> CX2032

R_G

-

500

100

R_G

500

ISL55211

FIGURE 32. 75Ω IMPEDANCE IMPLEMENTATIONS

V_CMInput

50

Here, the sum of the two internal R resistors at the higher two

G

gain settings is too low to retain a match for the 1:2 input step up

case. There, a pair of external series resistors are added to get

the total differential input impedance up to 300Ω on the

FIGURE 31. TEST CIRCUIT #3 COMMON MODE AC OUTPUT

MEASUREMENTS

secondary side of the transformer and the R element goes to

T

infinity. These two conditions are not particularly useful but

Figure 32 shows how to implement the full range of internal

conditions with the two turns ratios considered in Table 2.

Figure 32 also shows a pair of alternate input transformer types

from Pulse Engineering particularly suitable to the 75Ω case.

Single Supply, Input Transformer Coupled,

Design Considerations

The characterization circuit of Figure 29 shows one possible

input stage interface that offers several advantages. Where AC

coupling is adequate, the circuit of Figure 29 simplifies the input

common mode voltage control. If the source coming into this

stage is single-ended, the input transformer provides a zero

TABLE 2. EXTERNAL RESISTORS FOR A 75Ω INPUT

IMPEDANCE DESIGN

ISL55211 INTENDED TRANSFORMER + INTERNAL GAIN SETTINGS

INPUT

power conversion to differential. The two gain resistors (R in

G

XFMR

TURNS

RATIO

INTERNAL

GAIN

(V/V)

GAIN

(dB)

EXTERNAL EXTERNAL

Figure 29) provide both a portion of the input termination

R

VALUE

R VALUE

R

VALUE

G

T

S

impedance and the gain element for the amplifier. For 50Ω

(Ω)

V /V

(Ω)

214

375

600

750

Open

(Ω)

O

I

O

I

systems, these R resistors are too high with the turns ratios

G

1:1.4

1:2

250

125

100

250

125

100

2.8

5.6

7

9

0

shown in Figure 29 to provide the full match and an external R

T

resistor is required. This R element goes away at the highest

15

17

12

T

gain setting using a 1:2 input turns ratio transformer.

0

It is also possible to adapt this circuit to other input characteristic

impedances. Figure 32 shows a 75Ω example similar to Figure 2

while Table 2 shows the necessary external R values and

resulting gains.

4

0

1:2

6.7

16.5

25

50

1:2

This input interface also simplifies the input common mode

control. The V pin controls the output common mode voltage.

CM

In most DC-coupled FDA applications, the input common mode

voltage is determined by both this output common mode and the

source signal. In a configuration like Figure 29, there is no path

for a common mode current to flow from output to input, so the

input common mode voltage equals the output. A similar effect

could be achieved with just two blocking caps on the two R

G

resistors. A DC-coupled, single to differential, configuration will

also have a common mode input that is moving with the input

signal. Converting to just a differential signal at the amplifier, as

in Figure 29, removes any input signal related artifacts from the

input common mode making the ISL55211 behave as a

differential only VFA amplifier. There is only a very small

differential error signal at the inputs set by the loop gain, as in a

FN7868.0

June 21, 2011

12

ISL55211

normal single-ended VFA application, but no common mode

maximum differential V swing will be 4x this 0.6V

P-P

signal related terms.

single-ended limit or 2.4V . Where +Vs is increased, the limit

P-P

then becomes the 0.9V below V , but then the absolute

CM

The examples shown are using the transformer to convert from

single to differential. However, if the source is already

maximum differential V

is then 4 x 0.9V to 3.6V . So for

P-P

instance, to get this maximum output swing, increase the supply

differential, these same transformer input circuits can drive the

transformer differentially still providing impedance scaling if

needed and common mode rejection for both DC and AC

common mode issues. A good example would be differential

mixer outputs or SAW filter outputs. Those differential sources

voltage until +Vs - 1.5V > V + 0.9V. If we assume a V voltage

CM CM

of 1.3V for instance, then 1.3V + 0.9V + 1.5V = 3.7V will give an

unclipped 3.6V output capability. The V reported in

P-P P-P

Figure 27 is an asymmetrically clipped maximum swing. Going

10% above this 3.7V target to 4.1V will be within the

recommended operating range and give some tolerancing

could also be connected into the ISL55211 R resistors through

G

blocking caps as well eliminating the input transformer. The AC

termination impedance for the differential source will then be

headroom that would also suggest the V voltage be moved up

CM

to approximately 1.5V, which coincides with the default output

the sum of the two R resistors when simple blocking caps are

G

V

from Figure 27. Operating at +4.1V single supply in a

CM

Figure 29 type configuration will give the maximum linear

differential output swing of 3.6V

used.

.

P-P

Amplifier I/O Range Limits

The differential inputs internal to the ISL55211 also have

operating range limits relative to the supply voltages. Operating

in an AC-coupled circuit like Figure 29 will produce an input

common mode voltage equal to the outputs. The inputs can

The ISL55211 is intended principally to give the lowest IM3

performance on the lowest power for a differential I/O

application. The amplifier will work DC coupled and over a

relatively wide supply range of 3.0V to 4.2V supplies. The outputs

have both a differential and common mode operating range

limits while the input pins internal to the ISL55211 have a

common mode voltage operating range. For single supply

operation, the -Vs pins are at ground as is the exposed metal pad

on the underside of the package. The ISL55211 can operate split

supply where then -Vs will be a negative supply voltage and the

exposed metal pad is either connected to this negative supply or

left unconnected on an insulating board layer.

operate with full linearity with this V voltage down to 1.1V

CM

above the -Vs supply. On the default 1.2V output V on +3.3V

CM

supplies this gives a 100mV guardband on the input V

CM

voltages. Overriding the default V by applying a control voltage

CM

to the V pin should be done with care in going towards the

CM

negative supply due to this limit. On the + side, the maximum

input V above the -Vs supply is 2V so there is more room to

CM

move the output V up than down from the default value.

CM

Briefly, the I/O and V limits are as follows:

CM

Power Supply, Shutdown, and Thermal

Considerations

1. Maximum V setting = -Vs +2V

CM

The ISL55211 is intended for single supply operation from 3.0V

to 4.2V with an absolute maximum setting of 4.5V. The 3.3V

supply current is trimmed to be nominally 35mA at +25°C

ambient. Figure 28 shows the supply current for nominal +25°C

and -40°C to +85°C operation over the specified maximum

supply range. The input stage is biased from an internal voltage

reference from the negative supply giving the exceptional 90dB

low frequency PSRR shown in Figure 26.

2. Input common mode operating range (internal summing

junction pints of the ISL55211) of -Vs + 1.1V or to output V

+ 0.5V

CM

3. Output V minimum (on each side) is either -Vs + 0.3V or

O

output V - 0.9V

CM

4. Output V maximum (on each side) is +Vs - 1.5V

O

The output swing limits are often asymmetrical around the V

CM

voltage. The maximum single-ended swings are set by these two

limits - V is either -Vs + 0.3V or V - 0.9V, whichever is

Since the input stage bias is from a re-regulated internal supply,

a simple approach to single +5V operation can be supported as

shown in Figure 33. Here, a simple IR drop from the +5V supply

will bring the operating supply voltage for the ISL55211 into its

allowed range. Figure 33 shows example calculations for the

voltage range at the ISL55211 +Vs pin assuming a ±5%

tolerance on the +5V supply and a 35mA to 55mA range on the

total supply current. Considering the 34mA to 44mA quiescent

current range from Figure 28 over the -40°C to +85°C ambient,

and the 3.4V to 4.4V supply voltage range assumed here, this is

designing for a 1mA to 11mA average load current, which should

be adequate for most intended application loads. Good supply

decoupling at the device pins is required for this simple solution

to still provide exceptional HD performance.

O(MIN) CM

less. So for instance, on a single 3.3V supply with the default V

voltage of 1.2V, these two limits give the same result and the

CM

output pins can swing down to 0.3V above -Vs (= 0V). If, however,

the V pin is raised to 1.5V, then the minimum output voltage

CM

will become 1.5V - 0.9V = 0.6V.

V

is set by a headroom limit to the positive supply to be

= +Vs - 1.5V. Again, on a 3.3V single supply and the

O(MAX)

-V

O(MAX)

default 1.2V V setting, this means the maximum referenced to

CM

ground output pin voltages can be 3.3V - 1.5V = +1.8V or 0.6V

above the default V voltage.

CM

Using these default conditions, and the maximum positive

excursion of 0.6V above the 1.2V output V setting, the

CM

FN7868.0

June 21, 2011

13

ISL55211

+85°C maximum operating ambient from Figure 27, we get

4.5V*45mA*+120°C/W = +24°C rise above +85°C or

+5V ±5%

24.3

approximately +109°C operating T maximum - still well below the

J

35 55mA

3.4 4.4V

specified Absolute Maximum operating junction temperature of

+135°C.

+

2.2µF

10nF

10k

R_F

Noise Analysis

PD

The decompensated voltage feedback design of the ISL55211

provides very low input voltage and current noise. Based on the

ISL55210, these internal noise terms are 0.85nV/√Hz differential

voltage noise and a 5pA/√Hz current noise term on each side. Since

the ISL55211 is an internally fixed gain version, these internal noise

terms will produce only a few set of output noise values. Figure 34

shows the analysis model for just the ISL55211 with no input

transformer while Table 3 shows the resulting output and input

referred differential spot noise voltages using Equation 1.

+

R_O

R_G

C_IN

1:n

V_CM

V_O

V_i

R_O

R_G

-

R_F

ISL55211

4kTR_F

*

R_F

500

FIGURE 33. OPERATING FROM A SINGLE +5V SUPPLY

*

The ISL55211 includes a power shutdown feature that can be used

to reduce system power dissipation when signal path operation is

not required. This pin (Pd) is referenced to -Vs and must be asserted

low to activate the shutdown feature. When not used, a 10kΩ

external resistor to +Vs should be used to assert a high level at this

pin. Digital control on this pin can be either an open collector output

(using that 10kΩ pull-up) or a CMOS logic line running off the same

+Vs as the amplifier. For split supply operation, the Pd pins must be

pulled to below -Vs + 0.54V to disable.

i_N

4kTR_G

+

R_G

*

e_O

e_n

ISL55211

4kTR_G

R_G

-

Since the ISL55211 operates as a differential inverting op amp,

there is only modest signal path isolation when disabled, as shown

in Figure 24. The inputs include 2 pairs of back to back low

capacitance diodes intended to protect any subsequent devices

from large input signals during shutdown. Those diodes limit the

maximum overdrive voltage across the input to approximately 1.0V

*

i_N

500

R_F

*

4kTR_F

in each polarity. The internal R resistors of Test Circuit 1 limit the

G

current into those diodes under this condition.

FIGURE 34. AMPLIFIER ONLY NOISE MODEL

The supply current in shutdown does not reduce to zero as internal

circuitry is still active to hold the output common mode voltage at

With equal feedback and gain resistors, the total output noise

expression becomes very simple. This is shown as Equation 1.

the V voltage even during shutdown. This is intended to hold the

CM

ISL55211 outputs near the desired common mode output level

during shutdown. This improves the turn on characteristic and keeps

those output voltages in a safe range for downstream circuitry.

2

(EQ. 1)

∗

(e NG) + 2(i R ) + 2(4kTR NG)

N N F F

e

0

The NG term in this equation is the Noise Gain = 1 + R /R . The

F

G

The very low internal power dissipation of the ISL55211, along with

the excellent thermal conductivity of the TQFN package when the

last term in Equation 1 captures both the R and R resistor

F

G

noise terms. Table 3 evaluates this expression for the 3 possible

internal gains with a fixed 500Ω internal feedback. nV/√HZ

exposed metal pad is tied to a conductive plate, reduces the T rise

J

above ambient to very modest levels. Assuming a nominal 115mW

dissipation and using the 63°C/W measured thermal impedance

from Junction to ambient, gives a rise of only 0.115*63 = 7.2°C.

Operation at elevated ambient temperatures is easily supported

given this very low internal rise to junction.

TABLE 3. OUTPUT AND INPUT SPOT NOISE FROM EQUATION 1 FOR

THE 3 GAINS OF THE ISL55211

INPUT REFERRED

R

GAIN

V/V

NOISE GAIN

V/V

E

NI

nV/√Hz

G

O

The maximum internal junction temperatures would occur at

maximum supply voltage, +85°C maximum ambient operating,

and where the TQFN exposed pad is not tied to a conductive layer.

Where the TQFN must be mounted with an insulating layer to the

exposed metal plate, such as in a split supply application, device

measurements show an increased thermal impedance junction to

ambient of +120°C/W. Using this, and a maximum quiescent

internal power on 4.5V absolute maximum, which shows 45mA for

(Ω)

250

125

100

nV/√Hz

2

4

5

3

5

6

8.19

4.09

10.51

11.60

2.63

2.32

FN7868.0

June 21, 2011

14

ISL55211

TABLE 4. OUTPUT NOISE AND INPUT REFERRED EQUIVALENT NOISE FOR THE TRANSFORMER COUPLED INPUT

ISL55211 INTENDED TRANSFORMER + INTERNAL GAIN SETTINGS

TOTAL GAIN

INPUT REFERRED

INPUT XFMR

TURNS RATIO

INTERNAL

GAIN (V/V) GAIN (dB)

EXTERNAL

RESISTOR FOR

NOISE GAIN

V/V

E

NI

nV/√Hz

O

R

VALUE (Ω)

V /V

R VALUE (Ω)

NG (Ω)

nV/√Hz

G

O

I

O

I

T

1:1.4

1:2

250

2.8

5.6

7

9

122

162

277.48

155.92

132.88

312.48

208.61

200.00

2.80

4.21

4.76

2.60

3.40

3.50

7.94

2.834811

1.718338

1.46452

125

15

17

12

18

20

9.62

100

192

333

1020

10.25

7.68

250

4

1.920066

1.083876

0.879492

1:2

125

8

8.67

8

1:2

100

10

100

8.79

Adding an input transformer can improve the input referred noise

by adding a noiseless voltage gain. Starting from Test Circuit 1 of

Figure 29, and assuming the source shows a matched

Driving Cap and Filter Loads

Most applications will drive a resistive or filter load. The

ISL55211 is robust to direct capacitive load on the outputs up to

approximately 10pF. For frequency response flatness, it is best to

avoid any output pin capacitance as much as possible - as the

capacitance increases, the high frequency portion of the

ISL55211 (>1GHz) response will start to show considerable

peaking. No oscillations were observed up through 10pF load on

each output.

broadband source R that will be matched by the input referred

S

parallel combination of 2*R ||R , a noise gain analysis circuit

G

T

can be developed as shown in Figure 35.

R_F

500

R_T/2

R_G

For AC-coupled applications, an output network that is a small

series resistor (10 to 50Ω) into a blocking capacitor is preferred.

This series resistor will isolate parasitic capacitance to ground

from the internally closed loop output stage of the amplifier and

de-que the self resonance of the blocking capacitors. Once the

output stage sees this resistive element first, the remaining part

of a passive filter design can be done without fear of amplifier

instability.

+

n²R_S/2

ISL55211

-

Driving ADC's

R_G

500

R_F

R_T/2

Many of the intended applications for the ISL55211 are as a low

power, very high dynamic range, last stage interface to high

performance ADC's. The lowest power ADC's, such as the

ISLA214P50 shown on the front page, include an innovative

"Femto-Charge™" internal architecture that eliminates op amps

from the ADC design and only passes signal charge from stage to

stage. This greatly reduces the required quiescent power for

these ADC's but then that signal charge has to be provided by the

external circuit at the two input pins. This appears on an ADC like

the ISLA112P50 as a clock rate dependent common mode input

current that must be supplied by the interface circuit. At

500MHz, this DC current is 1.3mA on each input for the 14-bit

ISLA214P50.

FIGURE 35. NOISE GAIN MODEL FOR THE TRANSFORMER

COUPLED INPUT CIRCUIT OF FIGURE 29

Stepping through the 3 gain settings with two input transformers

will allow the noise gain to be calculated for the circuit of

Figure 35, which is all that is needed in Equation 1 to arrive at an

output differential noise (since R is fixed at 500Ω). Doing this

F

gives Table 4.

The signal gain is taken from the input of the transformer for this

analysis and shows the total input referred noise going below

0.9nV at the highest gain setting here. While this analysis is

including the approximate 0.9nV noise of a 50Ω source R, that

noise is assumed to be divided down by 2 to the input of the

transformer, which explains the total input referred noise

showing up as less than just a 50Ω resistor. The total output

differential noise goes below 9nV/√Hz at the higher gains

settings using this input transformer technique. For even lower

noise, consider the ISL55210 where the input R element is

generally not required. In that case, simply setting R to the

desired input Z and adjusting R to the desired gain will give an

output noise that is slightly lower than shown previously for the

Most interfaces will also include an interstage noise power

bandlimiting filter between the amplifier and the ADC. This filter

needs to be designed considering the loading of the amplifier,

any V level shifting that needs to take place, the filter shape,

CM

and this Icm issue into the ADC input pins. Here are 4 example

topologies suitable for different situations.

1. AC-coupled, broadband RLC interstage filter design. This

approach lets the amplifier operate at its desired output

common mode, then provides the ADC common mode

voltage and current through a bias path as part of the filters

T

G

F

designs last stage R values. The V is set to include the IR loss

from that voltage to the ADC inputs due to the I

b

current.

CM

same input transformer due to the removal of the R element.

T

FN7868.0

June 21, 2011

15

ISL55211

3. AC-coupled with output side transformer. This design includes

ADC

an output side transformer, very similar to ADC

L

characterization circuits. This approach allows a slightly lower

amplifier output swing (if N>1 is used) and very easy 2nd or

3rd order low pass responses to be implemented. It also

S

I_CM

+3.3V

1.2V

IN+

C

B

R

S

ISL55211

provides the I and V bias to the ADC through the

CM CM

C

T

R

T

transformer centertap. This approach would be attractive for

higher ADC input swing targets and more aggressive noise

power bandwidth control needs. Figure 1 on page 1 is an

example showing this approach.

C

IN

R

IN

V

B

V

CM1

C

B

R

S

R

T

C

T

L

S

IN-

ADC

I_CM

+3.3V

V_CM2

I_CM

R >R

IN+

t

s

V −I_cm×R =V

C

B

b

t

cm2

R

S

ISL55211

R

T

1:N

C

T

FIGURE 36. AC- COUPLED BROADBAND RLC INTERSTAGE FILTER

DESIGN

C

IN

R

IN

1.2V

V

CM1

C

B

R

S

2. AC-coupled, higher frequency range interstage filter design.

C

T

This design replaces the R resistors in Figure 35 with large

valued inductors and implements the filter just using shunt

T

R

T

IN-

resistors at the end of the RLC filter. In this case, the ADC V

CM

I_CM

can be tied to the centerpoint of the bias path inductors (very

much like a Bias-T) to provide the common mode voltage and

current to the ADC inputs. These bias inductors do limit the

low frequency end of the operation where, with 1µH values,

operation from 10MHz to 200MHz is supported using the

approach of Figure 37.

R< 30

T

V

CM2

2I_CM

FIGURE 38. AC-COUPLED WITH OUTPUT SIDE TRANSFORMER

4. DC-coupled with ADC V and I provided from the

CM CM

ADC

amplifier. Here, DC to very high frequency interstage low pass

filter can be provided. Again, the R element must be low to

reduce the IR drop from the V of the converter, which now

shows up on the output of the ISL55211, to the ADC input

pins.

S

L

S

I_CM

CM

+3.3V

1.2V

IN+

C

B

R

S

ISL55211

L

P

C

T

ADC

C

IN

R

IN

R

T

L

S

+3.3V

I_CM

V

CM1

IN+

C

B

R

S

L

P

C

T

L

S

R

S

ISL55211

IN-

C

T

C

IN

R

T

I_CM

R

IN

V

CM2

V

CM

Lp

>> L

s

R

S

L

S

C

T

IN-

FIGURE 37. AC-COUPLED, HIGHER FREQUENCY RLC INTERSTAGE

FILTER DESIGN

Rs ≤30Ω

I_CM

V_CM2

FIGURE 39. DC-COUPLED WITH A V

VOLTAGE FROM THE ADC

CM

FN7868.0

June 21, 2011

16

ISL55211

The primary test purpose for this board is to implement different

Layout Considerations

interstage differential passive filters intended for the ADC

interface along with the ADC input impedances. The board is

delivered with only the output R's loaded to give a 200Ω

differential load. This is done using the two 85Ω resistors as R9

The ISL55211 pinout is organized to isolate signal I/O along one

axis of the package with ground, power and control pins on the

other axis. Ground and power should be planes coming into the

upper and lower sides of the package (see “Pin Configuration” on

page 2). The signal I/O should be laid out as tight as possible.

and R , then the 4 0Ω elements (R , R , R , and R ) and

10 10 12 24 25

finally the two shunt elements R and R set to 35.5Ω.

13 14

Including the 50Ω measurement load on the output side of the

1:1 transformer reflecting in parallel with the two 35Ω resistors

takes the nominal AC shunt impedance to 71Ω||50Ω = 29.3Ω.

This adds to the two 85Ω series output elements to give a total

load across the amplifier outputs of 170Ω + 29.3Ω = 199.3Ω.

The ground pins and package backside metal contact should be

connected into a good ground plane. The power supply should

have both a large values electrolytic cap to ground, then a high

frequency ferrite beads, then 0.01µF SMD ceramic caps at the

supply pins. Some improvement in HD2 performance may be

experienced by placing and X2Y cap between the two Vs+ pins

and ground underneath the package on the board back side. This

is 3 terminal device that is included in the Evaluation board

layout.

To test a particular ADC interface RLC filter and converter input

impedance, replace R and R with RF chip inductors, load

11 12

C

and C with the specified ADC input capacitance and R

11 26

10

with the specified ADC differential input R. With these loaded,

the remaining resistive elements (R , R , R , R ) are set to

24 25 13 14

Evaluation Board (Rev. C)

hit a desired total parallel impedance to implement the desired

filter (must be < than the ADC input differential R since that sits

in parallel with any "external" elements) and achieve a 250Ω

source looking into each side of the tap point transformer.

Test circuit 1 (Figure 29) is implemented on an Evaluation Board

available from Intersil. This board includes a number of optional

features that not populated as the board is delivered. The full

Evaluation circuit is shown in Figure 40 where unloaded

(optional) elements are shown in green.

This Evaluation board includes a user's manual showing a

number of example circuits and tested results and is available on

the Intersil web site on the ISL55211 Product Information Page.

The nominal supply voltage for the board and device is a single

3.3V supply. From this, the ISL55210, ISL55211 generates an

internal common mode voltage of approximately 1.2V. That

voltage can be overridden by populating the two resistors and

potentiometer shown as R to R above.

19 21

FN7868.0

June 21, 2011

17

ISL55211

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest revision.

DATE

REVISION

FN7868.0

CHANGE

June 21, 2011

Initial Release

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page

on intersil.com: ISL55211

To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

FITs are available from our website at: http://rel.intersil.com/reports/search.php

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7868.0

June 21, 2011

19

ISL55211

Package Outline Drawing

L16.3x3D

16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 0, 3/10

4X 1.50

3.00

6

A

12X 0.50

PIN #1

INDEX AREA

B

13

16

6

PIN 1

INDEX AREA

12

1

1.60 SQ

4

9

(4X)

0.15

0.10 M C A B

16X 0.23±0.05

8

5

16X 0.40±0.10

TOP VIEW

4

BOTTOM VIEW

SEE DETAIL “X”

0.10 C

C

0.75 ±0.05

0.08 C

SIDE VIEW

(12X 0.50)

(2.80 TYP) ( 1.60)

(16X 0.23)

5

0 . 2 REF

C

(16X 0.60)

0 . 02 NOM.

0 . 05 MAX.

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.25mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

JEDEC reference drawing: MO-220 WEED.

7.

FN7868.0

June 21, 2011

20


型号：	ISL55211IRTZ-EVAL1Z
厂家：	Intersil
描述：	Wideband, Low Noise, Low Distortion, Fixed Gain, Differential Amplifier 宽带，低噪声，低失真，固定增益差分放大器放大器
文件：	总20页 (文件大小：1168K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL55211IRTZ-EVAL1Z [INTERSIL]

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