ISL59530_07_技术文档

ISL59530

®

Data Sheet

February 7, 2007

FN6220.3

16x16 Video Crosspoint

Features

The ISL59530 is a 300MHz 16x16 Video Crosspoint Switch.

Each input has an integrated DC-restore clamp and an input

buffer. Each output has a fast On-Screen Display (OSD)

switch (for inserting graphics or other video) and an output

buffer. The switch is non-blocking, so any combination of

inputs to outputs can be chosen, including one channel

driving multiple outputs. The Broadcast Mode directs one

input to all 16 outputs. The output buffers can be individually

controlled through the SPI interface, the gain can be

programmed to x1 or x2, and each output can be placed into

a high impedance mode.

• 16x16 non-blocking switch with buffered inputs and outputs

• 300MHz typical bandwidth

• 0.025%/0.05° dG/dP

• Output gain switchable x1 or x2 for each channel

• Individual outputs can be put in a high impedance state

• -90dB Isolation at 6MHz

• SPI digital interface

• Single +5V supply operation

• Pb-free plus anneal available (RoHS compliant)

The ISL59530 offers a typical -3dB signal bandwidth of

300MHz. Differential gain of 0.025% and differential phase of

0.05°, along with 0.1dB flatness out to 50MHz, make the

ISL59530 suitable for many video applications.

Applications

• Security camera switching

• RGB routing

The switch matrix configuration and output buffer gain are

programmed through an SPI/QSPI™-compatible three-wire

serial interface. The ISL59530 interface is designed to

facilitate both fast updates and initialization. On power-up, all

outputs are high impedance to avoid output conflicts.

• HDTV routing

Ordering Information

TAPE &

REEL

PKG.

DWG. #

The ISL59530 is available in a 356 ball BGA package and

specified over an extended -40°C to +85°C temperature range.

PART NUMBER

PACKAGE

ISL59530IKZ (Note)

-

356 Ld PBGA (Pb-free) V356.27x27

The single-supply ISL59530 can accommodate input signals

from 0V to 3.5V and output voltages from 0V to 3.8V. Each

input includes a clamp circuit that restores the input level to

an externally applied reference in AC-coupled applications.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100% matte

tin plate termination finish, which are RoHS compliant and compatible

with both SnPb and Pb-free soldering operations. Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

The ISL59531 is a fully differential input version of this device.

Block Diagram

V_S

VOVERn

OVERn

16 OVERLAY

VIDEO INPUTS

16 OVERLAY

CHANNEL

ENABLES

V_REF

CLAMP

16 VIDEO

OUTPUTS

OUT0 – OUT15

16 VIDEO

INPUTS

IN0 – IN15

16x16

SWITCH

MATRIX

CLAMP

AV

X1, X2

OUTPUT

ENABLE

CLAMP

ENABLE

SDI

V_SDO

SDO

SPI INTERFACE AND

CONTROL REGISTERS

SCLK

SLATCH

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL59530

Pinout

ISL59530

(356 LD BGA)

TOP VIEW

A

B

C

D

E

F

In12

In13

In14

In15

Over15

Over14

Out14

Out13

Over13

Vover13

Out12

Over12

Vover12

Out15

Vover15

Vover14

In11

In10

In9

In8

In7

In6

In5

In4

Vover11 Out11 Over11

Vover10 Out10 Over10

Vover9 Over9 Out9

Vover8 Over8 Out8

V

Vs

SDO

GND GND GND GND GND GND GND GND GND GND

G

H

J

SDO

RESET

SLATCH

SCLK

K

L

SDI

M

N

P

R

T

V

Vover7 Out7

Vover6 Out6

Over7

Over6

REF

Vover5 Over5 Out5

U

V

W

Y

Vs

NC

Vover0

Vover1

Vover2

Vover3

Vover4 Over4 Out4

Over0

Over1

Out2

Out3

In3

In2

In1

In0

Out0

Out1

Over2

Over3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

= NO BALLS

BALLS LABELLED “NC” SHOULD BE LEFT UNCONNECTED - DO NOT TIE THEM TO

GROUND!

BALLS WITH NO LABELS MAY BE TIED TO GROUND TO SLIGHTLY REDUCE

THERMAL IMPEDANCE.

FN6220.3

February 7, 2007

2

ISL59530

Absolute Maximum Ratings (T = +25°C)

A

Supply Voltage between V and GND. . . . . . . . . . . . . . . . . . . . 6.0V

S

Maximum power supply (V ) slew rate . . . . . . . . . . . . . . . . . . 1V/μs

ESD Classification

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V

Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

S

Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 40mA

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests

are at the specified temperature and are pulsed tests, therefore: T = T = T

A

J

C

DC Electrical Specifications

V = 5V, R = 150Ω unless otherwise noted.

S L

PARAMETER

DESCRIPTION

Power Supply Voltage

CONDITION

MIN

4.5

1.2

0.98

1.96

-1.5

0

TYP

MAX

5.5

UNIT

V

S

V

Power Supply for SDO output pin

Gain

Establishes serial data output high level

5.5

V

SDO

A

= 1

= 2

= 1

= 2

= 1

= 2

1

2

1.02

2.04

+1.5

3.5

V/V

%

V

A

V

GM

Gain Matching (to average of all other

outputs)

A

V

A

%

V

Video Input Voltage Range

Video Output Voltage Range

Input Bias Current

A

V

IN

V

A

0.1

-10

0.5

3.8

V

OUT

V

I

Clamp function disabled (DC coupled inputs)

-5

2

1

µA

mV

mA

dB

mA

B

Clamp function enabled, V = V

IN

+ 0.5V

10

REF

I

V

Input Current

Clamp function enabled

-110

8

REF

V

Output Offset Voltage

A

= 1

= 2

-20

-70

60

35

40

OS

V

A

-10

108

31

V

I

Output Current

Sourcing, R = 10Ω to GND

L

OUT

Sinking, R = 10Ω to 2.5V

24

L

PSRR

Power Supply Rejection Ratio

Supply Current

A

= 1 and A = 2

50

70

V

I

Enabled, all outputs enabled, no load current

Enabled, all outputs disabled, no load current

Disabled

275

135

1.2

320

165

1.8

360

195

2.4

S

AC Electrical Specifications

V = 5V, R = 150Ω unless otherwise noted.

S L

PARAMETER

BW -3dB

BW 0.1dB

SR

DESCRIPTION

3dB Bandwidth

CONDITION

MIN

TYP

300

50

MAX

UNIT

MHz

V/µs

ns

V

= 200mV , A = 2

V

OUT

P-P

0.1dB Bandwidth

Slew Rate

= 200mV , A = 2

P-P

V

= 2V , A = 2

300

520

12

740

P-P

V

T

Settling Time to 0.1%

Switching Glitch, Peak

Overlay Delay Time

Diff Gain

= 2V , A = 2

S

P-P

V

Glitch

A

= 1

40

mV

V

T

From OVER rising edge to output transition

6

ns

over

dG

dP

Xt

A

= 2, R = 150Ω

0.025

0.05

-85

18

%

V

L

Diff Phase

A

= 2, R = 150Ω

°

V

L

Hostile Crosstalk

Input Referred Noise Voltage

6MHz

dB

V

nV/√Hz

N

FN6220.3

February 7, 2007

3

ISL59530

Pin Descriptions (Continued)

Pin Descriptions

NAME

NUMBER

P20

M20

K19

H19

F20

D20

B17

B15

A13

A11

DESCRIPTION

Overlay Logic Control (with pulldown)

Overlay Video Input

NAME

NUMBER

DESCRIPTION

Crosspoint Video Input

OVER6

IN0

Y8

OVER7

IN1

Y6

Crosspoint Video Input

OVER8

IN2

Y4

Crosspoint Video Input

OVER9

IN3

Y2

Crosspoint Video Input

OVER10

OVER11

OVER12

OVER13

OVER14

OVER15

VOVER0

VOVER1

VOVER2

VOVER3

VOVER4

VOVER5

VOVER6

VOVER7

VOVER8

VOVER9

VOVER10

VOVER11

VOVER12

VOVER13

VOVER14

VOVER15

IN4

V1

Crosspoint Video Input

IN5

T1

Crosspoint Video Input

IN6

P1

Crosspoint Video Input

IN7

M1

Crosspoint Video Input

IN8

K1

Crosspoint Video Input

IN9

H1

Crosspoint Video Input

V10

V12

V14

V16

V18

T18

P18

M18

K18

H18

F18

D18

C17

C15

C13

C11

M3

IN10

F1

Crosspoint Video Input

Overlay Video Input

IN11

D1

Crosspoint Video Input

Overlay Video Input

IN12

A1

Crosspoint Video Input

Overlay Video Input

IN13

A3

Crosspoint Video Input

Overlay Video Input

IN14

A5

Crosspoint Video Input

Overlay Video Input

IN15

A7

Crosspoint Video Input

Overlay Video Input

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT10

OUT11

OUT12

OUT13

OUT14

OUT15

OVER0

OVER1

OVER2

OVER3

OVER4

OVER5

Y10

Y12

W14

W16

V20

T20

P19

M19

K20

H20

F19

D19

A17

A15

B13

B11

W10

W12

Y14

Y16

V19

T19

Crosspoint Video Output

Overlay Logic Control (with pulldown)

Overlay Video Input

V

DC-restore clamp reference input. In an

AC-coupled configuration (DC-Restore

clamp enabled), the sync tip of

composite video inputs will be restored

to this level. Set to 0.3 to 0.7V for

optimum performance.

REF

In an DC-coupled configuration

(DC-Restore clamp disabled), this pin

should be tied to ground.

Do not let the V

pin float! A

REF

pin drifts high and, if the

floating V

REF

clamp function is enabled, will cause all

of the outputs to simultaneously try to

drive ~4V DC into their 150Ω loads.

SLATCH

J3

Serial Latch. Serial data is latched into

ISL59530 on rising edge of SLATCH.

FN6220.3

February 7, 2007

4

ISL59530

Pin Descriptions (Continued)

NAME

SCLK

SDI

NUMBER

DESCRIPTION

Serial data clock

Serial data input

K3

L3

SDO

G3

Serial data output. Can be tied to SDI of

another ISL59530 to enable daisy-

chaining of multiple devices.

RESET

H3

D3

Reset input. Pull high then low to reset

device, but not needed in normal opera-

tion. Tie to ground in final application.

V

Power supply for SDO pin. Tie to +5V

for a 0V to 5V SDO output signal swing.

SDO

V

+5V power supply

Ground

S

GND

NC

No Connect - Do not electrically

connect to anything, including ground.

FN6220.3

February 7, 2007

5

ISL59530

Typical Performance Curves

15pF

V

=+5V

= 2

= 100Ω

V =+5V

s

S

A

= 1

V

L

R

= 100Ω

L

10pF

INPUT_CH 0

OUTPUT_CH 0

INPUT_CH 0

10pF

OUTPUT_CH 0

4.7pF

0pF

4.7pF

0pF

FIGURE 1. FREQUENCY RESPONSE - VARIOUS C , A = 1,

FIGURE 2. FREQUENCY RESPONSE - VARIOUS C , A = 2,

L V

L

V

MUX MODE

V

=+5V

= 2

= 0

S

V

=+5V

= 1

= 0pF

S

A

V

A

V

C

L

C

L

INPUT_CH 0

OUTPUT_CH 0

150Ω

INPUT_CH 0

OUTPUT_CH 0

150Ω

50Ω

500Ω

1.03kΩ

500Ω

1.03kΩ

FIGURE 3. FREQUENCY RESPONSE - VARIOUS R , A = 1,

FIGURE 4. FREQUENCY RESPONSE - VARIOUS R , A = 2,

L V

L

V

MUX MODE

OVERLAY MODE

A

= 1

= 100Ω

A

R

= 2

= 100Ω

V

L

R

L

C =0pF

INPUT_CH 0

L

INPUT_CH 0

OUTPUT_CH 15

FIGURE 5. FREQUENCY RESPONSE - OVERLAY INPUT,

= 1

FIGURE 6. FREQUENCY RESPONSE - OVERLAY INPUT,

= 2

A

V

FN6220.3

February 7, 2007

6

ISL59530

Typical Performance Curves (Continued)

V

=+5V

= 2

15pF

10pF

S

15pF

10pF

A

V

R

= 100Ω

L

INPUT_CH 0

OUTPUT_CH 0

4.7pF

V

=+5V

= 1

S

A

V

0pF

R

= 100Ω

L

INPUT_CH 0

OUTPUT_CH 0

FIGURE 7. FREQUENCY RESPONSE - VARIOUS C , A = 1,

FIGURE 8. FREQUENCY RESPONSE - VARIOUS C , A = 2,

L V

L

V

BROADCAST MODE

V

A

=+5V

= 2

= 0pF

V

=+5V

= 1

S

V

S

A

V

50Ω

C

= 0pF

L

150Ω

INPUT_CH 0

OUTPUT_CH 0

150Ω

50Ω

OUTPUT_CH 0

503Ω

1.03kΩ

FIGURE 9A. FREQUENCY RESPONSE - VARIOUS R , A = 1,

FIGURE 10. FREQUENCY RESPONSE - VARIOUS R , A = 2,

L

V

L

V

BROADCAST MODE

A

= 2

= 100Ω

= 0

A

= 1

= 100Ω

= 0

ADJACENT

INPUT_CH14

OUTPUT_CH15

V

ADJACENT

INPUT_CH14

OUTPUT_CH15

R

C

L

C

ALL HOSTILE

INPUT_CH0

OUTPUT_CH15

ALL HOSTILE

INPUT_CH0

OUTPUT_CH15

FIGURE 11. CROSSTALK - A = 1

V

FIGURE 12. CROSSTALK - A = 2

V

FN6220.3

February 7, 2007

7

ISL59530

Typical Performance Curves (Continued)

THD

V

=+5V

S

A =2

V

R =100Ω

L

INPUT_CH 1

OUTPUT_CH1

F

= 1MHz

IN

2nd HD

V

=+5V

S

2nd HD

A =2

V

R =100Ω

L

INPUT_CH 1

3rd HD

OUTPUT_CH 1

3rd HD

V

=2V

OP-P

FIGURE 13. HARMONIC DISTORTION vs FREQUENCY

FIGURE 14. HARMONIC DISTORTION vs V

OUT_P-P

FIGURE 15. DISABLED OUTPUT IMPEDANCE

FIGURE 16. ENABLED OUTPUT IMPEDANCE

MUX MODE

A

R

= 1

= 100Ω

V

L

INPUT_CH 0

OUTPUT_CH 0

FALL TIME

2.44ns

RISE TIME

2.42ns

MUX MODE

A

= 1

= 100Ω

V

R

L

INPUT_CH 0

OUTPUT_CH 0

TIME (ns)

FIGURE 17. RISE TIME - A = 1

V

FIGURE 18. FALL TIME - A = 1

V

FN6220.3

February 7, 2007

8

ISL59530

Typical Performance Curves (Continued)

MUX MODE

A

= 2

= 100Ω

V

R

L

INPUT_CH 0

FALL TIME

2.40ns

OUTPUT_CH 0

RISE TIME

2.32ns

MUX MODE

A

= 2

= 100Ω

V

R

L

INPUT_CH 0

OUTPUT_CH 0

TIME (ns)

FIGURE 19. RISE TIME - A = 2

FIGURE 20. FALL TIME - A = 2

V

MUX MODE

= 1

A

V

R =100Ω

L

INPUT_CH 0

OUTPUT_CH 0

SLEW RATE

-395V/µs

SLEW RATE

405V/µs

MUX MODE

= 1

A

V

R =100Ω

L

INPUT_CH 0

OUTPUT_CH 0

TIME (ns)

FIGURE 21. RISING SLEW RATE - A = 1

V

FIGURE 22. FALLING SLEW RATE - A = 1

V

MUX MODE

A

= 2

V

R =100Ω

L

INPUT_CH 0

OUTPUT_CH 0

SLEW RATE

-420V/µs

SLEW RATE

430V/µs

MUX MODE

A

= 2

V

R =100Ω

L

INPUT_CH 0

OUTPUT_CH 0

TIME (ns)

FIGURE 23. RISING SLEW RATE - A = 2

V

FIGURE 24. FALLING SLEW RATE - A = 2

V

FN6220.3

February 7, 2007

9

ISL59530

Typical Performance Curves (Continued)

OUTPUT

OVERLAY

LOGIC

INPUT

OVERLAY

LOGIC

INPUT

FIGURE 25. OVERLAY SWITCH TURN-ON DELAY TIME

FIGURE 26. OVERLAY SWITCH TURN-OFF DELAY TIME

A

= 2

= 100Ω

V

R

L

INPUT_CH 1

OUTPUT_CH 1

OSC = 40mV

A

= 2

= 100Ω

V

R

L

INPUT_CH 1

OUTPUT_CH 1

OSC = 40mV

FIGURE 27. DIFFERENTIAL GAIN, A = 2

V

FIGURE 28. DIFFERENTIAL PHASE, A = 2

V

A

= 2

= 100Ω

A

= 2

= 100Ω

V

R

L

INPUT_CH 1

OUTPUT_CH 1

OSC = 40mV

INPUT_CH 1

OUTPUT_CH 1

OSC = 40mV

FIGURE 29. DIFFERENTIAL GAIN, A = 2

V

FIGURE 30. DIFFERENTIAL PHASE, A = 2

V

FN6220.3

February 7, 2007

10

ISL59530

Typical Performance Curves (Continued)

A

= 1

= 100Ω

V

R

L

INPUT_CH 1

OUTPUT_CH1

OSC = 40mV

A

= 1

= 100Ω

V

R

L

INPUT_CH 1

OUTPUT_CH 1

OSC = 40mV

FIGURE 31. DIFFERENTIAL GAIN, A = 1

V

FIGURE 32. DIFFERENTIAL PHASE, A = 1

V

A

R

= 1

= 100Ω

A

= 1

= 100Ω

V

L

V

R

L

INPUT_CH 1

OUTPUT_CH 1

OSC = 40mV

INPUT_CH 1

OUTPUT_CH 1

OSC = 40mV

FIGURE 33. DIFFERENTIAL GAIN, A = 1

V

FIGURE 34. DIFFERENTIAL GAIN, A = 1

V

A

= 2

= 100Ω

A

= 2

= 100Ω

V

R

L

INPUT_CH 01

OUTPUT_CH 15

OSC = 40mV

INPUT_CH 01

OUTPUT_CH 15

OSC = 40mV

FIGURE 35. DIFFERENTIAL GAIN, A = 2

V

FIGURE 36. DIFFERENTIAL PHASE, A = 2

V

FN6220.3

February 7, 2007

11

ISL59530

Typical Performance Curves (Continued)

A

= 2

= 100Ω

V

R

L

INPUT_CH 01

OUTPUT_CH 15

OSC = 40mV

A

= 2

= 100Ω

V

R

L

INPUT_CH 01

OUTPUT_CH 15

OSC = 40mV

FIGURE 37. DIFFERENTIAL GAIN, A = 2

FIGURE 38. DIFFERENTIAL PHASE, A = 2

V

A

= 1

= 100Ω

V

R

L

INPUT_CH 01

OUTPUT_CH 15

OSC = 40mV

A

= 1

= 100Ω

V

R

L

INPUT_CH 01

OUTPUT_CH 15

OSC = 40mV

FIGURE 39. DIFFERENTIAL GAIN, A = 1

FIGURE 40. DIFFERENTIAL PHASE, A = 1

V

A

= 1

= 100Ω

A

R

= 1

= 100Ω

V

L

R

L

INPUT_CH 01

OUTPUT_CH 15

OSC = 40mV

INPUT_CH 01

OUTPUT_CH 15

OSC = 40mV

FIGURE 41. DIFFERENTIAL GAIN, A = 1

V

FIGURE 42. DIFFERENTIAL PHASE, A = 1

V

FN6220.3

February 7, 2007

12

ISL59530

Typical Performance Curves (Continued)

A

= 2

= 100Ω

V

R

L

INPUT_CH 01

OUTPUT_CH 01

OSC = 40mV

A

R

= 2

= 100Ω

V

L

INPUT_CH 01

OUTPUT_CH 01

OSC = 40mV

FIGURE 43. DIFFERENTIAL GAIN, OVERLAY, A = 2

FIGURE 44. DIFFERENTIAL PHASE, OVERLAY, A = 2

V

A

= 1

= 100Ω

V

R

L

INPUT_CH 01

OUTPUT_CH 01

OSC = 40mV

A

= 1

= 100Ω

V

R

L

INPUT_CH 01

OUTPUT_CH 01

OSC = 40mV

FIGURE 45. DIFFERENTIAL GAIN, OVERLAY, A = 1

V

FIGURE 46. DIFFERENTIAL PHASE, OVERLAY, A = 1

V

FN6220.3

February 7, 2007

13

ISL59530

3dB Bandwidth, MUX Mode, A = 1, R = 100Ω [MHz]

V

L

INPUT CHANNELS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

0

1

255

244

257

264

255

253

247

253

255

241

235

223

220

211

199

193

229

217

229

210

222

221

224

190

180

186

183

174

176

171

174

175

169

168

164

161

160

222

169

168

171

175

177

178

184

187

188

186

188

192

194

197

152

233

190

212

189

207

193

166

160

169

171

167

173

170

178

183

182

185

186

185

189

193

238

2

235

204

3

217

219

4

220

202

5

218

237

6

226

230

231

210

157

163

168

165

7

227

236

235

240

218

239

223

228

236

240

241

223

242

219

222

217

235

211

213

8

9

10

11

12

13

14

15

236

230

207

185

225

217

209

202

205

198

214

207

224

223

212

217

197

216

186

177

225

3dB Bandwidth, MUX Mode, A = 2, R = 100Ω [MHz]

V

L

INPUT CHANNELS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

0

1

295

268

277

279

269

263

259

263

262

253

246

241

236

233

227

316

290

397

384

405

395

220

211

216

213

201

196

201

203

194

187

184

182

178

183

288

183

192

196

192

196

205

212

210

215

213

216

220

223

240

299

250

385

234

396

291

188

183

196

192

200

211

216

214

216

217

225

230

293

2

300

289

3

408

392

4

391

402

5

407

298

6

404

398

394

388

283

407

411

410

7

411

407

307

308

402

387

383

412

307

300

402

403

387

385

413

415

398

394

8

9

10

11

12

13

14

15

417

293

385

367

412

400

412

396

391

379

272

244

419

413

279

274

396

385

407

230

324

276

FN6220.3

February 7, 2007

14

ISL59530

3dB Bandwidth, Broadcast Mode, A = 1, R = 100Ω [MHz]

V

L

INPUT CHANNELS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

0

1

215

214

210

212

206

203

201

204

202

196

194

193

191

189

187

198

195

183

184

188

172

178

174

171

169

165

163

167

164

160

157

156

151

153

151

152

153

157

159

167

171

170

169

171

174

175

178

145

157

145

140

146

144

158

159

164

170

175

174

178

174

178

181

2

188

147

3

178

143

4

174

150

5

177

161

6

156

160

161

157

151

156

160

7

187

182

183

170

172

170

171

175

176

168

172

157

160

151

155

158

161

154

159

8

9

10

11

12

13

14

15

170

169

161

155

160

167

162

157

156

160

170

167

164

166

172

173

162

164

161

149

167

179

3dB Bandwidth, Broadcast Mode, A = 2, R = 100Ω [MHz]

V

L

INPUT CHANNELS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

0

1

234

232

228

229

223

219

217

220

218

220

212

211

209

208

205

216

215

209

199

204

205

190

196

193

189

191

186

183

181

183

184

181

176

174

170

167

166

169

171

175

177

178

184

187

188

186

188

192

194

197

160

172

162

158

163

161

178

182

183

189

193

192

195

196

198

2

204

164

3

196

163

4

193

168

5

192

177

6

174

175

177

174

167

173

178

7

204

205

198

199

189

190

191

192

193

184

188

174

178

169

173

174

178

172

178

8

9

10

11

12

13

14

15

185

187

179

171

177

184

179

172

176

179

187

184

181

185

191

181

182

176

160

185

195

FN6220.3

February 7, 2007

15

ISL59530

Block Diagram

V_S

VOVERn

OVERn

16 OVERLAY

VIDEO INPUTS

16 OVERLAY

CHANNEL

ENABLES

V_REF

CLAMP

16 VIDEO

OUTPUTS

OUT0 – OUT15

16 VIDEO

INPUTS

IN0 – IN15

16x16

SWITCH

MATRIX

CLAMP

AV

X1, X2

OUTPUT

ENABLE

CLAMP

ENABLE

SDI

SCLK

V_SDO

SDO

SPI INTERFACE AND

CONTROL REGISTERS

SLATCH

first and the MSB (bit 15) is loaded last (see the Serial

Timing Diagram). After all 16 bits of data have been loaded

into the shift register, the rising edge of SLATCH updates the

internal registers.

General Description

The ISL59530 is a 16x16 integrated video crosspoint switch

matrix with input and output buffers and On-Screen Display

(OSD) insertion. This device operates from a single +5V

supply. Any output can be generated from any of the 16 input

video signal sources, and each output can have OSD

information inserted through a dedicated, fast 2:1 mux

located before the output buffer. There is also a Broadcast

mode allowing any one input to be broadcast to all 16

outputs. A DC restore clamp function enables the ISL59530

to AC-couple incoming video.

While the ISL59530 has an SDO (Serial Data Out) pin, it

does not have a register readback feature. The data on the

SDO pin is an exact replica of the incoming data on the SDI

pin, delayed by 15.5 SCLKs (an input bit is latched on the

rising edge of SLCK, and is output on SDO on the falling

edge of SLCK 15.5 SCLKs later). Multiple ISL59530’s can be

daisy-chained by connecting the SDO of one to the SDI of

the other, with SCLK and SLATCH common to all the daisy-

chained parts. After all the serial data is transmitted (16 bits *

n devices = 16*n SCLKs), the rising edge of SLATCH will

update the configuration registers of all n devices

simultaneously.

The ISL59530 offers a -3dB signal bandwidth of 300MHz.

Differential gain and differential phase of 0.025% and 0.05°

respectively, along with 0.1dB flatness out to 50MHz make

this ideal for multiplexing composite NTSC and PAL signals.

The switch matrix configuration and output buffer gain are

programmed through an SPI/QSPI™-compatible, three-wire

serial interface. The ISL59530 interface is designed to

facilitate both fast initialization and configuration changes.

On power-up, all outputs are initialized to the disabled state

to avoid output conflicts in the user’s system.

The Serial Timing Diagram and the Serial Timing

Parameters table on page 17show the timing requirements

for the serial interface.

Digital Interface

The ISL59530 uses a serial interface to program the

configuration registers. The serial interface uses three

signals (SCLK, SDI, and SLATCH) for programming the

ISL59530, while a fourth signal (SDO) enables optional

daisy-chaining of multiple devices. The serial clock can run

at up to 5MHz (5Mbits/s).

Serial Interface

The ISL59530 is programmed through a simple serial

interface. Data on the SDI (serial data input) pin is shifted

into a 16-bit shift register on the rising edge of the SCLK

(serial clock) signal. (This is continuously done regardless of

the state of the SLATCH signal.) The LSB (bit 0) is loaded

FN6220.3

February 7, 2007

16

ISL59530

Serial Timing Diagram

SLATCH

SLATCH falling edge timing/placement is a “don’t care.”

Serial data is latched only on rising edge of SLATCH.

t

SL

T

SCLK

t

HD

t

w

t

SD

B15

(MSB)

B0

(LSB)

SDI

B1

B2

B0

(LSB)

B0

B15

(previous)

B1

B2

SDO

(previous) (previous) (previous)

SDO = SDI delayed by 15.5 SCLKs to allow daisy-chaining of multiple ISL59530s. SDO changes on the falling edge of SCLK.

TABLE 1. SERIAL TIMING PARAMETERS

PARAMETER

RECOMMENDED OPERATING RANGE

DESCRIPTION

T

≥200ns

0.50 * T

≥20ns

SCLK period

t

Clock Pulse Width

Data Setup Time

Data Hold Time

W

t

SD

HD

t

≥20ns

t

≥20ns

Final SLCK rising edge (latching B15) to SLATCH rising edge

SL

Programming Model

The ISL59530 is configured by a series of 16-bit serial control words. The three MSBs (B15-13) of each serial word determine the

basic command:

TABLE 2. COMMAND FORMAT

B15

0

B14

0

B13

0

COMMAND

INPUT/OUTPUT: Maps input channels to output channels

OUTPUT ENABLE: Output enable for individual channels

GAIN SET: Gain (x1 or x2) for each channel

NUMBER OF WRITES

16 (1 channel per write)

4 (4 channels per write)

1

0

1

0

1

0

1

BROADCAST: Enables broadcast mode and selects the input channel to be

broadcast to all output channels

1

CONTROL: Clamp on/off, operational/standby mode, and global output

enable/disable

1

Mapping Inputs to Outputs

Inputs are mapped to their desired outputs using the input/output control word. Its format is:

TABLE 3. INPUT/OUTPUT WORD

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

0

I

0

O

0

3

2

1

0

3

2

1

I :I form the 4-bit word indicating the input channel (0 to 15), and O :O determine the output channel which that input channel

3 0

3

0

will map to. One input can be mapped to one or multiple outputs. To fully program the ISL59530, 16 INPUT/OUTPUT words must

be transmitted - one for each input channel.

FN6220.3

February 7, 2007

17

ISL59530

Enabling Outputs

The output enable control word is used to enable individual outputs. There are 16 channels to configure, so this is accomplished by

writing 4 serial words, each controlling a bank of four outputs at a time. The bank is selected by bits B9 and B8. The output enable

control word format is:

TABLE 4. OUTPUT ENABLE FORMAT

B15 B14 B13 B12 B11 B10

B9

0

B8

0

B7

B6

B5

B4

B3

B2

B1

B0

0

1

0

O

3

7

2

1

5

9

0

4

8

0

1

6

1

0

O

11

15

10

14

1

O

12

13

Setting the O bit = 0 tri-states the output. Setting the O bit = 1 enables the output if the Global Output Enable bit is also set (the

N

individual output enable bits are ANDed with the Global Output Enable bit before they are sent to the output stage).

Setting the Gain

The gain of each output may be set to x1 or x2 using the Gain Set word. It is in the same format as the output enable control word:

TABLE 5. GAIN SET FORMAT

B15 B14 B13 B12 B11 B10

B9

0

B8

0

B7

B6

B5

B4

B3

B2

B1

B0

0

1

0

G

3

7

2

6

1

5

9

0

4

8

0

1

0

G

11

15

10

14

1

G

12

13

Set G = 0 for a gain of x1 or 1 for a gain of x2.

N

Broadcast Mode

The Broadcast Mode routes one input to all 16 outputs. The broadcast control word is:

TABLE 6. BROADCAST FORMAT

B15 B14 B13 B12 B11 B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Enable Broadcast

0

1

I

0

3

2

1

0: Broadcast Mode Disabled

1: Broadcast Mode Enabled

I :I form the 4 bit word indicating the input channel (0 to 15) to be sent to all 16 outputs. Set the Enable Broadcast bit (B0) = 1 to

3 0

enable Broadcast Mode, or to 0 to disable Broadcast Mode. When Broadcast Mode is disabled, the previous channel assignments

are restored.

Control Word

The ISL59530’s power-on reset disables all outputs and places the part in a low-power standby mode. To enable the device, the

following control word should be sent:

TABLE 7. CONTROL WORD FORMAT

B15 B14 B13 B12 B11 B10

B9

B8 B7 B6 B5 B4 B3 B2

B1

B0

1

0

Clamp

0

Power

Global Output Enable

0: Clamp Disabled

1: Clamp Enabled

0: Standby

0: All outputs tristated

1: Operational 1: Individual Output Enable bits control outputs

The Clamp bit enables the input clamp function, forcing the AC-coupled signal’s most negative point to be equal to V

.

REF

Note: The Clamp bit turns the DC-Restore clamp function on or off for all channels - there is no DC-Restore on/off control for

individual channels. The DC-Restore function only works with signals with sync tips (composite video). Signals that do not have

sync tips (the Chroma/C signal in s-video and the Pb, Pr signals in Component video), will be severely distorted if run through a

DC-Restore/clamp function.

FN6220.3

February 7, 2007

18

ISL59530

For this reason, the ISL59530 must be in DC-coupled

mode (Clamp Disabled) to be compatible with s-video

and component video signals.

Linear Operating Region

In addition to bandwidth optimization, to get the best linearity

the ISL59530 should be configured to operate in its most

linear operating region. Figure 48 shows the differential gain

curve. The ISL59530 is a single supply 5V design with its

most linear region between 0.1 and 2V. This range is fine for

most video signals whose nominal signal amplitude is 1V.

The most negative input level (the sync tip for composite

video) should be maintained at 0.3V or above for best

operation.

Bandwidth Considerations

Wide frequency response (high bandwidth) in a video

system means better video resolution. Four sets of

frequency response curves are shown in Figure 47.

Depending on the switch configurations, and the routing (the

path from the input to the output), bandwidth can vary

between 100MHz and 350MHz. A short discussion of the

trade-offs — including matrix configuration, output buffer

gain selection, channel selection, and loading — follows.

2

MUX, A = 2

V

0

MUX, A = 1

V

BROADCAST,

= 1

-2

A

V

BROADCAST,

= 2

-4

-6

A

V

-8

FIGURE 48. DIFFERENTIAL GAIN RESPONSE

-10

1

10

100

1000

In a DC-coupled application, it is the system designer’s

responsibility to ensure that the video signal is always in the

optimum range.

FREQUENCY (MHz)

FIGURE 47. FREQUENCY RESPONSE FOR VARIOUS MODES

In multiplexer mode, one input typically drives one output

channel, while in broadcast mode, one input drives all 16

outputs. As the number of outputs driven increases, the

parasitic loading on that input increases. Broadcast Mode is

the worst-case, where the capacitance of all 16 channels

loads one input, reducing the overall bandwidth. In addition,

due to internal device compensation, an output buffer gain of

x2 has higher bandwidth than a gain of x1. Therefore, the

highest bandwidth configuration is multiplexer mode (with

each input mapped to only one output) and an output buffer

gain of x2.

When AC coupling, the ISL59530’s Clamp (also called “DC

restore”) function automatically and continuously adjusts the

DC level so that the most negative portion of the video is

always equal to V

.

REF

A discussion of the benefits of the DC restoration function

begins by understanding the Clamp circuit shown in

Figure 49. The incoming video signal is typically terminated

into 75Ω, then AC coupled through C , at which point it is

1

connected to the base of the buffer’s diff pair. These

components form the video path.

The Clamp function consists of Q , D , Q , D , the two

The relative locations of the input and output channels also

have significant impact on the device bandwidth (due to the

layout of the ISL59530 silicon). When the input and output

channels are further away, there are additional parasitics as

a result of the additional routing, resulting in lower

bandwidth.

1

2

current sources, and the 3 switches controlled by the Clamp

Enable signal. The V voltage is level-shifted up two

REF

diode drops (Q and D ) to the base of Q . If the voltage at

1

2

the cathode of D goes below V

, Q and D will turn on,

2

REF

2

keeping the IN voltage at V

. If the voltage at IN is

x

REF

x

greater than V

, Q and D are off and the IN node is

REF

2

x

The bandwidth does not change significantly with resistive

loading as shown in the typical performance curves.

However several of the curves demonstrate that frequency

response is sensitive to capacitance loading. This is most

significant when laying out the PCB. If the PCB trace length

between the output of the crosspoint switch and the back-

termination resistor is not minimized, the additional parasitic

capacitance will result in some peaking and eventually a

reduction in overall bandwidth.

high impedance. This is how the clamp function forces the

lowest portion of the video signal (the sync tip) to always be

equal to or greater than V

.

REF

To make sure that the sync tip is always equal to (not equal

to or greater than) V , i is constantly sinking ~2µA of

current from C . This causes each sync tip to be slightly

lower voltage than the previous sync tip, causing Q and D

2

to turn on at each sync tip and raise the voltage to V

REF 1

1

2

. The

REF

2µA pulldown with a 0.1uF capacitor and a 15kHz HSYNC

frequency results in 1.3mV of “droop” across every line, or

FN6220.3

February 7, 2007

19

ISL59530

0.2% of the video signal. Because 1.3mV is only 0.2% of a

0.7V video signal, this droop is imperceptible to the human

eye.

0.086µF. Figure 50 shows the result of C = 0.1µF

IN

delivering acceptable droop and C = 0.001µF producing

IN

excessive droop.

When the clamp function is disabled in the CONTROL

register (Clamp = 0) to allow DC-coupled operation, the

I

current sinks/sources are disabled and the input

CLAMP

passes through the DC Restore block unaffected. In this

application V may be tied to GND.

REF

Overlay Operation

The ISL59530 features an overlay feature, that allows an

external video signal or DC level to be inserted in place of

Q₂

D₁

that output channel’s video. When the OVER signal is

N

D₂

taken high, the output signal on the OUT pin is replaced

N

V_REF

~0.4V

Q₁

with the signal on the VOVER pin.

N

(110µA)

C₂

D₃

There are several ways the overlay feature can be used.

0.1µF

SS12

Toggling the OVER signal at the frame rate or slower will

N

INPUT

TO

BUFFER

INx

VIDEO_IN

replace the video frame(s) on the OUT pin with the video

N

C₁

0.1µF

supplied on the VOVER pin.

N

R₁

75

Another option (for OSD displays, for example), is to put a

DC level on the VOVER line and toggle the OVER signal

N

at the pixel rate to create a monocolor image “overlaid” on

channel N’s output signal.

i₁

CLAMP

ENABLE

Finally, by enabling the OVER signal for some portion of

N

each line over a certain amount of lines, a picture-in-picture

function can be constructed.

FIGURE 49. DC RESTORE BLOCK DIAGRAM

This is how the video is “DC-restored” after being AC

coupled into the ISL59530. The sync tip voltage will be equal

to V on the right side of C , regardless of the DC level of

It’s important to note that the overlay inputs do not have the

DC Restore function previously described - the overlay

signal is DC coupled into the output. It is the system

designer’s responsibility to ensure that the video levels are

in the ISL59530’s linear region and matching the output

channel’s offset and amplitude. One easy way to do this is to

run the video to be overlaid through one of the ISL59530’s

REF

1

the video on the left side of C . Due to various sources of

1

offset in the actual clamp function, the actual sync tip level is

typically about 75mV higher than V

REF

(for V = 0.4V).

REF

unused channels and then into the VOVER input.

N

The OVER pins all have weak pulldowns, so if they are

N

unused, they can either be left unconnected or tied to GND.

Power Dissipation and Thermal Resistance

With a large number of switches, it is possible to exceed the

+150°C absolute maximum junction temperature under

certain load current conditions. Therefore, it is important to

calculate the maximum junction temperature for an

application to determine if load conditions or package types

need to be modified to assure operation of the crosspoint

switch in a safe operating area.

FIGURE 50. DC RESTORE VIDEO WAVEFORMS

The maximum power dissipation allowed in a package is

determined according to:

It is important to choose the correct value for C . Too small

IN

a value will generate too much droop, and the image will be

visibly darker on the right than on the left. A C value that is

too large may cause the clamp to fail to converge. The droop

T

– T

JMAX AMAX

IN

--------------------------------------------

PD

=

MAX

Θ

JA

(EQ. 1)

rate (dV/dt) is i /C volts/second. In general, the droop

1

IN

voltage should be limited to <1 IRE over a period of one line

of video; so for 1 IRE = 7mV, I = 10µA maximum, and an

B

NTSC waveform we will set C > 10µA*60µs/7mV =

IN

FN6220.3

February 7, 2007

20

ISL59530

Where:

• T

= Maximum junction temperature = +125°C

= Maximum ambient temperature = +85°C

JMAX

AMAX

• θ = Thermal resistance of the package

JA

The maximum power dissipation actually produced by an IC

is the total quiescent supply current times the total power

supply voltage, plus the power in the IC due to the load, or:

n

V

OUTi

R

Li

-----------------

PD

= V × I

+

(V – V ) ×

OUTi

MAX

S

SMAX

S

∑

(EQ. 2)

i = 1

Where:

• V = Supply voltage = 5V

S

• I

SMAX

= Maximum quiescent supply current = 360mA

= Maximum output voltage of the application = 2V

• V

• R

OUT

= Load resistance tied to ground = 150

LOAD

• n = 1 to 16 channels

n

V

OUTi

R

Li

-----------------

= 2.44W

PD

= V × I

+

(V – V ) ×

OUTi

MAX

S

SMAX

S

∑

(EQ. 3)

i = 1

The required θ to dissipate 2.44W is:

JA

T

– T

AMAX

JMAX

--------------------------------------------

= 16.4(°C/W)

Θ

=

JA

PD

MAX

(EQ. 4)

Table 8 shows θ thermal resistance results with a

JA

Wakefield heatsink and without heatsink and various airflow.

At the thermal resistance equation shows, the required

thermal resistance depends on the maximum ambient

temperature.

TABLE 8. θ THERMAL RESISTANCE [°C/W]

JA

Airflow [LFM]

0

250

14.3

7.0

500

13.0

6.0

750

12.6

4.7

No Heatsink

18

Wakefield

658-25AB

Heatsink

16.0

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6220.3

February 7, 2007

21


型号：	ISL59530_07
厂家：	Intersil
描述：	16x16 Video Crosspoint 16×16视频交叉点
文件：	总22页 (文件大小：1230K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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