ISL59910IRZ-T7 [INTERSIL]
Triple Differential Receiver/Equalizer; 三重差分接收器/均衡器型号: | ISL59910IRZ-T7 |
厂家: | Intersil |
描述: | Triple Differential Receiver/Equalizer |
文件: | 总12页 (文件大小:482K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISL59910, ISL59913
®
Data Sheet
December 15, 2006
FN6406.0
Triple Differential Receiver/Equalizer
Features
The ISL59910 and ISL59913 are triple channel differential
receivers and equalizers. They each contain three high speed
differential receivers with five programmable poles. The
outputs of these pole blocks are then summed into an output
buffer. The equalization length is set with the voltage on a
single pin. The ISL59910 and ISL59913 output can also be
put into a high impedance state, enabling multiple devices to
be connected in parallel and used in multiplexing application.
• 150MHz -3dB bandwidth
• CAT-5 compensation
- 100MHz @ 600 ft
- 135MHz @ 300 ft
• 108mA supply current
• Differential input range 3.2V
• Common mode input range -4V to +3.5V
• ±5V supply
The gain can be adjusted up or down on each channel by 6dB
using its V
control signal. In addition, a further 6dB of gain
GAIN
can be switched in to provide a matched drive into a cable.
• Output to within 1.5V of supplies
• Available in 28 Ld QFN package
The ISL59910 and ISL59913 have a bandwidth of 150MHz
and consume just 108mA on ±5V supply. A single input
voltage is used to set the compensation levels for the
required length of cable.
• Pb-free plus anneal available (RoHS compliant)
Applications
The ISL59910 is a special version of the ISL59913 that
decodes syncs encoded onto the common modes of three
pairs of CAT-5 cable by the EL4543. (Refer to the EL4543
datasheet for details.)
• Twisted-pair receiving/equalizer
• KVM (Keyboard/Video/Mouse)
• VGA over twisted-pair
• Security video
The ISL59910 and ISL59913 are available in a 28 Ld QFN
package and are specified for operation over the full -40°C to
+85°C temperature range.
Pinouts
ISL59910
(28 LD QFN)
TOP VIEW
ISL59913
(28 LD QFN)
TOP VIEW
VSMO_B
VOUT_B
VSPO_B
VSPO_G
VOUT_G
VSMO_G
VSMO_R
VOUT_R
1
2
3
4
5
6
7
8
22 VSP
VSMO_B
VOUT_B
VSPO_B
VSPO_G
VOUT_G
VSMO_G
VSMO_R
VOUT_R
1
2
3
4
5
6
7
8
22 VSP
21 VINM_B
20 VINP_B
19 VINM_G
18 VINP_G
17 VINM_R
16 VINP_R
15 VSM
21 VINM_B
20 VINP_B
19 VINM_G
18 VINP_G
17 VINM_R
16 VINP_R
15 VSM
THERMAL
PAD
THERMAL
PAD
EXPOSED DIEPLATE SHOULD BE CONNECTED TO -5V
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL59910, ISL59913
Ordering Information
PART
NUMBER
PART
MARKING
PKG.
DWG. #
TAPE & REEL
PACKAGE
28 Ld QFN
ISL59910IRZ
(Note)
59910 CRZ
-
MDP0046
(Pb-free)
ISL59910IRZ-T7
(Note)
59910 CRZ
59913 CRZ
59913 CRZ
7”
-
28 Ld QFN
(Pb-free)
MDP0046
MDP0046
MDP0046
ISL59913IRZ
(Note)
28 Ld QFN
(Pb-free)
ISL59913IRZ-T7
(Note)
7”
28 Ld QFN
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN6406.0
December 15, 2006
2
ISL59910, ISL59913
Absolute Maximum Ratings (T = +25°C)
Operating Conditions
A
Supply Voltage between V + and V -. . . . . . . . . . . . . . . . . . . . .12V
Maximum Continuous Output Current per Channel. . . . . . . . . 30mA
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
S
S
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . V - -0.5V to V + +0.5V
S
S
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications
V
+ = V + = +5V, V - = V - = -5V, T = +25°C, exposed die plate = -5V, unless otherwise specified.
SA
A
SA
A
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
SR
Bandwidth
Slew Rate
(See Figure 1)
= -1V to +1V, V = 0.39, V = 0,
150
1.5
MHz
V
kV/µs
IN
= 75 + 75Ω
G
C
R
L
THD
Total Harmonic Distortion
10MHz 2V
out, V = 1V, X2 gain, V = 0
-50
dBc
P-P
G
C
DC PERFORMANCE
V(V Offset Voltage
Channel-to-Channel Offset Matching X2 = high, no equalization
INPUT CHARACTERISTICS
CMIR Common-Mode Input Range
)
X2 = high, no equalization
-110
-140
-15
0
+110
+140
mV
mV
OUT OS
ΔV
OS
-4/+3.5
-110
V
O
Output Noise
V
= 0V, V = 0V, X2 = HIGH, R = 150Ω,
LOAD
dBm
NOISE
G
C
Input 50Ω to GND, 10MHz
Measured at 10kHz
Measured at 10MHz
10k || 10pF load
CMRR
CMRR
CMBW
Common-Mode Rejection Ratio
Common-Mode Rejection Ratio
CM Amplifier Bandwidth
CM Slew Rate
-80
-55
50
dB
dB
MHz
V/µs
fF
CM
Measured @ +1V to -1V
100
600
SLEW
INDIFF
INDIFF
INCM
C
R
C
R
Differential Input Capacitance
Differential Input Resistance
CM Input Capacitance
Capacitance V
to V
INP
INP
INM
Resistance V
to V
1
1
MΩ
pF
INP
INM
Capacitance V
= V
to GND
1.2
INM
CM Input Resistance
Resistance V
= V
to GND
= 0V
MΩ
µA
INCM
INP
INP
INP
INM
INM
INM
+I
Positive Input Current
DC bias @ V
DC bias @ V
= V
= V
1
1
IN
-I
Negative Input Current
Differential Input Range
= 0V
µA
IN
V
V
- V when slope gain falls to 0.9
INM
2.5
50
V
INDIFF
INP
OUTPUT CHARACTERISTICS
V(V
)
Output Voltage Swing
Output Drive Current
R
R
= 150Ω
±3.5
60
V
OUT
L
I(V
)
= 10Ω, V
= 1V, V = 0V, X2 = high,
INM
mA
OUT
L
INP
V
= 0.39
G
R(V
)
CM Output Resistance of
at 100kHz
30
Ω
CM
VCM_R/G/B (ISL59913 only)
Gain
Gain
V
V
V
= 0, V = 0.39, X2 = 5, R = 150Ω
0.85
1.0
3
1.1
8
C
C
C
G
L
ΔGain @ DC
Channel-to-Channel Gain Matching
Channel-to-Channel Gain Matching
= 0, V = 0.39, X2 = 5, R = 150Ω
%
%
G
L
ΔGain @
= 0.6, V = 0.39, X2 = 5, R = 150Ω,
3
11
G
L
15MHz
Frequency = 15MHz
V(SYNC)
High Level output on V/H
(ISL59910 only)
V(V
)
V(V
)
SP
HI
OUT
SP
- 0.1V
FN6406.0
December 15, 2006
3
ISL59910, ISL59913
Electrical Specifications
V
+ = V + = +5V, V - = V - = -5V, T = +25°C, exposed die plate = -5V, unless otherwise specified.
SA
A
SA
A
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
V(SYNC)
Low Level output on V/H
(ISL59910 only)
V(SYNC
REF)
V(SYNC
REF)
LO
OUT
+ 0.1V
SUPPLY
I
I
Supply Current per Channel
Supply Current per Channel
Power Supply Rejection Ratio
V
= 5, V
= 0, V
= 0
= 0
32
36
65
39
mA
mA
dB
SON
ENBL
ENBL
INM
INM
V
0.2
0.4
SOFF
PSRR
DC to 100kHz, ±5V supply
LOGIC CONTROL PINS (ENABLE, X2)
V
V
Logic High Level
V
V
V
V
- V
- V
ref for guaranteed high level
ref for guaranteed low level
1.4
V
V
HI
IN
IN
IN
IN
LOGIC
LOGIC
Logic Low Level
0.8
50
15
LOW
I
I
Logic High Input Current
Logic Low Input Current
= 5V, V
= 0V, V
= 0V
= 0V
µA
µA
LOGICH
LOGICL
LOGIC
LOGIC
Pin Descriptions
ISL59910
PIN FUNCTION
-5V to blue output buffer
ISL59913
PIN FUNCTION
PIN
NUMBER
PIN NAME
VSMO_B
VOUT_B
VSPO_B
VSPO_G
VOUT_G
VSMO_G
VSMO_R
VOUT_R
VSPO_R
VCTRL
PIN NAME
VSMO_B
VOUT_B
VSPO_B
VSPO_G
VOUT_G
VSMO_G
VSMO_R
VOUT_R
VSPO_R
VCTRL
1
2
-5V to blue output buffer
Blue output voltage referenced to 0V pin
+5V to blue output buffer
Blue output voltage referenced to 0V pin
+5V to blue output buffer
3
4
+5V to green output buffer
+5V to green output buffer
5
Green output voltage referenced to 0V pin
-5V to green output buffer
Green output voltage referenced to 0V pin
-5V to green output buffer
6
7
-5V to red output buffer
-5V to red output buffer
8
Red output voltage referenced to 0V pin
+5V to red output buffer
Red output voltage referenced to 0V pin
+5V to red output buffer
9
10
11
Equalization control voltage (0V to 0.95V)
Equalization control voltage (0V to 0.95V)
VREF
Reference voltage for logic signals, V
CTRL
and
VREF
Reference voltage for logic signals, V
and
CTRL
V
pins
V
pins
GAIN
GAIN
12
13
14
15
16
17
18
19
20
21
22
23
VGAIN_R
VGAIN_G
VGAIN_B
VSM
Red channel gain voltage (0V to 1V)
VGAIN_R
VGAIN_G
VGAIN_B
VSM
Red channel gain voltage (0V to 1V)
Green channel gain voltage (0V to 1V)
Blue channel gain voltage (0V to 1V)
-5V to core of chip
Green channel gain voltage (0V to 1V)
Blue channel gain voltage (0V to 1V)
-5V to core of chip
VINP_R
VINM_R
VINP_G
VINM_G
VINP_B
VINM_B
VSP
Red positive differential input
Red negative differential input
Green positive differential input
Green negative differential input
Blue positive differential input
Blue negative differential input
+5V to core of chip
VINP_R
VINM_R
VINP_G
VINM_G
VINP_B
VINM_B
VSP
Red positive differential input
Red negative differential input
Green positive differential input
Green negative differential input
Blue positive differential input
Blue negative differential input
+5V to core of chip
HOUT
Decoded Horizontal sync referenced to
SYNCREF
VCM_R
Red common-mode voltage at inputs
24
25
VOUT
Decoded Vertical sync referenced to SYNCREF
VCM_G
VCM_B
Green common-mode voltage at inputs
Blue common-mode voltage at inputs
SYNCREF
Reference level for H
and V
logic outputs
OUT
OUT
FN6406.0
December 15, 2006
4
ISL59910, ISL59913
Pin Descriptions (Continued)
ISL59910
ISL59913
PIN FUNCTION
PIN
NUMBER
PIN NAME
X2
PIN FUNCTION
PIN NAME
26
27
28
Logic signal for x1/x2 output gain setting
Chip enable logic signal
X2
ENABLE
0V
Logic signal for x1/x2 output gain setting
Chip enable logic signal
ENABLE
0V
0V reference for output voltage
Must be connected to -5V
0V reference for output voltage
Thermal Pad
Typical Performance Curves
5
X =HIGH
X =LOW
2
GAIN
2
V
V
R
=0.35V
=0V
=150Ω
V
V
=0V
=0V
GAIN
CTRL
3
1
CTRL
LOAD
R
=150
LOAD
-1
-3
-5
1M
10M
100M 200M
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE OF ALL CHANNELS
FIGURE 2. GAIN vs FREQUENCY ALL CHANNELS
X =LOW
2
X =LOW
2
V
V
V
CTRL=0.25V
GAIN=0.25V
V =±5V
CTRL=1V
V =±5V
S
S
R =150Ω
R =150Ω
L
L
Source=-20dBm
V
V
=0V
=0.1V STEPS
GAIN
CTRL
Source=-20dBm
V
CTRL=0V
V
GAIN=0.25V
V
V
CTRL=0V
GAIN=0V
V
CTRL=0V
FIGURE 4. GAIN vs FREQUENCY FOR VARIOUS V
AND
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS V
CTRL
CTRL
V
GAIN
FN6406.0
December 15, 2006
5
ISL59910, ISL59913
Typical Performance Curves (Continued)
X =LOW
2
X =LOW
V
2
CTRL=1V
CABLE=3FT
V =±5V
S
V
V
=0.5V
=0.5V
=150Ω
GAIN
CTRL
R =150Ω
L
V
=1V
GAIN
SOURCE=-20dBm
R
LOAD
V
CTRL=0V
CABLE=3FT
V
CTRL=0V
CABLE=600FT
FIGURE 5. GAIN vs FREQUENCY FOR VARIOUS V
CABLE LENGTHS
AND
FIGURE 6. CHANNEL MISMATCH
CTRL
V
R
=0V
CTRL
V =±5V, R =150Ω
S
L
=150Ω
X
LOAD
2=HIGH
INPUT 50Ω TO GROUND
INPUT=50Ω TO GND
V
GAIN=1V
X
2=LOW
X
X
2=HiGH
2=LOW
V
V
CTRL=0V
CTRL=0V
FIGURE 7. OFFSET vs V
FIGURE 8. DC GAIN vs V
CTRL
GAIN
X =HIGH
2
X =HIGH
2
V
V
V =±5V
CTRL=0V
GAIN=0V
S
V =±5V
S
R =150Ω
L
R =150Ω
L
INPUT=50Ω TO GROUND
V
V
CTRL=0V
GAIN=1V
TOTAL
HARMONIC
3rd
HARMONIC
V
V
CTRL=1V
GAIN=1V
V
V
V
V
CTRL=0V
GAIN=1V
CTRL=1V
GAIN=0V
2nd
HAMONIC
FIGURE 10. OUTPUT NOISE
FIGURE 9. HARMONIC DISTORTION vs FREQUENCY
FN6406.0
December 15, 2006
6
ISL59910, ISL59913
Typical Performance Curves (Continued)
-10
-20
4
2
V
=0.35V
V
=0.35V
GAIN
GAIN
(ALL CHANNELS)
V =0V
CTRL
(ALL CHANNELS)
V
=0V
CTRL
X =HIGH
R
=150Ω
2
LOAD
X =HIGH
2
-40
0
-60
-2
-4
-6
-80
-100
100k
1M
10M
100M
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 11. COMMON-MODE REJECTION
FIGURE 12. CM AMPLIFIER BANDWIDTH
0
-20
-40
V
V
V
=5V
=0V
V
V
V
=-5V
EE
CC
CTRL
=0V
=0V
CTRL
=0V
GAIN
GAIN
-20
-40
(ALL CHANNELS)
INPUTS ON GND
(ALL CHANNELS)
INPUTS ON GND
-60
-60
-80
-80
-100
-100
-120
10
100
1k
10k 100k
1M
10M 100M
10
100
1k
10k 100k
1M
10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 13. (+)PSRR vs FREQUENCY
FIGURE 14. (-)PSRR vs FREQUENCY
BLUE
GREEN
X =LOW
2
V =±5V
S
R =150Ω
L
V
V
=1V
CTRL
=1V
RED
GAIN
FIGURE 15. BLUE CROSSTALK (CABLE LENGTH = 3ft.)
FIGURE 16. BLUE CROSSTALK (CABLE LENGTH = 600ft.)
FN6406.0
December 15, 2006
7
ISL59910, ISL59913
Typical Performance Curves (Continued)
GREEN
RED
X =LOW
2
V =±5V
S
R =150Ω
L
V
V
=1V
=1V
CTRL
GAIN
BLUE
FIGURE 17. GREEN CROSSTALK (CABLE LENGTH = 3ft.)
FIGURE 18. GREEN CROSSTALK (CABLE LENGTH = 600ft.)
RED
GREEN
X =LOW
2
V =±5V
S
R =150Ω
L
V
V
=1V
CTRL
=1V
BLUE
GAIN
FIGURE 19. RED CROSSTALK (CABLE LENGTH = 3ft.)
FIGURE 20. RED CROSSTALK (CABLE LENGTH =600ft.)
V
CTRL=0V
CABLE=3FT
V
CTRL=0.2V
CABLE=600FT
X =HIGH
2
V =±5V
S
R =150Ω
L
V
=0V
GAIN
INPUT=10MHz
FIGURE 21. RISE TIME AND FALL TIME
FIGURE 22. PULSE RESPONSE FOR VARIOUS CABLE
LENGTHS
FN6406.0
December 15, 2006
8
ISL59910, ISL59913
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
1
4.5
4
893mW
3.378W
3.5
3
0.8
0.6
0.4
0.2
0
2.5
2
1.5
1
0.5
0
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
The control reference and logic reference effectively remove
the necessity for the 0V rail and operation from ±5V (or 0V
and 10V) only is possible. However we still need a further
reference to define the 0V level of the single ended output
signal. The reference for the output signal is provided by the
0V pin. The output stage cannot pull fully up or down to either
supply so it is important that the reference is positioned to
allow full output swing. The 0V reference should be tied to a
'quiet ground' as any noise on this pin is transferred directly to
the output. The 0V pin is a high impedance pin and draws DC
bias currents of a few µA and similar levels of AC current.
Applications Information
Logic Control
The ISL59913 has two logical input pins, Chip Enable
(ENABLE) and Switch Gain (X2). The logic circuits all have a
nominal threshold of 1.1V above the potential of the logic
reference pin (VREF). In most applications it is expected that
this chip will run from a +5V, 0V, -5V supply system with logic
being run between 0V and +5V. In this case the logic
reference voltage should be tied to the 0V supply. If the logic
is referenced to the -5V rail, then the logic reference should
be connected to -5V. The logic reference pin sources about
60µA and this will rise to about 200µA if all inputs are true
(positive).
Equalizing
When transmitting a signal across a twisted pair cable, it is
found that the high frequency (above 1MHz) information is
attenuated more significantly than the information at low
frequencies. The attenuation is predominantly due to resistive
skin effect losses and has a loss curve which depends on the
resistivity of the conductor, surface condition of the wire and the
wire diameter. For the range of high performance twisted pair
cables based on 24awg copper wire (CAT-5 etc). These
parameters vary only a little between cable types and in general
cables exhibit the same frequency dependence of loss. (The
lower loss cables can be compared with somewhat longer
lengths of their more lossy brothers.) This enables a single
equalizing law equation to be built into the ISL59913.
The logic inputs all source up to 10µA when they are held at
the logic reference level. When taken positive, the inputs
sink a current dependent on the high level, up to 50µA for a
high level 5V above the reference level.
The logic inputs, if not used, should be tied to the
appropriate voltage in order to define their state.
Control Reference and Signal Reference
Analog control voltages are required to set the equalizer and
contrast levels. These signals are voltages in the range
0V to 1V, which are referenced to the control reference pin. It
is expected that the control reference pin will be tied to 0V
and the control voltage will vary from 0V to 1V. It is; however,
acceptable to connect the control reference to any potential
between -5V and 0V to which the control voltages are
referenced.
With a control voltage applied between pins VCTRL and
VREF, the frequency dependence of the equalization is
shown in Figure 8. The equalization matches the cable loss
up to about 100MHz. Above this, system gain is rolled off
rapidly to reduce noise bandwidth. The roll-off occurs more
rapidly for higher control voltages, thus the system (cable +
equalizer) bandwidth reduces as the cable length increases.
This is desirable, as noise becomes an increasing issue as
the equalization increases.
The control voltage pins themselves are high impedance.
The control reference pin will source between 0µA and
200µA depending on the control voltages being applied.
FN6406.0
December 15, 2006
9
ISL59910, ISL59913
an internal logic decoding block to provide Horizontal and
Vertical sync output signals (H and V ).
Contrast
OUT OUT
By varying the voltage between pins VGAIN and VREF, the
gain of the signal path can be changed in the ratio 4:1. The
gain change varies almost linearly with control voltage. For
normal operation it is anticipated the X2 mode will be selected
and the output load will be back matched. A unity gain to the
output load will then be achieved with a gain control voltage of
about 0.35V. This allows the gain to be trimmed up or down by
6dB to compensate for any gain/loss errors that affect the
contrast of the video signal. Figure 26 shows an example plot
of the gain to the load with gain control voltage.
BLUE CM
OUT (CH A)
GREEN CM
OUT (CH B)
RED CM
OUT (CH C)
V
SYNC
H
SYNC
2
1.8
1.6
1.4
1.2
1
TIME (0.5ms/DIV)
FIGURE 26. H AND V SYNCS ENCODED
TABLE 1. H AND V SYNC DECODING
RED CM
Mid
GREEN CM BLUE CM
H
V
SYNC
SYNC
High
Low
High
Low
Low
Mid
Low
Low
0.8
0.6
0.4
High
Low
Low
High
Low
High
Mid
High
High
0
0.2
0.4
0.6
0.8
1
Mid
High
V
GAIN
NOTE: Level ‘Mid’ is halfway between ‘High’ and ‘Low’
FIGURE 25. VARIATION OF GAIN WITH GAIN CONTROL
VOLTAGE
Power Dissipation
Common Mode Sync Decoding
The ISL59910 and ISL59913 are designed to operate with
±5V supply voltages. The supply currents are tested in
production and guaranteed to be less than 39mA per
channel. Operating at ±5V power supply, the total power
dissipation is:
The ISL59910 features common mode decoding to allow
horizontal and vertical synchronization information, which has
been encoded on the three differential inputs by the EL4543,
to be decoded. The entire RGB video signal can therefore be
transmitted, along with the associated synchronization
information, by using just three twisted pairs.
V
OUTMAX
----------------------------
PD
= 3 × 2 × V × I
+ (V - V ) ×
OUTMAX
MAX
S
SMAX
S
R
L
Decoding is based on the EL4543 encoding scheme, as
described in Figure 26 and Table 1. The scheme is a three-level
system, which has been designed such that the sum of the
common mode voltages results in a fixed average DC level with
no AC content. This eliminates the effect of EMI radiation into
the common mode signals along the twisted pairs of the cable
(EQ. 1)
where:
• PD
= Maximum power dissipation
MAX
• V = Supply voltage = 5V
S
The common mode voltages are initially extracted by the
ISL59910 from the three input pairs. These are then passed to
• I
= Maximum quiescent supply current per
MAX
channel = 39mA
• V
= Maximum output voltage swing of the
OUTMAX
application = 2V
R = Load resistance = 150Ω Ω
L
(EQ. 2)
PD
= 1.29W
MAX
θ
required for long term reliable operation can be
JA
calculated. This is done using Equation 3:
FN6406.0
December 15, 2006
10
ISL59910, ISL59913
Where
(Tj – Ta)
-----------------------
= 50.4CW
(EQ. 3)
θ
=
JA
PD
Tj is the maximum junction temperature (+150°C)
Ta is the maximum ambient temperature (+85°C)
For a QFN 28 package in a properly layout PCB heatsinking
copper area, +37°C/W θ thermal resistance can be
JA
achieved. To disperse the heat, the bottom heatspreader
must be soldered to the PCB. Heat flows through the
heatspreader to the circuit board copper then spreads and
converts to air. Thus the PCB copper plane becomes the
heatsink. This has proven to be a very effective technique. A
separate application note details the 28 Ld QFN. PCB
design considerations are available.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6406.0
December 15, 2006
11
ISL59910, ISL59913
QFN (Quad Flat No-Lead) Package Family
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY
(COMPLIANT TO JEDEC MO-220)
A
SYMBOL QFN44 QFN38
QFN32
TOLERANCE
±0.10
NOTES
D
B
A
A1
b
0.90
0.02
0.25
0.20
7.00
5.10
7.00
5.10
0.50
0.55
44
0.90 0.90
0.90
0.02
0.22
0.20
5.00
-
-
0.02 0.02
0.25 0.23
0.20 0.20
5.00 8.00
+0.03/-0.02
±0.02
-
1
2
3
PIN #1
I.D. MARK
c
Reference
Basic
-
D
-
E
D2
E
3.80 5.80 3.60/2.48
7.00 8.00 6.00
5.80 5.80 4.60/3.40
Reference
Basic
8
-
E2
e
Reference
Basic
8
-
2X
0.075 C
0.50 0.80
0.40 0.53
0.50
0.50
32
L
±0.05
-
2X
0.075 C
N
38
7
32
8
Reference
Reference
Reference
4
6
5
TOP VIEW
ND
NE
11
7
11
12
8
9
0.10 M C A B
b
TOLER-
ANCE NOTES
L
SYMBOL QFN28 QFN24
QFN20
QFN16
0.90
PIN #1 I.D.
3
A
0.90
0.02
0.90 0.90
0.02 0.02
0.90
0.02
±0.10
-
-
1
2
3
A1
0.02
+0.03/
-0.02
b
c
0.25
0.20
4.00
2.65
5.00
3.65
0.50
0.40
28
0.25 0.30
0.20 0.20
4.00 5.00
2.80 3.70
5.00 5.00
3.80 3.70
0.50 0.65
0.40 0.40
0.25
0.20
4.00
2.70
4.00
2.70
0.50
0.40
20
0.33
±0.02
-
-
(E2)
0.20 Reference
4.00 Basic
2.40 Reference
4.00 Basic
2.40 Reference
D
-
5
NE
D2
E
-
-
E2
e
-
7
(D2)
BOTTOM VIEW
0.65
0.60
16
Basic
-
L
±0.05
-
N
24
5
20
5
Reference
Reference
Reference
4
6
5
0.10 C
ND
NE
6
5
4
e
C
8
7
5
5
4
SEATING
PLANE
Rev 10 12/04
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
0.08 C
SEE DETAIL "X"
N LEADS
& EXPOSED PAD
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
SIDE VIEW
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
(c)
2
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
A
C
7. Inward end of terminal may be square or circular in shape with radius
(b/2) as shown.
(L)
A1
N LEADS
8. If two values are listed, multiple exposed pad options are available.
Refer to device-specific datasheet.
DETAIL X
FN6406.0
December 15, 2006
12
相关型号:
ISL59920IRZ-TR
IC SPECIALTY CONSUMER CIRCUIT, PQCC20, 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220, QFN-20, Consumer IC:Other
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