ISL6744ABZ_技术文档

ISL6744

®

Data Sheet

September 22, 2005

FN9147.8

Intermediate Bus PWM Controller

Features

• Precision Duty Cycle and Deadtime Control

The ISL6744 is a low cost, primary side, double-ended

controller intended for applications using full and half-bridge

topologies for unregulated DC/DC converters. It is a voltage-

mode PWM controller designed for half-bridge and full-

bridge power supplies. It provides precise control of

switching frequency, adjustable soft-start, precise deadtime

control with deadtimes as low as 35ns, and overcurrent

shutdown.

• 100µA Start-up Current

• Adjustable Delayed Overcurrent Shutdown and Restart

• Adjustable Oscillator Frequency Up to 2MHz

• 1A MOSFET Gate Drivers

• Adjustable Soft-Start

Low start-up and operating currents allow for easy biasing in

both AC/DC and DC/DC applications. This advanced

BiCMOS design features low start-up and operating

currents, adjustable switching frequency up to 1MHz, 1A

FET drivers, and very low propagation delays for a fast

response to overcurrent faults.

• Internal Over Temperature Protection

• 35ns Control to Output Propagation Delay

• Small Size and Minimal External Component Count

• Input Undervoltage Protection

• Pb-Free Plus Anneal Available (RoHS Compliant)

Ordering Information

Applications

• Telecom and Datacom Isolated Power

TEMP.

PKG.

PART NUMBER

RANGE (°C)

PACKAGE

DWG. #

ISL6744AU

-40 to 105

8 Ld MSOP

M8.118

• DC Transformers

ISL6744AUZ

(Note)

8 Ld MSOP

(Pb-free)

• Bus Converters

ISL6744AB

-40 to 105

8 Ld SOIC

M8.15

Pinout

ISL6744 (SOIC, MSOP)

TOP VIEW

ISL6744ABZ

(Note)

8 Ld SOIC

(Pb-free)

Add “-T” suffix for tape and reel.

SS

RTD

CS

1

8

7

6

5

VDD

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

OUTB

OUTA

GND

2

3

4

CT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6744

Absolute Maximum Ratings

Thermal Information

Thermal Resistance (Typical, Note 1)

8 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . .-55°C to 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V

θ

(°C/W)

JA

128

98

DD

OUTA, OUTB . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to V

DD

Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5V

Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A

ESD Classification

Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V

Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .100V

Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1000V

Operating Conditions

Temperature Range

ISL6744AU . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 105°C

Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 9-16 VDC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

2. All voltages are to be measured with respect to GND, unless otherwise specified.

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

schematic. 9V < V < 16V, R = 51.1kΩ, C = 470pF, T = -40°C to 105°C (Note 4), Typical values are at

D

TD

T

A

T

= 25°C

A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

SUPPLY VOLTAGE

Start-Up Current, I

V

< START Threshold

DD

-

175

-

µA

mA

V

DD

Operating Current, I

R

C

, C

LOAD OUTA,B

= 0

2.89

5

DD

= 1nF

-

8.5

6.6

6.3

-

OUTA,B

UVLO START Threshold

UVLO STOP Threshold

Hysteresis

5.9

5.3

-

6.3

5.7

0.6

V

CURRENT SENSE

Current Limit Threshold

CS to OUT Delay

0.55

0.6

35

10

-

0.65

V

(Note 4)

-

ns

CS Sink Current

8

mA

µA

Input Bias Current

-1

1

PULSE WIDTH MODULATOR

Minimum Duty Cycle

Maximum Duty Cycle

V

< C Offset

-

0

-

%

ERROR

T

C

= 470pF, R = 51.1kΩ

TD

94

99

1

T

= 470pF, R = 1.1kΩ (Note 4)

TD

-

%

C

to SS Comparator Input Gain

(Note 4)

-

V/V

T

SS to SS Comparator Input Gain

0.8

-

FN9147.8

September 22, 2005

4

ISL6744

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

schematic. 9V < V < 16V, R = 51.1kΩ, C = 470pF, T = -40°C to 105°C (Note 4), Typical values are at

D

TD

T

A

T

= 25°C (Continued)

A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

OSCILLATOR

Charge Current

143

1.925

45

156

2

170

2.075

65

µA

V

R

Voltage

TD

Discharge Current Gain

-

µA/µA

V

C

Valley Voltage

Peak Voltage

0.75

2.70

0.8

2.80

0.85

2.90

T

V

T

SOFT-START

Charging Current

SS Clamp Voltage

45

3.8

-

68

4.2

-

µA

V

4.0

3.9

15

Overcurrent Shutdown Threshold Voltage

Overcurrent Discharge Current

Reset Threshold Voltage

(Note 4)

V

12

23

µA

V

0.25

0.27

0.30

OUTPUT

High Level Output Voltage (VOH)

V

OUT

- V

or V ,

OUTB

-

0.5

2.0

V

DD

OUTA

I

= -100mA

Low Level Output Voltage (VOL)

Rise Time

I

= 100mA

-

0.5

17

20

1.0

60

V

OUT

C

= 1nF, V

= 12V

ns

GATE

DD

Fall Time

THERMAL PROTECTION

Thermal Shutdown

Thermal Shutdown Clear

Hysteresis, Internal Protection

NOTES:

(Note 4)

-

145

130

15

-

°C

3. Specifications at -40°C are guaranteed by design, not production tested.

4. Guaranteed by design, not 100% tested in production.

FN9147.8

September 22, 2005

5

ISL6744

Typical Performance Curves

4

3

65

1-10

CT =

1000pF

680pF

470pF

60

55

50

45

CT = 270pF

CT = 100pF

100

10

40

0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

10

20

30

40

50

60

70

80

90

100

RTD CURRENT (mA)

RTD (kΩ)

FIGURE 1. OSCILLATOR CT DISCHARGE CURRENT GAIN

FIGURE 2. DEADTIME vs CAPACITANCE

600

500

400

300

200

1.03

1.02

1.01

1.00

0.99

0.98

0.97

0.96

0.95

100

0

-40 -25 -10

5

20

35

50

65

80

95 110

100

200 300

400 500

600

700 800

900 1000

CT (pF)

TEMPERATURE (°C)

FIGURE 3. CAPACITANCE vs OSCILLATOR FREQUENCY

FIGURE 4. CHARGE CURRENT vs TEMPERATURE

(RTD = 49.9kΩ)

1.07

1.06

1.05

1.04

1.03

1.02

1.01

1.00

0.99

0.98

0

10

20

30

40

50

60

70

80

90

100

RTD (kΩ)

FIGURE 5. TIMING CAPACITOR VOLTAGE vs RTD

FN9147.8

6

September 22, 2005

ISL6744

Functional Description

Pin Descriptions

V

- V

DD

is the power connection for the IC. To optimize

to GND with a ceramic

and GND pins as possible.

DD

Features

noise immunity, bypass V

capacitor as close to the V

DD

The ISL6744 PWM is an excellent choice for low cost bridge

topologies for applications requiring accurate frequency and

deadtime control. Among its many features are 1A FET

drivers, adjustable soft-start, overcurrent protection and

internal thermal protection, allowing a highly flexible design

with minimal external components.

The total supply current, I , will be dependent on the load

DD

applied to outputs OUTA and OUTB. Total I

DD

current is the

sum of the quiescent current and the average output current.

Knowing the operating frequency, Fsw, and the output

loading capacitance charge, Q, per output, the average

output current can be calculated from:

Oscillator

The ISL6744 has an oscillator with a frequency range to

(EQ. 1)

I

= 2 • Q • Fsw

OUT

2MHz, programmable using a resistor R and capacitor C .

TD

T

The switching period may be considered to be the sum of

the timing capacitor charge and discharge durations. The

R

- This is the oscillator timing capacitor discharge current

TD

control pin. A resistor is connected between this pin and

GND. The current flowing through the resistor determines

the magnitude of the discharge current. The discharge

current is nominally 55x this current. The PWM deadtime is

determined by the timing capacitor discharge duration.

charge duration is determined by C and the internal current

T

source (assumed to be 160µA in the formula). The discharge

duration is determined by R and C .

TD

T

4

T

≈ 1.25×10 • C

s

(EQ. 2)

(EQ. 3)

C

T

C - The oscillator timing capacitor is connected between

T

1

----------------------------------------------------------------------------

this pin and GND.

T

≈

• R

• C

T

s

D

TD

CTDischargeCurrentGain

CS - This is the input to the overcurrent protection comparator.

The overcurrent comparator threshold is set at 0.600V nominal.

The CS pin is shorted to GND at the end of each switching

cycle. Depending on the current sensing source impedance, a

series input resistor may be required due to the delay between

the internal clock and the external power switch.

1

OSC

T

= T + T = ---------------

s

(EQ. 4)

OSC

C

D

F

where T and T are the approximate charge and discharge

C

D

times, respectively, T

period, and F

is the oscillator free running

is the oscillator frequency. One output

OSC

switching cycle requires two oscillator cycles. The actual

times will be slightly longer than calculated due to internal

propagation delays of approximately 5ns/transition. This

delay adds directly to the switching duration, and also

causes overshoot of the timing capacitor peak and valley

voltage thresholds, effectively increasing the peak-to-peak

voltage on the timing capacitor. Additionally, if very low

charge and discharge currents are used, there will be an

Exceeding the overcurrent threshold will start a delayed

shutdown sequence. Once an overcurrent condition is

detected, the soft-start charge current source is disabled.

The soft-start capacitor begins discharging through a 15µA

current source, and if it discharges to less than 3.9V

(Sustained Overcurrent Threshold), a shutdown condition

occurs and the OUTA and OUTB outputs are forced low.

When the soft-start voltage reaches 0.27V (Reset

Threshold) a soft-start cycle begins.

increased error due to the input impedance at the C pin.

T

The above formulae help with the estimation of the

frequency. Practically, effects like stray capacitances that

affect the overall C capacitance, variation in R voltage

If the overcurrent condition ceases, and then an additional

50µs period elapses before the shutdown threshold is

reached, no shutdown occurs. The SS charging current is

re-enabled and the soft-start voltage is allowed to recover.

T

TD

and charge current over temperature, etc. exist, and are best

evaluated in-circuit. Equation 2 follows from the basic

GND - Reference and power ground for all functions on this

device. Due to high peak currents and high frequency

operation, a low impedance layout is necessary. Ground

planes and short traces are highly recommended.

dV

capacitor current equation, i = C × . In this case, with

dt

variation in dV with R (Figure 5), and in charge current

TD

(Figure 4), results from Equation 2 would differ from the

calculated frequency. The typical performance curves may

be used as a tool along with the above equations as a more

accurate tool to estimate the operating frequency more

accurately.

OUTA and OUTB - Alternate half cycle output stages. Each

output is capable of 1A peak currents for driving power

MOSFETs or MOSFET drivers. Each output provides very

low impedance to overshoot and undershoot.

The maximum duty cycle, D, and deadtime, DT, can be

calculated from:

SS - Connect the soft-start timing capacitor between this pin

and GND to control the duration of soft-start. The value of the

capacitor determines the rate of increase of the duty cycle

during start-up, controls the overcurrent shutdown delay, and

the overcurrent and short circuit hiccup restart period.

D = T ⁄ T

(EQ. 5)

C

OSC

DT = (1 – D) ⋅ T

s

(EQ. 6)

OSC

FN9147.8

7

September 22, 2005

ISL6744

Soft-Start Operation

The ISL6744 features a soft-start using an external capacitor

in conjunction with an internal current source. Soft-start

reduces stresses and surge currents during start-up.

Typical Application

The Typical Application Schematic features the ISL6744 in

an unregulated half-bridge DC/DC converter configuration,

often referred to as a DC Transformer or Bus Converter.

The oscillator capacitor signal, C , is compared to the

T

The input voltage is 48V ±10% DC. The output is a nominal

12V when the input voltage is at 48V. Since this is an

unregulated topology, the output voltage will vary

proportionately with input voltage. The load regulation is a

function of resistance between the source and the converter

output. The output is rated at 8A.

soft-start voltage, SS, in the SS comparator which drives the

PWM latch. While the SS voltage is less than 3.5V, duty

cycle is limited. The output pulse width increases as the

soft-start capacitor voltage increases up to 3.5V. This has

the effect of increasing the duty cycle from zero to the

maximum pulse width during the soft-start period. When the

soft-start voltage exceeds 3.5V, soft-start is completed.

Soft-start occurs during start-up and after recovery from an

overcurrent shutdown. The soft-start voltage is clamped

to 4V.

Circuit Elements

The converter design is comprised of the following functional

blocks:

Input Filtering: L1, C1, R1

Gate Drive

Half-Bridge Capacitors: C2, C3

Isolation Transformer: T1

The ISL6744 is capable of sourcing and sinking 1A peak

current, and may also be used in conjunction with a

MOSFET driver such as the ISL6700 for level shifting. To

limit the peak current through the IC, an external resistor

may be placed between the totem-pole output of the IC

(OUTA or OUTB pin) and the gate of the MOSFET. This

small series resistor also damps any oscillations caused by

the resonant tank of the parasitic inductances in the traces of

the board and the FET’s input capacitance.

Primary Snubber: C13, R10

Start Bias Regulator: CR3, R2, R7, C6, Q5, D1

Supply Bypass Components: C15, C4

Main MOSFET Power Switch: QH, QL

Current Sense Network: T2, CR1, CR2, R5, R6, R11, C10,

C14

Overcurrent Operation

Control Circuit: U1, C18, C16, D2

Overcurrent delayed shutdown is enabled once the soft-start

cycle is complete. If an overcurrent condition is detected, the

soft-start charging current source is disabled and the soft-

start capacitor is allowed to discharge through a 15µA

source. At the same time a 50µs retriggerable one-shot timer

is activated. It remains active for 50µs after the overcurrent

condition ceases. If the soft-start capacitor discharges to

3.9V, the output is disabled. This state continues until the

soft-start voltage reaches 270mV, at which time a new soft-

start cycle is initiated. If the overcurrent condition stops at

least 50µs prior to the soft-start voltage reaching 3.9V, the

soft-start charging currents revert to normal operation and

the soft-start voltage is allowed to recover.

Output Rectification and Filtering: QR1, QR2, QR3, QR4,

L2, C9, C8

Secondary Snubber: R8, R9, C11, C12

FET Driver: U4

Bootstrap components for driver: CR4, C5

ZVS Resonant Delay (Optional): L3, C7

Design Specifications

The following design requirements were selected for

evaluation purposes:

Thermal Protection

Switching Frequency, Fsw: 235kHz

An internal temperature sensor protects the device should

the junction temperature exceed 145°C. There is

approximately 15°C of hysteresis.

V

I

: 48 ± 10% V

IN

: 12V (nominal)

OUT

: 8A (steady state)

Ground Plane Requirements

Careful layout is essential for satisfactory operation of the

OUT

P

: 100W

OUT

device. A good ground plane must be employed. V

be bypassed directly to GND with good high frequency

capacitance.

should

DD

Efficiency: 95%

Ripple: 1%

FN9147.8

8

September 22, 2005

ISL6744

Since the converter is operating open loop at nearly 100%

duty cycle, the turns ratio, N, is simply the ratio of the input

voltage to the output voltage divided by 2.

n

SR

S

V

n

P

48

IN

(EQ. 7)

N = ------------------------ = --------------- = 2

S

V

• 2

12 • 2

OUT

SR

The factor of 2 in the denominator is due to the half-bridge

topology. Only half of the input voltage is applied to the

primary of the transformer.

FIGURE 6. TRANSFORMER SCHEMATIC

A PC44HPQ20/6 “E-Core” plus a PC44PQ20/3 “I-Core” from

TDK were selected for the transformer core. The ferrite

material is PC44.

Transformer Design

The design of a transformer for a half-bridge application is a

straightforward affair, although iterative. It is a process of

many compromises, and even experienced designers will

produce different designs when presented with identical

requirements. The iterative design process is not presented

here for clarity.

The core parameter of concern for flux density is the

effective core cross-sectional area, Ae. For the PQ core

pieces selected:

2

Ae = 0.62cm or 6.2e -5m

Using Faraday’s Law, V = N dΦ/dt, the number of primary

turns can be determined once the maximum flux density is

set. An acceptable Bmax is ultimately determined by the

allowable power dissipation in the ferrite material and is

influenced by the lossiness of the core, core geometry,

operating ambient temperature, and air flow. The TDK

datasheet for PC44 material indicates a core loss factor of

The abbreviated design process follows:

• Select a core geometry suitable for the application.

Constraints of height, footprint, mounting preference, and

operating environment will affect the choice.

• Determine the turns ratio.

• Select suitable core material(s).

3

~400mW/cm with a ± 2000 gauss 100kHz sinusoidal

• Select maximum flux density desired for operation.

excitation. The application uses a 235kHz square wave

excitation, so no direct comparison between the application

and the data can be made. Interpolation of the data is

• Select core size. Core size will be dictated by the

capability of the core structure to store the required

energy, the number of turns that have to be wound, and

the wire gauge needed. Often the window area (the space

used for the windings) and power loss determine the final

core size.

3

required. The core volume is approximately 1.6cm , so the

estimated core loss is

f

3

mW

----------

3

200kHz

act

---------------

---------------------

P

≈

• cm

•

= 0.4 • 1.6 •

= 1.28

W

loss

f

100kHz

meas

cm

• Determine maximum desired flux density. Depending on

the frequency of operation, the core material selected, and

the operating environment, the allowed flux density must

be determined. The decision of what flux density to allow

is often difficult to determine initially. Usually the highest

flux density that produces an acceptable design is used,

but often the winding geometry dictates a larger core than

is indicated based on flux density alone.

(EQ. 8)

1.28W of dissipation is significant for a core of this size.

Reducing the flux density to 1200 gauss will reduce the

dissipation by about the same percentage, or 40%.

Ultimately, evaluation of the transformer’s performance in

the application will determine what is acceptable.

• Determine the number of primary turns.

• Select the wire gauge for each winding.

• Determine winding order and insulation requirements.

• Verify the design.

From Faraday’s Law and using 1200 gauss peak flux density

(∆B = 2400 gauss or 0.24 tesla)

–6

V

• T

ON

53 • 2 • 10

IN

N = ----------------------------- = ---------------------------------------------------- = 3.56

turns

(EQ. 9)

–5

2 • A • ∆B

e

2 • 6.2 • 10 • 0.24

For this application we have selected a planar structure to

achieve a low profile design. A PQ style core was selected

because of its round center leg cross section, but there are

many suitable core styles available.

Rounding up yields 4 turns for the primary winding. The peak

flux density using 4 turns is ~1100 gauss. From EQ. 7, the

number of secondary turns is 2.

The volts/turn for this design ranges from 5.4V at V = 43V

IN

to 6.6V at V = 53V. Therefore, the synchronous rectifier

IN

(SR) windings may be set at 1 turn each with proper FET

selection. Selecting 2 turns for the synchronous rectifier

FN9147.8

September 22, 2005

9

ISL6744

windings would also be acceptable, but the gate drive losses

would increase.

The primary windings have an RMS current of approximately

5 A (I x N /N at ~ 100% duty cycle). The primary is

OUT

S

P

configured as 2 layers, 2 turns per layer to minimize the

winding stack height. Allowing 0.020 inches edge clearance

and 0.010 inches between turns yields a trace width of

0.0575 inches. Ignoring the terminal and lead-in resistance,

and using EQ. 11, the inner trace has a resistance of

4.25mΩ, and the outer trace has a resistance of 5.52mΩ.

The resistance of the primary then is 19.5mΩ at 20°C. The

total DC power loss for the primary at 20°C is 489mW.

The next step is to determine the equivalent wire gauge for

the planar structure. Since each secondary winding

conducts for only 50% of the period, the RMS current is

(EQ. 10)

I

= I

•

D = 10 • 0.5 = 7.07

A

RMS

OUT

where D is the duty cycle. Since an FR-4 PWB planar

winding structure was selected, the width of the copper

traces is limited by the window area width, and the number

of layers is limited by the window area height. The PQ core

selected has a usable window area width of 0.165 inches.

Allowing one turn per layer and 0.020 inches clearance at

the edges allows a maximum trace width of 0.125 inches.

Using 100 circular mils(c.m.)/A as a guideline for current

density, and from EQ. 10, 707c.m. are required for each of

the secondary windings (a circular mil is the area of a circle

0.001 inches in diameter). Converting c.m. to square mils

Improved efficiency and thermal performance could be

achieved by selecting heavier copper weight for the

windings. Evaluation in the application will determine its

need.

The order and geometry of the windings affects the AC

resistance, winding capacitance, and leakage inductance of

the finished transformer. To mitigate these effects,

interleaving the windings is necessary. The primary winding

is sandwiched between the two secondary windings. The

winding layout appears below.

2

yields 555mils (0.785 sq. mils/c.m.). Dividing by the trace

width results in a copper thickness of 4.44mils (0.112mm).

Using 1.3mils/oz. of copper requires a copper weight of

3.4oz. For reasons of cost, 3oz. copper was selected.

One layer of each secondary winding also contains the

synchronous rectifier winding. For this layer the secondary

trace width is reduced by 0.025 inches to 0.100 inches(0.015

inches for the SR winding trace width and 0.010 inches

spacing between the SR winding and the secondary

winding).

The choice of copper weight may be validated by calculating

the DC copper losses of the secondary winding. Ignoring the

terminal and lead-in resistance, the resistance of each layer

of the secondary may be approximated using EQ. 11.

FIGURE 7A. TOP LAYER: 1 TURN SECONDARY AND SR

WINDINGS

2πρ

R = -----------------------

Ω

(EQ. 11)

r













2

----

t • ln

r

1

where

R = Winding resistance

ρ = Resistivity of copper = 669e-9Ω-inches at 20°C

t = Thickness of the copper (3 oz.) = 3.9e-3 inches

r = Outside radius of the copper trace = 0.324 or 0.299

2

inches

r = Inside radius of the copper trace = 0.199 inches

1

The winding without the SR winding on the same layer has a

DC resistance of 2.21mΩ. The winding that shares the layer

with the SR winding has a DC resistance of 2.65mΩ. With

the secondary configured as a 4 turn center tapped winding

(2 turns each side of the tap), the total DC power loss for the

secondary at 20°C is 486mW.

FIGURE 7B. INT. LAYER 1: 1 TURN SECONDARY WINDING

FN9147.8

10

September 22, 2005

ISL6744

∅0.689

∅0.358

0.807

0.639

0.403

0.169

0.000

FIGURE 7C. INT. LAYER 2: 2 TURNS PRIMARY WINDING

0.000 0.184

0.479

0.774

1.054

FIGURE 7G. PWB DIMENSIONS

MOSFET Selection

The criteria for selection of the primary side half-bridge FETs

and the secondary side synchronous rectifier FETs is largely

based on the current and voltage rating of the device.

However, the FET drain-source capacitance and gate

charge cannot be ignored.

The zero voltage switch (ZVS) transition timing is dependent

on the transformer’s leakage inductance and the

capacitance at the node between the upper FET source and

the lower FET drain. The node capacitance is comprised of

the drain-source capacitance of the FETs and the

FIGURE 7D. INT. LAYER 3: 2 TURNS PRIMARY WINDING

transformer parasitic capacitance. The leakage inductance

and capacitance form an LC resonant tank circuit which

determines the duration of the transition. The amount of

energy stored in the LC tank circuit determines the transition

voltage amplitude. If the leakage inductance energy is too

low, ZVS operation is not possible and near or partial ZVS

operation occurs. As the leakage energy increases, the

voltage amplitude increases until it is clamped by the FET

body diode to ground or V , depending on which FET

IN

conducts. When the leakage energy exceeds the minimum

required for ZVS operation, the voltage is clamped until the

energy is transferred. This behavior increases the time

window for ZVS operation. This behavior is not without

consequences, however. The transition time and the period

of time during which the voltage is clamped reduces the

effective duty cycle.

FIGURE 7E. INT. LAYER 4: 1 TURN SECONDARY WINDING

The gate charge affects the switching speed of the FETs.

Higher gate charge translates into higher drive requirements

and/or slower switching speeds. The energy required to

drive the gates is dissipated as heat.

The maximum input voltage, V , plus transient voltage,

IN

determines the voltage rating required. With a maximum

input voltage of 53V for this application, and if we allow a

10% adder for transients, a voltage rating of 60V or higher

will suffice.

FIGURE 7F. BOTTOM LAYER: 1 TURN SECONDARY AND SR

WINDINGS

FN9147.8

September 22, 2005

11

ISL6744

The RMS current through each primary side FET can be

determined from EQ. 10, substituting 5A of primary current

Once the estimated transition time is determined, it must be

verified directly in the application. The transformer leakage

inductance was measured at 125nH and the combined

capacitance was estimated at 2000pF. Calculations indicate

a transition period of ~25ns. Verification of the performance

for I

(assuming 100% duty cycle). The result is 3.5A

OUT

RMS. Fairchild FDS3672 FETs, rated at 100V and 7.5A

(r = 22mΩ), were selected for the half-bridge

DS(ON)

switches.

yielded a value of T closer to 45ns.

D

The synchronous rectifier FETs must withstand

approximately one half of the input voltage assuming no

switching transients are present. This suggests that a device

capable of withstanding at least 30V is required. Empirical

testing in the circuit revealed switching transients of 20V

were present across the device indicating a rating of at least

60V is required.

The remainder of the switching half-period is the charge

time, T , and can be found from

C

–9

1

T

= -------------------- – T = ---------------------------------- – 45 • 10

= 2.08

µs

C

D

3

2 • F

Sw

2 • 235 • 10

(EQ. 14)

where F

Sw

is the converter switching frequency.

The RMS current rating of 7.07A for each SR FET requires a

Using Figure 3, the capacitor value appropriate to the

desired oscillator operating frequency of 470kHz can be

low r

to minimize conduction losses, which is difficult to

DS(ON)

find in a 60V device. It was decided to use two devices in

parallel to simplify the thermal design. Two Fairchild FDS5670

devices are used in parallel for a total of four SR FETs. The

selected. A C value of 100pF, 150pF, or 220pF is

T

appropriate for this frequency. A value of 150pF was

selected.

FDS5670 is rated at 60V and 10A (r

= 14mΩ).

DS(ON)

To obtain the proper value for R , EQ. 3 is used. Since

TD

there is a 10ns propagation delay in the oscillator circuit, it

Oscillator Component Selection

The desired operating frequency of 235kHz for the converter

was established in the Design Criteria section. The

oscillator frequency operates at twice the frequency of the

converter because two clock cycles are required for a

complete converter period.

must be included in the calculation. The value of R

selected is 10kΩ.

TD

Output Filter Design

The output filter inductor and capacitor selection is simple

and straightforward. Under steady state operating conditions

the voltage across the inductor is very small due to the large

duty cycle. Voltage is applied across the inductor only during

the switch transition time, about 45ns in this application.

Ignoring the voltage drop across the SR FETs, the voltage

During each oscillator cycle the timing capacitor, C , must be

T

charged and discharged. Determining the required

discharge time to achieve zero voltage switching (ZVS) is

the critical design goal in selecting the timing components.

The discharge time sets the deadtime between the two

outputs, and is the same as ZVS transition time. Once the

discharge time is determined, the remainder of the period

becomes the charge time.

across the inductor during the on time with V = 48V is

IN

V

• N • (1 – D)

S

IN

-----------------------------------------------

(EQ. 15)

V

= V – V =

OUT

≈ 250

mV

L

S

2N

P

The ZVS transition duration is determined by the

where

V is the inductor voltage

transformer’s primary leakage inductance, L , by the FET

lk

Coss, by the transformer’s parasitic winding capacitance,

and by any other parasitic elements on the node. The

parameters may be determined by measurement,

calculation, estimate, or by some combination of these

methods.

L

V

is the voltage across the secondary winding

S

V

is the output voltage

OUT

If we allow a current ramp, ∆I, of 5% of the rated output

current, the minimum inductance required is

π L • (2C

+ C

xfrmr

)

lk

oss

(EQ. 12)

-------------------------------------------------------------------

t

≈

s

zvs

2

V

• T

∆I

L

ON

0.25 • 2.08

------------------------

(EQ. 16)

L ≥

= ---------------------------- = 1.04

µH

0.5

Device output capacitance, Coss, is non-linear with applied

voltage. To find the equivalent discrete capacitance, Cfet, a

charge model is used. Using a known current source, the

time required to charge the MOSFET drain to the desired

operating voltage is determined and the equivalent

capacitance is calculated.

An inductor value of 1.5µH, rated for 18A was selected.

With a maximum input voltage of 53V, the maximum output

voltage is about 13V. The closest higher voltage rated

capacitor is 16V. Under steady state operating conditions the

ripple current in the capacitor is small, so it would seem

appropriate to have a low ripple current rated capacitor.

However, a high rated ripple current capacitor was selected

Ichg • t

(EQ. 13)

Cfet = -------------------

F

V

FN9147.8

12

September 22, 2005

ISL6744

based on the nature of the intended load, multiple buck

regulators. To minimize the output impedance of the filter, a

SANYO OSCON 16SH150M capacitor in parallel with a

22µF ceramic capacitor were selected.

reduction of the average current through the inductor. The

implication is that the converter can not supply the same

output current in current limit that it can supply under steady

state conditions. The peak current limit setpoint must take

this behavior into consideration. A 5.11Ω current sense

resistor was selected for the rectified secondary of current

transformer T2 for the ISL6744Eval 1, corresponding to a

peak current limit setpoint of about 11A.

Current Limit Threshold

The current limit threshold is fixed at 0.6V nominal, which is

the reference to the overcurrent protection comparator. The

current level that corresponds to the overcurrent threshold

must be chosen to allow for the dynamic behavior of an open

loop converter. In particular, the low inductor ripple current

under steady state operation increases significantly as the

duty cycle decreases.

Performance

The major performance criteria for the converter are

efficiency, and to a lesser extent, load regulation. Efficiency,

load regulation and line regulation performance are

demonstrated in the following Figures.

As expected, the output voltage varies considerably with line

and load when compared to an equivalent converter with a

closed loop feedback. However, for applications where tight

regulation is not required, such as those applications that

use downstream DC/DC converters, this design approach is

viable.

14

13

12

11

100

95

90

85

75

70

10

9

8

0.9950

0.9960

0.9970

0.9980

0.9990

1.000

TIME (ms)

V (L1:1)

I (L1)

FIGURE 8. STEADY STATE SECONDARY WINDING

VOLTAGE AND INDUCTOR CURRENT

15

10

5

0

1

2

3

4

5

6

7

8

9

10

LOAD CURRENT (A)

FIGURE 10. EFFICIENCY vs LOAD V = 48V

IN

12.5

12.25

12

0.986 0.988

0.990 0.992 0.994 0.996 0.998 1.000

TIME (ms)

11.75

11.5

11.25

11

V (L1:1)

I (L1)

FIGURE 9. SECONDARY WINDING VOLTAGE AND

INDUCTOR CURRENT DURING CURRENT LIMIT

OPERATION

Figures 8 and 9 show the behavior of the inductor ripple

under steady state and overcurrent conditions. In this

example, the peak current limit is set at 11A. The peak

current limit causes the duty cycle to decrease resulting in a

0

1

2

3

4

5

6

7

8

9

10

LOAD CURRENT (A)

FIGURE 11. LOAD REGULATION AT V = 48V

IN

FN9147.8

September 22, 2005

13

ISL6744

13.5

13

12.5

12

11.5

11

10.5

42 43

44

45

46

47

48

49

50

51

52

53

INPUT VOLTAGE (V)

FIGURE 12. LINE REGULATION AT I

= 1A

OUT

FIGURE 14. FET DRAIN-SOURCE VOLTAGE

Waveforms

Typical waveforms can be found in the following Figures.

Figure 13 shows the output voltage ripple and noise at a 5A.

FIGURE 15. FET D-S VOLTAGE NEAR-ZVS TRANSITION

FIGURE 13. OUTPUT RIPPLE AND NOISE - 20MHz BW

Figures 14 and 15 show the voltage waveforms at the

switching node shared by the upper FET source and the

lower FET drain. In particular, Figure 15 shows near ZVS

operation at 5A of load when the upper FET is turning off

and the lower FET is turning on. ZVS operation occurs

completely, implying that all the energy stored in the node

capacitance has been recovered. Figure 16 shows the

switching transition between outputs, OUTA and OUTB

during steady state operation. The deadtime duration of

46.9ns is clearly shown.

A 2.7V zener is added between the Vdd pins of ISL6700 and

ISL6744, in order to ensure that the PWM turns on only after

the driver has turned on, thereby ensuring the soft-start

function. Figure 17 shows the soft-start operation.

FIGURE 16. OUTA - OUTB TRANSITION

FN9147.8

September 22, 2005

14

ISL6744

FIGURE 17. OUTPUT SOFT-START

Component List

REFERENCE

DESIGNATOR

VALUE

1.0µF

3.3µF

1.0µF

0.1µF

4.7µF

Open

DESCRIPTION

C1

C2, C3

C4

Capacitor, 1812, X7R, 100V, 20%

Capacitor, 1812, X5R, 50V, 20%

Capacitor, 0805, X5R, 16V, 10%

Capacitor, 0603, X7R, 16V, 10%

Capacitor, 0805, X5R, 10V, 20%

C5

C6, C15

C7

Capacitor, 0603, Open or Optional Discrete Stray Capacitance

Capacitor, 1812, X5R, 16V, 20%

C8

22µF

C9

150µF

1000pF

Capacitor, Radial, Sanyo 16SH150M

C10, C11, C12,

C13, C14

Capacitor, 0603, X7R, 50V, 10%

C16

150pF

Capacitor, 0603, COG, 16V, 5%

Capacitor, 0603, X7R, 16V, 10%

Diode, Schottky, BAT54S, 30V

Diode, Schottky, BAT54, 30V

Diode, Schottky, SMA, 100V, 2.1A

Zener, 10V,Zetex BZX84C10ZXCT-ND

Zener, 2.7V, BZX84C2V7

C18

0.01µF

CR1, CR2

CR3

CR4

D1

D2

L1

190nH

1.5µH

Short

Pulse, P2004T

L2

L3

Bitech, HM73-301R5

Jumper or Optional Discrete Leakage Inductance

Keystone, 1514-2

P1, P2, P3, P4

Q5

NPN

Transistor, ON MJD31C

QL, QH

FET, Fairchild FDS3672, 100V

FN9147.8

15

September 22, 2005

ISL6744

Component List (Continued)

REFERENCE

DESIGNATOR

VALUE

DESCRIPTION

QR1, QR2, QR3,

QR4

FET, Fairchild FDS5670, 60V

R1

R2

3.3

3.01K

5.11

Resistor, 2512, 1%

Resistor, 0603, 1%

Resistor, 0805, 1%

Resistor, 2512, 1%

Resistor, 0603, 1%

Midcom 31718

R5

R6

205

R7

75.0K

20.0

R8, R9

R10

R11

R12

T1

18

100

10.0K

Custom

5002

T2

Midcom 31719R

Keystone

TP1, TP2, TP4,

TP5, TP6

SP1

U1

Tektronix Scope Jack, 131-4353-00

Intersil ISL6744AU, MSOP8

Intersil ISL6700IB, SOIC

U4

FN9147.8

16

September 22, 2005

ISL6744

Mini Small Outline Plas tic Packages (MSOP)

N

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES

MILLIMETERS

E1

E

SYMBOL

MIN

MAX

MIN

0.94

0.05

0.75

0.25

0.09

2.95

MAX

1.10

0.15

0.95

0.36

0.20

3.05

NOTES

A

A1

A2

b

0.037

0.002

0.030

0.010

0.004

0.116

0.043

0.006

0.037

0.014

0.008

0.120

-

-B-

0.20 (0.008)

INDEX

AREA

1 2

A

B

C

-

TOP VIEW

4X θ

9

0.25

(0.010)

R1

c

-

R

GAUGE

PLANE

D

3

E1

e

4

SEATING

PLANE

L

0.026 BSC

0.65 BSC

-

-C-

4X θ

L1

A

A2

E

0.187

0.016

0.199

0.028

4.75

0.40

5.05

0.70

-

L

6

SEATING

PLANE

L1

N

0.037 REF

0.95 REF

-

0.10 (0.004)

-A-

C

b

8

7

-H-

A1

e

R

0.003

-

0.07

-

D

0.20 (0.008)

C

R1

0

-

o

5

15

5

15

-

a

SIDE VIEW

C

L

o

0

6

0

6

-

α

E

1

-B-

Rev. 2 01/03

0.20 (0.008)

C

D

END VIEW

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs and are measured at Datum Plane. Mold flash, protrusion

and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions

- H -

and are measured at Datum Plane.

Interlead flash and

protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- B -

to be determined at Datum plane

-A -

10. Datums

and

.

- H -

11. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only.

FN9147.8

17

September 22, 2005

ISL6744

Small Outline Plastic Packages (SOIC)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

N

INDEX

0.25(0.010)

M

B M

H

AREA

INCHES MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

NOTES

-B-

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

0.0688

0.0098

0.020

-

1

2

3

L

9

SEATING PLANE

A

0.0075

0.1890

0.1497

0.0098

0.1968

0.1574

-

-A-

3

h x 45°

D

4

-C-

0.050 BSC

1.27 BSC

-

α

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C

A M B S

N

α

8

7

NOTES:

0°

8°

0°

8°

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Rev. 1 6/05

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9147.8

18

September 22, 2005


型号：	ISL6744ABZ
厂家：	Intersil
描述：	Intermediate Bus PWM Controller 中间总线PWM控制器控制器
文件：	总18页 (文件大小：401K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6744ABZ [INTERSIL]

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