ISL6745A [INTERSIL]

Improved Bridge Controller with Precision Dead Time Control; 改进的桥控制器，提供高精度死区时间控制


型号：	ISL6745A
厂家：	Intersil
描述：	Improved Bridge Controller with Precision Dead Time Control 改进的桥控制器，提供高精度死区时间控制控制器
文件：	总9页 (文件大小：192K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6745A

Data Sheet

September 11, 2008

FN6703.1

Improved Bridge Controller with Precision

Dead Time Control

Features

• Precision Duty Cycle and Deadtime Control

• 100µA Start-up Current

The ISL6745A is a low-cost double-ended voltage-mode

PWM controller designed for half-bridge and full-bridge

power supplies and line-regulated bus converters. It

provides precise control of switching frequency, adjustable

soft-start, and overcurrent shutdown. In addition, the

ISL6745A allows for accurate adjustment of MOSFET

non-overlap time (“deadtime”) with deadtimes as low as

35ns, allowing power engineers to optimize the efficiency of

open-loop bus converters. The ISL6745A also includes a

control voltage input for closed-loop PWM and line voltage

feed-forward functions. The ISL6745A is identical to the

ISL6745, but is optimized for higher noise environments.

• Adjustable Delayed Overcurrent Shutdown and Re-Start

• Adjustable Oscillator Frequency Up to 2MHz

• 1A MOSFET Gate Drivers

• Adjustable Soft-Start

• Internal Over-Temperature Protection

• 35ns Control to Output Propagation Delay

• Small Size and Minimal External Component Count

• Input Undervoltage Protection

Low start-up and operating currents allow for easy biasing in

both AC/DC and DC/DC applications. This advanced

BiCMOS design also features adjustable switching

frequency up to 1MHz, 1A FET drivers, and very low

propagation delays for a fast response to overcurrent faults.

The ISL6745A is available in a space-saving MSOP-10

package and is guaranteed to meet rated specifications over

a wide -40°C to +105°C temperature range.

• Pb-Free (RoHS Compliant)

Applications

• Half-bridge Converters

• Full-bridge Converters

• Line-regulated Bus Converters

• AC/DC Power Supplies

Ordering Information

• Telecom, Datacom, and File Server Power

PART

NUMBER

(Note)

TEMP.

RANGE

(°C)

PART

MARKING

PACKAGE

(Pb-Free)

PKG.

DWG. #

Pinout

ISL6745A

(10 LD MSOP)

TOP VIEW

ISL6745AAUZ* 6745A

-40 to +105 10 Ld MSOP M10.118

*Add “-T” suffix for tape and reel. Please refer to TB347 for details on

reel specifications.

RTD

VERR

VDD

NOTE: These Intersil Pb-free plastic packaged products employ

special Pb-free material sets, molding compounds/die attach

materials, and 100% matte tin plate plus anneal (e3 termination

finish, which is RoHS compliant and compatible with both SnPb and

Pb-free soldering operations). Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J STD-020.

VDDP

OUTB

OUTA

GND

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Internal Architecture

V_DDP

V_BIAS

5.00V

V_DD

OUTA

OUTB

UVLO

PWM TOGGLE

V_BIAS

INTERNAL

OT SHUTDOWN

130°C - 150°C

70µA

GND

V_BIAS

SS CLAMP

15µA

R_TD

2.0V

SS CHARGED

3.9V

I_RTD

4.0V

V_BIAS

160µA

OC LATCH

PEAK

2.8V

CLK

C_T

RESET

DOMINANT

VALLEY

SS LOW

0.27V

0.8V

50µs

RETRIGGERABLE

ONE SHOT

FAULT LATCH

SET DOMINANT

I_DCH

PWM LATCH

SET

V_BIAS

DOMINANT

V_BIASUV

4.65V ↓ 4.80V ↑

OC DETECT

0.6V

PWM COMPARATOR

V_BIA

C_T

15µA

0.8

V_ERR

0.8

Typical Application - Telecom DC/DC Converter

VIN+

+ VOUT

CR1

CR2

C10

36V TO 75V

(100V Max.)

RETURN

VIN-

CR4

CR3

ISL2100A

VDD

VSS

R11

ISL6745A

R10

VDD

RTD VDDP

VERR OUTB

OUTA

GND

TL431

VR2

VR1

ISL6745A

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V

Thermal Resistance (Typical, Note 1)

(°C/W)

155

OUTA, OUTB . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to V

10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5V

Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A

Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C

Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 9V to 16V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

2. All voltages are to be measured with respect to GND, unless otherwise specified.

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram on page 2 and Typical

Application schematic on page 3. 9V < V

< 16V, R = 51.1kΩ, C = 470pF, T = -40°C to +105°C, Typical

values are at T = +25°C; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise

specified. Temperature limits established by characterization and are not production tested.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

SUPPLY VOLTAGE

Start-Up Current, I

< START Threshold

175

8.5

6.6

6.3

µA

Operating Current, I

= 1nF

OUTA,B

UVLO START Threshold

UVLO STOP Threshold

Hysteresis

5.9

5.3

6.3

5.7

0.6

CURRENT SENSE

Current Limit Threshold

CS to OUT Delay

0.55

0.6

0.65

(Note 3)

CS Sink Current

µA

Input Bias Current

-1

PULSE WIDTH MODULATOR

Minimum Duty Cycle

Maximum Duty Cycle

< C Offset

ERROR

= 470pF, R = 51.1kΩ

0.8

= 470pF, R = 1.1kΩ (Note 3)

to PWM Comparator Input Gain

V/V

ERR

(Note 3)

SS to PWM Comparator Input Gain

OSCILLATOR

0.8

Charge Current

= +25°C

143

1.925

156

170

2.075

µA

Voltage

Discharge Current Gain

µA/µA

Valley Voltage

Peak Voltage

0.75

2.70

0.8

2.80

0.85

2.90

FN6703.1

September 11, 2008

ISL6745A

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram on page 2 and Typical

Application schematic on page 3. 9V < V

< 16V, R = 51.1kΩ, C = 470pF, T = -40°C to +105°C, Typical

values are at T = +25°C; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise

specified. Temperature limits established by characterization and are not production tested. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

SOFT-START

Net Charging Current

3.8

4.2

µA

SS Clamp Voltage

4.0

3.9

Overcurrent Shutdown Threshold Voltage

Overcurrent Discharge Current

Reset Threshold Voltage

OUTPUT

(Note 3)

µA

0.25

0.27

0.31

High Level Output Voltage (VOH)

- V

or V ,

OUTB

0.5

2.0

OUTA

= -100mA

OUT

Low Level Output Voltage (VOL)

Rise Time

= 100mA

0.5

1.0

OUT

= 1nF, V

= 12V

GATE

Fall Time

THERMAL PROTECTION

Thermal Shutdown

Thermal Shutdown Clear

Hysteresis, Internal Protection

NOTES:

(Note 3)

145

130

°C

3. Limits established by characterization and are not production tested.

FN6703.1

September 11, 2008

ISL6745A

Typical Performance Curves

1-10

CT = 1000pF

CT = 680pF

CT = 470pF

CT = 270pF

CT = 100pF

100

0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

100

RTD CURRENT (mA)

RTD (kΩ)

FIGURE 1. OSCILLATOR CT DISCHARGE CURRENT GAIN

FIGURE 2. DEADTIME vs CAPACITANCE

600

500

400

300

200

1.03

1.02

1.01

1.00

0.99

0.98

0.97

0.96

0.95

100

-40 -25 -10

95 110

100

200 300

400 500

600

700 800

900

CT (pF)

TEMPERATURE (°C)

FIGURE 3. CAPACITANCE vs OSCILLATOR FREQUENCY

FIGURE 4. CHARGE CURRENT vs TEMPERATURE

(RTD = 49.9kΩ)

1.07

1.06

1.05

1.04

1.03

1.02

1.01

1.00

0.99

0.98

100

RTD (kΩ)

FIGURE 5. TIMING CAPACITOR VOLTAGE vs RTD

FN6703.1

September 11, 2008

ISL6745A

during start-up, controls the overcurrent shutdown delay, and

the overcurrent and short circuit hiccup restart period.

Pin Descriptions

- V is the power connection for the IC. To optimize

noise immunity, bypass V

to GND with a ceramic

- The inverting input of the PWM comparator. The

ERR

capacitor as close to the V

and GND pins as possible.

error voltage is applied to this pin to control the duty cycle.

Increasing the signal level increases the duty cycle. The

node may be driven with an external error amplifier or an

opto-coupler.

The total supply current, I , will be dependent on the load

applied to outputs OUTA and OUTB. Total I

sum of the quiescent current and the average output current.

current is the

Knowing the operating frequency, F , and the output

loading capacitance charge, Q, per output, the average

output current can be calculated from Equation 1:

- V

DDP

is the separate collector supply to the gate

pin helps isolate the analog

DDP

drive. Having a separate V

circuitry from the high power gate drive noise.

DDP

= 2 • Q • F

(EQ. 1)

OUT

Functional Description

- This is the oscillator timing capacitor discharge current

Features

control pin. A resistor is connected between this pin and

GND. The current flowing through the resistor determines

the magnitude of the discharge current. The discharge

current is nominally 55x this current. The PWM deadtime is

determined by the timing capacitor discharge duration.

The ISL6745A PWM is an excellent choice for low cost

bridge topologies for applications requiring accurate

frequency and deadtime control. Among its many features

are 1A FET drivers, adjustable soft-start, overcurrent

protection and internal thermal protection, allowing a highly

flexible design with minimal external components.

C - The oscillator timing capacitor is connected between

this pin and GND.

Oscillator

CS - This is the input to the overcurrent protection comparator.

The overcurrent comparator threshold is set at 0.600V nominal.

The CS pin is shorted to GND at the end of each switching

cycle. Depending on the current sensing source impedance, a

series input resistor may be required due to the delay between

the internal clock and the external power switch.

The ISL6745A has an oscillator with a frequency range to

2MHz, programmable using a resistor R and capacitor C .

The switching period may be considered to be the sum of

the timing capacitor charge and discharge durations. The

charge duration is determined by C and the internal current

source (assumed to be 160µA in the formula). The discharge

Exceeding the overcurrent threshold will start a delayed

shutdown sequence. Once an overcurrent condition is

detected, the soft-start charge current source is disabled.

The soft-start capacitor begins discharging through a 15µA

current source, and if it discharges to less than 3.9V

(Sustained Overcurrent Threshold), a shutdown condition

occurs and the OUTA and OUTB outputs are forced low.

When the soft-start voltage reaches 0.27V (Reset

Threshold) a soft-start cycle begins.

duration is determined by R and C .

≈ 1.25×10 • C

(EQ. 2)

(EQ. 3)

----------------------------------------------------------------------------

≈

• R

• C

CTDischargeCurrentGain

---------------

= T + T =

(EQ. 4)

OSC

where T and T are the approximate charge and discharge

times, respectively, T

is the oscillator free running

is the oscillator frequency. One output

If the overcurrent condition ceases, and then an additional

50µs period elapses before the shutdown threshold is

reached, no shutdown occurs. The SS charging current is

re-enabled and the soft-start voltage is allowed to recover.

OSC

period, and F

OSC

switching cycle requires two oscillator cycles. The actual

times will be slightly longer than calculated due to internal

propagation delays of approximately 5ns/transition. This

delay adds directly to the switching duration, and also

causes overshoot of the timing capacitor peak and valley

voltage thresholds, effectively increasing the peak-to-peak

voltage on the timing capacitor. Additionally, if very low

charge and discharge currents are used, there will be an

GND - Reference and power ground for all functions on this

device. Due to high peak currents and high frequency

operation, a low impedance layout is necessary. Ground

planes and short traces are highly recommended.

OUTA and OUTB - Alternate half cycle output stages. Each

output is capable of 1A peak currents for driving power

MOSFETs or MOSFET drivers. Each output provides very

low impedance to overshoot and undershoot.

increased error due to the input impedance at the C pin.

The above formulae help with the estimation of the

frequency. Practically, effects like stray capacitances that

affect the overall C capacitance, variation in R voltage

SS - Connect the soft-start timing capacitor between this pin

and GND to control the duration of soft-start. The value of the

capacitor determines the rate of increase of the duty cycle

and charge current over-temperature, etc. exist, and are

best evaluated in-circuit. Equation 2 follows from the basic

capacitor current equation, i = C × . In this case, with

FN6703.1

September 11, 2008

ISL6745A

variation in dV with R (Figure 5), and in charge current

Overcurrent Operation

(Figure 4), results from Equation 2 would differ from the

calculated frequency. The typical performance curves may

be used as a tool along with the previous equations as a

more accurate tool to estimate the operating frequency more

accurately.

Overcurrent delayed shutdown is enabled once the soft-start

cycle is complete. If an overcurrent condition is detected, the

soft-start charging current source is disabled and the

soft-start capacitor is allowed to discharge through a 15µA

source. At the same time a 50µs retriggerable one-shot timer

is activated. It remains active for 50µs after the overcurrent

condition ceases. If the soft-start capacitor discharges to

3.9V, the output is disabled. This state continues until the

soft-start voltage reaches 270mV, at which time a new

soft-start cycle is initiated. If the overcurrent condition stops

at least 50µs prior to the soft-start voltage reaching 3.9V, the

soft-start charging currents revert to normal operation and

the soft-start voltage is allowed to recover.

The maximum duty cycle, D, and deadtime, DT, can be

calculated from:

D = T ⁄ T

(EQ. 5)

OSC

DT = (1 – D) ⋅ T

(EQ. 6)

OSC

Soft-Start Operation

The ISL6745A features a soft-start using an external

Thermal Protection

capacitor in conjunction with an internal current source.

Soft-start reduces stresses and surge currents during

start-up.

An internal temperature sensor protects the device should

the junction temperature exceed +145°C. There is

approximately +15°C of hysteresis.

The oscillator capacitor signal, C , is compared to the

soft-start voltage, SS, in the SS comparator which drives the

PWM latch. While the SS voltage is less than 3.5V, duty

cycle is limited. The output pulse width increases as the

soft-start capacitor voltage increases up to 3.5V. This has

the effect of increasing the duty cycle from zero to the

maximum pulse width during the soft-start period. When the

soft-start voltage exceeds 3.5V, soft-start is completed.

Soft-start occurs during start-up and after recovery from an

overcurrent shutdown. The soft-start voltage is clamped to 4V.

Ground Plane Requirements

Careful layout is essential for satisfactory operation of the

device. A good ground plane must be employed. V

be bypassed directly to GND with good high frequency

capacitance.

should

Gate Drive

The ISL6745A is capable of sourcing and sinking 1A peak

current, and may also be used in conjunction with a

MOSFET driver such as the ISL6700 for level shifting. To

limit the peak current through the IC, an external resistor

may be placed between the totem-pole output of the IC

(OUTA or OUTB pin) and the gate of the MOSFET. This

small series resistor also damps any oscillations caused by

the resonant tank of the parasitic inductances in the traces of

the board and the FET’s input capacitance.

FN6703.1

September 11, 2008

ISL6745A

Mini Small Outline Plastic Packages (MSOP)

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

0.94

0.05

0.75

0.18

0.09

2.95

MAX

1.10

0.15

0.95

0.27

0.20

3.05

NOTES

-B-

0.20 (0.008)

INDEX

AREA

0.037

0.002

0.030

0.007

0.004

0.116

0.043

0.006

0.037

0.011

0.008

0.120

1 2

TOP VIEW

4X θ

0.25

(0.010)

GAUGE

PLANE

SEATING

PLANE

-C-

4X θ

0.020 BSC

0.50 BSC

0.187

0.016

0.199

0.028

4.75

0.40

5.05

0.70

SEATING

PLANE

0.10 (0.004)

-A-

0.037 REF

0.95 REF

-H-

0.003

0.07

0.20 (0.008)

SIDE VIEW

-B-

0.20 (0.008)

END VIEW

Rev. 0 12/02

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs and are measured at Datum Plane. Mold flash, protrusion

and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions

- H -

and are measured at Datum Plane.

Interlead flash and

protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- B -

-A -

10. Datums

and

to be determined at Datum plane

- H -

11. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6703.1

September 11, 2008

ISL6745A [INTERSIL]

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