ISL6745AU [RENESAS]
1A SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PDSO10, PLASTIC, MO-187BA, MSOP-10;
| 型号： | ISL6745AU |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1A SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PDSO10, PLASTIC, MO-187BA, MSOP-10 信息通信管理 开关 光电二极管 |
| 文件： | 总8页 (文件大小：412K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NOT RECOMMENDED FOR NEW DESIGNS
RECOMMENDED REPLACEMENT PART
ISL6745A
DATASHEET
ISL6745
FN9161
Rev.6.00
Sept 1, 2005
Bridge Controller with Precision Dead Time Control
The ISL6745 is a low-cost double-ended voltage-mode
PWM controller designed for half-bridge and full-bridge
power supplies and line-regulated bus converters. It
provides precise control of switching frequency, adjustable
soft-start, and overcurrent shutdown. In addition, the
ISL6745 allows for accurate adjustment of MOSFET non-
overlap time (“deadtime”) with deadtimes as low as 35ns,
allowing power engineers to optimize the efficiency of open-
loop bus converters. The ISL6745 also includes a control
voltage input for closed-loop PWM and line voltage feed-
forward functions.
Features
• Precision Duty Cycle and Deadtime Control
• 100A Start-up Current
• Adjustable Delayed Overcurrent Shutdown and Re-Start
• Adjustable Oscillator Frequency Up to 2MHz
• 1A MOSFET Gate Drivers
• Adjustable Soft-Start
• Internal Over Temperature Protection
• 35ns Control to Output Propagation Delay
• Small Size and Minimal External Component Count
• Input Undervoltage Protection
Low start-up and operating currents allow for easy biasing in
both AC/DC and DC/DC applications. This advanced
BiCMOS design also features adjustable switching
frequency up to 1MHz, 1A FET drivers, and very low
propagation delays for a fast response to overcurrent faults.
The ISL6745 is available in a space-saving MSOP-10
package and is guaranteed to meet rated specifications over
a wide -40°C to 105°C temperature range.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Half-bridge Converters
Ordering Information
• Full-bridge Converters
TEMP. RANGE
(°C)
PKG.
DWG. #
• Line-regulated Bus Converters
• AC/DC Power Supplies
PART NUMBER
PACKAGE
ISL6745AU
-40 to 105
-40 to 105
10 Ld MSOP M10.118
• Telecom, Datacom, and File Server Power
ISL6745AUZ
(See Note)
10 Ld MSOP M10.118
(Pb-free)
Pinout
Add -T suffix to part number for tape and reel packaging
ISL6745 (MSOP)
TOP VIEW
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
SS
RTD
VERR
CS
1
10
9
VDD
VDDP
2
3
8
OUTB
OUTA
GND
7
4
5
CT
6
FN9161 Rev.6.00
Sept 1, 2005
Page 1 of 8
Internal Architecture
VDDP
FL
VBIAS
VBIAS
5.00 V
VDD
OUTA
OUTB
Q
T
UVLO
Q
+
-
PWM TOGGLE
VBIAS
INTERNAL
OT SHUTDOWN
130 - 150 C
BG
70 uA
GND
ON
SS
VBIAS
+
-
SS CLAMP
15 uA
RTD
-
2.0 V
+
SS CHARGED
3.9 V
IRTD
-
+
4.0 V
S
R
Q
Q
VBIAS
160 uA
OC LATCH
ON
-
PEAK
2.8 V
CLK
S
R
Q
Q
+
CT
Q
Q
RESET
DOMINANT
-
VALLEY
SS LOW
0.27 V
+
0.8 V
+
50 µS
-
RETRIGGERABLE
ONE SHOT
SS
FAULT LATCH
SET DOMINANT
S
Q
S
R
Q
Q
FL
IDCH
R
Q
PWM LATCH
SET
ON
VBIAS
DOMINANT
-
VBIAS UV
4.65V 4.80V
+
BG
OC DETECT
CS
+
-
0.6 V
PWM COMPARATOR
+
VBIAS
CT
-
-
15 uA
VERR
SS
0.8
0.8
ISL6745
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V
Thermal Resistance (Typical, Note 1)
(°C/W)
128
DD
OUTA, OUTB . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to V
JA
DD
10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A
ESD Classification
Maximum Junction Temperature . . . . . . . . . . . . . . . .-55°C to 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Human Body Model (Per JEDEC22 std. Method A114-B) . Class 2
Machine Model (Per JEDEC22 std. Method A115-A). . . . .Class A
Operating Conditions
Temperature Range
ISL6745AU . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 105°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 9-16 VDC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. All voltages are to be measured with respect to GND, unless otherwise specified.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic. 9V < V < 16V, R = 51.1k, C = 470pF, T = -40°C to 105°C (Note 4), Typical values are at
DD
TD
T
A
T
= 25°C
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY VOLTAGE
Start-Up Current, I
V
< START Threshold
DD
-
-
-
175
8.5
6.6
6.3
-
A
mA
V
DD
Operating Current, I
C
= 1nF
5
DD
OUTA,B
UVLO START Threshold
UVLO STOP Threshold
Hysteresis
5.9
5.3
-
6.3
5.7
0.6
V
V
CURRENT SENSE
Current Limit Threshold
CS to OUT Delay
0.55
0.6
35
10
-
0.65
V
(Note 4)
-
-
-
ns
CS Sink Current
8
mA
A
Input Bias Current
-1
1
PULSE WIDTH MODULATOR
Minimum Duty Cycle
Maximum Duty Cycle
V
< C Offset
-
-
-
-
-
-
-
0
-
%
%
ERROR
T
C
= 470pF, R = 51.1k
TD
94
99
0.8
1
T
T
C
= 470pF, R = 1.1k(Note 4)
TD
-
%
V
to PWM Comparator Input Gain
to PWM Comparator Input Gain
-
V/V
V/V
V/V
ERR
C
(Note 4)
(Note 4)
-
T
SS to PWM Comparator Input Gain
0.8
-
FN9161 Rev.6.00
Sept 1, 2005
Page 3 of 8
ISL6745
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic. 9V < V < 16V, R = 51.1k, C = 470pF, T = -40°C to 105°C (Note 4), Typical values are at
DD
TD
T
A
T
= 25°C (Continued)
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OSCILLATOR
Charge Current
T
= 25°C
143
1.925
45
156
2
170
2.075
65
A
V
A
R
Voltage
TD
Discharge Current Gain
-
A/A
V
C
C
Valley Voltage
Peak Voltage
0.75
2.70
0.8
2.80
0.85
2.90
T
V
T
SOFT-START
Net Charging Current
SS Clamp Voltage
45
3.8
-
-
68
4.2
-
A
V
4.0
3.9
15
Overcurrent Shutdown Threshold Voltage
Overcurrent Discharge Current
Reset Threshold Voltage
(Note 4)
(Note 4)
V
12
23
A
V
0.25
0.27
0.30
OUTPUT
High Level Output Voltage (VOH)
V
- V
or V ,
OUTB
-
0.5
2.0
V
DD
OUTA
I
= -100mA
OUT
Low Level Output Voltage (VOL)
Rise Time
I
= 100mA
-
-
-
0.5
17
20
1.0
60
60
V
OUT
C
= 1nF, V
= 1nF, V
= 12V
= 12V
ns
ns
GATE
GATE
DD
Fall Time
C
DD
THERMAL PROTECTION
Thermal Shutdown
Thermal Shutdown Clear
Hysteresis, Internal Protection
NOTES:
(Note 4)
(Note 4)
(Note 4)
-
-
-
145
130
15
-
-
-
°C
°C
°C
3. Specifications at -40°C are guaranteed by design, not production tested.
4. Guaranteed by design, not 100% tested in production.
FN9161 Rev.6.00
Sept 1, 2005
Page 4 of 8
ISL6745
Typical Performance Curves
4
3
65
1-10
1-10
CT =
1000pF
680pF
470pF
60
55
50
45
CT = 270pF
CT = 100pF
100
10
40
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
10
20
30
40
50
60
70
80
90
100
RTD CURRENT (mA)
RTD (k)
FIGURE 1. OSCILLATOR CT DISCHARGE CURRENT GAIN
FIGURE 2. DEADTIME vs CAPACITANCE
600
500
400
300
200
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
100
0
-40 -25 -10
5
20
35
50
65
80
95 110
100
200 300
400 500
600
700 800
900 1000
CT (pF)
TEMPERATURE (°C)
FIGURE 3. CAPACITANCE vs OSCILLATOR FREQUENCY
FIGURE 4. CHARGE CURRENT vs TEMPERATURE
(RTD = 49.9k)
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0
10
20
30
40
50
60
70
80
90
100
RTD (k)
FIGURE 5. TIMING CAPACITOR VOLTAGE vs RTD
FN9161 Rev.6.00
Sept 1, 2005
Page 5 of 8
ISL6745
during start-up, controls the overcurrent shutdown delay, and the
overcurrent and short circuit hiccup restart period.
Pin Descriptions
V
- V
is the power connection for the IC. To optimize
to GND with a ceramic capacitor
and GND pins as possible.
DD
DD
noise immunity, bypass V
as close to the V
DD
V
- The inverting input of the PWM comparator. The error
DD
ERR
voltage is applied to this pin to control the duty cycle.
Increasing the signal level increases the duty cycle. The node
may be driven with an external error amplifier or an opto-
coupler.
The total supply current, I , will be dependent on the load
DD
applied to outputs OUTA and OUTB. Total I
sum of the quiescent current and the average output current.
current is the
DD
Knowing the operating frequency, F , and the output loading
capacitance charge, Q, per output, the average output current
can be calculated from:
V
- V
DDP
is the separate collector supply to the gate drive.
pin helps isolate the analog circuitry
SW
DDP
Having a separate V
from the high power gate drive noise.
DDP
I
= 2 Q F
A
(EQ. 1)
OUT
SW
Functional Description
R
- This is the oscillator timing capacitor discharge current
TD
Features
control pin. A resistor is connected between this pin and GND.
The current flowing through the resistor determines the
magnitude of the discharge current. The discharge current is
nominally 55x this current. The PWM deadtime is determined
by the timing capacitor discharge duration.
The ISL6745 PWM is an excellent choice for low cost bridge
topologies for applications requiring accurate frequency and
deadtime control. Among its many features are 1A FET drivers,
adjustable soft-start, overcurrent protection and internal
thermal protection, allowing a highly flexible design with
minimal external components.
C - The oscillator timing capacitor is connected between this
T
pin and GND.
Oscillator
CS - This is the input to the overcurrent protection comparator.
The overcurrent comparator threshold is set at 0.600V nominal.
The CS pin is shorted to GND at the end of each switching cycle.
Depending on the current sensing source impedance, a series
input resistor may be required due to the delay between the
internal clock and the external power switch.
The ISL6745 has an oscillator with a frequency range to 2MHz,
programmable using a resistor R and capacitor C .
TD
T
The switching period may be considered to be the sum of the
timing capacitor charge and discharge durations. The charge
duration is determined by C and the internal current source
T
(assumed to be 160A in the formula). The discharge duration
Exceeding the overcurrent threshold will start a delayed
shutdown sequence. Once an overcurrent condition is
detected, the soft-start charge current source is disabled. The
soft-start capacitor begins discharging through a 15µA current
source, and if it discharges to less than 3.9V (Sustained
Overcurrent Threshold), a shutdown condition occurs and the
OUTA and OUTB outputs are forced low. When the soft-start
voltage reaches 0.27V (Reset Threshold) a soft-start cycle
begins.
is determined by R and C .
TD
T
4
T
1.2510 C
s
(EQ. 2)
(EQ. 3)
C
T
1
----------------------------------------------------------------------------
T
R
C
T
s
D
TD
CTDischargeCurrentGain
1
---------------
T
= T + T =
D
s
(EQ. 4)
OSC
C
F
OSC
where T and T are the approximate charge and discharge
C
D
times, respectively, T
is the oscillator free running period,
If the overcurrent condition ceases, and then an additional
50µs period elapses before the shutdown threshold is reached,
no shutdown occurs. The SS charging current is re-enabled
and the soft-start voltage is allowed to recover.
OSC
and F
is the oscillator frequency. One output switching
OSC
cycle requires two oscillator cycles. The actual times will be
slightly longer than calculated due to internal propagation
delays of approximately 5ns/transition. This delay adds directly
to the switching duration, and also causes overshoot of the
timing capacitor peak and valley voltage thresholds, effectively
increasing the peak-to-peak voltage on the timing capacitor.
Additionally, if very low charge and discharge currents are
used, there will be an increased error due to the input
GND - Reference and power ground for all functions on this
device. Due to high peak currents and high frequency
operation, a low impedance layout is necessary. Ground
planes and short traces are highly recommended.
OUTA and OUTB - Alternate half cycle output stages. Each
output is capable of 1A peak currents for driving power
MOSFETs or MOSFET drivers. Each output provides very low
impedance to overshoot and undershoot.
impedance at the C pin.
T
The above formulae help with the estimation of the frequency.
Practically, effects like stray capacitances that affect the overall
C capacitance, variation in R voltage and charge current
SS - Connect the soft-start timing capacitor between this pin and
GND to control the duration of soft-start. The value of the
capacitor determines the rate of increase of the duty cycle
T
TD
over temperature, etc. exist, and are best evaluated in-circuit.
Equation 2 follows from the basic capacitor current equation,
dV
dt
i = C
. In this case, with variation in dV with R (Figure
TD
FN9161 Rev.6.00
Sept 1, 2005
Page 6 of 8
ISL6745
5), and in charge current (Figure 4), results from Equation 2
would differ from the calculated frequency. The typical
performance curves may be used as a tool along with the
previous equations as a more accurate tool to estimate the
operating frequency more accurately.
Overcurrent Operation
Overcurrent delayed shutdown is enabled once the soft-start
cycle is complete. If an overcurrent condition is detected, the
soft-start charging current source is disabled and the soft-start
capacitor is allowed to discharge through a 15µA source. At
the same time a 50µs retriggerable one-shot timer is activated.
It remains active for 50µs after the overcurrent condition
ceases. If the soft-start capacitor discharges to 3.9V, the output
is disabled. This state continues until the soft-start voltage
reaches 270mV, at which time a new soft-start cycle is initiated.
If the overcurrent condition stops at least 50µs prior to the soft-
start voltage reaching 3.9V, the soft-start charging currents
revert to normal operation and the soft-start voltage is allowed
to recover.
The maximum duty cycle, D, and deadtime, DT, can be
calculated from:
D = T T
(EQ. 5)
C
OSC
DT = 1 – D T
s
(EQ. 6)
OSC
Soft-Start Operation
The ISL6745 features a soft-start using an external capacitor in
conjunction with an internal current source. Soft-start reduces
stresses and surge currents during start-up.
Thermal Protection
An internal temperature sensor protects the device should the
junction temperature exceed 145°C. There is approximately
15°C of hysteresis.
The oscillator capacitor signal, C , is compared to the soft-start
T
voltage, SS, in the SS comparator which drives the PWM latch.
While the SS voltage is less than 3.5V, duty cycle is limited.
The output pulse width increases as the soft-start capacitor
voltage increases up to 3.5V. This has the effect of increasing
the duty cycle from zero to the maximum pulse width during the
soft-start period. When the soft-start voltage exceeds 3.5V,
soft-start is completed. Soft-start occurs during start-up and
after recovery from an overcurrent shutdown. The soft-start
voltage is clamped to 4V.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. V
should
DD
be bypassed directly to GND with good high frequency
capacitance.
Gate Drive
The ISL6745 is capable of sourcing and sinking 1A peak
current, and may also be used in conjunction with a MOSFET
driver such as the ISL6700 for level shifting. To limit the peak
current through the IC, an external resistor may be placed
between the totem-pole output of the IC (OUTA or OUTB pin)
and the gate of the MOSFET. This small series resistor also
damps any oscillations caused by the resonant tank of the
parasitic inductances in the traces of the board and the FET’s
input capacitance.
© Copyright Intersil Americas LLC 2004-2005. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9161 Rev.6.00
Sept 1, 2005
Page 7 of 8
ISL6745
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.18
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.27
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.007
0.004
0.116
0.116
0.043
0.006
0.037
0.011
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X
9
0.25
(0.010)
R1
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
L
0.020 BSC
0.50 BSC
-
-C-
4X
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
SEATING
PLANE
L1
N
0.037 REF
10
0.95 REF
10
-
0.10 (0.004)
-A-
C
C
b
7
-H-
A1
e
R
0.003
0.003
-
-
0.07
0.07
-
-
-
D
0.20 (0.008)
C
R1
-
o
o
o
o
a
SIDE VIEW
5
15
5
15
-
C
L
o
o
o
o
0
6
0
6
-
E
1
-B-
Rev. 0 12/02
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
-A -
10. Datums
and
to be determined at Datum plane
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only
FN9161 Rev.6.00
Sept 1, 2005
Page 8 of 8
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