ISL6752AAZA_技术文档

DATASHEET

ISL6752

FN9181

Rev 4.00

August 1, 2016

ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier

Control

The ISL6752 is a high-performance, low-pin count alternative

Features

Zero-Voltage Switching (ZVS) full-bridge PWM controller. Like

• Adjustable resonant delay for ZVS operation

Intersil’s ISL6551, it achieves ZVS operation by driving the upper

bridge FETs at a fixed 50% duty cycle while the lower bridge FETs

are trailing-edge modulated with adjustable resonant switching

delays. Compared to the more familiar phase-shifted control

method, this algorithm offers equivalent efficiency and improved

overcurrent and light load performance with less complexity in a

lower pin count package.

• Synchronous rectifier control outputs with adjustable

delay/advance

• Current-mode control

• 3% current limit threshold

• Adjustable dead time control

• 175µA start-up current

The ISL6752 features complemented PWM outputs for

Synchronous Rectifier (SR) control. The complemented

outputs may be dynamically advanced or delayed relative to

the PWM outputs using an external control voltage.

• Supply UVLO

• Adjustable oscillator frequency up to 2MHz

• Internal over-temperature protection

• Buffered oscillator sawtooth output

• Fast current sense to output delay

• Adjustable cycle-by-cycle peak current limit

• 70ns leading edge blanking

• Multi-pulse suppression

This advanced BiCMOS design features precision dead time

and resonant delay control and an oscillator adjustable to

2MHz operating frequency. Additionally, multi-pulse

suppression ensures alternating output pulses at low duty

cycles where pulse skipping may occur.

Related Literature

• AN1262, “Designing with the ISL6752, ISL6753 ZVS

Full-Bridge Controllers”

• Pb-free (RoHS compliant)

• AN1603, “ISL6752/54EVAL1Z ZVS DC/DC Power Supply

with Synchronous Rectifiers User Guide”

Applications

• ZVS full-bridge converters

• Telecom and datacom power

• Wireless base station power

• File server power

• AN1619, “Designing with ISL6752DBEVAL1Z and

ISL6754DBEVAL1Z Control Cards”

• Industrial power systems

Pin Configuration

ISL6752

(16 LD QSOP)

TOP VIEW

VADJ

VREF

VERR

CTBUF

RTD

1

2

3

4

5

6

7

8

16 VDD

15 OUTLL

14 OUTLR

13 OUTUL

12 OUTUR

11 OUTLLN

10 OUTLRN

RESDEL

CT

9

GND

CS

FN9181 Rev 4.00

August 1, 2016

Page 1 of 18

ISL6752

Ordering Information

PART NUMBER

PACKAGE

(Notes 1, 2, 3)

PART MARKING

TEMP. RANGE (°C)

-40 to +105

(RoHS COMPLIANT)

PKG. DWG. #

M16.15A

ISL6752AAZA

ISL 6752AAZ

16 Ld QSOP

ISL6752/54EVAL1Z

ISL6752DBEVAL1Z

NOTES:

Evaluation Board

1. Add “T” suffix for 2.5k unit Tape and Reel options. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6752. For more information on MSL, please see tech brief TB363

TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS

PARAMETERS

Topology

ISL6754

ISL6753

ISL6752

ISL6551

Zero-Voltage Switching (ZVS)

Zero-Voltage Switching

(ZVS)

Zero-Voltage-Switching

(ZVS)

Topology Characteristic Full-bridge ZVS

Full-bridge ZVS

Control Mode

Peak current-mode or voltage

mode

Peak current-mode

mode

8.75V

7V

UVLO Rising (V)

UVLO Falling (V)

8.75V

7V

8.75V

7V

9.6V

8.6V

16V

V

(maximum)

20V

BIAS

No-Load Operating

Current

11mA (typica), 15.5mA

(maximum)

11mA (typical), 15.5mA

(maximum)

11mA (typical), 15.5mA

(maximum)

13mA

# of PWM Outputs

6

4

6

FET Driver I

OUT

10mA

1A

(maximum)

Maximum Duty Cycle (%) 99

99

FN9181 Rev 4.00

August 1, 2016

Page 2 of 18

ISL6752

Absolute Maximum Ratings (Note 5)

Thermal Information

Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to +20.0V

OUTxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to VDD

Thermal Resistance Junction to Ambient (Typical)



(°C/W)

100

JA

16 Ld QSOP (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to V

+ 0.3V

REF

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . .-55°C to +150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493

VREF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to 6.0V

Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1A

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C

Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . . . 9VDC to 16VDC

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4.  is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

5. All voltages are with respect to GND.

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 3

and “typical application on Figure 2 on page 4 and Figure 3 on page 5. 9V < V < 20V, RTD = 10.0kΩ CT = 470pF, T = -40°C to +105°C, Typical values

DD

A

are at T = +25°C.

A

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 10)

TYP

(Note 10)

UNIT

SUPPLY VOLTAGE

Supply Voltage

-

20

400

15.5

9.00

7.50

-

V

µA

mA

V

Start-Up Current, I

V

= 5.0V

DD

-

175

11.0

8.75

7.00

1.75

DD

Operating Current, I

DD

R

, C

LOAD OUT

= 0

-

UVLO START Threshold

UVLO STOP Threshold

Hysteresis

8.00

6.50

-

V

REFERENCE VOLTAGE

Overall Accuracy

I

= 0mA to -10mA

4.850

5.000

5.150

V

VREF

Long Term Stability

T

= +125°C, 1000 hours (Note 6)

-

3

-

mV

mA

A

Operational Current (Source)

Operational Current (Sink)

Current Limit

-10

5

-

V

= 4.85V

-15

-

-100

REF

CURRENT SENSE

Current Limit Threshold

CS to OUT Delay

VERR = V

REF

0.97

1.00

1.03

50

V

ns

Ω

Excl. LEB (Note 6)

(Note 6)

-

50

-

35

Leading Edge Blanking (LEB) Duration

CS to OUT Delay + LEB

CS Sink Current Device Impedance

Input Bias Current

70

100

130

20

T

= +25°C

-

A

V

= 1.1V

= 0.3V

-

CS

-6.00

65

-2.00

95

µA

mV

CS to PWM Comparator Input Offset

PULSE WIDTH MODULATOR

VERR Pull-Up Current Source

T

= +25°C

80

A

VERR = 2.50V

= 0mA

0.80

4.20

-

1.00

1.30

mA

V

VERR V

OH

I

-

LOAD

Minimum Duty Cycle

VERR < 0.6V

0

%

FN9181 Rev 4.00

August 1, 2016

Page 6 of 18

ISL6752

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 3

and “typical application on Figure 2 on page 4 and Figure 3 on page 5. 9V < V < 20V, RTD = 10.0kΩ CT = 470pF, T = -40°C to +105°C, Typical values

DD

A

are at T = +25°C. (Continued)

A

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 10)

TYP

94

97

99

-

(Note 10)

UNIT

%

Maximum Duty Cycle (Per Half-Cycle)

VERR = 4.20V, V = 0V (Note 7)

CS

-

RTD = 2.0kΩ, CT = 220pF

RTD = 2.0kΩ CT = 470pF

-

%

-

%

Zero Duty Cycle VERR Voltage

VERR to PWM Comparator Input Offset

VERR to PWM Comparator Input Gain

Common-Mode (CM) Input Range

OSCILLATOR

0.85

0.7

0.31

0

1.20

0.9

0.35

4.45

V

T

= +25°C

0.8

0.33

-

V

A

V/V

V

(Note 6)

Frequency Accuracy, Overall

165

-10

-

183

-

201

10

kHz

%

Frequency Variation with VDD

Temperature Stability

T

= +25°C, (F

- F

)/F

0.3

4.5

1.5

-200

20

1.7

%

A

20V- 10V 10V

V

= 10V, |F

- F |/F

0°C

-

%

DD

-40°C 0°C

|F

- F

|/F

(Note 6)

-

%

0°C 105°C

25°C

Charge Current

T

= +25°C

-193

19

-207

23

µA

A

Discharge Current Gain

CT Valley Voltage

µA/µA

Static Threshold

Static Value

0.75

2.75

1.92

1.97

0

0.80

2.80

2.00

-

0.88

2.88

2.05

2.03

2.00

2.05

0.44

0.10

V

CT Peak Voltage

CT Peak-to-Peak Voltage

RTD Voltage

V

RESDEL Voltage Range

V

CTBUF Gain (V

/V

CTBUF Offset from GND

)

V

= 0.8V, 2.6V

= 0.8V

1.95

0.34

-

2.0

0.40

-

V/V

V

CTBUFp-p CTp-p

CT

CTBUF V

OUTPUT

V(I

LOAD

V

= 0mA, I

= -2mA),

= 0mA),

V

OH

LOAD

= 2.6V

CT

V(I

V

= 2mA, I

-

0.10

V

OL

LOAD

= 0.8V

CT

High Level Output Voltage (V

)

I

= -10mA, V to V

DD

-

0.5

1.0

V

OH

OUT

OH

Low Level Output Voltage (V

Rise Time

)

= 10mA, VOL to GND

-

0.5

OL

OUT

C

= 220pF, V = 15V (Note 6)

-

110

200

150

1.25

3

ns

V

OUT

DD

Fall Time

= 220pF, V = 15V (Note 6)

-

90

DD

= 1mA (Note 8)

LOAD

UVLO Output Voltage Clamp

V

= 7V, I

-

DD

Output Delay/Advance Range

OUTLLN/OUTLRN relative to OUTLL/OUTLR

V

= 2.50V (Note 6)

< 2.425V

ns

V

ADJ

V

-40

40

2.575

0

-300

300

5.000

2.425

ADJ

V

> 2.575V

ADJ

Delay/Advance Control Voltage Range

OUTLLN/OUTLRN relative to OUTLL/OUTLR

OUTLxN Delayed

OUTLxN Advanced

V

FN9181 Rev 4.00

August 1, 2016

Page 7 of 18

ISL6752

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 3

and “typical application on Figure 2 on page 4 and Figure 3 on page 5. 9V < V < 20V, RTD = 10.0kΩ CT = 470pF, T = -40°C to +105°C, Typical values

DD

A

are at T = +25°C. (Continued)

A

MIN

MAX

PARAMETER

TEST CONDITIONS

= +25°C (OUTLx Delayed) (Note 9)

VADJ = 0

(Note 10)

TYP

(Note 10)

UNIT

VADJ Delay Time

T

A

280

92

61

300

105

70

320

118

80

ns

VADJ = 0.5V

VADJ = 1.0V

VADJ = 1.5V

48

41

55

65

VADJ = 2.0V

50

58

T

= +25°C (OUTLxN Delayed)

A

VADJ = V

280

86

59

47

300

100

68

320

114

77

ns

REF

- 0.5V

- 1.0V

- 1.5V

- 2.0V

55

62

41

48

55

THERMAL PROTECTION

Thermal Shutdown

(Note 6)

130

115

-

140

125

15

150

135

-

°C

Thermal Shutdown Clear

Hysteresis, Internal Protection

NOTES:

6. Limits established by characterization and are not production tested.

7. This is the maximum duty cycle achievable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may be obtained using

other values for these components. See Equations 1 through 3.

8. Adjust V below the UVLO stop threshold prior to setting at 7V.

DD

9. When OUTx is delayed relative to OUTLxN (VADJ < 2.425V), the delay duration as set by VADJ should not exceed 90% of the CT discharge time

(dead time) as determined by CT and RTD.

10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

FN9181 Rev 4.00

August 1, 2016

Page 8 of 18

ISL6752

Typical Performance Curves

25

24

23

22

21

20

19

18

1.02

1.01

1.00

0.99

0.98

-40 -25 -10

5

20

35

50 65

80 95 110

0

200

400

600

800

1000

TEMPERATURE (°C)

RTD CURRENT (µA)

FIGURE 4. REFERENCE VOLTAGE vs TEMPERATURE

FIGURE 5. CT DISCHARGE CURRENT GAIN vs RTD CURRENT

4

3

1-10

CT = 1000pF

CT = 680pF

3

1-10

RTD = 10kΩ

100

RTD = 50kΩ

CT = 220pF

CT = 100pF

CT = 330pF

100

10

CT = 470pF

RTD = 100kΩ

10

0.1

1

10

0

10 20 30 40 50 60 70 80 90 100

RTD (kΩ)

CT (nF)

FIGURE 6. DEAD TIME (DT) vs CAPACITANCE

FIGURE 7. CAPACITANCE vs FREQUENCY

determined by the timing capacitor discharge duration. The

voltage at RTD is nominally 2V.

Pin Descriptions

VDD - VDD is the power connection for the IC. To optimize noise

immunity, bypass VDD to GND with a ceramic capacitor as

close to the VDD and GND pins as possible.

CS - This is the input to the overcurrent comparator. The

overcurrent comparator threshold is set at 1V nominal. The CS

pin is shorted to GND at the termination of either PWM output.

VDD is monitored for supply voltage Undervoltage Lock-Out

(UVLO). The start and stop thresholds track each other

resulting in relatively constant hysteresis.

Depending on the current sensing source impedance, a series

input resistor may be required due to the delay between the

internal clock and the external power switch. This delay may

result in CS being discharged prior to the power switching

device being turned off.

GND - Signal and power ground connections for this device.

Due to high peak currents and high frequency operation, a low

impedance layout is necessary. Ground planes and short

traces are highly recommended.

OUTUL and OUTUR - These outputs control the upper bridge

FETs and operate at a fixed 50% duty cycle in alternate

sequence. OUTUL controls the upper left FET and OUTUR

controls the upper right FET. The left and right designation may

be switched as long as they are switched in conjunction with

the lower FET outputs, OUTLL and OUTLR.

VREF - The 5.0V reference voltage output having 3% tolerance

over line, load and operating temperature. Bypass to GND with

a 0.1µF to 2.2µF low ESR capacitor.

CT - The oscillator timing capacitor is connected between this

pin and GND. It is charged through an internal 200µA current

source and discharged with a user adjustable current source

controlled by RTD.

RESDEL - Sets the resonant delay period between the toggle of

the upper FETs and the turn on of either of the lower FETs. The

voltage applied to RESDEL determines when the upper FETs

switch relative to a lower FET turning on. Varying the control

voltage from 0V to 2V increases the resonant delay duration

from 0 to 100% of the dead time. The control voltage divided

by 2 represents the percent of the dead time equal to the

resonant delay. In practice the maximum resonant delay must

RTD - This is the oscillator timing capacitor discharge current

control pin. The current flowing in a resistor connected

between this pin and GND determines the magnitude of the

current that discharges CT. The CT discharge current is

nominally 20x the resistor current. The PWM dead time is

FN9181 Rev 4.00

August 1, 2016

Page 9 of 18

ISL6752

be set lower than 2V to ensure that the lower FETs, at

maximum duty cycle, are OFF prior to the switching of the

upper FETs.

Functional Description

Features

OUTLL and OUTLR - These outputs control the lower bridge FETs,

are pulse width modulated, and operate in alternate sequence.

OUTLL controls the lower left FET and OUTLR controls the lower

right FET. The left and right designation may be switched as long

as they are switched in conjunction with the upper FET outputs,

OUTUL and OUTUR.

The ISL6752 PWM is an excellent choice for low cost ZVS

full-bridge applications requiring adjustable synchronous

rectifier drive. With its many protection and control features, a

highly flexible design with minimal external components is

possible. Among its many features are a very accurate

overcurrent limit threshold, thermal protection, a buffered

sawtooth oscillator output suitable for slope compensation,

synchronous rectifier outputs with variable delay/advance

timing, and adjustable frequency.

OUTLLN and OUTLRN - These outputs are the complements of

the PWM (lower) bridge FETs. OUTLLN is the complement of

OUTLL and OUTLRN is the complement of OUTLR. These

outputs are suitable for control of synchronous rectifiers. The

phase relationship between each output and its complement

is controlled by the voltage applied to VADJ.

If synchronous rectification is not required, please consider the

ISL6753 controller.

Oscillator

VADJ - A 0V to 5.0V control voltage applied to this input sets

the relative delay or advance between OUTLL/OUTLR and

OUTLLN/OUTLRN. The phase relationship between

OUTUL/OUTUR and OUTLL/OUTLR is maintained regardless of

the phase adjustment between OUTLL/OUTLR and

OUTLLN/OUTLRN.

The ISL6752 has an oscillator with a programmable frequency

range to 2MHz, which can be programmed with a resistor and

capacitor.

The switching period is the sum of the timing capacitor charge

and discharge durations. The charge duration is determined by

CT and a fixed 200µA internal current source. The discharge

duration is determined by RTD and CT.

Voltages below 2.425V result in OUTLLN/OUTLRN being

advanced relative to OUTLL/OUTLR. Voltages above 2.575V

result in OUTLLN/OUTLRN being delayed relative to

OUTLL/OUTLR. A voltage of 2.50V ±75mV results in zero phase

difference. A weak internal 50% divider from VREF results in

no phase delay if this input is left floating.

3

t

 11.5  10  CT

S

(EQ. 1)

C

–9

(EQ. 2)

t

 0.06  RTD  CT + 50  10

S

D

The range of phase delay/advance is either zero or 40ns to

300ns with the phase differential increasing as the voltage

deviation from 2.5V increases. The relationship between the

control voltage and phase differential is non-linear. The gain

(t/V) is low for control voltages near 2.5V and rapidly

increases as the voltage approaches the extremes of the

control range. This behavior provides the user increased

accuracy when selecting a shorter delay/advance duration.

1

----------

t

= t + t =

D

S

(EQ. 3)

SW

C

f

SW

Where t and t are the charge and discharge times,

respectively, CT is the timing capacitor in Farads, RTD is the

discharge programming resistance in ohms, t is the

C

D

SW

is the oscillator frequency. One

oscillator period, and f

SW

output switching cycle requires two oscillator cycles. The

actual times will be slightly longer than calculated due to

internal propagation delays of approximately 10ns/transition.

This delay adds directly to the switching duration, but also

causes overshoot of the timing capacitor peak and valley

voltage thresholds, effectively increasing the peak-to-peak

voltage on the timing capacitor. Additionally, if very small

discharge currents are used, there will be increased error due

to the input impedance at the CT pin. The maximum

recommended current through RTD is 1mA, which produces a

CT discharge current of 20mA.

When the PWM outputs are delayed relative to the SR outputs

(VADJ < 2.425V), the delay time should not exceed 90% of the

dead time as determined by RTD and CT.

VERR - The control voltage input to the inverting input of the

PWM comparator. The output of an external Error Amplifier

(EA) is applied to this input, either directly or through an

opto-coupler, for closed loop regulation. VERR has a nominal

1mA pull-up current source.

CTBUF - CTBUF is the buffered output of the sawtooth oscillator

waveform present on CT and is capable of sourcing 2mA. It is

offset from ground by 0.40V and has a nominal valley-to-peak

gain of 2. It may be used for slope compensation.

The maximum duty cycle, D, and percent dead time, DT, can be

calculated from Equations 4 and 5:

t

C

(EQ. 4)

----------

D =

t

SW

DT = 1 – D

(EQ. 5)

FN9181 Rev 4.00

August 1, 2016

Page 10 of 18

ISL6752

Implementing Soft-Start

Slope Compensation

The ISL6752 does not have a soft-start feature. Soft-start can

be implemented externally using the components shown in

Figure 5. The RC network governs the rate of rise of the

transistor’s base, which clamps the voltage at VERR.

Peak current-mode control requires slope compensation to

improve noise immunity, particularly at lighter loads, and to

prevent current loop instability, particularly for duty cycles

greater than 50%. Slope compensation may be accomplished

by summing an external ramp with the current feedback signal

or by subtracting the external ramp from the voltage feedback

error signal. Adding the external ramp to the current feedback

signal is the more popular method.

1

2

3

4

5

6

7

8

1

6

VREF

VERR

1

5

1

4

1

3

1

2

1

0

9

From the small signal current-mode model [1] it can be shown

that the naturally-sampled modulator gain, Fm, without slope

compensation, is expressed in Equation 7:

R

ISL6752

1

-----------------

Fm =

(EQ. 7)

S t

n SW

C

Where S is the slope of the sawtooth signal and t

SW

is the

n

duration of the half-cycle. When an external ramp is added, the

modulator gain becomes Equation 8:

1

FIGURE 8. IMPLEMENTING SOFT-START

(EQ. 8)

------------------------------------

--------------------------

Fm =

=

S + S t

m S t

c n SW

n

e

SW

The values of R and C should be selected to control the rate of

rise of VERR to the desired soft-start duration. The soft-start

duration may be calculated from Equation 6.

Where S is slope of the external ramp and:

e

S

e

S

n

------

m

= 1 +

(EQ. 9)

c









V

– V

be

SS



-------------------------------------------

(EQ. 6)

t = –RC  ln 1 –

S





The criteria for determining the correct amount of external

ramp can be determined by appropriately setting the damping

factor of the double-pole located at half the oscillator

frequency. The double-pole will be critically damped if the

Q-factor is set to 1, and over-damped for Q > 1, and

under-damped for Q < 1. An under-damped condition can

result in current loop instability.

0.001R

-------------------

VREF +



Where V is the soft-start clamp voltage, V is the base

SS be

emitter voltage drop of the transistor, and  is the DC gain of

the transistor. If  is sufficiently large, that term may be

ignored. The Schottky diode discharges the soft-start capacitor

so that the circuit may be reset quickly.

1

(EQ. 10)

-------------------------------------------------

Q =

m 1 – D – 0.5

c

Gate Drive

The ISL6752 outputs are capable of sourcing and sinking

Where D is the percent of on-time during a half cycle. Setting

Q = 1 and solving for S yields in Equation 11:

10mA (at rated V , V ) and are intended to be used in

OH OL

e

conjunction with integrated FET drivers or discrete bipolar

totem pole drivers. The typical ON-resistance of the outputs is

50Ω.

1







– 1

(EQ. 11)

--

-------------

S

= S

+ 0.5

e

n





1 – D

Overcurrent Operation

Since S and S are the on-time slopes of the current ramp

and the external ramp, respectively, they can be multiplied by

n

e

The cycle-by-cycle peak current control results in

pulse-by-pulse duty cycle reduction when the current feedback

signal exceeds 1.0V. When the peak current exceeds the

threshold, the active output pulse is immediately terminated.

This results in a well controlled decrease in output voltage as

the load current increases beyond the current limit threshold.

The ISL6752 will operate continuously in an overcurrent

condition.

t

to obtain the voltage change that occurs during t

.

ON

1



1







– 1

--

-------------

V

= V

+ 0.5

(EQ. 12)

e

n



1 – D

Where V is the change in the current feedback signal during

n

the on-time and V is the voltage that must be added by the

e

external ramp.

V can be solved for in terms of input voltage, current

n

transducer components, and output inductance yielding in

Equation 13:

The propagation delay from CS exceeding the current limit

threshold to the termination of the output pulse is increased by

the Leading Edge Blanking (LEB) interval. The effective delay is

the sum of the two delays and is nominally 105ns.

t

 V  R

CS

O

N

SW

1

S





P





--------------------------------------- ------- --

V

=



+ D – 0.5

V

(EQ. 13)

e



N

 L

N

CT

O

FN9181 Rev 4.00

August 1, 2016

Page 11 of 18

ISL6752

Where R is the current sense burden resistor, N is the

CS CT

representation of the sawtooth signal that appears on the CT

pin. It is offset from ground by 0.4V and is 2x the peak-to-peak

amplitude of CT (0.4V to 4.4V). A typical application sums this

signal with the current sense feedback and applies the result to

the CS pin, as shown in Figure 9.

current transformer turns ratio, L is the output inductance, V

O

is the output voltage, and N and N are the secondary and

S

P

primary turns, respectively.

The inductor current, when reflected through the isolation

transformer and the current sense transformer to obtain the

current feedback signal at the sense resistor yields in

Equation 14:

1

2

3

4

5

6

7

8

ISL6752

N

 R

D  t

N

S

N

P



















S

CS

SW

------------------------

-------------------

-------

(EQ. 14)

V

=

I

+

V



– V

O

V

CS

O

IN

N

 N

2L

O

CTBUF

P

CT

R

Where V is the voltage across the current sense resistor and

CS

9

I

is the output current at current limit.

O

CS

Since the peak current limit threshold is 1.0V, the total current

feedback signal plus the external ramp voltage must sum to

this value.

R

6

C

4

R

CS

V

+ V

= 1

CS

(EQ. 15)

e

Substituting Equations 13 and 14 into Equation 15 and solving

for R yields in Equation 16:

CS

N

 N

FIGURE 9. ADDING SLOPE COMPENSATION

1

P

CT

----------------------- ----------------------------------------------------

R

=





(EQ. 16)

CS

N

V

O

1

D





S





-------

-- ---

+

I

+

t

O

SW

L



2

O

Assuming the designer has selected values for the RC filter

placed on the CS pin, the value of R required to add the

9

appropriate external ramp can be found by superposition.

For simplicity, idealized components have been used for this

discussion, but the effect of magnetizing inductance must be

considered when determining the amount of external ramp to

add. Magnetizing inductance provides a degree of slope

compensation to the current feedback signal and reduces the

amount of external ramp required. The magnetizing

DV

– 0.4 + 0.4  R

6

CTBUF

------------------------------------------------------------------------------

(EQ. 20)

V

– V

=

CS

V

e

R

+ R

9

6

Rearranging to solve for R yields Equation 21:

9

DV

– 0.4 – V + V

+ 0.4  R

CS 6

CTBUF

e

inductance adds primary current in excess of what is reflected

from the inductor current in the secondary.

-----------------------------------------------------------------------------------------------------------------

R

=



9

V

– V

CS

e

(EQ. 21)

V

 Dt

SW

IN

(EQ. 17)

-----------------------------

I

=

A

P

L

The value of R determined in Equations 16 must be rescaled

CS

m

so, that the current sense signal presented at the CS pin is that

predicted by Equation 14. The divider created by R and R

makes this necessary.

6

9

Where V is the input voltage that corresponds to the duty

IN

cycle D and L is the primary magnetizing inductance. The

m

R

+ R

9

R

9

effect of the magnetizing current at the current sense resistor,

6

--------------------

(EQ. 22)

R

=

 R

CS

R

, is expressed in Equation 18:

CS

I  R

P

CS

(EQ. 18)

-------------------------

V

=

V

Example:

CS

N

CT

V

= 280V

= 12V

IN

If V is greater than or equal to V , then no additional slope

CS

e

O

compensation is needed and R becomes Equation 19:

CS

L

= 2.0µH

O

N

CT

---------------------------------------------------------------------------------------------------------------------------------

R

=

CS

Np/Ns = 20

Lm = 2mH

N

Dt

N

V

 Dt









S

SW

S

IN SW

-------

--------------

-------

-----------------------------

 I

+

 V



– V

O

+



O

IN

N

P

2L

O

N

P

L



m

(EQ. 19)

I

= 55A

O

If V is less than V , then Equation 16 is still valid for the

CS

Oscillator Frequency, f

Duty Cycle, D = 85.7%

= 400kHz

e

SW

value of R , but the amount of slope compensation added by

CS

the external ramp must be reduced by V

.

CS

N

= 50

CT

Adding slope compensation may be accomplished in the

ISL6752 using the CTBUF signal. The CTBUF is an amplified

R = 499Ω

6

FN9181 Rev 4.00

August 1, 2016

Page 12 of 18

ISL6752

Solve for the current sense resistor, R , using Equation 16.

CS

and Equation 21 becomes:

2D – V + V   R

6

R

= 15.1Ω.

CS

e

CS

-----------------------------------------------------------

(EQ. 24)

R

=



9

V

– V

CS

e

Determine the amount of voltage, V , that must be added to the

e

current feedback signal using Equation 13.

The buffer transistor used to create the external ramp from CT

should have a sufficiently high gain (>200) so as to minimize the

required base current. Whatever base current is required reduces

the charging current into CT and will reduce the oscillator

frequency.

V = 153mV

e

Next, determine the effect of the magnetizing current from

Equation 18.

V = 91mV

CS

ZVS Full-Bridge Operation

Using Equation 21, solve for the summing resistor, R , from

9

The ISL6752 is a full-bridge zero-voltage switching (ZVS) PWM

controller that behaves much like a traditional hard switched

topology controller. Rather than drive the diagonal bridge

switches simultaneously, the upper switches (OUTUL, OUTUR) are

driven at a fixed 50% duty cycle and the lower switches (OUTLL,

OUTLR) are pulse width modulated on the trailing edge.

CTBUF to CS.

R = 30.1kΩ

9

Determine the new value of R , R’ , using Equation 22.

CS CS

R’ = 15.4Ω

CS

This discussion determines the minimum external ramp that is

required. Additional slope compensation may be considered for

design margin.

CT

If the application requires dead time of less than about 500ns,

the CTBUF signal may not perform adequately for slope

compensation. CTBUF lags the CT sawtooth waveform by 300ns

to 400ns. This behavior results in a non-zero value of CTBUF

when the next half-cycle begins when the dead time is short.

DEAD TIME

PWM

OUTLL

OUTLR

OUTUR

PWM

Under these situations, slope compensation may be added by

externally buffering the CT signal as shown in Figure 10.

RESONANT

DELAY

1

OUTUL

RESDEL

WINDOW

2

3

4

5

6

7

8

VREF

ISL6752

FIGURE 11. BRIDGE DRIVE SIGNAL TIMING

To understand how the ZVS method operates, one must include

the parasitic elements of the circuit and examine a full switching

cycle.

R

9

CT

CS

VIN+

UL

UR

D1

R

6

VOUT+

RTN

L_L

C

CT

4

R_CS

LL

LR

D2

VIN-

FIGURE 12. IDEALIZED FULL-BRIDGE

FIGURE 10. ADDING SLOPE COMPENSATION USING CT

Figure 12, the power semiconductor switches have been

replaced by ideal switch elements with parallel diodes and

capacitance, the output rectifiers are ideal, and the transformer

leakage inductance has been included as a discrete element.

The parasitic capacitance has been lumped together as switch

capacitance, but represents all parasitic capacitance in the

circuit including winding capacitance. Each switch is designated

by its position; Upper Left (UL), Upper Right (UR), Lower Left (LL),

and Lower Right (LR). The beginning of the cycle, shown in

Using CT to provide slope compensation instead of CTBUF

requires the same calculations, except that Equations 20 and 21

require modification. Equation 20 becomes:

2D  R

6

--------------------

V

– V

=

CS

V

(EQ. 23)

e

R

+ R

9

6

FN9181 Rev 4.00

August 1, 2016

Page 13 of 18

ISL6752

Figure 13, is arbitrarily set as having switches UL and LR on and

UR and LL off. The direction of the primary and secondary

formed by the leakage inductance and the parasitic capacitance.

The resonant transition may be estimated from Equation 25.

currents are indicated by I and I , respectively.

P

S



2

1

-------------------------------------

 =

(EQ. 25)

VIN+

2

UL

UR

1

R

I_S

-------------- ---------

–

D1

2

L

L C

L

P

4L

VOUT+

RTN

L_L

I_P

Where  is the resonant transition time, L is the leakage

inductance, C is the parasitic capacitance, and R is the

equivalent resistance in series with L and C .

L

P

LL

LR

L

P

D2

The resonant delay is always less than or equal to the dead time

and may be calculated using Equation 26.

VIN-

V

resdel

2

-------------------



=

 DT

S

(EQ. 26)

FIGURE 13. UL TO LR POWER TRANSFER CYCLE

resdel

The UL to LR power transfer period terminates when switch LR

turns off as determined by the PWM. The current flowing in the

primary cannot be interrupted instantaneously, so it must find an

alternate path. The current flows into the parasitic switch

capacitance of LR and UR, which charges the node to VIN and

then forward biases the body diode of upper switch UR.

Where 

resdel

is the desired resonant delay, V

resdel

is a voltage

between 0V and 2V applied to the RESDEL pin, and DT is the

dead time (see Equations 1 through 5).

When the upper switches toggle, the primary current that was

flowing through UL must find an alternate path. It

charges/discharges the parasitic capacitance of switches UL and

LL until the body diode of LL is forward-biased. If RESDEL is set

properly, switch LL will be turned on at this time. The output

inductor does not assist this transition. It is purely a resonant

transition driven by the leakage inductance.

VIN+

UL

UR

I_S

D1

L_L

VOUT+

RTN

I_P

LL

LR

VIN+

D2

UL

UR

I_S

D1

VIN-

VOUT+

RTN

L_L

FIGURE 14. UL TO UR FREE-WHEELING PERIOD

I_P

The primary leakage inductance, L , maintains the current,

L

LL

LR

which now circulates around the path of switch UL, the

transformer primary, and switch UR. When switch LR opens, the

output inductor current free-wheels through both output diodes,

D1 and D2. During the switch transition, the output inductor

current assists the leakage inductance in charging the upper and

lower bridge FET capacitance.

D2

VIN-

FIGURE 15. UPPER SWITCH TOGGLE AND RESONANT TRANSITION

The second power transfer period commences when switch LL

closes. With switches UR and LL on, the primary and secondary

currents flow, as indicated in Figure 16.

The current flow from the previous power transfer cycle tends to

be maintained during the free-wheeling period because the

transformer primary winding is essentially shorted. Diode D1

may conduct very little or none of the free-wheeling current,

depending on circuit parasitics. This behavior is quite different

than occurs in a conventional hard-switched full-bridge topology

where the free-wheeling current splits nearly evenly between the

output diodes, and flows not at all in the primary.

VIN+

UL

UR

D1

VOUT+

RTN

L_L

This condition persists through the remainder of the half cycle.

LL

LR

During the period when CT discharges (also referred to as the

dead time), the upper switches toggle. Switch UL turns off and

switch UR turns on. The actual timing of the upper switch toggle

is dependent on RESDEL, which sets the resonant delay. The

voltage applied to RESDEL determines how far in advance the

toggle occurs prior to a lower switch turning on. The ZVS

transition occurs after the upper switches toggle and before the

diagonal lower switch turns on. The required resonant delay is

1/4 of the period of the LC resonant frequency of the circuit

D2

VIN-

FIGURE 16. UR TO LL POWER TRANSFER CYCLE

The UR to LL power transfer period terminates when switch LL

turns off, as determined by the PWM. The current flowing in the

primary must find an alternate path. The current flows into the

parasitic switch capacitance, which charges the node to VIN and

FN9181 Rev 4.00

August 1, 2016

Page 14 of 18

ISL6752

then forward biases the body diode of upper switch UL. As before,

the output inductor current assists in this transition. The primary

leakage inductance, L , maintains the current, which now

CT

L

circulates around the path of switch UR, the transformer primary,

and switch UL. When switch L opens, the output inductor current

L

OUTLL

free wheels predominantly through diode D1. Diode D2 may

actually conduct very little or none of the free-wheeling current,

depending on circuit parasitics. This condition persists through

the remainder of the half-cycle.

OUTLR

VIN+

UL

UR

I_S

OUTLLN

(SR1)

D1

L_L

VOUT+

RTN

I_P

OUTLRN

(SR2)

LL

LR

D2

FIGURE 19. BASIC WAVEFORM TIMING

VIN-

Referring to Figure 19, the SRs alternate between being both on

during the free-wheeling portion of the cycle (OUTLL/LR off) and

one or the other being off when OUTLL or OUTLR is on. If OUTLL is

on, its corresponding SR must also be on, indicating that OUTLRN

is the correct SR control signal. Likewise, if OUTLR is on, its

corresponding SR must also be on, indicating that OUTLLN is the

correct SR control signal.

FIGURE 17. UR - UL FREE-WHEELING PERIOD

When the upper switches toggle, the primary current that was

flowing through UR must find an alternate path. It

charges/discharges the parasitic capacitance of switches UR and

LR until the body diode of LR is forward-biased. If RESDEL is set

properly, switch LR will be turned on at this time.

A useful feature of the ISL6752 is the ability to vary the phase

relationship between the PWM outputs (OUTLL, OUT LR) and their

complements (OUTLLN, OUTLRN) by ±300ns. This feature allows

the designer to compensate for differences in the propagation

times between the PWM FETs and the SR FETs. A voltage applied

to VADJ controls the phase relationship.

VIN+

UL

LL

UR

LR

I_S

D1

D2

VOUT+

RTN

L_L

I_P

CT

VIN-

FIGURE 18. UPPER SWITCH TOGGLE AND RESONANT TRANSITION

OUTLL

The first power transfer period commences when switch LR

closes and the cycle repeats. The ZVS transition requires that the

leakage inductance has sufficient energy stored to fully charge

OUTLR

the parasitic capacitances. Since the energy stored is

proportional to the square of the current (1/2 L I ), the ZVS

L P

OUTLLN

(SR1)

2

resonant transition is load dependent. If the leakage inductance

is not able to store sufficient energy for ZVS, a discrete inductor

may be added in series with the transformer primary.

OUTLRN

(SR2)

Synchronous Rectifier Outputs and Control

FIGURE 20. WAVEFORM TIMING WITH PWM OUTPUTS DELAYED, 0V

< VADJ < 2.425V

The ISL6752 provides double-ended PWM outputs, OUTLL and

OUTLR, and Synchronous Rectifier (SR) outputs, OUTLLN and

OUTLRN. The SR outputs are the complements of the PWM

outputs. It should be noted that the complemented outputs are

used in conjunction with the opposite PWM output, i.e., OUTLL

and OUTLRN are paired together and OUTLR and OUTLLN are

paired together.

FN9181 Rev 4.00

August 1, 2016

Page 15 of 18

ISL6752

+VDD

CT

ISL6752

VADJ

VDD

OUTLL

VREF

OUTLL

VERR

CTBUF

RTD

OUTLR

OUTUL

OUTUR

OUTLR

ON/OFF

OUTLLN

(SR1)

RESDEL OUTLLN

(OPEN = OFF

GND = ON)

CT

CS

OUTLRN

GND

OUTLRN

(SR2)

FIGURE 21. WAVEFORM TIMING WITH SR OUTPUTS DELAYED,

FIGURE 22. ON/OFF CONTROL USING VDD

2.575V < VADJ < 5.0V

Fault Conditions

Setting VADJ to VREF/2 results in no delay on any output. The no

delay voltage has a ±75mV tolerance window. Control voltages

below the VREF/2 zero delay threshold cause the PWM outputs,

OUTLL/LR, to be delayed. Control voltages greater than the

VREF/2 zero delay threshold cause the SR outputs, OUTLLN/LRN,

to be delayed. It should be noted that when the PWM outputs,

OUTLL/LR, are delayed, the CS to output propagation delay is

increased by the amount of the added delay.

A fault condition occurs if VREF or VDD fall below their

undervoltage lockout (UVLO) thresholds or if the thermal

protection is triggered. When a fault is detected the outputs are

disabled low. When the fault condition clears the outputs are

re-enabled.

An overcurrent condition is not considered a fault and does not

result in a shutdown.

The delay feature is provided to compensate for mismatched

propagation delays between the PWM and SR outputs as may be

experienced when one set of signals crosses the

primary-secondary isolation boundary. If required, individual

output pulses may be stretched or compressed as required using

external resistors, capacitors and diodes.

Thermal Protection

Internal die over-temperature protection is provided. An

integrated temperature sensor protects the device should the

junction temperature exceed +140°C. There is approximately

+15°C of hysteresis.

When the PWM outputs are delayed, the 50% upper outputs are

equally delayed, thus the resonant delay setting is unaffected.

Ground Plane Requirements

Careful layout is essential for satisfactory operation of the device.

A good ground plane must be employed. VDD and VREF should

be bypassed directly to GND with good high frequency

capacitance.

On/Off Control

The ISL6753 does not have a separate enable/disable control

pin. The PWM outputs, OUTLL/OUTLR, may be disabled by pulling

VERR to ground. Doing so reduces the duty cycle to zero, but the

upper 50% duty cycle outputs, OUTUL/OUTUR, will continue

operation. Likewise, the SR outputs OUTLLN/OUTLRN will be

active high.

References

[1] Ridley, R., “A New Continuous-Time Model for Current Mode

Control”, IEEE Transactions on Power Electronics, Vol. 6, No.

2, April 1991.

If the application requires that all outputs be off, then the supply

voltage, VDD, must be removed from the IC. This may be

accomplished as shown in Figure 19.

FN9181 Rev 4.00

August 1, 2016

Page 16 of 18

ISL6752

Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.

Please go to the web to make sure that you have the latest revision.

DATE

REVISION

FN9181.4

CHANGE

August 1, 2016

- Updated to new template.

- On page 1: Added “Related Literature”.

- Ordering information table on page 2: Added “ISL6752/54EVAL1Z” and “ISL6752DBEVAL1Z”. Updated

Note 1 in the ordering information table to include tape and reel options.

- Added Table 1 on page 2.

- Electrical Specifications table on page 6: Updated “REFERENCE VOLTAGE” section, from “IVREF = 0mA

to 10mA” to “0mA” to “-10mA”.

- Updated POD M16.15A to most recent revision with change as follows:

Convert to new POD format. Added land pattern.

- Added revision history and about Intersil verbiage.

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products

address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product

information page found at www.intersil.com.

You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.

Reliability reports are also available from our website at www.intersil.com/support.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9181 Rev 4.00

August 1, 2016

Page 17 of 18

ISL6752

Package Outline Drawing

M16.15A

16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (QSOP/SSOP)

0.150” WIDE BODY

Rev 3, 8/12

16

INDEX

6.20

5.84

AREA

3.99

4

M

B

0.25(0.010)

3.81

-B-

1

TOP VIEW

DETAIL “X”

SEATING PLANE

GAUGE

PLANE

3

1.73

1.55

-A-

4.98

4.80

-C-

0.89

0.41

0.25

0.010

0.249

0.102

0.635 BSC

0.41

0.25

0.31

0.20

x 45°

5

0.10(0.004)

7

0.17(0.007)

M

C A M B S

SIDE VIEW 1

8°

0°

1.55

1.40

0.249

0.191

7.11

5.59

SIDE VIEW 2

4.06

0.38

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number

95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Package length does not include mold flash, protrusions or gate burrs. Mold flash,

protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Package width does not include interlead flash or protrusions. Interlead flash and

protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be

located within the crosshatched area.

0.635

6. Terminal numbers are shown for reference only.

7. Lead width does not include dambar protrusion. Allowable dambar protrusion shall be

0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition.

8. Controllingdimension: MILLIMETER.

TYPICAL RECOMMENDED LAND PATTERN

FN9181 Rev 4.00

August 1, 2016

Page 18 of 18


型号：	ISL6752AAZA
厂家：	RENESAS TECHNOLOGY CORP
描述：	ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control 信息通信管理开关光电二极管
文件：	总18页 (文件大小：964K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6752AAZA [RENESAS]

相关型号：

ISL6752AAZA-T

ISL6752DBEVAL1Z

ISL6752_06

ISL6753

ISL6753AAZA

ISL6753AAZA-T

ISL6753_06

ISL6754

ISL6754AAZA

ISL6755

ISL6755AAZA

ISL6801