ISL70003SEHX_技术文档

DATASHEET

Radiation Hardened and SEE Hardened 3V to 13.2V, 6A

Buck Regulator

ISL70003SEH

Features

The ISL70003SEH is a radiation and SEE hardened

synchronous buck regulator capable of operating over an

input voltage range of 3.0V to 13.2V. With integrated

MOSFETs, this highly efficient single chip power solution

provides a tightly regulated output voltage that is externally

adjustable from 0.6V to ~90% of the input voltage.

Continuous output load current capability is 6A for

T ≤+125°C and 3A for T ≤ +150°C.

• Acceptance tested to 50krad(Si) (LDR) wafer-by-wafer

• ±1% reference voltage over line, temperature and radiation

• Integrated MOSFETs 31mΩPFET/21mΩ NFET

- 95% peak efficiency

• Externally adjustable loop compensation

• Supports DDR applications (V tracks V

/2)

voltage

TT DDQ

J

- Buffer amplifier for generating V

- 3A current sinking capability

REF

The ISL70003SEH uses voltage mode control architecture

with feed-forward and switches at a selectable frequency of

500kHz or 300kHz. Loop compensation is externally

adjustable to allow for an optimum balance between stability

and output dynamic performance. The internal synchronous

power switches are optimized for high efficiency and

excellent thermal performance.

• Grounded lid eliminates charge build up

• IMON pin for output current monitoring

• Adjustable analog soft-start

• Diode emulation for increased efficiency at light loads

• 500kHz or 300kHz operating frequency synch wording

• Monotonic start-up into prebiased load

• Full military temperature range operation

The chip features two logic-level disable inputs that can be

used to inhibit pulses on the phase (LXx) pins in order to

maximize efficiency based on the load current. The

ISL70003SEH also supports DDR applications and contains a

buffer amplifier for generating the V

voltage.

REF

- T = -55°C to +125°C

A

High integration, best in class radiation performance and a

feature filled design make the ISL70003SEH an ideal choice

to power many of todays small form factor applications.

- T = -55°C to +150°C

J

• Radiation tolerance

- High dose rate (50-300rad(Si)/s). . . . . . . . . . . 100krad(Si)

Applications

• FPGA, CPLD, DSP, CPU core and I/O supply voltages

- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . 100krad(Si)*

* Limit established by characterization.

• DDR memory supply voltages

• SEE hardness

2

- SEB and SEL LET . . . . . . . . . . . . . . . . 86.4MeV•cm /mg

TH

- SET at LET 86.4MeV•cm /mg . . . . . . . . . . . < ±3% ΔV

• Low-voltage, high-density distributed power systems

2

OUT

Related Literature

• AN1897, ISL70003SEHEV1Z Evaluation Board

2

- SEFI LET . . . . . . . . . . . . . . . . . . . . . . . . . 60MeV•cm /mg

TH

• Electrically screened to DLA SMD 5962-14203

• AN1915, ISL70003SEH iSim:PE Model

• AN1913, Single Event Effects Testing of the ISL70003SEH,

3V to 13.2V, 6A Synchronous Buck Regulator

• AN1924, Total Dose Testing of the ISL70003SEH Radiation

Hardened Point Of Load Regulator

100

95

90

85

9V

80

75

70

5V

2.5V

65

3.3V

60

55

50

0

1

2

3

4

5

6

LOAD CURRENT (A)

FIGURE 1. POWER DISTRIBUTION SOLUTION FOR RAD HARD LOW

POWER FPGA’s

FIGURE 2. EFFICIENCY vs LOAD, V = 12V, f

IN

= 300kHz

SW

ALL OUTPUTS ACTIVE

May 12, 2016

FN8604.5

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

ISL70003SEH

Table of Contents

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Typical Application Schematics. . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . 9

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . .12

DDR Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Derating Current Capability . . . . . . . . . . . . . . . . . . . . . . . . . 23

General Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Output Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Feedback Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Modulator Break Frequency Equations . . . . . . . . . . . . . . . . . 25

Compensation Break Frequency Equations . . . . . . . . . . . . . 25

PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

PCB Plane Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

PCB Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . 26

LX Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Thermal Management for Ceramic Package . . . . . . . . . . . . 26

Lead Strain Relief . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Heatsink Mounting Guidelines . . . . . . . . . . . . . . . . . . . . . . . . 26

Heatsink Electrical Potential. . . . . . . . . . . . . . . . . . . . . . . . . . 26

Heatsink Mounting Materials . . . . . . . . . . . . . . . . . . . . . . . . . 26

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Power Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Soft -Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Weight of Packaged Device . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Lid Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Fault Monitoring and Protection . . . . . . . . . . . . . . . . . . . . . .18

Die Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Undervoltage and Overvoltage Monitor. . . . . . . . . . . . . . . . . . 18

Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Die Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Interface Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Layout Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Step and Repeat. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Voltage Feed-forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Switching Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . 20

Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Setting the Overcurrent Protection Level . . . . . . . . . . . . . . . . 20

Disabling the Power Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

IMON Current Sense Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Diode Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DDR Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

About Intersil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

R64.A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

R64.C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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ISL70003SEH

Functional Block Diagram

AVDD

DVDD

POR and ON/OFF

CONTROL

LINEAR

REGULATORs

POR_VIN

RT/CT

SEL1

SEL2

RAMP

IMON

CURRENT

SENSE

PVINx

SOFT

START

SS_CAP

PWM

CONTROL

LOGIC

NI

GATE

DRIVE

LXx

EA

COMP

FB

VERR

VOUT

MONITOR

SGND

PGOOD

REF

PGNDx

PWM

REFERENCE

0.6V

OCSETA

OCSETB

OVERCURRENT

ADJUST

BUFIN-

BUFIN+

DDR VREF

BUFFER AMP

DGND

AGND

PGNDx

BUF

BUFOUT

SYNC

FSEL

DE

FIGURE 3. FUNCTIONAL BLOCK DIAGRAM

Ordering Information

ORDERING SMD

NUMBER (Note 1)

PART NUMBER

(Note 2)

TEMPERATURE

RANGE (°C)

PACKAGE

(RoHS Compliant)

PACKAGE

DRAWING

5962R1420301VXC

ISL70003SEHVF

ISL70003SEHVFE

-55 to +125

64 Ld CQFP

R64.A

5962R1420301VYC

64 Ld CQFP with Heatsink

R64.C

5962R1420301V9A

ISL70003SEHVX

Die

N/A

ISL70003SEHF/PROTO

ISL70003SEHFE/PROTO

ISL70003SEHX/SAMPLE

ISL70003SEHEV1Z

64 Ld CQFP

R64.A

R64.C

64 Ld CQFP with Heatsink

Die

N/A

Evaluation Board

NOTES:

1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be

used when ordering.

2. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both

SnPb and Pb-free soldering operations.

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ISL70003SEH

Pin Configuration

ISL70003SEH

(64 LD CQFP)

TOP VIEW

BOTTOM SIDE DETAIL

FOR PIN 1 LOCATION

53 52 51 50 49

64 63 62 61 60 59 58 57 56 55 54

1

2

3

4

5

6

7

8

9

LX3

NI

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1 (NI)

PGND3

PGND4

LX4

FB

VERR

POR_VIN

VREFA

AVDD

PVIN4

(Note 3)

PVIN5

LX5

AGND

DGND

PGND5

PGND6

LX6

VREF_OUTS

DVDD

10

11

12

13

14

15

16

VREFD

ENABLE

RT/CT

PVIN6

PVIN7

LX7

FSEL

PGND7

PGND8

LX8

HEATSINK OUTLINE *

SYNC

SS_CAP

28 29 30 31 32

17 18 19 20 21 22 23 24 25 26 27

* Indicates heatsink package R64.C

NOTE:

3. The ESD triangular mark is indicative of pin #1 location. It is part of the device marking and is

placed on the lid in the quadrant where pin #1 is located.

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ISL70003SEH

Pin Descriptions

PIN NUMBER

PIN NAME ESD CIRCUIT

DESCRIPTION

1

NI

1

This pin is the non-inverting input to the internal error amplifier. Connect this pin to the REF pin for

typical applications or the BUFOUT pin for DDR memory power applications.

2

FB

1

This pin is the inverting input to the internal error amplifier. An external type III compensation network

should be connected between this pin and the VERR pin. The connection between the FB resistor divider

and the output inductor should be a Kelvin connection to optimize performance.

3

4

VERR

1

This pin is the output of the internal error amplifier. An external compensation network should be

connected between this pin and the FB pin.

POR_VIN

This pin is the power-on reset input to the IC. This is a comparator-type input with a rising threshold of

0.6V and programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND

with a 10nF ceramic capacitor to mitigate SEE.

5

VREFA

3

This pin is the output of the internal linear regulator and the bias supply input to the internal analog

control circuitry. Locally filter this pin to AGND using a 0.47µF ceramic capacitor as close as possible to

the IC.

6

7

AVDD

AGND

5

1, 3

2, 4

4

This pin provides the supply for internal linear regulator of the ISL70003SEH. The supply to AVDD

should be locally bypassed using a ceramic capacitor. Tie AVDD to the PVINx pins.

This pin is the analog ground associated with the internal analog control circuitry. Connect this pin

directly to the PCB ground plane.

8

DGND

This pin is the ground associated with the internal digital control circuitry. Connect this pin directly to

the PCB ground plane.

9

VREF_OUTS

DVDD

This pin is the output of the internal linear regulator and the supply input to the internal reference

circuit. Locally filter this pin to AGND using a 0.47µF ceramic capacitor as close as possible to the IC.

10

11

6

This pin provides the supply for the internal linear regulator of the ISL70003SEH. The supply to DVDD

should be locally bypassed using a ceramic capacitor. Tie DVDD to the PVINx pin.

VREFD

4

This pin is the output of the internal linear regulator and the bias supply input to the internal digital

control circuitry. Locally filter this pin to DGND using a 0.47µF ceramic capacitor as close as possible

to the IC.

12

13

14

15

16

ENABLE

RT/CT

FSEL

6

2

This pin is a logic-level enable input. Pulling this pin low powers down the chip by placing it into a very

low power sleep mode.

A resistor to VIN and a capacitor to GND provide feed-forward to keep a constant modulator gain of 4.8

as VIN varies.

This pin is the oscillator frequency select input. Tie this pin to 5V to select a 300kHz nominal oscillator

frequency. Tie this pin to the PCB ground plane to select a 500kHz nominal oscillator frequency.

SYNC

This pin is the frequency synchronization input to the IC. This pin should be tied to GND to free-run from

the internal oscillator or connected to an external clock for external frequency synchronization.

SS_CAP

This pin is the soft-start input. Connect a ceramic capacitor from this pin to the PCB ground plane to set

the soft-start output ramp time in accordance with Equation 1:

t

= C

 V  I

REF SS

(EQ. 1)

SS

where:

t

C

= soft-start output ramp time

= soft-start capacitance

SS

V

= reference voltage (0.6V typical)

REF

I

= soft-start charging current (23µA typical)

SS

Soft-start time is adjustable from approximately 2ms to 200ms. The range of the soft-start capacitor

should be 82nF to 8.2µF, inclusive.

17, 18, 19, 20, 21

22

GND

2

6

Connect this pin to the PCB ground plane.

PGOOD

This pin is the power-good output. This pin is an open-drain logic output that is pulled to DGND when

the output voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage

from 0V to 13.2V, independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is

recommended. Bypass this pin to the PCB ground plane with a 10nF ceramic capacitor to mitigate SEE.

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ISL70003SEH

Pin Descriptions(Continued)

PIN NUMBER

PIN NAME ESD CIRCUIT

DESCRIPTION

23, 28, 32, 37,

38, 43, 44, 49,

53, 58

PVINx

7

These pins are the power supply inputs to the corresponding internal power blocks. These pins must be

connected to a common power supply rail, which should fall in the range of 3V to 13.2V. Bypass these

pins directly to PGNDx with ceramic capacitors located as close as possible to the IC. When sinking

current or at a no load condition, the inductor valley current will be negative. During any time when the

inductor valley current is negative and the ISL70003 is exposed to a heavy ion environment, the abs

max PVIN voltage must be ≤13.7V.

29

SEL1

2

This pin is a logic-level disable (high) input working in conjunction with SEL2. These pins form a two-bit

logic input that set the number of active power blocks. This allows the ISL70003SEH current capability

to be tailored to the load current level the application requires and achieve the highest possible

efficiency.

30

31

SEL2

DE

2

This pin is a logic-level disable input. Pulling this pin high inhibits pulses on the LXx outputs. See

description of Pin 29, SEL1, for more information.

The DE pin enables or disables Diode Emulation. When it is HIGH, diode emulation is allowed.

Otherwise, continuous conduction mode is forced.

24, 27, 33, 36,

39, 42, 45, 48,

54, 57

LXx

These pins are the switch node connections to the internal power blocks and should be connected to

the output filter inductor. Internally, these pins are connected to the synchronous MOSFET power

switches.

50

51

52

NC/HS

IMON

N/A

1

This is a No Connect pin that is not connected to anything internally. In the R64.C package (heatsink

option) this pin is electrically connected to the heatsink on the underside of the package. Connect this

pin and/or the heatsink to a thermal plane.

IMON is a current source output that is proportional to the sensed current through the regulator. If not

used it is recommended to tie IMON to VREFA. It is also acceptable to tie IMON to GND through a

resistor.

SGND

1

7

This pin is connected to an internal metal trace that serves as a noise shield. Connect this pin to the

PCB ground plane.

25, 26, 34, 35,

40, 41, 46, 47,

55, 56

PGNDx

These pins are the power grounds associated with the corresponding internal power blocks. Connect

these pins directly to the PCB ground plane. These pins should also connect to the negative terminals

of the input and output capacitors. The package lid is internally connected to PGNDx

59

60

61

62

63

64

OCSETA

OCSETB

BUFIN+

BUFIN-

BUFOUT

REF

3

1

3

1

This pin is the redundant output overcurrent set input. Connect a resistor from this pin to the PCB

ground plane to set the output overcurrent threshold.

This pin is the primary output overcurrent set input. Connect a resistor from this pin to the PCB ground

plane to set the output overcurrent threshold.

This pin is the input to the internal unity gain buffer amplifier. For DDR memory power applications,

connect the VTT voltage to this pin.

This pin is the inverting input to the buffer amplifier. For DDR memory power applications, connect

BUFOUT to this pin. Bypass this pin to the PCB ground plane with a 0.1µF ceramic capacitor.

This pin is the output of the buffer amplifier. In DDR power applications, connect this pin to the

reference input of the DDR memory. The buffer needs a minimum of 1.0µF load capacitor for stability.

This pin is the output of the internal reference voltage. Bypass this pin to the PCB ground plane with a

220nF ceramic capacitor located as close as possible to the IC. The bypass capacitor is needed to

mitigate SEE.

VREFA

PIN #

VREFD

PIN #

AVDD

PVINx

PIN #

7V

CLAMP

12V

CLAMP

12V

CLAMP

7V

CLAMP

12V

CLAMP

PGNDx

CIRCUIT 7

AGND

CIRCUIT 3

DGND

AGND

CIRCUIT 5

DGND

CIRCUIT 4

DGND

CIRCUIT 6

CIRCUIT 1

CIRCUIT 2

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ISL70003SEH

Typical Application Schematics

VIN = 12V

100k

+

5 x 1µF

4x100µF

22k

51k

3k

7.15k

10nF

370pF

PGOOD

10nF

VIMON

22

51

PGOOD

LX10

IMON

10k

24

27

5

9

11

LX9

VREFA

VREFOUTS

VREFD

3.3µH

33

36

39

42

45

48

54

57

LX8

LX7

LX6

LX5

LX4

LX3

LX2

VOUT = 3.3V

1µF

0.47µF

150µF

x3

+

10

15

16

ISL70003SEH

SYNC

SS

1nF

LX1

357

0.1µF

51.1k

59

60

OCA

25k

1nF

6.8nF

4.02k

2

3

1

FB

VERR

NI

REF

OCB

12pF

5.49k

64

2.7nF

0.22µF

FIGURE 4. ISL70003SEH SINGLE UNIT OPERATION

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ISL70003SEH

Typical Application Schematics (Continued)

VIN = 5V

25k

4k

+

5 x 1µF

4x100µF

22k

3k

10nF

370pF

PGOOD

10nF

VIMON

22

51

PGOOD

LX10

IMON

10k

24

27

5

9

11

LX9

LX8

LX7

LX6

LX5

LX4

LX3

LX2

LX1

VREFA

VREFOUTS

VREFD

1.5µH

33

36

39

42

45

48

54

57

VDDQ = 2.5V

0.47µF

1µF

3 x 150µF

+

10

15

16

ISL70003SEH

SYNC

SS

1nF

715

59

60

OCA

OCB

25k

0.1µF

1nF

6.8nF

4.02k

2

3

FB

VERR

NI

REF

1

31.2k

68pF

7.87k

64

4nF

0.33µF

VREF = 1.25V

1µF

25k

+

5 x 1µF

4x100µF

22k

3k

4k

10nF

370pF

PGOOD

10nF

64

REF

22

PGOOD

51

0.22µF

IMON

10k

24

27

LX10

LX9

5

VREFA

9

2.2µH

33

36

39

42

45

48

54

57

LX8

LX7

LX6

LX5

LX4

LX3

LX2

LX1

VREFOUTS

11

VTT = 1.25V

1µF

0.47µF

VREFD

3 x 150µF

+

10

1nF

15

16

ISL70003SEH

SYNC

SS

400

59

60

OCA

OCB

25k

0.1µF

6.8nF

8.2k

1.6nF

2

3

FB

VERR

22.9k

82pF

22.9k

8.2k

1

NI

15nF

25k

7.87k

FIGURE 5. ISL70003SEH DDR MEMORY POWER SOLUTION

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Absolute Maximum Ratings

Thermal Information

LXx, PVINx . . . . . . . . . . . . . . . . . . . . . . . . . . . .PGNDx - 0.3V to PGNDx + 16V

LXx, PVINx (Note 4). . . . . . . . . . . . . . . . . . . PGNDx - 0.3V to PGNDx + 14.7V

LXx, PVINx (Note 5). . . . . . . . . . . . . . . . . . . PGNDx - 0.3V to PGNDx + 13.7V

AVDD - AGND, DVDD - DGND . . . . . . . . . . . . . . . . . . . . . . . . . . PVINx to -0.3V

VREFA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GNDA - 0.3V to GNDA + 5.5V

VREFD, VREF_OUTS . . . . . . . . . . . . . . . . . . . . .GNDD - 0.3V to GNDD + 5.5V

Signal Pins (Note 10) . . . . . . . . . . . . . . . . . . . GNDA - 0.3V to VREFA + 0.3V

Digital Control Pins (Note 11) . . . . . . . . . . . . .GNDD - 0.3V to VREFD+ 0.3V

SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND - 0.3V to DGND + 2.5V

PGOOD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GNDD - 0.3V to DVDD

RTCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GNDD - 0.3V to DVDD

ESD Rating

Thermal Resistance (Typical)

CQFP Package R64.A (Notes 6, 7) . . . . . . .

CQFP Package R64.C (Notes 8, 9) . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C



_JA(°C/W)



_JC(°C/W)

34

17

1.5

0.7

Recommended Operating Conditions

Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

PVINx, AVDD, DVDD . . . . . . . . . . . . . . . . . . . . . . . . 3.3V ±10% to 12V ±10%

Human Body Model (Tested per MIL-STD-883 TM3015.7) . . . . . . . . 2kV

Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 200V

Charge Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

2

4. For operation in a heavy ion environment at LET = 86.4 MeV•cm /mg at 125°C (T ) and sourcing 7A load current.

C

5. For operation in a heavy ion environment at LET = 86.4 MeV•cm /mg at 125°C (T ) with any negative inductor current to sinking -4A load current.

2

C

6.  is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

7. For  , the “case temp” location is the center of the package underside.

JC

8.  is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379.

9. For  , the “case temp” location is the center of the exposed metal heatsink on the package underside.

JC

10. POR_VIN, FB, NI, VERR, OCSETA, OCSETB, BUFOUT, BUFIN-, BUFIN+, IMON and REF pins.

11. FSEL, EN, SYNC, SEL1, SEL2, and DE pins.

Electrical Specifications Unless otherwise noted, V = AVDD = DVDD = PVINx = EN = 3V - 13.2V; GND = AGND = DGND = PGNDx =

IN

GNDx = 0V; POR_V = FB = 0.65V; SYNC = LXx = Open Circuit; PGOOD is pulled up to VREFD with a 3k resistor; REF is bypassed to GND with a 220nF

IN

capacitor; SS is bypassed to GND with a 100nF capacitor; I

= 0A; T = TJ = +25°C. (Note 4). Boldface limits apply across the operating temperature

OUT

A

range, -55°C to +125°C; over a total ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 - 300rad(Si)/s; or over a total ionizing dose of

50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s.

MIN

MAX

PARAMETER

POWER SUPPLY

TEST CONDITIONS

(Note 15)

TYP

(Note 15)

UNITS

Operating Supply Current

Standby Supply Current

Shutdown Supply Current

PV = 13.2V, FSEL = 1

INx

80

30

20

10

1.5

0.4

125

60

mA

PV = 13.2V, FSEL = 0

INx

PV = 3.0V, FSEL = 1

INx

PV = 3.0V, FSEL = 0

INx

60

PV = 13.2V, SEL1 = SEL2 = GND, FSEL = 1

INx

30

PV = 13.2V, SEL1 = SEL2 = GND, FSEL = 0

INx

30

PV = 3.0V, SEL1 = SEL2 = GND, FSEL = 1

INx

15

PV = 3.0V, SEL1 = SEL2 = GND, FSEL = 0

INx

15

PV = 13.2V, EN = GND

INx

3.0

1.0

PV = 3.0V, EN = GND

INx

LINEAR REGULATORS

Output Voltage

AVDD, DVDD = 13.2V

4.5

50

5.0

5.5

V

Current Limit

190

mA

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Electrical Specifications Unless otherwise noted, V = AVDD = DVDD = PVINx = EN = 3V - 13.2V; GND = AGND = DGND = PGNDx =

IN

GNDx = 0V; POR_V = FB = 0.65V; SYNC = LXx = Open Circuit; PGOOD is pulled up to VREFD with a 3k resistor; REF is bypassed to GND with a 220nF

IN

capacitor; SS is bypassed to GND with a 100nF capacitor; I

= 0A; T = TJ = +25°C. (Note 4). Boldface limits apply across the operating temperature

OUT

A

range, -55°C to +125°C; over a total ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 - 300rad(Si)/s; or over a total ionizing dose of

50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued)

MIN

MAX

PARAMETER

POWER-ON RESET

TEST CONDITIONS

(Note 15)

TYP

(Note 15)

UNITS

POR Pin Input Voltage

POR Sink Current

ENABLE

0.56

9.6

0.6

12

0.64

14.4

V

µA

Enable VIH Voltage

Enable VIL Voltage

Enable (EN) Leakage

SELECT PHASE

2

V

0.8

10

EN = 4.5V

1.0

µA

SEL 1, 2 VIH Voltage

SEL 1, 2 VIL Voltage

SEL 1, 2 Leakage Current

PWM CONTROL LOGIC

Switching Frequency

2

V

0.8

10

SEL1, 2 = VREFD

1.0

µA

FSEL = 1

255

425

300

500

250

160

200

5

345

575

320

220

270

kHz

ns

FSEL = 0

Minimum On Time

Minimum Off Time

SS = GND (Note 14)

(Note 14)

ns

(Note 14)

ns

Modulator Gain (V ΔV

)

R = 22kΩ, C = 370pF, FSEL = 0

V/V

kHz

V

IN / OSC

T

R = 36kΩ, C = 370pF, FSEL = 1

4.8

T

External Synchronization Frequency Range FSEL = 1, PV = 3.0V

INx

255

425

2

300

500

345

575

FSEL = 0, PV = 3.0V

INx

SYNC VIH Voltage

SYNC VIL Voltage

0.8

4

V

Synchronization Input Leakage Current

SOFT-START

SYNC = VREFD

SS = GND

1.0

µA

Soft-start Source Current

Soft-start Discharge ON-Resistance

Soft-start Discharge Time

REFERENCE VOLTAGE

Reference Voltage Tolerance

ERROR AMPLIFIER

20

23

3.0

256

27

µA

Ω

6.0

(Note 14)

Clock Cycles

VREF + Error Amplifier V

0.594

0.6

0.606

V

IO

DC Gain

(Note 14)

80

7

dB

MHz

V

Gain-bandwidth Product

Maximum Output Voltage

Slew Rate

V

= 5.5V

3.5

-3

4.2

8.5

IN

(Note 14)

= 0.6V, PV = 13.2V

V/µs

nA

Feedback (FB) Input Leakage Current

V

250

3

FB

INx

Offset Voltage (V

)

0

mV

IO

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ISL70003SEH

Electrical Specifications Unless otherwise noted, V = AVDD = DVDD = PVINx = EN = 3V - 13.2V; GND = AGND = DGND = PGNDx =

IN

GNDx = 0V; POR_V = FB = 0.65V; SYNC = LXx = Open Circuit; PGOOD is pulled up to VREFD with a 3k resistor; REF is bypassed to GND with a 220nF

IN

capacitor; SS is bypassed to GND with a 100nF capacitor; I

= 0A; T = TJ = +25°C. (Note 4). Boldface limits apply across the operating temperature

OUT

A

range, -55°C to +125°C; over a total ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 - 300rad(Si)/s; or over a total ionizing dose of

50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued)

MIN

MAX

PARAMETER

POWER BLOCKS

TEST CONDITIONS

(Note 15)

TYP

(Note 15)

UNITS

Upper Device r

PV = 3.0V

INx

170

120

90

420

310

240

210

1

700

600

455

425

3

mΩ

µA

DS(ON)

PV = 5.5V

INx

Lower Device r

PV = 3.0V

INx

DS(ON)

PV = 5.5V

INx

60

LXx Output Leakage

Dead Time

EN = LXx = GND, Single LXx Output

EN = GND, LXx = PV , Single LXx Output

INx

1

3

µA

Within a Single Power Block or between Power

Blocks (Note 14)

4

ns

POWER-GOOD SIGNAL

Rising Threshold

V

as a % of V

107

2

111

3.5

89

115

5

%

FB

REF

Rising Hysteresis

Falling Threshold

85

2

93

5

%

Falling Hysteresis

3.5

%

Power-good Drive

PV = 3V, PGOOD = 0.4V, EN = GND

IN

7.2

mA

µA

Power-good Leakage

PROTECTION FEATURES

Undervoltage Protection

Undervoltage Trip Threshold

Undervoltage Recovery Threshold

Overcurrent Protection

Overcurrent Accuracy

BUFFER AMPLIFIER

PV = PGOOD = 13.2V

IN

1

V

as a % of V , Test mode

REF

71

86

75

90

79

94

%

FB

as a % of V , Test mode

REF

FB

ROCSETA, B = 6kΩ (IOC = 0.6A/LX) V = 12V

IN

0.43

0.6

0.77

A/LX

kHz

Gain Bandwidth Product

C

= 1µF, I

SOURCE

= 1mA, A = 1, V

OUT

= 1.25V

200

L

V

(Note 14)

Source Current Capability

Sink Current Capability

Offset Voltage

20

4

mA

µA

250

-4

400

0

mV

IMON CURRENT MONITOR

IMON Sense Time

145

-14

215

100

300

14

ns

µA/A

µA

IMON Output Current Gain

IMON Gain Accuracy

NOTES:

I

= 1A/Power Stage, LXx Off Time >300ns

LOAD

12. Typical values shown are not guaranteed.

13. The 0A to 6A output current range may be reduced by Minimum LXx On Time and Minimum LXx Off Time specifications.

14. Limits established by characterization or analysis and are not production tested.

15. Parameters with MIN and/or MAX limits are 100% tested at -55°C, +25°C and +125°C, unless otherwise specified.

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Typical Performance Curves Unless otherwise noted, V = 12V, V = 3.3V, I = 3A, f = 500kHz,

IN

OUT

SW

C

= 4x 100µF + 5x1µF, L

= 3.3µH, C = 3x 150µF + 1µF, T = +25°C, All outputs active.

IN

100

OUT

OUT A

100

95

90

85

80

75

70

65

60

55

50

90

85

9V

80

5V

75

70

65

60

55

50

3.3V

2.5V

5V

2.5V

3.3V

0

1

2

3

4

5

6

0

1

2

3

4

5

6

LOAD CURRENT (A)

FIGURE 6. EFFICIENCY vs LOAD, V = 12V, 300kHz

IN

FIGURE 7. EFFICIENCY vs LOAD, V = 12V, 500kHz

IN

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

1.5V

2.5V

1.8V

2.5V

1.8V

1.2V

3.3V

1.5V

3.3V

1.2V

0

1

2

3

4

5

6

0

1

2

3

4

5

6

LOAD CURRENT (A)

FIGURE 9. EFFICIENCY vs LOAD, V = 5V, 500kHz

IN

FIGURE 8. EFFICIENCY vs LOAD, V = 5V, 300kHz

IN

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

1.8V

1.2V

1.8V

1.5V

1.2V

2.5V

0

1

2

3

4

5

6

0

1

2

3

4

5

6

LOAD CURRENT (A)

FIGURE 11. EFFICIENCY vs LOAD, V = 3.3V, 500kHz

IN

FIGURE 10. EFFICIENCY vs LOAD, V = 3.3V, 300kHz

IN

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Typical Performance Curves Unless otherwise noted, V = 12V, V = 3.3V, I = 3A, f = 500kHz,

IN

OUT

SW

C

= 4x 100µF + 5x1µF, L

= 3.3µH, C

= 3x 150µF + 1µF, T = +25°C, All outputs active. (Continued)

IN

OUT

A

4.5

4.0

3.5

4.0

9V

3.5

3.0

2.5

2.0

1.5

1.0

0.5

9V

3.0

5V

2.5

2.0

1.5

5V

3.3V

1.0

3.3V

2.5V

0.5

2.5V

0.0

0

1

2

3

4

5

6

0

1

2

3

4

5

6

LOAD CURRENT (A)

FIGURE 12. POWER LOSS, V = 12V, 300kHz

IN

FIGURE 13. POWER LOSS, V = 12V, 500kHz

IN

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.3V

2.5V

1.8V

1.5V

1.8V

1.2V

0

1

2

3

4

5

6

0

1

2

3

4

5

6

LOAD CURRENT (A)

FIGURE 15. POWER LOSS, V = 5V, 500kHz

IN

FIGURE 14. POWER LOSS, V = 5V, 300kHz

IN

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

1.2V

2.5V

1.5V

1.8V

1.2V

1.8V

1.5V

1.2V

0

1

2

3

4

5

6

0

1

2

3

4

5

6

LOAD CURRENT (A)

FIGURE 16. POWER LOSS, V = 3.3V, 300kHz

IN

FIGURE 17. POWER LOSS, V = 3.3V, 500kHz

IN

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Typical Performance Curves Unless otherwise noted, V = 12V, V = 3.3V, I = 3A, f = 500kHz,

IN

OUT

SW

C

= 4x 100µF + 5x1µF, L

= 3.3µH, C

= 3x 150µF + 1µF, T = +25°C, All outputs active. (Continued)

IN

OUT

A

3.35

1.818

1.812

1.806

1.800

1.794

1.788

1.782

3.34

3.33

3.32

3.31

3.30

3.29

3.28

0

1

2

3

4

5

6

2

4

6

8

10

12

14

LOAD CURRENT (A)

INPUT VOLTAGE (V)

FIGURE 19. LINE REGULATION, V

= 1.8V, LOAD = 3A

FIGURE 18. LOAD REGULATION

OUT

606

604

602

600

598

596

594

606

604

602

600

598

596

594

-55°C

PV = 13.2V

IN

PV = 3V

IN

+25°C

+125°C

-60

-40

-20

0

20

40

60

80

100 120 140

2

4

6

8

10

12

14

INPUT VOLTAGE (V)

TEMPERATURE (°C)

FIGURE 20. REFERENCE VOLTAGE vs TEMPERATURE

FIGURE 21. REFERENCE VOLTAGE vs V

IN

6.00

5.75

5.50

5.25

5.00

4.75

4.50

4.25

4.00

545

495

445

395

345

295

245

500kHz

PV = 13.2V

IN

PV = 3V

IN

PV = 3V

IN

300kHz

PV = 13.2V

IN

2

4

6

8

10

12

14

-60

-40

-20

0

20

40

60

80

100 120 140

INPUT VOLTAGE (V)

TEMPERATURE (°C)

FIGURE 23. SWITCHING FREQUENCY vs TEMPERATURE

FIGURE 22. MODULATOR GAIN vs V

IN

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Typical Performance Curves Unless otherwise noted, V = 12V, V = 3.3V, I = 3A, f = 500kHz,

IN

OUT

SW

C

= 4x 100µF + 5x1µF, L

= 3.3µH, C

= 3x 150µF + 1µF, T = +25°C, All outputs active. (Continued)

IN

OUT

A

ENABLE, 5V/DIV

LXx VOLTAGE, 5V/DIV

INDUCTOR CURRENT, 2A/DIV

OUTPUT VOLTAGE, 2V/DIV

PGOOD, 10V/DIV

FIGURE 25. MONOTONIC SOFT-START WITH 6A LOAD, CCM

FIGURE 24. MONOTONIC SOFT-START WITH NO LOAD, CCM

ENABLE, 5V/DIV

LXx VOLTAGE, 5V/DIV

OUTPUT VOLTAGE, 2V/DIV

PGOOD, 10V/DIV

OUTPUT VOLTAGE, 2V/DIV

PGOOD, 10V/DIV

FIGURE 26. MONOTONIC SOFT-START WITH 1.5V PREBIASED LOAD

FIGURE 27. MONOTONIC SOFT-START WITH NO LOAD, DEM

LXx VOLTAGE, 5V/DIV

INDUCTOR CURRENT, 2A/DIV

INDUCTOR CURRENT, 1A/DIV

OUTPUT VOLTAGE, 20mV/DIV

FIGURE 28. STEADY STATE OPERATION NO LOAD, CCM

FIGURE 29. STEADY STATE OPERATION FULL LOAD, CCM

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Typical Performance Curves Unless otherwise noted, V = 12V, V = 3.3V, I = 3A, f = 500kHz,

IN

OUT

SW

C

= 4x 100µF + 5x1µF, L

= 3.3µH, C

= 3x 150µF + 1µF, T = +25°C, All outputs active. (Continued)

IN

OUT

OUT A

INDUCTOR CURRENT, 2A/DIV

LXx VOLTAGE, 5V/DIV

INDUCTOR CURRENT, 0.5A/DIV

OUTPUT VOLTAGE, 20mV/DIV

OUTPUT VOLTAGE, 200mV/DIV

FIGURE 30. DIODE EMULATION OPERATION, V

OUT

= 1.2V, 125mA LOAD

FIGURE 31. 6A LOAD TRANSIENT RESPONSE, DIODE EMULATION

INDUCTOR CURRENT, 2A/DIV

OUTPUT VOLTAGE, 50mV/DIV

FIGURE 33. 6A LOAD TRANSIENT RESPONSE

FIGURE 32. 3A LOAD TRANSIENT RESPONSE

LXx VOLTAGE, 5V/DIV

INDUCTOR CURRENT, 10A/DIV

INDUCTOR CURRENT, 5A/DIV

OUTPUT VOLTAGE, 2V/DIV

SS VOLTAGE, 2V/DIV

PGOOD, 10V/DIV

FIGURE 34. OVERCURRENT RESPONSE

FIGURE 35. HICCUP RESPONSE IN OCP

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ISL70003SEH

Functional Description

Initialization

The ISL70003SEH is a monolithic synchronous buck regulator IC

with integrated power MOSFETs. The device utilizes voltage-mode

control with feed-forward and switches at a nominal frequency of

500kHz or 300kHz. It is fabricated on a 0.6μm BiCMOS junction

isolated process optimized for power management applications.

With this chip and a handful of external components, a complete

synchronous buck DC/DC converter can be readily implemented.

The converter accepts an input voltage ranging from 3V to 13.2V

and provides a tightly regulated output voltage ranging from 0.6V

to ~90% of the input voltage at output currents ranging from 0A

to 6A. Typical applications include Point Of Load (POL) regulation

for FPGAs, CPLDs, DSPs, DDR memory and microprocessors.

The ISL70003SEH initializes based on the state of the EN input

and POR input. Successful initialization prompts a soft-start

interval and the regulator begins slowly ramping the output

voltage. Once the commanded output voltage is within the

proper window of operation, the power-good signal changes state

from low to high indicating proper regulator operation.

Enable

The EN pin accepts TTL/CMOS logic input as described in the

Electrical Specifications” table on page 9. When the voltage on

the EN pin exceeds its logic rising threshold, the controller

monitors the POR voltage before initiating the soft-start function

for the PWM regulator. When EN is pulled low, the device enters

shutdown mode and the supply current drops to a typical value of

1.5mA. All internal power devices are held in a high-impedance

state while in shutdown mode. Due to the internal 5V clamp, the

EN pin should be driven no higher than 5V or excessive leakage

current may be seen on the pin. In standalone applications the

EN pin may be tied to an input voltage >5V through a 50kΩ

resistor to minimize the current into the EN pin. The current

should not be allowed to exceed 160µA at any operating voltage.

Power Blocks

PVIN1

LX1

PGND1

PVIN6

LX6

PGND6

POWER BLOCK 6

OCPB and IMON

POWER BLOCK 1

POWER BLOCK 2

POWER BLOCK 3

PVIN2

LX2

PGND2

PVIN7

LX7

PGND7

POWER BLOCK 7

POWER BLOCK 8

PVIN3

LX3

PVIN8

LX8

PGND8

V

> 5.0V

PGND3

IN

PVINx

PVIN9

LX9

PGND9

PVIN4

LX4

PGND4

POWER BLOCK 9

POWER BLOCK 10

POWER BLOCK 4

R1

51kΩ

PVIN5

LX5

PGND5

PVIN10

LX10

PGND10

ENABLE

POWER BLOCK 5

and OCPA

COMPARATOR

EN

+

V

R

Note: Shaded blocks indicate pilot current and current sensors.

-

POR

LOGIC

FIGURE 36. POWER BLOCK DIAGRAM

The power output stage of the regulator consists of ten power

blocks that are paralleled to provide full 6A output current

capability at T = +125°C. The block diagram in Figure 36 shows

J

a top level view of the individual power blocks.

FIGURE 37. ENABLE TO V FOR >5.0 INPUT VOLTAGE

IN

SEL1 and SEL2 pins allow users to disable power blocks in order

to reduce switching losses in light load applications. Depending

on the state of these pins the ISL70003SEH can operate with 2,

4, or 10 active power blocks and also be placed in a sleep mode.

Power-On Reset

After the EN input requirements are met, the ISL70003SEH

remains in shutdown until the voltage at the POR pin rises above

its threshold. The POR circuitry prevents the controller from

attempting to soft-start before sufficient bias is present at the

PVINx pins.

Each power block has a power supply input pin, PVINx, a phase

output pin, LXx and a power supply ground pin, PGNDx. All PVINx

pins must be connected to a common power supply rail and all

PGNDx pins must be connected to a common ground. LXx pins

should be connected to the output inductor based on the

required load current and the state of the SEL1, SEL2 pins, but

must include the LX5 and LX6 pins. The unused LXx pins should

be left unconnected.

As shown in Figure 38 on page 18, the POR circuit features a

comparator type input. The POR circuit allows the level of the

input voltage to precisely gate the turn-on/turn-off of the

regulator. An internal I

current sink with a typical value of

POR

12µA is only active when the voltage on the POR pin is below the

enable threshold so it can pull the POR pin low. As V rises, the

Scaled pilot devices associated with power blocks 5 and 6

provide current feedback for overcurrent detection and the IMON

current monitor feature. Power blocks 5 and 6 must be

connected to the output inductor at all times for proper

operation.

IN

POR enable level is set by the resistor divider (R and R ) from

1

2

V

and the internal sink current source, I .

IN

POR

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ISL70003SEH

output load current does not exceed the overcurrent trip level of

the regulator.

V

I

C

= 0.6V

R

V

REF

V

--------------

= 12µA

t

= C



(EQ. 4)

IN

POR

SS

I

SS

= 10nF

POR

PVINx

V

OUT

---------------

I

= C



(EQ. 5)

INRUSH

OUT

t

SS

The soft-start capacitor is immediately discharged by a 3.0Ω

resistor whenever POR conditions are not met or EN is pulled low.

The soft-start discharge time is equal to 256 clock cycles.

V

IN

POR

COMPARATOR

R

1

POR

+

V

OUT

V

I

R

= 0.6V

REF

SS

V

R

C

POR

2

= 23µA

= 2.2Ω

-

POR

LOGIC

R

T

D

FB

I

POR

R

B

ERROR

AMPLIFIER

SS

NI

-

C

SS

+

FIGURE 38. POR CIRCUIT

V

REF

PWM

R

D

LOGIC

Equation 2 defines the relationship between the resistor divider,

I

SS

sink current and POR rising level (V

).

PORR

R

1

R

2

------

V

= V



1 +

+ I

 R

POR 1

(EQ. 2)

PORR

R

REF

V

REF

Once the voltage at the POR pin reaches the enable threshold,

the I current sink turns off.

C

REF

POR

With the part enabled and the I

FIGURE 39. SOFT-START CIRCUIT

current sink off, the falling level

POR

(V

) is set by the resistor divider network and is defined by

Equation 3.

PORF

Power-Good

R

1

A power-good indicator is the final step of initialization. After a

successful soft-start, the PGOOD pin releases and the voltage

rises with an external pull-up resistor. The power-good signal

transitions low immediately when the EN pin is pulled low.

(EQ. 3)

------

V

= V



R

1 +

PORF

R

2

The difference between the POR rising and falling levels provides

adjustable hysteresis so that noise on V does not interfere with

the enabling or disabling of the regulator.

IN

The PGOOD pin is an open-drain logic output and can be pulled

up to any voltage from 0V to 13.2V. The pull-up resistor should

have a nominal value from 1kΩ to 10kΩ. The PGOOD pin should

be bypassed to DGND with a 10nF ceramic capacitor to mitigate

SEE.

Soft -Start

The ISL70003SEH soft-start function uses an internal current

source and an external capacitor to reduce stresses and surge

current during start-up.

Fault Monitoring and Protection

Once the POR and enable circuits are satisfied, the regulator

waits 32 clock cycles and then initiates a soft-start. Figure 39

shows that the soft-start circuit clamps the error amplifier

reference voltage to the voltage on an external soft-start

capacitor connected to the SS pin. The soft-start capacitor is

The ISL70003SEH actively monitors the output voltage and

current to detect fault conditions. Fault conditions trigger

protective measures to prevent damage to the regulator and the

external load device. One common power-good indication signal

is provided for linking to external system monitors. The

schematic in Figure 40 on page 19 outlines the interaction

between the fault monitors and the power-good signal.

charged by an internal I current source. As the soft-start

SS

capacitor is charged, the output voltage slowly ramps to the set

point determined by the reference voltage and the feedback

network. Once the voltage on the SS pin is equal to the internal

reference voltage, the soft-start interval is complete. The

soft-start output ramp interval is defined in Equation 4 and is

adjustable from approximately 2ms to 200ms. The value of the

Undervoltage and Overvoltage Monitor

The power-good pin (PGOOD) is an open-drain logic output which

indicates that the converter is operating properly and the output

voltage is within a set window. The Undervoltage (UV) and

Overvoltage (OV) comparators create the output voltage window.

soft-start capacitor, C , should range from 82nF to 8.2µF,

SS

inclusive. The peak in-rush current can be computed from

Equation 5. The soft-start interval should be selected long

enough to insure that the peak in-rush current plus the peak

The power-good circuitry monitors the FB pin and compares it to

the rising and falling thresholds shown in the “Electrical

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ISL70003SEH

Specifications” table on page 11. If the feedback voltage

Upon detection of an overcurrent condition, the upper MOSFET

will be immediately turned off and will not be turned on again

until the next switching cycle. Upon detection of the initial

overcurrent condition, the overcurrent fault counter is set to 1. If,

on the subsequent cycle, another overcurrent condition is

detected, the OC fault counter will increment, however, if the

sampled current falls below the threshold the counter is reset. If

there are 4 sequential OC fault detections, the counter will

overflow and the regulator will be shutdown under an overcurrent

fault condition, pulling PGOOD low.

exceeds the typical rising limit of 111% of the reference voltage,

the PGOOD pin pulls low. The PGOOD pin continues to pull low

until the feedback voltage falls to a typical of 107.5% of the

reference voltage. If the feedback voltage drops below a typical

of 89% of the reference voltage, the PGOOD pin pulls low. The

PGOOD pin continues to pull low until the feedback voltage rises

to a typical 92.5% of the reference voltage. The PGOOD pin then

releases and signals the return of the output voltage within the

power-good window

ꢆꢇ

0.666V

PGOOD

LOAD CURRENT, 5A/DIV

ꢅ

+

ꢄ

OV

-

ꢃ

0A

ꢂ

ꢁ

OUTPUT VOLTAGE, 1V/DIV

+

-

UV

ꢀ

FB

COUNTER/

POR/ ON-OFF

CONTROL

0.534V

0ꢉV

ꢈ

I

SEN

SOFT-START VOLTAGE, 1V/DIV

-

OCP

+

ꢆ

UVP

OCSETB

OCSETA

+

0V

ꢇ

-

I

5ms/DIV

SEN

-

0.45V

OCP

FIGURE 1. OVERCURRENT BEHAVIOR IN HICCUP MODE

+

After the regulator shuts down, it enters a delay interval, allowing

the device to cool. The delay interval is approximately equal to

512 clock cycles plus 1 soft-start intervals. The overcurrent

counter is reset entering the delay interval. The protection logic

initiates a normal soft-start once the delay interval ends. If the

output successfully soft-starts, the power-good signal goes high

and normal operation continues. If overcurrent conditions

continue to exist during the soft-start interval, the overcurrent

counter must overflow before the regulator shutdowns the output

again. This hiccup mode continues indefinitely until the output

soft-starts successfully (see Figure 1).

FIGURE 40. POWER-GOOD AND PROTECTION CIRCUITRY

Undervoltage Protection

A hysteretic comparator monitors the FB pin of the regulator. The

feedback voltage is compared to an undervoltage threshold that

is a fixed percentage of the reference voltage, typically 75%.

Once the comparator trips, indicating a valid undervoltage

condition, an undervoltage counter increments. The counter is

reset if the feedback voltage rises back above the undervoltage

threshold plus a specified amount of hysteresis outlined in the

“Electrical Specifications” table on page 11. If there are 4

consecutive undervoltage detections the counter will overflow

and the undervoltage protection logic shuts down the regulator,

pulling PGOOD low.

Application Information

Voltage Feed-forward

Feed-forward is used to maintain a constant modulator gain and

achieve optimum loop response over a wide input voltage range.

A resistor from PVINx to RTCT and a capacitor from RTCT to

PGNDx are used to adjust the amplitude of the sawtooth ramp

proportional to the input voltage. The capacitor value must be

chosen so that it is large enough for mitigation of single event

transients but low enough for the internal MOSFET device to pull

the pin to ground. The following table gives the recommended

After the regulator shuts down, it enters a delay interval,

approximately equivalent to 512 clock cycles plus 1 soft-start

intervals, allowing the device to cool. The undervoltage counter is

reset entering the delay interval. The protection logic initiates a

normal soft-start once the delay interval ends. If the output

successfully soft-starts, the power-good signal goes high and

normal operation continues. If undervoltage conditions continue

to exist during the soft-start interval, the undervoltage counter

must overflow before the regulator shuts down again. This hiccup

mode continues indefinitely until the output soft-starts

successfully.

values for R and C for a given switching frequency. These

T

values will achieve a constant modulator gain across the

complete input voltage range.

MODULATOR

GAIN (TYP)

Overcurrent Protection

FSEL STATE

f

(kHz)

R (kΩ)

C (pF)

T

SW

500

300

T

A pilot device integrated into the PMOS transistor of Power Blocks

5 and 6 sample the current each cycle. This current feedback is

scaled and compared to an overcurrent threshold based on the

resistor value tied from pins OCSETA and OCSETB to AGND.

0

1

22

36

370

5

4.8

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ISL70003SEH

Switching Frequency Selection

R

 0.6V

1

(EQ. 6)

R

= ------------------------------------------

4

There are a number of variables to consider when choosing the

switching frequency. A high switching frequency increases the

switching losses but may lead to a decrease in output filter size.

A lower switching frequency may increase efficiency but may

lead to more output voltage ripple and increased output filter

size.

V

– 0.6V

OUT

If the output voltage desired is 0.6V, then R is left unpopulated.

4

Setting the Overcurrent Protection Level

The ISL70003SEH features dual redundancy in the overcurrent

detection circuitry, which helps avoid false overcurrent triggering

due to single event effects. Two external resistors from pins

OCSETA and OCSETB to AGND set the level of the over current

protection (OCP) trip point. The OCP circuit senses the peak

current across a pilot device not the average current so it is

On the ISL70003SEH the switching frequency is determined by

the state of the TTL/CMOS compatible FSEL pin. A logic low will

set the regulator to operate with a 500kHz switching frequency,

while a logic high sets a 300kHz switching frequency.

important to determine the overcurrent trip point (I

) greater

) plus half

OCP

Synchronization

than the maximum output continuous current (I

MAX

The ISL70003SEH can be synchronized to an external clock with

a frequency range of 500kHz ±15% or 300kHz ±15%, depending

on the state of the FSEL pin.

the maximum inductor ripple current (ΔI).

Use Equation 7 to determine the inductor ripple current:

V

– V

OUT

IN

f

The SYNC pin accepts the external clock signal and the regulator

will be synchronized in phase with the external clock. During

start-up the regulator will use its internal oscillator to regulate

the output voltage. Once soft-start is complete and PGOOD is

released, the regulator will synchronize to the external clock

signal. This feature allows the ISL70003SEH regulator to be the

power source to the external components that will be providing

the external clock without the requirement that a signal must be

present at the SYNC pin before start-up.

-------------------------------

I =

 D

(EQ. 7)

 L

SW

Where f

is the switching frequency, L is the output inductor

SW

value and D is duty cycle. Once an I

satisfies Equation 8:

value is chosen that

OCP

I

2

-----

I

 I

+

MAX

(EQ. 8)

OCP

Equation 9 may be used to determine the value of R

and

OCSETA

Output Voltage Selection

R

with all 10 power blocks active.

OCSETB

36024

----------------

R

=

(EQ. 9)

OCSETA B

I

OCP

L

V

O

OUT

LXx

The minimum value for R

equivalent to a 12.25A I

is 2.94kΩ which is

OCSET(A,B)

level.

C

OCP

O

R

1

ERROR

AMPLIFIER

Disabling the Power Blocks

The ISL70003SEH offers two TTL/CMOS compatible power block

select pins, SEL1 and SEL2, which form a two-bit logic input that

are used to turn off the internal power blocks. Depending on the

state of the SEL1 and SEL2 pins, the ISL70003SEH can operate

with 2, 4 or 10 power blocks on or have all the outputs in a

tr-state mode. This allows the designer to reduce switching

losses in low current applications, where all power blocks are not

needed to supply the load current. Table 1 on page 20 compares

the logic state of SEL1 and SEL2 with the current capability of the

regulator and the number of active LXx pins.

FB

NI

-

R

4

+

REF

V

REF

C

REF

FIGURE 41. OUTPUT VOLTAGE SELECTION

The output voltage of the regulator can be programmed via an

external resistor divider that is used to scale the output voltage

relative to the reference voltage. The reference voltage and the

non-inverting input to the error amplifier are not internally

connected, therefore, for standalone applications the REF pin

must be tied to the NI pin (see Figure 41). The REF pin should be

bypassed to AGND with a 220nF ceramic capacitor to mitigate

SEE. It should be noted that no current (sourcing or sinking) is

available from the REF pin.

TABLE 1. LOGIC STATE COMPARISON

SEL2

SEL1

LOAD CAPABILITY

STATE

ACTIVE LXx PINS

(T = +125°C)

J

0

1

0

1

0

1

All

5, 6, 7, 8

5, 6

6A

2.4A

1.2A

N/A

None

The output voltage programming resistor, R , will depend on the

4

value chosen for the feedback resistor R and the desired output

voltage of the regulator. The value for the feedback resistor is

typically between 5kΩ and 25kΩ.

1

With both SEL pins in a logic high state, the ISL70003SEH is in a

low power sleep mode where all outputs are tri-stated. Once the

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ISL70003SEH

logic activates the power blocks, the regulator ramps the output

voltage to its set value within a soft-start interval, however, the

device no longer goes through the preinitialization phase.

Transitions between the number of active LXx pins through the

use of SEL1 and SEL2 should not be done while the part is

operating. On the fly transitions will cause glitches on the output

voltage which may exceed transient requirements. It is

recommended to place the ISL70003SEH in standby mode, by

pulling SEL1 and SEL2 HIGH, and then change the number of

active LXx pins.

VIMON VOLTAGE

200mV/DIV

INDUCTOR

CURRENT

2A/DIV

The overcurrent trip point scales depending on the number of

active power blocks. Equation 10 may be used to determine the

value of R

and R

when less than 10 power blocks

OCSETA

OCSETB

TIME (5µs/DIV)

are active:

FIGURE 42. IMON RESPONSE TO 6A LOAD STEP

3602.4  N

----------------------------

R

=

(EQ. 10)

OCSETA B

I

OCP

Where N is the number of active phases.

VIMON VOLTAGE

IMON Current Sense Output

200mV/DIV

The ISL70003SEH provides a current monitor function through

IMON. Current monitoring informs designers if down steam loads

are operating as expected. It is also useful in the prototype and

debug phase of the design and during normal operation to

measure the overall performance of a system. The IMON pin

outputs a high speed analog current source that is proportional

to the sensed peak current through the ISL70003SEH. In typical

INDUCTOR

CURRENT

2A/DIV

applications, a resistor R

convert the sensed current to voltage, V

IMON

is connected to the IMON pin to

, which is

proportional to the peak current, as shown in Equation 11:

IMON

TIME (5µs/DIV)

FIGURE 43. IMON RESPONSE TO 6A LOAD RELEASE

I

 R

IMON

N

–6

SAMPLE

--------------------------------------------------



V

= 100  10

(EQ. 11)

IMON

It is important to note that if the on time of the lower NMOS FET

is shorter than the IMON current sense time (300ns max), the

IMON output is tri-stated after 4 consecutive failed sense

occurrences.

where V

is the voltage at the IMON pin, R

IMON

is the resistor

is the current through

IMON

between the IMON pin and AGND, I

SAMPLE

the converter at the time IMON samples the current, and N is the

number of active power blocks. I

Equation 12.

may be calculated from

SAMPLE

Diode Emulation

Diode Emulation (DE) allows for higher converter efficiency under

light load situations. In DE mode, the low-side MOSFET conducts

when the current is flowing from source to drain and does not

allow reverse current, emulating a diode. As shown in Figure 44,

when the LGATE signal is HIGH, the low-side MOSFET carries

current, creating negative voltage on the phase node due to the

voltage drop across the ON-resistance. When the DE pin is pulled

HIGH, the ISL70003SEH will be in diode emulation mode and

detect the zero current crossing of the inductor current and turn

off the lower MOSFET to prevent the inductor current from

reversing direction and creating unnecessary power loss. This

ensures that Discontinuous Conduction Mode (DCM) is achieved.

Since diode emulation prevents the low-side MOSFET from

sinking current, no negative spike at the output is generated

during pre-biased startup when DE mode is active.

t

 f

I

2

SAMPLE

SW









-----

-----------------------------------------

I

= I

+

LOAD

–

I 

(EQ. 12)

SAMPLE

1 – D

Where t

is the time it takes the IMON circuitry to sample

SAMPLE

the current (300ns, max.), I

is the load current and ΔI is the

LOAD

inductor peak-to-peak ripple current as calculated in Equation 7.

A small capacitor should be placed between the IMON pin and

AGND to reduce the noise impact and mitigate single event

transients. If this pin is not used, it is best connected to VREFA. It

is also acceptable to tie to GND through a resistor.

Figures 42 and 43 show the response of the IMON current

monitor due to a load step with a R

ceramic capacitor in parallel.

= 10kΩ and 100pF

IMON

After a significantly fast load release transient, diode emulation

will not allow the converter to bring the output voltage back down

following the hump created by the inductor energy dump into the

output capacitor bank. The ISL70003SEH overcomes this issue

by monitoring the output of the error amplifier and allowing the

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ISL70003SEH

low-side MOSFET to turn on and sink the necessary current

DDR Configuration

needed to properly regulate the output voltage. The same

mechanism allows the converter to properly regulate the output

voltage when starting into a prebiased condition where the

prebias level is greater than the desired output voltage.

V

DDQ

R

ISL70003SEH 1/2

V

IN

T1

ERROR

PVIN

x

FB

NI

AMPLIFIER

-

R

B1

L

O

V

LX

DDQ

+

x

LXx

C

O1

V

DDQ

REF

PGND

x

V

UGATE

LGATE

REF

R

T1

B1

ISL70003SEH 2/2

ERROR

V

IN

I

L

V

TT

PVIN

NI

x

AMPLIFIER

+

R

T2

FIGURE 44. DIODE EMULATION

FB

L

O

-

V

TT

LX

x

BUFFER

AMPLIFIER

+

R

The DE pin is not intended to actively change states while the

regulator is operating. If any part of the inductor current is below

zero and the DE pin changes state there will be a glitch on the

output voltage. However, if the state of the DE pin changes state

when the inductor current is positive, no change in the operation

of the regulator will be seen.

B2

B

C

+

O2

PGND

x

-

B

V

DDQ

-

R

OUTB

V

REF

C

R

O3

DDR Application

High through put Double Data Rate (DDR) memory ICs are

replacing traditional memory ICs in space applications. A novel

feature associated with this type of memory are the referencing

and data bus termination techniques. These techniques employ

FIGURE 45. SIMPLIFIED DDR APPLICATION SCHEMATIC

In the DDR application presented in Figure 45, an independent

architecture is implemented to generate the voltages needed for

a reference voltage, V , that tracks the center point of V

REF DDQ

DDR memory applications. Consequently, both V

and V are

DDQ

TT

and V voltages, and an additional V power source where all

SS TT

derived independently from the main power source. The first

regulator supplies the 2.5V for the V voltage. The output

terminating resistors are connected. Despite the additional

power source, the overall memory power consumption is reduced

compared to traditional termination.

DDQ

voltage is set by external dividers R and R . The second

T1

regulator generates the V rail typically = V

B1

DDQ

/2. The resistor

TT

divider network R and R are used to set the output voltage to

The added power source has a cluster of requirements that

should be observed and considered. Due to the reduced

differential thresholds of DDR memory, the termination power

T2 B2

1.25V. The V

DDQ

rail has an additional voltage divider network

consisting of R and R , the midpoint is connected to the

T1 B1

noninverting input pin of the V regulator’s error amplifier (NI),

TT

supply voltage, V , closely tracks V

/2 voltage.

TT

DDQ

effectively providing a tracking function for the V voltage.

TT

Another very important feature of the termination power supply

is the capability to operate at equal efficiency in sourcing and

The noninverting input of the buffer amplifier is connected to the

center point of the external R/R divider from the VDDQ output.

The output of the buffer is tied back to the inverting input for

unity gain configuration. The buffer output voltage serves as a

1.25V reference (VREF) for the DDR memory chips. Sourcing

capability of the buffer amplifier is 10mA typical (20mA max)

and needs a minimum of 1µF load capacitance for stability.

sinking modes. The V supply regulates the output voltage with

TT

the same degree of precision when current is flowing from the

supply to the load, and when the current is diverted back from

the load into the power supply.

The ISL70003SEH regulator possesses several important

enhancements that allow reconfiguration for DDR memory

applications. Two ISL70003SEH ICs will provide all three voltages

required in a DDR memory compliant system.

Diode emulation mode of operation must be disabled on the V

TT

regulator to allow sinking capability. In the event both channels

are enabled simultaneously, the soft-start capacitor on the VDDQ

regulator should be two to three times larger than the soft-start

capacitor on the V regulator. This allows the VDDQ regulator

TT

voltage to be the lowest input into the error amplifier of the V

regulator and dominate the soft-start ramp. However, if the V

TT

regulator is enabled later than the VDDQ, the soft-start capacitor

can be any value based on design goals.

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ISL70003SEH

Each regulator has its own fault protections and must be

General Design Guide

individually configured. All the sink current on the V regulator is

TT

provided by the VDDQ rail, the overcurrent protection on the

This design guide is intended to provide a high-level explanation

of the steps necessary to design the power stage and feedback

compensation network of a single phase power converter. It is

assumed that the reader is familiar with many of the basic skills

and techniques in switch mode power supply design. In addition

to this guide, Intersil provides an evaluation board that includes

schematic, bills of materials and board layout.

VDDQ rail will limit the amount of current that the V rail will

TT

sink.

When sinking current or at a no load condition, the inductor

valley current is negative, see Figure 28. During any time when

the inductor valley current is negative and the ISL70003 is

exposed to a heavy ion environment the abs max PVIN voltage

must be ≤13.7V, see Note 5 on page 9.

Output Inductor Selection

SEL1 and SEL2 may be tied together and used to place the V

TT

regulator in sleep mode, common to DDR applications. The

outputs will be tri-stated, however the buffer amplifier is still

The output inductor is selected to minimize the converter’s

response time to a load transient and meet steady state output

voltage ripple requirements. The inductor value determines the

converter’s inductor ripple current and the output voltage ripple

is a function of the inductor ripple current. The output voltage

ripple and the inductor ripple current are approximated by using

Equation 13:

active and the VREF voltage will be present even if the V is in

TT

sleep mode. When SEL1 and SEL2 are asserted low, the V

TT

regulator will ramp up the voltage. The ramp is controlled and

timing is based on soft-start capacitor value.

Refer to Figure 5 on page 8 for complete DDR power solution

typical application circuit schematic.

V

– V

V

OUT

V

IN

f

OUT

------------------------------------------- ---------------

I =



V

= I  ESR

OUT

 L

SW

(EQ. 13)

Derating Current Capability

Increasing the value of inductance reduces the ripple current and

output voltage ripple. However, the large inductance values

reduce the converter’s response time to a load transient.

Most space programs issue specific derating guidelines for parts,

but these guidelines take the pedigree of the part into account.

For instance, a device built to MIL-PRF-38535, such as the

ISL70003SEH, is already heavily derated from a current density

standpoint. However, a mil-temp or commercial IC that is

up-screened for use in space applications may need additional

current derating to ensure reliable operation because it was not

built to the same standards as the ISL70003SEH.

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. The response time is the time required to slew the

inductor current from an initial current value to the transient

current level. During this interval the difference between the

inductor current and the transient current level must be

supplied by the output capacitor. Minimizing the response time

can minimize the output capacitance required.

The response time to a transient is different for the application of

load and the removal of load. Equation 14, gives the approximate

response time interval for application and removal of a transient

load.

L x I

TRAN

L x I

TRAN

OUT

t

=

t

=

FALL

RISE

V

- V

IN OUT

V

(EQ. 14)

Where I

is the transient load current step, t

is the

TRAN

RISE

response time to the application of load, and t

FALL

response time to the removal of load. The worst case response

time can be either at the application or removal of load. Be sure

to check both Equations 13 and 14 at the minimum and

maximum output levels for the worst case response time.

FIGURE 46. CURRENT vs TEMPERATURE

Figure 46 shows the maximum average output current of the

ISL70003SEH with respect to junction temperature. These plots

take into account the worst-case current share mismatch in the

power blocks and the current density requirement of

Output Capacitor Selection

An output capacitor is required to filter the inductor current and

supply the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current. The

load transient requirements are a function of the slew rate (di/dt)

and the magnitude of the transient load current. These

requirements are generally met with a mix of capacitors and

careful layout.

5

2

MIL-PRF-38535 (< 2 x 10 A/cm ). The plot clearly shows that

the ISL70003SEH can handle 7A at +150°C from a worst-case

current density standpoint, but the part is rated to 3A. Therefore,

no further current derating of the ISL70003SEH is needed.

High-frequency capacitors initially supply the transient and slow

the current load rate seen by the bulk capacitors. The bulk filter

FN8604.5

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ISL70003SEH

capacitor values are generally determined by the ESR (Effective

Series Resistance) and voltage rating requirements rather than

actual capacitance requirements.

In a typical converter design, the ESR of the output capacitor

bank dominates the transient response. The ESR and the ESL are

typically the major contributing factors in determining the output

capacitance. The number of output capacitors can be

determined by using Equation 16, which relates the ESR and ESL

of the capacitors to the transient load step and the voltage limit

(ΔVo).

High-frequency decoupling capacitors should be placed as close

to the power pins of the load as physically possible. Be careful

not to add inductance in the circuit board wiring that could

cancel the usefulness of these low inductance components.

The shape of the output voltage waveform during a load transient

that represents the worst case loading conditions will ultimately

determine the number of output capacitors and their type. When

this load transient is applied to the converter, most of the energy

required by the load is initially delivered from the output

capacitors. This is due to the finite amount of time required for

the inductor current to slew up to the level of the output current

required by the load. This phenomenon results in a temporary dip

in the output voltage. At the very edge of the transient, the

Equivalent Series Inductance (ESL) of each capacitor induces a

spike that adds on top of the existing voltage drop due to the

Equivalent Series Resistance (ESR).

ESL ² dI

tran

------------------------------------------- + E S R ² I

(EQ. 16)

tran

dt

Number of Capacitors = --------------------------------------------------------------------------------------------

V

o

If ΔV

SAG

and/or ΔV are found to be too large for the output

HUMP

voltage limits, then the amount of capacitance may need to be

increased. In this situation, a trade-off between output inductance

and output capacitance may be necessary.

The ESL of the capacitors, which is an important parameter in

the previous equations, is not usually listed in databooks.

Practically, it can be approximated using Equation 17 if an

Impedance vs Frequency curve is given for a specific capacitor:

After the initial spike, attributable to the ESR and ESL of the

capacitors, the output voltage experiences sag. This sag is a

direct consequence of the amount of capacitance on the output.

1

ESL = -----------------------------------------------------

2

(EQ. 17)

C2 ²  ² f



res

Where: f is the frequency where the lowest impedance is

res

achieved (resonant frequency).

ΔV

HUMP

The ESL of the capacitors becomes a concern when designing

circuits that supply power to loads with high rates of change in

the current.

V

OUT

ΔV

ESR

ΔV

SAG

Input Capacitor Selection

ESL

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic capacitors for

high-frequency decoupling and bulk capacitors to supply the

current needed each time the upper MOSFET turns on. Place the

small ceramic capacitors physically close to the MOSFETs and

between the drain of the upper MOSFET and the source of the

lower MOSFET.

I

OUT

I

TRAN

FIGURE 47. TYPICAL TRANSIENT RESPONSE

The important parameters for the bulk input capacitance are the

voltage rating and the RMS current rating. For reliable operation,

select bulk capacitors with voltage and current ratings above the

maximum input voltage and largest RMS current required by the

circuit. Their voltage rating should be at least 1.25x greater than

the maximum input voltage, while a voltage rating of 1.5x is a

conservative guideline. For most cases, the RMS current rating

requirement for the input capacitor of a buck regulator is

approximately 1/2 the DC load current.

During the removal of the same output load, the energy stored in

the inductor is dumped into the output capacitors. This energy

dumping creates a temporary hump in the output voltage. This

hump, as with the sag, can be attributed to the total amount of

capacitance on the output. Figure 47 shows a typical response to

a load transient.

The amplitudes of the different types of voltage excursions can

be approximated using Equation 15.

dI

The maximum RMS current through the input capacitors may be

closely approximated using Equation 18:

tran

V

= ESR ² I

V

= ESL ² ---------------------

ESR

tran

ESL

dt

2

L

² I

V_OUT

---------------

V_IN



 

 

 

V

_IN– V_OUTV_OUT

OUT tran

2

1

-----^O-----^U----^T- x I

x 1 –

+ -------- x ----------------------------------- x---------------







V

= ----------------------------------------------------------------------------



SAG

OUT



C

² V – V



OUT

MAX

V_IN

12 Lxf

V_IN

OUT

IN



OSC

(EQ. 18)

2

L

² I

OUT tran

For surface mount designs, solid tantalum capacitors can be

used, but caution must be exercised with regard to the capacitor

surge current rating. These capacitors must be capable of

handling the surge current at power-up. Some capacitor series

available from reputable manufacturers are surge current tested.

= -------------------------------------------------

HUMP

C

² V

OUT

(EQ. 15)

OUT

Where I

tran

Output Capacitance

= Output Load Current Transient and C

= Total

OUT

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ISL70003SEH

Feedback Compensation

Figure 48 highlights the voltage-mode control loop for a

synchronous rectified buck converter. The output voltage (V

100

f

P2

Z1 Z2

P1

80

60

40

20

0

)

OUT

OPEN LOOP

ERROR AMP GAIN

is regulated to the reference voltage level. The error amplifier

output (V ) is compared with the oscillator (OSC) triangular

EA

wave to provide a Pulse-Width Modulated (PWM) wave with an

20LOG

(R /R )

2

1

20LOG

(V /DV

amplitude of V at the PHASE node. The PWM wave is smoothed

IN

)

OSC

IN

by the output filter (L and C ).

O

COMPENSATION

GAIN

CLOSED LOOP

GAIN

MODULATOR

GAIN

-20

-40

-60

V

IN

DRIVER

OSC

f

PWM

LC

f

ESR

100k

FREQUENCY (Hz)

L

O

COMPARATOR

V

OUT

10

100

1k

10k

1M

10M

-

PHASE

+

C

ΔV

OSC

O

FIGURE 49. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

ESR

(PARASITIC)

Equation 20 relates the compensation network’s poles, zeros

and gain to the components (R , R , R , C , C and C ) in

Z

FB

V

1

2

3

1

2

3

EA

Figure 48. Use these guidelines for locating the poles and zeros

of the compensation network:

Z

-

IN

+

REFERENCE

ERROR

AMP

1. Pick Gain (R /R ) for desired converter bandwidth.

2

1

st

2. Place 1 Zero Below Filter’s Double Pole (~75% F ).

LC

DETAILED COMPENSATION COMPONENTS

nd

3. Place 2 Zero at Filter’s Double Pole.

Z

FB

V

OUT

C

st

1

Z

4. Place 1 Pole at the ESR Zero.

IN

nd

C

5. Place 2 Pole at Half the Switching Frequency.

R

3

2

3

2

6. Check Gain against Error Amplifier’s Open-Loop Gain.

7. Estimate Phase Margin - Repeat if Necessary.

R

1

VERR

FB

-

Compensation Break Frequency Equations

+

R

4

1

f

= ----------------------------------------------

f

= -------------------------------------------------------------------------

Z1

P1

REFERENCE

R

2 x R x C

C

x C

2













1

2

+ C

2

---------------------------

2 x R

x

2

C

1









1

V

= 0.6 ¥ 1 + -------

1



OUT

f

= ------------------------------------------------------------------------

2 x R + R  x C

f

= ----------------------------------------------

2 x R x C

R



Z2

P2

4

1

3

FIGURE 48. VOLTAGE-MODE BUCK CONVERTER COMPENSATION

(EQ. 20)

Figure 49 shows an asymptotic plot of the DC/DC converter’s

gain vs frequency. The actual Modulator Gain has a high gain

peak due to the high Q factor of the output filter and is not shown

in Figure 49. Using the guidelines provided should give a

Compensation Gain similar to the curve plotted. The open loop

error amplifier gain bounds the compensation gain. Check the

The modulator transfer function is the small-signal transfer

function of V /V . This function is dominated by a DC Gain and

OUT EA

the output filter (L and C ), with a double pole break frequency at

O

f

and a zero at f

. The DC gain of the modulator is simply the

LC

ESR

input voltage (V ) divided by the peak-to-peak oscillator voltage

IN

ΔV

OSC

. The ISL70003SEH incorporates a feed-forward loop that

compensation gain at f with the capabilities of the error

P2

accounts for changes in the input voltage. This maintains a

constant modulator gain of 5, typical.

amplifier. The Closed Loop Gain is constructed on the graph of

Figure 49 by adding the Modulator Gain (in dB) to the

Compensation Gain (in dB). This is equivalent to multiplying the

modulator transfer function to the compensation transfer

function and plotting the gain. The compensation gain uses

external impedance networks Z and Z to provide a stable,

high bandwidth (BW) overall loop. A stable control loop has a

gain crossing with -20dB/decade slope and a phase margin

greater than +45°. Include worst case component variations

when determining phase margin. A more detailed explanation of

voltage mode control of a buck regulator can be found in Tech

Brief TB417, entitled “Designing Stable Compensation Networks

for Single Phase Voltage Mode Buck Regulators”.

Modulator Break Frequency Equations

1

f

= -----------------------------------------------------

f

= -----------------------------------------------------

LC

ESR

2 x ESR x C

FB

IN

2 x

L

x C

O

(EQ. 19)

The compensation network consists of the error amplifier and

the impedance networks Z and Z . The goal of the

IN

FB

compensation network is to provide a closed loop transfer

function with the highest 0dB crossing frequency (f ) and

0dB

adequate phase margin. Phase margin is the difference between

the closed loop phase at f

and 180°.

0dB

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ISL70003SEH

LX Connection

PCB Design

Use a small island of copper to connect the LXx pins of the IC to

the output inductor on layers 1 and 4. Void the copper on layers 2

and 3 adjacent to the island to minimize capacitive coupling to

the power and ground planes. Place most of the island on layer 4

to minimize the amount of copper that must be voided from the

ground plane (layer 2).

PCB design is critical to high-frequency switching regulator

performance. Careful component placement and trace routing

are necessary to reduce voltage spikes and minimize

undesirable voltage drops. Selection of a suitable thermal

interface material is also required for optimum heat dissipation

and to provide lead strain relief.

Keep all other signal traces as short as possible.

PCB Plane Allocation

A minimum of four layers of two ounce copper are

Thermal Management for Ceramic Package

recommended. Layer 2 should be a dedicated ground plane with

all critical component ground connections made with vias to this

layer. Layer 3 should be a dedicated power plane split between

the input and output power rails. Layers 1 and 4 should be used

primarily for signals, but can also provide additional power and

ground islands as required.

For optimum thermal performance, place a pattern of vias on the

top layer of the PCB directly underneath the IC. Connect the vias

to the plane which serves as a heatsink. To ensure good thermal

contact, thermal interface material such as a Sil-Pad or thermally

conductive epoxy should be used to fill the gap between the vias

and the bottom of the IC of the ceramic package.

PCB Component Placement

Lead Strain Relief

Components should be placed as close as possible to the IC to

minimize stray inductance and resistance. Prioritize the

placement of bypass capacitors on the pins of the IC in the order

shown: REF, SS, AVDD, DVDD, PVINx (high-frequency capacitors),

EN, PGOOD, PVINx (bulk capacitors).

The package leads protrude from the bottom of the package and

the leads need forming to provide strain relief. On the ceramic

bottom package R64.A, the Sil-pad or epoxy maybe be used to fill

the gap left between the PCB board and the bottom of the

package when lead forming is completed. On the heatsink option

of the package R64.C, the lead forming should be made so that

the bottom of the heatsink and the formed leads are flush.

Locate the output voltage resistive divider as close as possible to

the FB pin of the IC. The top leg of the divider should connect

directly to the output of the inductor via a kelvin trace and the

bottom leg of the divider should connect directly to AGND. This

AGND connection should also be a kelvin trace connected to the

closest ground to the inductor output. The junction of the

resistive divider should connect directly to the FB pin.

Heatsink Mounting Guidelines

The R64.C package option has a heatsink mounted on the

underside of the package. The following JESD-51x series

guidelines may be used to mount the package:

1. Place a thermal land on the PCB under the heatsink.

If desired place a Schottky clamp diode as close as possible to

the LXx and PGNDx pins of the IC. A small series R-C snubber

connected from the LXx pins to the PGNDx pins may be used to

damp high-frequency ringing on the LXx pins if desired.

2. The land should be approximately the same size as to 1mm

larger than the 10.16x10.16mm heatsink.

3. Place an array of thermal vias below the thermal land.

- Via array size: ~9x9 = 81 thermal vias.

L

V

OUT

- Via diameter: ~0.3mm drill diameter with plated copper on

the inside of each via.

LXx

3A

C

OUT

R

C

S

- Via pitch: ~1.2mm.

S

- Vias should drop to and contact as much metal area as

feasible to provide the best thermal path.

R

T

PGNDx

FB

ERROR

AMPLIFIER

Heatsink Electrical Potential

-

The heatsink is connected to pin 50 within the package; thus the

PCB design and potential applied to pin 50 will therefore define

the heatsink potential.

R

NI

B

+

REF

Heatsink Mounting Materials

C

REF

In the case of electrically conductive mounting methods

(conductive epoxy, solder, etc) the thermal land, vias and

connected plane(s) below must be the same potential as pin 50.

FIGURE 50. SCHOTTKY DIODE AND R-C SNUBBER

In the case of electrically non-conductive mounting methods

(non-conductive epoxy), the heatsink and pin 50 could have

different electrical potential than the thermal land, vias and

connected plane(s) below.

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ISL70003SEH

TOP METALLIZATION

Package Characteristics

Weight of Packaged Device

Type: AlCu (99.5%/0.5%)

Thickness: 2.7µm ±0.4µm

1.43 Grams (typical) - R64.A Package

2.65 Grams (typical) - R64.C Package

BACKSIDE FINISH

Silicon

Lid Characteristics

PROCESS

Finish: Gold

Lid Potential: PGND

0.6µM BiCMOS Junction Isolated

ASSEMBLY RELATED INFORMATION

Die Characteristics

Substrate and Lid Potential

Die Dimensions

PGND

8300µm x 8300µm (327 mils x 327 mils)

Thickness: 300µm ±25.4µm (12 mils ±1 mil)

ADDITIONAL INFORMATION

Worst Case Current Density

Interface Materials

5

2

<2 x 10 A/cm

GLASSIVATION

Transistor Count

Type: Silicon Oxide and Silicon Nitride

Thickness: 0.3µm ±0.03µm to 1.2µm ±0.12µm

26,144

Metallization Mask Layout

ISL70003SEH

DE

PVIN2

LX2

PVIN9

LX9

PGND2

PGND9

PGND1

LX1

PGND10

LX10

PVIN1

PVIN10

IMON

SGND

SEL2

SEL1

PGOOD

OCSETA

OCSETB

BUFIN+

BUFIN-

BUFOUT

VREF

GND

ORIGIN

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ISL70003SEH

TABLE 2. LAYOUT X-Y COORDINATES

X

(µm)

Y

dX

(µm)

dY

(µm)

BOND WIRES

SIZE (0.001”)

PAD NAME

PAD NUMBER

(µm)

NI

1

0

135

254

135

254

135

254

135

254

135

254

135

254

1.5

3

FB

2

452

0

Verr

3

929

0

POR_VIN

VrefA

VDDA

GNDA

GNDD

Vref OUTs

VDDD

VrefD

ENABLE

RtCt

4

1371

1854

2577

3104

3589

4035

4713

5420

5846

6274

6579

6976

7201

7140

6350

5387

6350

7140

7220

7140

6655

6247

5801

5393

4908

4497

4011

0

5

58

6

60

3

7

60

3

8

60

3

9

60

3

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

60

3

60

3

0

1.5

3

0

F300

0

Sync

0

SS Cap

TDI

51

345

639

934

1228

1522

1902

2275

2569

3285

3771

4179

4625

5033

5518

6303

7578

6788

5825

6788

7578

6788

Zap

TDO

TST Trim

TCLK

Pgood

SEL1

SEL2

PVin10

LX10

3

PGND10

PGND9

LX9

3

PVin9

Deon

3

1.5

3

PVin8

LX8

3

PGND8

PGND7

LX7

3

PVin7

PVin6

LX6

3

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ISL70003SEH

TABLE 2. LAYOUT X-Y COORDINATES (Continued)

X

(µm)

Y

dX

(µm)

dY

(µm)

BOND WIRES

SIZE (0.001”)

PAD NAME

PAD NUMBER

40

(µm)

PGND6

PGND5

LX5

3603

3157

2749

2264

1853

1367

960

5825

6788

7578

6788

5825

254

3

41

42

43

44

45

46

PVin5

PVin4

LX4

PGND4

PGND3

LX3

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

514

106

5825

6788

7578

5518

5033

4625

4179

3771

3285

2561

2201

1841

1481

1121

761

254

135

254

135

3

PVin3

PVIN2

LX2

-379

411

3

PGND2

PGND1

LX1

1374

411

3

PVin1

Imon

-379

-438

3

1.5

sgnd

OCSETA

OCSETB

Buf IN +

Buf IN -

Buf OUT

Vref

401

41

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

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ISL70003SEH

Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.

Please go to the web to make sure that you have the latest revision.

DATE

REVISION

FN8604.5

CHANGE

May 12, 2016

Updated Ordering information table on page 3.

Updated Note 1.

Removed Pb-Free Reflow reference under “Thermal Information” on page 9 as it is not applicable to hermetic

packages.

Corrected Equation 20 on page 25.

February 6, 2015

FN8604.4

On page 6, added text in the FB, PVINx, SEL1, SEL2 and IMON pin descriptions.

On page 7 corrected pin names in Figure 4.

On page 8 corrected pin names in Figure 5.

On page 9, updated Note 5 by adding "with any negative inductor current".

On page 23, added the fifth paragraph under the DDR Configuration section.

On page 26, added text to the second paragraph under “PCB Component Placement”.

March 7, 2014

March 3, 2014

FN8604.3

FN8604.2

FN8604.1

Added new feedback link, updated Related Literature and updated About Intersil.

Cosmetic edits throughout file.

Initial Release.

December 20, 2013

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products

address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product

information page found at www.intersil.com.

You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.

Reliability reports are also available from our website at www.intersil.com/support.

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ISL70003SEH

Package Outline Drawing

R64.A

64 CERAMIC QUAD FLATPACK PACKAGE (CQFP)

Rev 5, 10/13

1.118 (28.40)

1.080 (27.43)

0.567 (14.40)

0.547 (13.90)

0.290 (7.37)

0.255 (6.48)

64

49

0.025 (0.635) BSC

1

PIN 1

INDEX AREA

48

0.567 (14.40)

0.547 (13.90)

1.118 (28.40)

1.080 (27.43)

0.010 (0.25)

0.006 (0.15)

33

16

17

32

SEE DETAIL "A"

TOP VIEW

0.105 (2.67)

0.075 (1.91)

0.008 (0.20)

REF

0.0075 (0.188)

0.005 (0.125)

SIDE VIEW

DETAIL “A”

0.100 (2.537)

0.085 (2.157)

0.380 (9.655)

0.370 (9.395)

PIN 1

INDEX AREA

1

64

NOTE:

1. All dimensions are in inches (millimeters).

BOTTOM VIEW

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ISL70003SEH

Package Outline Drawing

R64.C

64 CERAMIC QUAD FLATPACK PACKAGE (CQFP) WITH BOTTOM HEATSINK

Rev 1, 10/13

1.118 (28.40)

1.080 (27.43)

0.567 (14.40)

0.547 (13.90)

0.290 (7.37)

0.255 (6.48)

64

49

0.025 (0.635) BSC

1

PIN 1

INDEX AREA

48

0.567 (14.40)

0.547 (13.90)

1.118 (28.40)

1.080 (27.43)

0.010 (0.25)

0.006 (0.15)

33

16

17

32

SEE DETAIL "A"

TOP VIEW

0.135 (3.43)

0.111 (2.82)

0.0075 (0.188)

0.005 (0.125)

SIDE VIEW

HEATSINK

0.405 (10.29)

0.395 (10.03)

0.100 (2.537)

0.085 (2.157)

0.380 (9.655)

0.370 (9.395)

0.008 (0.20)

REF

0.048 (1.22)

REF

0.026 (0.66) MIN.

DETAIL "A"

2

HEATSINK

0.405 (10.29)

0.395 (10.03)

PIN 1

INDEX AREA

1

64

NOTES:

1. All dimensions are in inches (millimeters)

2. Dimension shall be measured at point of exit

(beyond the meniscus) of the lead from the body.

BOTTOM VIEW

FN8604.5

May 12, 2016

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32


型号：	ISL70003SEHX
厂家：	Intersil
描述：	Acceptance tested to 50krad
文件：	总32页 (文件大小：1934K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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