ISL71831SEHVF [INTERSIL]
Radiation Hardened 5V 32-Channel Analog Multiplexer;
| 型号： | ISL71831SEHVF |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened 5V 32-Channel Analog Multiplexer |
| 文件： | 总20页 (文件大小：1045K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
Radiation Tolerant 5V 16-Channel Analog Multiplexer
ISL71830SEH
Features
The ISL71830SEH is a radiation tolerant, 16-channel
multiplexer that is fabricated using Intersil’s proprietary P6-SOI
process technology to provide excellent latch-up performance.
It operates with a single supply range from 3V to 5.5V and has
a 4-bit address line plus an enable that can be driven with
adjustable logic thresholds to conveniently select one of 16
available channels. An inactive channel is separated from the
active channel by a high impedance, which inhibits any
interaction between them.
• DLA SMD# 5962-15247
• Fabricated using P6 SOI process technology
• Rail-to-rail operation
• No latch-up
• Low rDS(ON). . . . . . . . . . . . . . . . . . . . . . . . . .<120Ω (maximum)
• Single supply operation . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V
- Adjustable logic threshold control
The ISL71830SEH’s low rDS(ON) allows for improved signal
integrity and reduced power losses. The ISL71830SEH is also
designed for cold sparing, making it excellent for redundancy
in high reliability applications. It is designed to provide a high
impedance to the analog source in a powered off condition,
making it easy to add additional backup devices without
incurring extra power dissipation. The ISL71830SEH also has
analog overvoltage protection on the input that disables the
switch during an overvoltage event to protect upstream and
downstream devices.
• Cold sparing capable . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 7V
• Analog overvoltage range . . . . . . . . . . . . . . . . . . . . -0.4V to 7V
• Switch input off leakage . . . . . . . . . . . . . . . . . . . . . . . . . 120nA
• Transition times (tAHL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70ns
• Internally grounded metal lid
• Break-before-make switching
• ESD protection ≥5kV (HBM)
• Operating temperature range. . . . . . . . . . . .-55°C to +125°C
The ISL71830SEH is available in a 28 Ld CDFP and operates
across the extended temperature range of -55°C to +125°C.
• Radiation tolerance
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . . .75krad(Si)
- SEL/SEB LETTH (V+ = 6.5V). . . . . . . . . . . . . 60MeV•cm2/mg
A 32-channel version is also available offered in a 48 Ld CQFP.
Refer to the ISL71831SEH datasheet for more information. For
a list of differences, refer to Table 1 on page 2.
• All lots are assurance tested to 75krad (0.01rad(Si)/s)
wafer-by-wafer.
Related Literature
• For a full list of related documents, visit our website
- ISL71830SEH product page
Applications
• Telemetry signal processing
• Harsh environments
• Down-hole drilling
ISL71830SEH
90
IN01
IN02
IN03
80
+125°C
70
+25°C
OUT
ADC
60
50
40
.
.
.
IN16
30
-55°C
20
10
0
4
ADDRESS
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
COMMON-MODE VOLTAGE (V)
EN
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 5V)
November 18, 2016
FN8758.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC. 2015,2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL71830SEH
Ordering Information
SMD ORDERING NUMBER
PART NUMBER
PACKAGE
PKG.
(Note 2)
(Note 1)
TEMP RANGE (°C)
-55 to +125
(RoHS COMPLIANT)
DWG. #
5962L1524701VXC
ISL71830SEHVF
28 Ld CDFP
K28.A
K28.A
N/A
ISL71830SEHF/PROTO
ISL71830SEHVX
-55 to +125
28 Ld CDFP
DIE
5962L1524701V9A
-55 to +125
N/A
ISL71830SEHX/SAMPLE
ISL71830SEHEV1Z
-55 to +125
DIE
N/A
Evaluation Board
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information” table must be used when ordering.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
ISL71830SEH
NUMBER OF CHANNELS
OUTPUT LEAKAGE
60nA
PACKAGE
28 Ld CDFP
48 Ld CQFP
16
32
ISL71831SEH
120nA
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2
ISL71830SEH
Pin Configuration
ISL71830SEH
(28 LD CDFP)
TOP VIEW
+
V
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OUT
NC
IN8
IN7
IN6
IN5
IN4
IN3
IN2
IN1
EN
A0
NC
NC
2
3
IN16
IN15
IN14
IN13
IN12
IN11
IN10
IN9
4
5
6
7
8
9
10
11
12
13
14
GND
VREF
A3
A1
A2
Pin Descriptions
ESD
PIN NAME
OUT
CIRCUIT
PIN NUMBER
DESCRIPTION
2
1
-
28
1
Output for multiplexer.
Positive power supply.
Not electrically connected.
Input for multiplexer.
V+
NC
2, 3, 27
INx
1
4, 5, 6, 7, 8, 9, 10, 11,
19, 20, 21, 22, 23, 24, 25, 26
Ax
EN
1
1
1
-
14, 15, 16, 17
Address lines for multiplexer.
18
13
12
-
Enable control for multiplexer (active low).
Reference voltage used to set logic thresholds.
Ground
VREF
GND
LID
-
Package lid is internally connected to GND (Pin 12).
VDD
PIN #
9V CLAMP
PIN #
9V CLAMP
GND
9V CLAMP
GND
CIRCUIT 1
CIRCUIT 2
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ISL71830SEH
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage (V+ to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Maximum Supply Voltage (V+ to GND) (Note 5) . . . . . . . . . . . . . . . . . . .6.5V
Analog Input Voltage Range (INx). . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 7V
Digital Input Voltage Range (EN, Ax) . . . . . . . . . . . . . . . (GND - 0.4V) to VREF
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
ESD Tolerance
Thermal Resistance (Typical)
28 Ld CDFP (Notes 3, 4) . . . . . . . . . . . . . . .
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
JA (°C/W)
55
JC (°C/W)
8.5
Recommended Operating Conditions
Human Device Model (Tested per MIL-STD-883 TM 3015) . . . . . . . . 5kV
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 250V
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . . 250V
Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 5.5V
V
REF to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. For JC, the “case temp” location is the center of the package underside.
5. Tested in a heavy ion environment at LET = 60MeV•cm2/mg at +125°C.
+
Electrical Specifications, V = 5V GND = 0V, V = 3.3V, V = 3.3V, V = 0V, T = +25°C, unless otherwise noted. Boldface
REF
IH
IL
A
limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 75krad(Si) with exposure at a low dose
rate of <10mrad(Si)/s.
MIN
MAX
PARAMETER
Analog Input Signal Range
Channel On-Resistance
SYMBOL
VIN
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNIT
V
0
-
V+
rDS(ON)
V+ = 4.5V, VIN = 0V to V+
40
-
120
Ω
I
OUT = 1mA
V+ = 4.5V, VIN = 0V, 2.25V, 4.5V
OUT = 1mA
rDS(ON) Match Between Channels
ΔrDS(ON)
-
5
Ω
I
On-Resistance Flatness
Switch Input Off Leakage
rFLAT(ON)
IIN(OFF)
V+ = 4.5V, VIN = 0V to V+
-
-
-
40
30
Ω
V+ = 5.5V, VIN = 5V,
-30
nA
Unused inputs and VOUT = 0.5V
V+ = 5.5V, VIN = 0.5V,
Unused inputs and VOUT = 5V
-30
-
-
30
nA
nA
Switch Input Off Overvoltage Leakage
IIN(OFF-OV)
IIN(POWER-OFF)
IIN(POWER-OFF)
IIN(ON-OV)
V+ = 5.5V, VIN = 7V,
-30
30
Unused inputs and VOUT = 0V,
TA = +25°C, -55°C
TA = +125°C
-30
-30
-20
-
-
-
120
30
nA
nA
nA
Post radiation, +25°C
Switch Input Off Leakage with Supply
Voltage Grounded
VIN = 7V, VOUT = 0V
V+ = VEN = VREF = 0V,
TA = +25°C, -55°C
20
TA = +125°C
-20
-20
-20
-
-
-
50
20
20
nA
nA
nA
Post radiation, +25°C
Switch Input Off Leakage with Supply
Voltage Open
VIN = 7V, VOUT = 0V
V+ = VEN = VREF = Open,
TA = +25°C, -55°C
TA = +125°C
-20
-20
-
-
-
50
20
nA
nA
µA
Post radiation, +25°C
V+ = 5.5V, VIN = 7V, VOUT = OPEN
Switch On Input Leakage with
Overvoltage Applied to the Input
2.75
5.50
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ISL71830SEH
+
Electrical Specifications, V = 5V GND = 0V, V = 3.3V, V = 3.3V, V = 0V, T = +25°C, unless otherwise noted. Boldface
REF
IH
IL
A
limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 75krad(Si) with exposure at a low dose
rate of <10mrad(Si)/s. (Continued)
MIN
MAX
PARAMETER
SYMBOL
IOUT(OFF)
TEST CONDITIONS
V+ = 5.5V, VOUT = 5V,
(Note 6)
TYP
-
(Note 6)
UNIT
nA
Switch Output Off Leakage
-30
30
All inputs = 0.5V,
TA = +25°C, -55°C
TA = +125°C
0
-
-
-
150
30
nA
nA
nA
Post radiation, +25°C
-30
-30
V+ = 5.5V, VOUT = 0.5V,
All inputs = 5V,
30
TA = +25°C, -55°C
TA = +125°C
-60
-30
-30
0
nA
nA
nA
Post radiation, +25°C
-
-
30
30
Switch Output Leakage with Switch
Enabled
IOUT(ON)
V+ = 5.5V, VIN = VOUT = 5V
All unused inputs at 0.5V,
TA = +25°C, -55°C
TA = +125°C
0
-
-
-
150
30
nA
nA
nA
Post radiation, +25°C
-30
-30
V+ = 5.5V, VIN = VOUT = 0.5V
All unused inputs at 5V,
TA = +25°C, -55°C
30
TA = +125°C
-60
-30
1.3
-0.1
-0.1
-
-
-
-
-
-
-
0
nA
nA
V
Post radiation, +25°C
V+ = 5.5V, VREF = 3.3V
V+ = 5.5V, VEN = VA = VREF
V+ = 5.5V, VEN = VA = 0V
V+ = VREF = VEN = 5.5V
30
Logic Input Voltage High/Low
Input Current with VAH, VENH
Input Current with VAL, VENL
Quiescent Supply Current
VIH/L
1.6
0.1
0.1
100
IAH, IENH
IAL, IENL
ISUPPLY
µA
µA
nA
VA = 0V, TA = +25°C, -55°C
TA = +125°C
-
-
-
-
-
-
300
300
200
nA
nA
nA
Post radiation, +25°C
V+ = VREF = VEN = 5.5V
Reference Quiescent Supply Current
IREF
VA = 0V
DYNAMIC
Addressing Transition Time
Break-Before-Make Delay
Enable Turn-On Time
Enable Turn-Off Time
Charge Injection
Off Isolation
tAHL
tBBM
V+ = 4.5V; Figure 3
10
5
-
70
40
40
40
5
ns
ns
ns
ns
pC
dB
dB
V+ = 4.5V; Figure 5
18
tEN(ON)
tEN(OFF)
VCTE
V+ = 4.5V; Figure 4
-
-
V+ = 4.5V; Figure 4
-
-
CL = 100pF, VIN = 0V, Figure 6
VEN = VREF, RL = OPEN, f = 1kHz
-
1.4
VISO
60
73
-
-
-
Crosstalk
VCT
VEN = 0V, f = 1kHz, VP-P = 1V,
RL = OPEN
-
Input Capacitance
Output Capacitance
CIN(OFF)
f = 1MHz
f = 1MHz
-
-
-
-
5
pF
pF
COUT(OFF)
25
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ISL71830SEH
+
Electrical Specifications, V = 3.3V
V
= 3.3V, V = 3.3V, V = 0V, T = +25°C, unless otherwise noted. Boldface limits
REF IH IL A
apply across the operating temperature range, -55°C to +125°C.; over a total ionizing dose of 75krad(Si) with exposure at a low dose rate of
<10mrad(Si)/s.
MIN
MAX
PARAMETER
Analog Input Signal Range
Channel On-Resistance
SYMBOL
VIN
CONDITIONS
(Note 6)
TYP
-
(Note 6)
UNIT
V
0
V+
rDS(ON)
V+ = 3V, VIN = 0V to V+
25
70
200
Ω
I
OUT = 1mA
V+ = 3V, VIN = 0.5V, 2.5V
OUT = 1mA
V+ = 3V
IN = 0V to V+
V+ = 3.6V
IN = 3.1V,
rDS(ON) Match Between Channels
On-Resistance Flatness
ΔrDS(ON)
rFLAT(ON)
IIN(OFF)
-
-
-
-
-
5
Ω
Ω
I
50
30
V
Switch Input Off Leakage
-30
nA
V
Unused inputs and VOUT = 0.5V
V+ = 3.6V
-30
-
-
30
nA
nA
V
IN = 0.5V,
Unused inputs and VOUT = 3.1V
Switch Input Off Overvoltage Leakage
IIN(OFF-OV)
V+ = 3.6V
-30
30
V
IN = 7V,
Unused inputs and VOUT = 0V,
TA = +25°C, -55°C
TA = +125°C
-30
-30
1.8
-
-
-
100
30
nA
Post radiation, +25°C
V+ = 3.6V, VIN = 7V, VOUT = OPEN
Switch On Input Leakage with
Overvoltage Applied to the Input
IIN(ON-OV)
IOUT(OFF)
3.6
µA
nA
Switch Output Off Leakage
V+ = 3.6V, VOUT = 3.1V,
All inputs = 0.5V,
-30
-
30
TA = +25°C, -55°C
TA = +125°C
0
-
-
-
60
30
30
nA
nA
nA
Post radiation, +25°C
-30
-30
V+ = 3.6V, VOUT = 0.5V,
All inputs = 3.1V,
TA = +25°C, -55°C
TA = +125°C
0
-
-
-
30
30
30
nA
nA
nA
Post radiation, +25°C
-30
-30
Switch Output Leakage with Switch
Enabled
IOUT(ON)
V+ = 3.6V, VIN = VOUT = 3.1V
All unused inputs at 0.5V,
TA = +25°C, -55°C
TA = +125°C
0
-
-
-
30
30
30
nA
nA
nA
Post radiation, +25°C
-30
-30
V+ = 3.6V, VIN = VOUT = 0.5V
All unused inputs at 3.1V,
TA = +25°C, -55°C
TA = +125°C
0
-30
-
-
-
-
30
30
nA
nA
nA
Post radiation, +25°C
V+ = VREF = VEN = 3.6V
Quiescent Supply Current
ISUPPLY
100
VA = 0V, TA = +25°C, -55°C
TA = +125°C
-
-
-
-
-
-
300
300
200
nA
nA
nA
Post radiation, +25°C
V+ = VREF = VEN = 3.6V, VA = 0V
Reference Quiescent Supply Current
IREF
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ISL71830SEH
+
Electrical Specifications, V = 3.3V
V
= 3.3V, V = 3.3V, V = 0V, T = +25°C, unless otherwise noted. Boldface limits
REF IH IL A
apply across the operating temperature range, -55°C to +125°C.; over a total ionizing dose of 75krad(Si) with exposure at a low dose rate of
<10mrad(Si)/s. (Continued)
MIN
MAX
PARAMETER
SYMBOL
DYNAMIC
tAHL
tBBM
tEN(ON)
tEN(OFF)
NOTE:
CONDITIONS
(Note 6)
TYP
(Note 6)
UNIT
Addressing Transition Time
Break-Before-Make Delay
Enable Turn-On Time
V+ = 3V; Figure 3
10
-
100
50
ns
ns
ns
ns
V+ = 3V; Figure 5
V+ = 3V; Figure 4
V+ = 3V; Figure 4
5
-
25
-
-
50
Enable Turn-Off Time
-
50
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or
design.
TABLE 2. TRUTH
A3
X
A2
X
A1
X
A0
X
EN
1
“ON” CHANNEL
None
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
2
3
0
0
0
1
1
0
1
0
0
0
4
5
0
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
6
0
7
0
8
1
9
1
10
11
12
13
14
15
16
1
1
1
1
1
1
NOTE:
7. X = Don’t care, “1” = Logic High, “0” = Logic Low.
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ISL71830SEH
Timing Diagrams
95()
³ꢄꢄꢄꢄ´
ISL71830SEH
ꢀꢁꢂ
ꢀꢁꢂ
A3
A2
A1
A0
IN01
IN02-IN15
IN16
V+, 0V
0V, V+
VREF
0V
³ꢁꢁꢁꢁ´
50䃈
ꢁ9
ꢃ
9
W
W
$+/
$+/
ꢅꢁꢂ
ꢅꢁꢂ
0V
EN
OUT
VOUT
287387
10k䃈
50pF
ꢁ9
FIGURE 4. ADDRESS TIME TO OUTPUT DIAGRAM
FIGURE 3. ADDRESS TIME TO OUTPUT TEST CIRCUIT
ISL71830SEH
VREF
EN
V+
A3
A2
A1
A0
IN01
IN02-IN16
50%
50%
0V
V+
VOUT
OUT
90%
EN
t
ENABLE
VREF
0V
1kΩ
50pF
OUTPUT
Ω
50
t
DISABLE
10%
0V
FIGURE 6. TIME TO ENABLE/DISABLE OUTPUT DIAGRAM
FIGURE 5. TIME TO ENABLE/DISABLE OUTPUT TEST CIRCUIT
VREF
ISL71830SEH
A3
A2
A1
A0
IN01
IN02-IN15
IN16
V+
ADDRESS
0V
VREF
0V
50Ω
+
V
0V
EN
OUT
VOUT
50%
100Ω
50pF
OUT
0V
t
BBM
FIGURE 7. BREAK-BEFORE-MAKE TEST CIRCUIT
FIGURE 8. BREAK-BEFORE-MAKE DIAGRAM
VREF
ISL71830SEH
ADDRESS
A3
A2
A1
A0
IN01
IN02-IN15
IN16
0V
VREF
0V
50䃈
0V
Q = 100pF * ΔVOUT
ΔVOUT
0V
EN
OUT
VOUT
OUT
0V
100pF
FIGURE 9. CHARGE INJECTION TEST CIRCUIT
FIGURE 10. CHARGE INJECTION DIAGRAM
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ISL71830SEH
Typical Performance Curves V+ = 5V, VREF = 3.3V, VIN = 0V, RL = Open, TA = +25°C,
unless otherwise specified.
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
+125°C
+125°C
+25°C
+25°C
-55°C
-55°C
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
COMMON-MODE VOLTAGE (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
COMMON-MODE VOLTAGE (V)
FIGURE 11. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 4.5V)
FIGURE 12. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 5V)
80
140
+125°C
70
120
+125°C
60
50
40
30
20
10
0
+25°C
100
80
60
-55°C
+25°C
40
-55°C
2
20
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
1
3
4
5
COMMON-MODE VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
FIGURE 13. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 5.5V)
FIGURE 14. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 3V)
120
120
+125°C
+125°C
100
100
80
60
40
80
60
+25°C
-55°C
40
20
0
+25°C
3.0
-55°C
1.0
20
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.5
2.0
2.5
3.5
COMMON-MODE VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
FIGURE 15. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 3.3V)
FIGURE 16. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 3.6V)
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ISL71830SEH
Typical Performance Curves V+ = 5V, VREF = 3.3V, VIN = 0V, RL = Open, TA = +25°C,
unless otherwise specified. (Continued)
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
+125°C
+25°C
+125°C
-55°C
-55°C
+25°C
3.0
3.5
4.0
4.5
5.0
5.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 18. ADDRESS PROPAGATION DELAY (LOW TO HIGH)
FIGURE 17. ADDRESS PROPAGATION DELAY (HIGH TO LOW)
40
35
2V/DIV
+125°C
30
25
20
t
= 44.087ns
ADLH
15
t
= 34.382ns
ADHL
-55°C
10
5
+25°C
5.0
1V/DIV
0
3.0
3.5
4.0
4.5
5.5
200ns/DIV
SUPPLY VOLTAGE (V)
FIGURE 19. ADDRESS PROPAGATION DELAY
FIGURE 20. BREAK-BEFORE-MAKE DELAY
60
50
40
30
20
10
0
2V/DIV
+125°C
1V/DIV
t
= 17.929ns
BBM
-55°C
+25°C
3.0
3.5
4.0
4.5
5.0
5.5
200ns/DIV
SUPPLY VOLTAGE (V)
FIGURE 21. BREAK-BEFORE-MAKE DELAY
FIGURE 22. ENABLE TO OUTPUT PROPAGATION DELAY
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ISL71830SEH
Typical Performance Curves V+ = 5V, VREF = 3.3V, VIN = 0V, RL = Open, TA = +25°C,
unless otherwise specified. (Continued)
60
+125°C
2V/DIV
50
40
1V/DIV
t
= 41.720ns
DISABLE
-55°C
30
20
10
0
+25°C
t
= 22.670ns
ENABLE
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
200ns/DIV
FIGURE 23. DISABLE TO OUTPUT PROPAGATION DELAY
FIGURE 24. ENABLE/DISABLE PROPAGATION DELAY
120
90
80
70
60
50
40
30
20
10
0
100
80
60
40
20
0
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 25. OFF ISOLATION (V+ = 5V, +25°C, RL = 511Ω)
FIGURE 26. OFF ISOLATION (V+ = 5V, +25°C, RL= OPEN)
120
2.00
+125°C
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0
100
80
60
40
20
0
+25°C
-55°C
100
1k
10k
100k
1M
10M
3.0
3.5
4.0
4.5
5.0
5.5
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
FIGURE 27. CROSSTALK (V+ = 5V, +25°C, RL = OPEN)
FIGURE 28. CHARGE INJECTION
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ISL71830SEH
+
Post Low Dose Rate Radiation Characteristics (V = 5V) Unless otherwise
specified, V+ = 5V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This
data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed.
120
100
80
60
40
20
0
120
100
80
60
40
20
0
V
= 0.5V
IN
V
= 0.5V
IN
V
= 2.25V
V
= 2.25V
30
V
= 4V
V
= 4V
IN
IN
IN
IN
0
10
20
40
50
60
70
80
0
10
20
30
40
50
60
70
80
LOW DOSE RATE RADIATION (krad(Si))
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 29. rDS(ON) (V+ = 4.5V), BIASED
FIGURE 30. rDS(ON) (V+ = 4.5V), GROUNDED
120
120
100
80
60
40
20
0
100
80
60
40
20
0
GROUNDED
GROUNDED
BIASED
BIASED
10
20
30
40
50
60
70
80
0
0
10
20
30
40
50
60
70
80
LOW DOSE RATE RADIATION (krad(Si))
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 31. rDS(ON) MINIMUM (V+ = 4.5V)
FIGURE 32. rDS(ON) MAXIMUM (V+ = 4.5V)
45
40
35
30
25
20
15
10
5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
GROUNDED
BIASED
GROUNDED
BIASED
0
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
LOW DOSE RATE RADIATION (krad(Si))
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 33. rDS(ON) FLATNESS (V+ = 4.5V)
FIGURE 34. rDS(ON) MATCH (V+ = 4.5V, VIN = 0.5V)
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ISL71830SEH
+
Post Low Dose Rate Radiation Characteristics (V = 5V) Unless otherwise
specified, V+ = 5V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This
data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. (Continued)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.8
0.6
0.4
0.2
0
GROUNDED
GROUNDED
BIASED
-0.2
-0.4
-0.6
-0.8
-1.0
BIASED
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
LOW DOSE RATE RADIATION (krad(Si))
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 35. rDS(ON) MATCH (V+ = 4.5V, VIN = 4V)
FIGURE 36. IS(OFF) (V+ = 5.5V, VIN = 5V)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.8
0.6
0.4
0.2
0
BIASED
GROUNDED
GROUNDED
-0.2
-0.4
-0.6
-0.8
-1.0
BIASED
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
LOW DOSE RATE RADIATION (krad(Si))
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 37. IS(OFF) (V+ = 5.5V, VS = 7V)
FIGURE 38. IS(ON) (V+ = 5.5V, VIN = 5V)
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
GROUNDED
GROUNDED
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
BIASED
BIASED
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
LOW DOSE RATE RADIATION (krad(Si))
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 39. ID(ON) (V+ = 5.5V, VIN = 5V)
FIGURE 40. ID(OFF) (V+ = 3.6V, VIN = 3.1V)
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ISL71830SEH
+
Post Low Dose Rate Radiation Characteristics (V = 3.3V) Unless otherwise
specified, V+ = 3.3V, VCM = 0,VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This
data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed.
120
100
80
60
40
20
0
120
100
80
60
40
20
0
V
= 0.5V
IN
V = 1.5V
IN
V
= 0.5V
V
= 1.5V
IN
IN
V
= 2.5V
V
= 2.5V
IN
IN
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
LOW DOSE RATE RADIATION (krad(Si))
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 41. rDS(ON) (V+ = 3V), BIASED
FIGURE 42. rDS(ON) (V+ = 3V), GROUNDED
120
100
80
60
40
20
0
120
100
80
60
40
20
0
GROUNDED
BIASED
BIASED
GROUNDED
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
LOW DOSE RATE RADIATION (krad(Si))
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 43. rDS(ON) MINIMUM (V+ = 3V)
FIGURE 44. rDS(ON) MAXIMUM (V+ = 3V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
45
40
35
30
25
20
15
10
5
GROUNDED
GROUNDED
BIASED
BIASED
0
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
LOW DOSE RATE RADIATION (krad(Si))
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 46. rDS(ON) MATCH (V+ = 3V, VIN = 0.5V)
FIGURE 45. rDS(ON) FLATNESS (V+ = 3V)
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ISL71830SEH
+
Post Low Dose Rate Radiation Characteristics (V = 3.3V) Unless otherwise
specified, V+ = 3.3V, VCM = 0,VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This
data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. (Continued)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.8
0.6
0.4
0.2
0
GROUNDED
GROUNDED
BIASED
-0.2
-0.4
-0.6
-0.8
-1.0
BIASED
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
LOW DOSE RATE RADIATION (krad(Si))
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 47. rDS(ON) MATCH (V+ = 3V, VIN = 2.5V)
FIGURE 48. IS(OFF) (V+ = 3.6V, VIN = 3.1V)
1.0
0.8
0.6
0.4
0.2
0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
GROUNDED
GROUNDED
BIASED
-0.2
-0.4
-0.6
-0.8
-1.0
BIASED
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
LOW DOSE RATE RADIATION (krad(Si))
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 49. IS(OFF) (V+ = 3.6V, VIN = 7V)
FIGURE 50. IS(ON) (V+ = 3.6V, VIN = 7V)
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
GROUNDED
BIASED
GROUNDED
BIASED
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
LOW DOSE RATE RADIATION (krad(Si))
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 51. ID(ON) (V+ = 3.6V, VIN = 3.1V)
FIGURE 52. ID(OFF) (V+ = 3.6V, VIN = 3.1V)
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ISL71830SEH
ISL71830SEH vs ISL71831SEH
Applications Information
A 32-channel version of the ISL71830SEH is available in a 48 Ld
CQFP. In terms of performance specs, the parts are very similar
in behavior. Apart from the apparent increase in channel density,
the ISL71831SEH does have slightly higher output leakage
compared to the ISL71830SEH due to having more channels
connected to the output. The supply current for the ISL71831SEH
is also a bit higher compared to the ISL71830SEH.
Power-Up Considerations
The circuit is designed to be insensitive to any given power-up
sequence between V+ and VREF, however, it is recommended
that all supplies power-up relatively close to each other.
Overvoltage Protection
The ISL71830SEH has overvoltage protection on both the input
as well as the output. On the output, the voltage is limited to a
diode past the rails. Each of the inputs has independent
overvoltage protection that works regardless of the switch being
selected. If a switch experiences an overvoltage condition, the
switch is turned off. As soon as the voltage returns within the
rails, the switch returns to normal operation.
VREF and Logic Functionality
The VREF pin sets the logic threshold for the ISL71830SEH. The
range for VREF is between 3V and 5.5V. The switching point is set
to around 50% of the voltage presented to VREF. This switching
point allows for both 5V and 3.3V logic control.
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ISL71830SEH
Assembly Related Information
Die Characteristics
SUBSTRATE POTENTIAL
Die Dimensions
Floating
2026µm x 2240µm (79.7638 mils x 88.1890 mils)
Thickness: 483µm ± 25µm (19 mils ± 1 mil)
Additional Information
Interface Materials
WORST CASE CURRENT DENSITY
1.6 x 105 A/cm2
GLASSIVATION
Type: 12kÅ Silicon Nitride on 3kÅ Oxide
TRANSISTOR COUNT
TOP METALLIZATION
3875
Type: 300Å TiN on 2.8µm AlCu
In Bondpads, TiN has been removed.
Weight of Packaged Device
2.091 grams
BACKSIDE FINISH
Lid Characteristics
Silicon
Finish: Gold
Potential: Grounded, tied to package pin 12
PROCESS
P6SOI
Metalization Mask Layout
IN16
IN15
IN8
V+
OUT
IN7
IN14
IN13
IN12
IN6
IN5
IN4
IN11
IN10
IN9
IN3
IN2
IN1
EN
BAR
GND
VREF
A3
A2
A1
A0
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ISL71830SEH
TABLE 3. ISL71830SEH DIE LAYOUT X-Y COORDINATES
ΔX
ΔY
X
Y
PAD NUMBER
PAD NAME
IN8
PACKAGING PIN
P26
P28
P1
(µm)
(µm)
(µm)
(µm)
1
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
1693.925
1050.875
844.875
201.8
1939.8
1915.8
1915.8
1939.8
1693.8
1477.8
1271.8
1065.8
859.8
5
OUT
V+
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
IN16
IN15
IN14
IN13
IN12
IN11
IN10
IN9
P4
P5
201.8
P6
201.8
P7
201.8
P8
201.8
P9
201.8
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
201.8
653.8
201.8
442.8
GND
VREF
A3
206.225
440.35
201.8
201.8
676.35
201.8
A2
912.35
201.8
A1
1148.35
1384.35
1620.35
1693.925
1693.925
1693.925
1693.925
1693.925
1693.925
1693.925
201.8
A0
201.8
EN
201.8
IN1
442.8
IN2
653.8
IN3
859.8
IN4
1065.8
1271.8
1477.8
1693.8
IN5
IN6
IN7
NOTE: Origin of coordinates is the center of the die.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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ISL71830SEH
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to the web to make sure that you have the latest revision.
DATE
REVISION
FN8758.3
CHANGE
November 18, 2016
Added ESD diagrams to the “Pin Descriptions” on page 3.
Updated Related Literature section.
March 4, 2016
FN8758.2
FN8758.1
Page 1 Features, changed the following:
From: SEL/B immune to LET 60MeV•mg/cm2
To: SEL/B immune to LET 60MeV•cm2/mg
December 10, 2015
Changed rON to rDS(ON) throughout datasheet
Changed in Features on page 1 last item under “Radiation tolerance” “V+ = 5V” to “V+ = 6.5V”
Changed in Description and Features on page 1 supply voltage from “3.3V to 5V” to “3V to 5.5V”.
Removed ADDR throughout datasheet from:
Pin Configuration from pins 14 through 17 on page 3
“Pin Descriptions” on page 3, “Absolute Maximum Ratings” on page 4 and Table 3 on page 18.
Abs Max Section, page 4, changed:
Maximum Supply Voltage (V+ to GND) (Note 5) . . . . . . 7V
TO:
Maximum Supply Voltage (V+ to GND) (Note 5) . . . . . 6.5V
Electrical Spec table:
page 4
Changed TYP from 60 to 40
page 5
tBBM changed TYP from 15 to 18
VCTE changed TYP from 2 to 1.4
Swapped the "VEN = " statements between Off Isolation and Crosstalk.
Off Isolation changed:
From: 60dB (TYP)
To: 60dB (MIN) and
Crosstalk changed:
From: 73dB (TYP)
To: 73dB (MIN)
page 6
Changed TYP from 60 to 70
page 7
tBBM changed TYP from 15 to 25
“Timing Diagrams” on page 8
Figures 5 and 7 changed 500 to 50Ω
On page 7 added Truth table.
Replaced die plot on page 17, changed VDD to V+.
Page 18 X-Y Coordinates table, changed VDD to V+
Figure 7 changed 1000 on bottom right resistor to 100Ω.
Y-Axis Changes:
Figure 20: from ADDRESS DELAY (ns) to: tBMM DELAY (ns)
Figure 22: from ADDRESS DELAY (ns) to: tENABLE DELAY (ns)
Figure 23: from ADDRESS DELAY (ns) to: tDISABLE DELAY (ns)
September 24, 2015
FN8758.0
Initial Release
About Intersil
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address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
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ISL71830SEH
Ceramic Metal Seal Flatpack Packages (Flatpack)
K28.A MIL-STD-1835 CDFP3-F28 (F-11A, CONFIGURATION B)
A
28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INCHES MILLIMETERS
MIN
A
e
PIN NO. 1
ID AREA
SYMBOL
MAX
0.115
0.022
0.019
0.009
0.006
0.740
0.520
0.550
-
MIN
1.14
0.38
0.38
0.10
0.10
-
MAX
2.92
0.56
0.48
0.23
0.15
18.80
13.21
13.97
-
NOTES
D
A
b
0.045
0.015
0.015
0.004
0.004
-
-
-
-A-
-B-
S1
b1
c
-
-
b
c1
D
-
E1
3
-
0.004
Q
H
A - B
D
S
0.036
M
H
A - B
S
C
D
S
M
S
E
0.460
-
11.68
-
E
E1
E2
E3
e
3
-
-D-
A
0.180
0.030
4.57
0.76
-H-
-C-
-
-
7
-
L
E2
L
E3
E3
0.050 BSC
1.27 BSC
SEATING AND
BASE PLANE
c1
LEAD FINISH
k
0.008
0.250
0.026
0.00
-
0.015
0.370
0.045
-
0.20
6.35
0.66
0.00
-
0.38
9.40
1.14
-
2
-
L
BASE
METAL
Q
S1
M
N
8
6
-
(c)
b1
0.0015
0.04
M
M
(b)
28
28
-
SECTION A-A
Rev. 0 5/18/94
NOTES:
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area
shown. The manufacturer’s identification shall not be used as a pin
one identification mark. Alternately, a tab (dimension k) may be
used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits
of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass over-
run.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness. The maximum limits of
lead dimensions b and c or M shall be measured at the centroid of
the finished lead surfaces, when solder dip or tin plate lead finish is
applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materi-
als shall be molded to the bottom of the package to cover the leads.
8. Dimension Q shall be measured at the point of exit (beyond the me-
niscus) of the lead from the body. Dimension Q minimum shall be
reduced by 0.0015 inch (0.038mm) maximum when solder dip lead
finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
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For the most recent package outline drawing, see K28.A.
FN8758.3
November 18, 2016
20
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