ISL87060MIK_技术文档

ISL837030, ISL83740

®

FN8013.5

Datasheet

May 2002

Modem Reference

Designs

Features

• Programmable modulation

The ISL837030 and ISL83740 Broadband Wireless Modem

Reference Designs support a wide range of modulation

orders and symbol rates.*

Both: QPSK, 8PSK, 16QAM, 32QAM

ISL83740 only: 64QAM, 128QAM

• Flexible data rates

ISL83740: up to 238Mbps

ISL837030: up to 160Mbps

In both Reference Designs, sophisticated coding,

equalization, and symbol recovery techniques are employed,

resulting in robust wireless link performance.

• Programmable symbol rates

The ISL837030 and ISL83740 Reference Designs support

high-capacity digital microwave radios with data rates up to

238Mbps (ISL83740) and 160Mbps (ISL837030). They

provide a flexible, high performance, economical solution for

fixed wireless applications.

• Reed Solomon (RS) encoding/decoding

• Concatenated coding using RS and PTCM inner code

• FCC and ETSI spectral mask compliance

• Powerful equalization

* Differences between the ISL837030 and ISL83740 are marked in text as

needed. Also see Release Notes on page 25.

Includes

• Sample ISL87060MIK Modulator and ISL87060DIK

Demodulator Chip Sets for development and test.

Benefits

• Eliminates the need to develop custom ASICs

• Complete Manufacturing Documentation Package: Bill of

Materials, Schematics, PCBA Fabrication Files, including

Gerber Files.

• Optimizes wireless link capacity and Bit Error Rate (BER)

performance

• Enables rapid prototyping and compliance testing

• Proven technology

• Test Documentation.

• Embedded Monitor and Control Software provides

comprehensive setup and test capabilities. Accepts

commands in binary or ASCII format.

• Optional Evaluation Kit supports demo requirements,

performance evaluation, and lab testing

Optional Evaluation Kit

The modem PCBA is mounted on an Evaluation Platform,

allowing the modem to be set up and tested in a standard lab

environment. Includes VHF and L-band IF Interfaces and a

sophisticated Graphical User Interface for Windows

operating systems. (ISL83700EVAL/ISL83740EVAL)

ISL87060MIK

Modulator/

Encoder

Differential

Baseband

Outputs

Data

LPF

DAC

Level

TrimDAC

Offset

ASYNC

Serial

Baseband

Loopback

Controller

FLASH

Modem PCBA

ISL87060DIK

Demodulator/

Decoder

Decimating

Matched

Filter

Differential

Baseband

Inputs

Data

ADC

LPF

FIGURE 1 Simplified Block Diagram

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

CommLink™ is a trademark of Intersil Americas Inc.

ISL837030, ISL83740

CONTENTS

LIST OF FIGURES

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . 3

Modulator Functions . . . . . . . . . . . . . . . . . . . . . . 5

1. ISL87060MIK Modulator ASSP . . . . . . . 5

2. Digital to Analog Converter (DAC) . . . . . 5

3. Low Pass Filter (LPF) . . . . . . . . . . . . . . 5

4. Rate Exchange . . . . . . . . . . . . . . . . . . . 5

Demodulator Functions . . . . . . . . . . . . . . . . . . . 5

1. Low Pass Filter (LPF) . . . . . . . . . . . . . . 5

2. ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3. FPGA Decimating Filter . . . . . . . . . . . . . 5

4. ISL87060DIK Demodulator ASSP . . . . . 5

5. Baseband Loopback . . . . . . . . . . . . . . . 5

6. Automatic Gain Control (AGC) . . . . . . . . 6

The Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Monitor and Control Software . . . . . . . . . . . . . . 6

Performance Specifications . . . . . . . . . . . . . . . . . . . . 7

Modem Parameters . . . . . . . . . . . . . . . . . . . . . . 7

Modulation, Inner Code Rates, and Ranges . . . 7

Modulator Performance Specifications . . . . . . . 8

Modulator Input Requirements . . . . . . . . . . . . . . 8

Modulator Output Electrical Specifications . . . . . 8

Demodulator Input Requirements . . . . . . . . . . . 9

Demodulator Input Electrical Specifications . . . . 9

Demodulator Performance Specifications . . . . 10

BER Performance (Typical) . . . . . . . . . . . . . . . 10

Controller Parameters . . . . . . . . . . . . . . . . . . . 11

Environmental & Physical Specifications . . . . . . . . . 12

Physical Interface Definition . . . . . . . . . . . . . . . . . . . 13

80-Pin Digital/Power Connector . . . . . . . . . . . . 14

Power Supply Signals . . . . . . . . . . . . . . . 15

M&C Port Signals . . . . . . . . . . . . . . . . . . . 15

Modulator Data Interface Signals . . . . . . . 15

Demodulator Data Interface Signals . . . . 16

Miscellaneous Signals . . . . . . . . . . . . . . . 17

Reserved . . . . . . . . . . . . . . . . . . . . . . . . . 17

8-Pin Baseband Connectors . . . . . . . . . . . . . . 18

Data Timing and Packet Definition . . . . . . . . . . . . . . 19

Modulator Data Input Timing . . . . . . . . . . . . . . 19

Modulator Packet Definition . . . . . . . . . . . . . . . 19

Demodulator Data Output Timing . . . . . . . . . . 20

Demodulator RS Data Packet Definition . . . . . 20

AGC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . 22

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Support

1. Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3. Modem Printed Circuit Board Assembly (PCBA) . . . . . . . . . . . . 4

4. Acquisition/Tracking Range at Low Baud Rates . . . . . . . . . . . 10

5. Modem PCBA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6. Digital/Power Connector Pin Configuration . . . . . . . . . . . . . . . 14

7. Modulator Connector Pin Configuration . . . . . . . . . . . . . . . . . . 18

8. Demodulator Connector Pin Configuration . . . . . . . . . . . . . . . 18

9. Modulator Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 19

10. Modulator Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . 19

11. Demodulator Data Output Timing . . . . . . . . . . . . . . . . . . . . . 20

12. Demodulator Data Packet Definition . . . . . . . . . . . . . . . . . . . 20

13. AGC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

14. Modem PCBA Mechanical Dimensions (Top View) . . . . . . . . 22

15. Modulator Baseband Interface to ISL83740EVAL/ISL83700EVAL

Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

16. Unbalanced Demodulator Baseband Interface, Shorter Runs 24

17. Unbalanced Demodulator Baseband Interface, Longer Runs 24

Ordering Information

PART NUMBER

DESCRIPTION

ISL83740REF-CD

ISL83740 Reference Design (QPSK,

8PSK, 16QAM, 32QAM, 64QAM,

128QAM)

ISL837030REF-CD ISL837030 Reference Design (QPSK,

8PSK, 16QAM, 32QAM)

ISL837030KIT-xxx

ISL83740EVAL

ISL83700EVAL

Kit versions supply sample chips in

lots of 24 to 120, in 24-unit increments.

Applies to either Reference Design.

ISL83740 Evaluation Kit (QPSK,

8PSK, 16QAM, 32QAM, 64QAM,

128QAM)

ISL837030 Evaluation Kit (QPSK,

8PSK, 16QAM, 32QAM)

ISL87060MIK

ISL87060DIK

Modulator Chip

Demodulator Chip

Related Documentation . . . . . . . . . . . . . . . . . . . . . . 25

Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . 25

All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation

7585 Irvine Center Drive

Suite 100

Irvine, CA 92618

TEL: (949) 341-7000

FAX: (949) 341-7123

EUROPE

ASIA

Intersil Corporation

2401 Palm Bay Rd.

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TEL: (321) 724-7000

FAX: (321) 724-7946

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1006 Lausanne

Switzerland

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FAX: +41 21 6140579

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TST, Kowloon Hong Kong

TEL: +852 2723 6339

FAX: +852 2730 1433

FN8013.5

2

ISL837030, ISL83740

Functional Description

.

The modem PCBA architecture implements a complete

baseband transmit and receive function:

Intersil’s broadband wireless modem devices are fully

integrated and support a wide range of modulation

orders and symbol rates. Sophisticated coding,

equalization, and symbol recovery techniques are

employed to enable robust wireless link performance.

1. Modulator Function

Converts byte-wide parallel data, encodes and digitizes

it, and generates a differential baseband analog signal.

This signal can then be up-converted to any IF/RF

frequency the user requires.

The complete modem Printed Circuit Board Assemblies

(PCBAs) with standard hardware and software

interfaces enable equipment manufacturers to rapidly

integrate Intersil modem functionality into their system

products.

2. Demodulator Function

Accepts a differential analog baseband signal. Filters,

decodes, corrects, and converts it to byte-wide digital

data and clock.

The ISL837030 and ISL83740 Modem Reference

Designs provide a flexible, high performance,

economical solution for fixed wireless applications. The

modem design provides an off-the-shelf solution for

users interested in easily integrating a complete modem

into their products.

3. Controller

Incorporates everything necessary to control and monitor

the modem.

I Data

10

External Sync

Data Input

2-1

Mux

10

200 Msps

DAC

Passive

LPF

ISL87060MIK

Modulator/

Encoder

Q Data

10

Byte Clock

2-1

Passive

LPF

200 Msps

DAC

Mux

+3.3V

+5V

+12V

-12V

Rate

Exchange

FPGA

Sample Clock

Q Level/Bal

I Level/Bal

VCO

ASYNC Serial

Q Offset

Controller

I Offset

FLASH

512k X 16

TrimDAC

Digital AGC

Analog AGC

Baseband

Loopback

XO

Clock PLL

AGC

DAC

Modem PCBA

AGC

10

Packet Sync

Data Output

8

Passive

LPF

100 Msps

ADC

FPGA

Decimating

Matched

Filter

ISL87060DIK

Demodulator/

Decoder

I Data

10

Data Clock

Data Flag

Q Data

Passive

LPF

100 Msps

ADC

10

FIGURE 2 Functional Block Diagram

FN8013.5

3

ISL837030, ISL83740

F u n c t i o n a l D e s c r i p t i o n

D1

D3

Controller

FPGA

Rate

Exchange

ISL87060DIK

Demodulator

D4

D5

FLASH

Memory

ISL87060MIK

Modulator

FPGA

Decimating

Matched

Filter

D6

MUX

Trim

DAC

MUX

DAC

ADC

DAC

FIGURE 3 Modem Printed Circuit Board Assembly (PCBA)

LED INDICATORS

D1 Controller Status

D3 Modem Ready

LIGHT INDICATORS

Blinking indicates controller is functional. Solid off or on indicates not functional.

Light on indicates modem is ready to accept user commands. Equivalent to the

MODEM_RDY signal on the interface connector.

D4 PLL Lock Detect

D5 Alarm IRQ

Light on indicates that the modulator rate exchange has successfully locked to

the interface input byte clock.

Light on signals active alarm condition. Equivalent to the IRQ signal on the

interface connector.

D6 Demod Lock

Light on indicates that the demodulator has successfully locked to the input

baseband signal.

FN8013.5

4

ISL837030, ISL83740

F u n c t i o n a l D e s c r i p t i o n

Modulator Functions

Demodulator Functions

The modulator accepts byte-wide parallel data, encodes it,

digitizes it, and produces a balanced analog signal output.

This signal can then be up-converted to whatever RF/IF

frequency the application requires. It consists of four

functions:

The demodulator accepts differential analog baseband I and

Q signals, then filters, decodes, corrects, and converts them

to byte-wide digital data and clock. It consists of six functions:

1. Low Pass Filter (LPF)

The LPF eliminates any undesired baseband high frequency

artifacts caused by the down conversion process.

1. ISL87060MIK Modulator ASSP

The modulator ASSP provides a digital representation of a

modulated analog signal. The chip accepts byte-wide TTL

data and applies:

2. ADC

The Analog to Digital Converter (ADC) provides a digital

representation of the modulated baseband analog signal. It

provides eight bits of data for each of the I and Q channels.

• Energy Dispersal

• Reed-Solomon Forward Error Correction (FEC)

• Convolutional Interleaving

3. FPGA Decimating Filter

A Field Programmable Gate Array (FPGA) based Decimating

Matched Filter is provided for additional filtering based on the

desired symbol rate. Multiple FPGA designs are required to

cover the full symbol range. They are stored in the

processor’s FLASH memory and loaded as required, based

on configuration parameters. The modem automatically

toggles between the FPGA designs depending on the baud

rate.

• Symbol Generation for various modulation formats with

or without Convolutional Coding

• Pulse Shaping

• Tuning

The digital output from the ASSP consists of eight 10-bit

ports, four for I and four for Q. Each port represents at least

one of four samples per symbol which requires multiplexing

before it is applied to the Digital to Analog Converter (DAC).

4. ISL87060DIK Demodulator ASSP

The demodulator ASSP accepts quantized baseband I and Q

signals and provides all necessary demodulation functions

including:

2. Digital to Analog Converter (DAC)

The DAC section muxes each of the four 10-bit ports and

converts them into an analog signal representation of the

digital values produced by the ASSP. The DAC samples at a

minimum of four samples per symbol based on the ASSP’s

Interpolator setting.

• Carrier and Symbol Acquisition and Tracking

• Adaptive Equalization

• Data Estimation

• Convolutional Deinterleaving

• Energy Dispersal Removal

TrimDACs, controlled by the processor, provide fine

adjustment of the amplitude and DC offset of the I and Q

output signals. Two of the TrimDACs control the reference

voltage used by the output DACs, thereby adjusting the

output signal amplitude. The default setting corresponds to a

zero adjustment.

• Decoding Functions, including Reed-Solomon

decoding

5. Baseband Loopback

The modulator baseband output can be configured to be

connected to the input of the demodulator. This allows in-

system functional verification of the modem. The loop-back

circuit is implemented with a fully differential buffered/switch

circuit. When engaged, the loop-back signals are summed

with the normal I and Q input signals to the demodulator. This

configuration does not require that either the normal

modulator I/Q outputs or the normal demodulator I/Q inputs

be disconnected. Operation is transparent to the normal

loading on these interfaces.

3. Low Pass Filter (LPF)

The analog signal from the DAC is then filtered to eliminate

undesired digitizing effects. The TrimDAC is used to control

the offset voltage of the output signal, allowing the user to

adjust the balance between the I and Q baseband output

signals for upconverter optimization.

4. Rate Exchange

The Rate Exchange function generates clocks by converting

the byte-wide interface clock to an ASSP processing clock. It

then provides the sample clocks to the DAC and Mux

sections. The relationship between the byte clock input and

the other clocks varies dramatically depending on the FEC

and Interpolator settings within the ASSP.

The loop-back signals are summed with the

normal input signals. Therefore, when loopback

is enabled the system must be set to minimize

the signal input from the normal demodulator I/Q

input path.

FN8013.5

5

ISL837030, ISL83740

F u n c t i o n a l D e s c r i p t i o n

Demodulator (Continued)

Monitor and Control Software

The modem PCBA is configured and monitored using

Intersil’s embedded Monitor and Control (M&C) software.

This software is used to set parameters such as:

6. Automatic Gain Control (AGC)

The demodulator ASSP provides a parallel data word to be

used by the AGC to optimize the dynamic range of the input

signal to the demodulator. The ASSP averages the

magnitude of the input baseband signal, subtracts that from a

target value, and accumulates the results. The AGC value is

available in either serial digital or analog form. The AGC

value output is proportional to the amount by which the

incoming signal’s amplitude must be increased in order for its

level to reach the desired target. Therefore, an increase in

the AGC value indicates that the signal level at the input to

the AGC amplifier/attenuator has actually decreased. The

modem operates in two different AGC modes:

• modulation type

• code rate

• payload rate

• symbol rate

• output level/offset

• AGC control

• diagnostics

• Open loop is used when there is no external AGC loop

implemented.

• self-test

• loopback

• alarms

• Closed loop is used when the modem’s AGC features

are to be used.

• baseband loopback

• Alpha (pulse shape)

• statistics

For best performance, closed loop mode is suggested. This

automatically sets the demodulator input level to the optimum

value. The system default is open loop mode until any AGC

parameter is initialized from the host.

• BER

• EVM

The Controller

• demodulator stress

• phase & amplitude imbalance

• and more

The Controller is a highly integrated device used to eliminate

the complexities of interfacing with the Intersil ASSPs

directly. It incorporates everything necessary to control and

monitor the modem.

For details, see the Programmer’s Reference AN9935.

The Controller’s processor takes high-level commands from

the user and determines what is required to configure and

monitor the ASSPs. This relieves the user from any real-time

interfacing and algorithm implementation issues.

The executable firmware is held in FLASH memory that is in-

circuit upgradeable. This allows the user to upgrade the code

or load in a new algorithm as required via the asynchronous

serial port (the Monitor and Control port).

FN8013.5

6

ISL837030, ISL83740

Performance Specifications

Modem Parameters

ITEM

DESCRIPTION

Symbol Rate Range

Payload Data Rate Range

3.0Mbaud to 42.514Mbaud

5.6Mbps to 238Mbps (ISL83740)

5.6Mbps to 160Mbps (ISL837030)

Outer Code (Reed Solomon)

Packet Size

(255, 238) Internal Sync Mode only

(240, 223) External Sync Mode only

See Demodulator RS Data Packet Definition on

page 20.

Power Consumption

FEC Modes

18.75W Maximum

FEC disabled, RS FEC only, concatenated

convolutional inner code with RS outer code

Pulse Shape (Alpha)

Square Root Nyquist, programmable

α (0.15 to 0.35) in 0.05 steps

Tx Carrier Tuning Range

± 500kHz, programmable in 1kHz steps

Non-zero tuner offsets may not meet more stringent

mask requirements.

Rx Digital Matched Filter

32-tap Root Raised Cosine

0.20 rolloff factor

Bandwidth tracks selected symbol rate

Modulation, Inner Code Rates, and Ranges

MODULATION

TYPE

INNER CODE

PAYLOAD RATE

SYMBOL RATE

RANGE IN Mbaud

1

2

RATE

RANGE IN Mbps

ASCII

QPSK

8PSK

BINARY

ISL83740

ISL837030

ISL83740

ISL837030

0

1

2

1

12

5.6000 to 79.3595

1

3/4

7/8

1

12

2

8.4000 to 119.0392 8.4000 to 119.0392

9.8000 to 138.8791 9.8000 to 138.8791

11.2000 to 158.7189 11.2000 to 158.7189

12.6000 to 178.5588 12.6000 to 160.0000

14.0000 to 198.3987 14.0000 to 160.0000

14.0000 to 198.3987

16QAM

3.0000 to 42.5140

6

All Payload Rates:

3.0000 to 42.5140

12

3

32QAM

64QAM

128QAM

4

6

8

4/5

9/10

1

8

3.0000 to 38.0953

3.0000 to 34.2857

12

4

5/6

11/12

1

N/A

9

15.4000 to 218.2385

16.8000 to 238.0784

12

5

6/7

1

2

A rate of 1 is equivalent to No Inner Code.

Ranges valid for Internal Sync (RS 255, 238).

To avoid significant performance degradation, interleaving must be enabled when using

concatenated coding rates (any rate other than 1). See the mdLeaver command in the

Programmer’s Reference AN9935.

FN8013.5

7

ISL837030, ISL83740

P e r f o r m a n c e S p e c i f i c a t i o n s

Modulator Performance Specifications

ITEM

DESCRIPTION

Baseband Amplitude Imbalance

< 0.1dB after initial trim, over temperature and life

< 0.2dB typical without trim

Spectral flatness (relative to ideal RRC spectrum) +0.1dB, -0.5dB

Baseband Phase Imbalance

< 0.5°, over temperature and life

I/Q Average Group Delay Imbalance

0.3ns maximum

Residual Output Voltage Noise Floor (>100MHz) Less than -110dBmV/Hz rms differential

I/Q Anti-alias Filter Low Pass Response

I/Q AC Coupling High Pass Response

Tx Symbol Timing Jitter (1kHz to baud/2)

Spurious Components (below 140MHz)

3-pole, -3dB at 32.0MHz

1-pole, -3dB at 75Hz

1.0° rms, referred to symbol period

DAC Aliasing Component (15Mbaud to

17.5Mbaud, 29.75Mbaud to 35Mbaud)

-55dBc or better

DAC Aliasing Component (other baud rates) -65dBc or better

Miscellaneous Spurious Components

Less than -80dBc

Spurious Outputs (above 140MHz)

Modulator Input Requirements

ITEM

DESCRIPTION

Input Data Byte Clock Phase Noise

F

F_BAUD

F_BYTE

2

< (2.0 X ^BYTE) rms, when integrated from 300Hz to

EVM and BER may be degraded if this parameter

is exceeded.

When integrated over an offset bandwidth of 500Hz to half the byte

rate frequency, then scaled proportionally to the symbol rate

frequency.

Modulator Output Electrical Specifications

ITEM

DESCRIPTION

Output Signal Type

Fully balanced differential, AC Coupled

Baseband Output Level into recommended load¹Nominal: 1.9V p-p. Maximum: 2.2V p-p

Baseband Output Adjust/Resolution¹

Baseband Offset Trim¹

Programmable -4dB to

Programmable 31mV in 0.244mV steps into 1.2k

at +2.5V bias (Offset adjustment of 0VDC to +5VDC through 95k

+

1.5dB, in approximately 0.04dB steps.

±

Ω

load

Ω

connected to output). For details, see the Programmer’s Reference

AN9935.

Load Impedance (Required)

1.20kΩ ± 20%, < 20pF, each leg to ground

The modulator pulse shaping, interpolation, and Applicable Standards: FCC 47CFR 101.111; ETSI EN 300-197,

analog anti-alias filtering have been designed to 198, 430, and 431; ETSI EN 301-128.

meet the requirements of applicable FCC, IC,

ITU, and ETSI standard spectral masks.

1

Output levels are not guaranteed when using the modulator tuner.

FN8013.5

8

ISL837030, ISL83740

P e r f o r m a n c e S p e c i f i c a t i o n s

Demodulator Input Requirements

ITEM

DESCRIPTION

Symbol Frequency Error

Spectral Slope Error

±

Up to

200 ppm of symbol rate

± 2dB average tilt across passband

Average I/Q Group Delay

Imbalance

< 6% of symbol period, up to 40Mbaud

< 1.5ns for 40Mbaud to 42.5Mbaud

I/Q Group Delay Response

Flatness (p-p delay variation

across 3dB spectrum)

Carrier Leakage Component

-30dBc or better for QPSK, 8PSK, 16QAM

-35dBc or better for 32QAM, 64QAM, 128QAM

(64QAM and 128QAM available in ISL83740 only)

< 1.0dB maximum

Baseband Source Amplitude

Error

Baseband Source Phase

Imbalance

< 5° maximum

Demodulator Input Electrical Specifications

ITEM

DESCRIPTION

Input Signal Type

Input Impedance

Balanced differential, DC Coupled

Balanced: 1.00k differential

Unbalanced: 1.00k

Ω

In unbalanced mode, source impedances of both legs should be

approximately equal to avoid DC offset at the ADCs. Matched source

impedances of < 100Ω are recommended.

Baseband Input Level

Baseband Input Bias

1.00V p-p for full scale at ADC

Current: Source outputs must sink 0.4mA for 0.00VDC input source,

each leg Offset: < 10µA

Open Circuit Input Bias Voltage

Input Overload Level

600mVDC (baseband loopback off)

Approximately 2.5V p-p

FN8013.5

9

ISL837030, ISL83740

P e r f o r m a n c e S p e c i f i c a t i o n s

Demodulator Performance Specifications

ITEM

DESCRIPTION

1

Rx Carrier Tracking Range

± 400kHz

1

Rx Carrier Acquisition Range

Programmable from 50kHz to 400kHz in increments of 1kHz. For

details, see the Programmer’s Reference AN9935.

1

The maximum Acquisition and Tracking Rate Range is less than 400kHz when the baud rate is less than

6.6Mbaud, as shown in FIGURE 4.

450

400

350

300

250

200

150

100

3

4

5

6

7

8

Symbol Rate (MBaud)

FIGURE 4 Acquisition/Tracking Range at Low Baud Rates

BER Performance (Typical)

PARAMETERS

MODULATION

INNER

CODE RATE

BER

TYPE

Eb/No

CONDITIONS

1.0E-8 BER

QPSK

1

8.1dB

8PSK,

1

11.6dB

12.2dB

14.8dB

18.7dB

7.8dB

16QAM

32QAM

64QAM

16QAM

1

•

Standard setup using low-cost VHF IF

1

interface loopback

1.0E-10 BER

3/4

7/8

4/5

9/10

5/6

11/12

6/7

1

9.0dB

64QAM and

128QAM available

in ISL83740 only.

32QAM

64QAM

128QAM

9.7dB

11.4dB

12.7dB

15.0dB

17.2dB

BER < 1.0E-11

•

Standard setup using low-cost VHF IF

Residual BER, 32QAM

FEC disabled

1

interface loopback

•

No added noise

Baseband loopback, no noise

0

1

Performance is based on a standard setup using the Evaluation Platform’s VHF interface under typical operating

conditions at baud rates > 10Mbaud as defined in Demodulator Input Requirements on page 9. All loop

bandwidths are set by default to accommodate severe multipath distortions. Performance can be increased

significantly by adjusting loop bandwidths for a less severe environment. Performance is 0.5dB to 1dB better when

using the Evaluation Platform’s high performance L-band interface.

FN8013.5

10

ISL837030, ISL83740

P e r f o r m a n c e S p e c i f i c a t i o n s

Controller Parameters

ITEM

DESCRIPTION

•

TTL Level UART, RXD, TXD only, no handshake

Monitor and Control (M&C) Port

115.2kBaud

8 bits

No Parity

1 Stop Bit

Can be performed via M&C port

Independent of Application Code Update

Cannot be done during modem operation

FPGA Configuration Update

Application Code Update

Reset Time from Power Up

On-board FLASH memory holds up to four Decimating

Matched Filter configurations

Can be performed via M&C port

•

Independent of FPGA Configuration Update

Cannot be done during modem operation

Boot-loader write protected to ensure unconditional

recovery.

8 seconds

•

FN8013.5

11

ISL837030, ISL83740

Environmental & Physical Specifications

Reliability

MTBF 457,000 hours (52 years) per Bellcore Standard TR-332

Power Supply Requirements

VOLTAGE

CURRENT

+5VDC

±

5%

100mA

+3.3VDC

±

5A

-8.75VDC to -12VDC

+8.75VDC to +12VDC

100mA

Temperature and Humidity Tolerances

ENVIRONMENT

OPERATING

STORAGE

Temperature

-40

°C to 85

°C

-50

°

C to 150°C

Humidity (non-condensing)

<95%

99%

Operating humidity

tolerance can be

increased by

conformal coating.

Board Size and Weight

(Excluding connectors)

Length and Width

Height on Top

Height on Bottom

Weight

6” X 6”

0.3” plus heatsink

0.11”

5 oz.

Demodulator ASSP Airflow Requirements

AAVID

HEATSINK

HEIGHT

FOR 85°C OPERATION FOR 70°C OPERATION

(4.3°C/W REQUIRED)

(6.1°C/W REQUIRED)

UNIT

372024

371924¹

372824

1.100”

0.550”

0.230”

≥

125

265

400

0

linear feet

per minute

≥

165

300

1

Included in ISL83740EVAL/ISL83700EVAL Evaluation Platform configurations.

FN8013.5

12

ISL837030, ISL83740

Physical Interface Definition

The following figure highlights the board connectors:

BOTTOM VIEW

80-pin Connector

Pin 1

Actual Connector Pins

are on Bottom

8-Pin Modulator

2

4

6

1

3

5

Baseband Connector

2

4

6

8

1

3

5

7

80

79

8-Pin Demodulator

Baseband Connector

TOP VIEW

80-pin Connector

8-Pin Demodulator

Baseband Connector

80

78

76

79

77

75

8

6

4

2

7

5

3

1

2

1

8-Pin Modulator

Baseband Connector

Pin 1

FIGURE 5 Modem PCBA Connectors

FN8013.5

13

ISL837030, ISL83740

P h y s i c a l I n t e r f a c e D e f i n i t i o n

80-Pin Digital/Power Connector

Modem Connector Part #: Samtec TSW-140-07-T-D

Suggested Mating Connector: SAMTEC SSW-140-22-T-D

The following figure shows the pin configuration for the 80-pin digital/power connector. For additional

details, see the following pages.

2

4

6

+3.3VDC

1

3

5

7

DGROUND

DIN

0

2

4

6

DIN

1

3

5

7

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

9

+3.3VDC

MOD_DCLK

reserved

IRQ

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

DGROUND

MOD PSYNC

_

reserved

RESET

TXD

RXD

+3.3VDC

reserved

DGROUND

reserved

MODEM_PRESENT1

MODEM_PRESENT2

AGC

_DATA

reserved

DGROUND

AGC

_CLK

+3.3VDC

AGC

_SYNC

MODEM_RDY

DEMOD

_LK

+5VDC

DGROUND

DMD

DGROUND

DMD DFLAG

_DCLK

+3.3VDC

DMD_PSYNC

_

DOUT

0

2

4

6

DOUT

1

3

5

7

DOUT

DGROUND

reserved

AGROUND

DMD_DATAOK

reserved

AGROUND

-ANALOG_VDC

+

ANALOG

_VDC

reserved

ANALOG

_AGC

FIGURE 6 Digital/Power Connector Pin Configuration

FN8013.5

14

ISL837030, ISL83740

P h y s i c a l I n t e r f a c e D e f i n i t i o n

Power Supply Signals

PIN(S)

SIGNAL NAME

DESCRIPTION

Positive Analog Voltage

Negative Analog Voltage

CHARACTERISTIC

+8.75VDC to +12VDC

-8.75VDC to -12VDC

78

77

+ANALOG_VDC

-ANALOG_VDC

+3.3VDC

1

11

23

51

59

Digital Voltage

±

5%

56

+5VDC

75

76

AGROUND

Analog Ground

Digital Ground

2

12

24

52

57

60

71

DGROUND

M&C Port Signals

PIN(S)

SIGNAL NAME

DESCRIPTION

CHARACTERISTIC

22

RXD

Status data from modem (output) TTL V = 2.4V minimum

OH

V

= 0.6V maximum

OL

21

TXD

Control data to modem (input)

TTL V = 2.3V minimum

IH

V

= 0.8V maximum

IL

Modulator Data Interface Signals

PIN(S)

SIGNAL NAME

DIN0

DESCRIPTION

CHARACTERISTIC

3

4

Data input LSB

DIN1

5

DIN2

Data Input

6

DIN3

TTL V = 2.3V minimum

7

DIN4

IH

V

= 0.8V maximum

8

DIN5

IL

9

DIN6

10

13

DIN7

Data input MSB

MOD_DCLK

Byte rate input clock. Data

sampled on rising edge.

14

MOD_PSYNC

When in external sync byte mode,

active high flag indicates sync

byte location in input transport

stream. When not used leave

open or tie low.

FN8013.5

15

ISL837030, ISL83740

P h y s i c a l I n t e r f a c e D e f i n i t i o n

Demodulator Data Interface Signals

PIN(S)

63

SIGNAL NAME

DOUT0

DESCRIPTION

CHARACTERISTIC

Data output LSB

64

DOUT1

65

DOUT2

Data Output

66

DOUT3

67

DOUT4

68

DOUT5

69

DOUT6

TTL V

≥

2.4V minimum

70

DOUT7

Data output MSB

OH

V

≤ 0.4V maximum

61

DMD_PSYNC

Active high signal indicates sync

byte is available on bus.

OL

62

58

DMD_DFLAG

DMD_DCLK

Active high signal indicates valid

data is available on bus. Low

indicates Reed Solomon Parity or

sync byte is on bus.

Byte output clock. Data transitions

on falling edge. This clock is

ASSP Process Clock gated when

valid data is output from the

ASSP. Valid data includes sync

and parity bytes.

72

80

DMD_DATAOK

ANALOG_AGC

Active high signal indicates

presence of RS-correctable

packet. Indicates the current

output packet contains no errors.

A voltage representative of the

digital value calculated by the

ASSP. The ASSP averages the

magnitude of the input baseband

signal, subtracts that from a target

value, and accumulates the

results.

Range: 0VDC to 3.0VDC

Impedance: 100

Current: 3mA maximum

Ω

±

Update Rate: approximately

every 2,000 symbols

49

AGC_CLK

Serial clock output. Data

transitions on rising edge, should

be stored on the falling edge.

TTL V

V

≥

≤

2.4V minimum

0.4V maximum

OH

OL

53

47

AGC_SYNC

AGC_DATA

Active low signal used to bound

valid data out.

Serial data, 12 bits AGC, 4 bits

padding. Data transitions on rising

edge of AGC_CLK. See AGC

Timing on page 21.

FN8013.5

16

ISL837030, ISL83740

P h y s i c a l I n t e r f a c e D e f i n i t i o n

Miscellaneous Signals

PIN(S)

SIGNAL NAME

DESCRIPTION

CHARACTERISTIC

20

RESET

Active low hard reset.

Open Drain

Resets processor and ASSPs to

their initial conditions. This signal

is extended by 350ms by a device

used to monitor VCC and the

state of the reset signal.

V

≥

≤

2.0V minimum

0.8V maximum

IH

IL

5k pullup to 3.3V on modem

19

IRQ

Active low interrupt request

indicates modem requires

attention.

When enabled this signal asserts,

indicating that a fault condition

exists on the modem.

TTL V

V

≥

≤

2.4V minimum

0.4V maximum

OH

55

54

DEMOD_LK

Demodulator lock indicator.

low = lock

OL

MODEM_RDY

Active high indicates modem is

Ready.

Indicates modem is available after

power up or reset. Typical time is

less than 8 seconds after valid

3.3V or RESET

4.7k pullup to 3.3V

Use either 45 or

.

45

OR

46

MODEM_PRESENT1

MODEM_PRESENT2

Can be used for modem presence

detect.

46; do not tie

together.

Reserved

PIN(S)

DESCRIPTION

15-18

Leave all unused pins

unconnected. Some are

used for test and some

are reserved for future

expansion.

25-44

48

50

73-74

79

FN8013.5

17

ISL837030, ISL83740

P h y s i c a l I n t e r f a c e D e f i n i t i o n

8-Pin Baseband Connectors

Modem Connector Part Number: Samtec TSW-104-07-T-D

Modulator Analog Baseband Connector

MOD I+

GND

MOD Q+

GND

MOD I-

GND

MOD Q-

GND

2

4

6

8

1

3

5

7

FIGURE 7 Modulator Connector Pin Configuration

PIN(S)

SIGNAL NAME

DESCRIPTION

CHARACTERISTIC

1

2

5

6

MOD I+

MOD I-

MOD Q+

MOD Q-

GND

I Baseband Analog Output

1.9V p-p differential with

Q Baseband Analog Output

Ground

1.2k

Ω, < 20pF load

3

4

7

8

Demodulator Analog Baseband Connector

DMD I+

GND

DMD Q+

GND

DMD I-

GND

DMD Q-

GND

2

4

6

8

1

3

5

7

FIGURE 8 Demodulator Connector Pin Configuration

PIN(S)

SIGNAL NAME

DESCRIPTION

CHARACTERISTIC

1

2

5

6

DMD I+

DMD I-

DMD Q+

DMD Q-

GND

I Baseband Analog Input

1.0V p-p nominal

Q Baseband Analog Input

Ground

1.0k

Ω, < 25pF load

3

4

7

8

FN8013.5

18

ISL837030, ISL83740

Data Timing and Packet Definition

Modulator Data Input Timing

Tscpw

Tscf

MOD_DCLK

Tddhld

Tddsu

FIGURE 9 Modulator Data Input Timing

SYMBOL

Tscf

DESCRIPTION

Shift_Clk Clock Period

Shift_Clk Pulse Width

Data Setup Time

MIN

UNITS

50.0

8.0

nsec

Tscpw

Tddsu

12.0

1.0

Tddhld

Data Hold Time

Modulator Packet Definition

Reed Solomon Packet

Sync Byte

Data

(223 bytes)

(1)

DIN [7..0]

MOD_PSYNC

1

External Sync Byte Mode.

FIGURE 10 Modulator Packet Definition

1

When using Internal Sync Byte Mode, byte-wide data is input to the modulator at a constant rate defined by the

configured data rate. Reed Solomon packetization is transparent to the input interface.

FN8013.5

19

ISL837030, ISL83740

D a t a T i m i n g a n d P a c k e t D e f i n i t i o n

Demodulator Data Output Timing

Tper

Thpul

DMD_DCLK¹

Tdcf

DMD_PSYNC,

DMD_DFLAG,

DMD_DATAOK

Tdcd

DOUT[7..0]

1

The DMD_DCLK is asynchronous to the output data rate and is a gated version of the demodulator’s process clock. Its

periodicity varies significantly based on Symbol Rate and Decimating Filter configurations. If a continuous output

clock is desired, the user must provide some form of “elastic buffer” external to the modem.

FIGURE 11 Demodulator Data Output Timing

SYMBOL

DESCRIPTION

DMD_DCLK Clock Period

MIN

MAX

UNITS

Tper

11.76

N/A

Note: Worst case, assumes consecutive

pulses are gated by the demodulator.

nsec

Thpul

Tdcf

DMD_DCLK High Width

3.7

N/A

2

Delay Clock to DMD_DFLAG

,

DMD_PSYNC

-.05

Tdcd

Delay Clock to DOUT

Demodulator RS Data Packet Definition

Sync Byte

Reed Solomon

Parity¹

Payload Bytes

DOUT[7..0]

DMD_PSYNC

DMD_DFLAG

DMD_DATAOK

(1)

Valid Packet

1

Sixteen Reed Solomon parity bytes are output whether encoding is enabled or disabled.

FIGURE 12 Demodulator Data Packet Definition

Reed Solomon (RS) packet size is calculated as follows:

• RS Packet Size = 1 Sync Byte + Payload Bytes + 16 RS Parity Bytes

• Sync byte: (external sync mode) supplied by the host connected to the transmitting modem, (internal sync

mode) supplied internally by the transmitting modem

• Payload bytes: supplied by the host connected to the transmitting modem

• RS parity bytes: supplied internally by the transmitting modem

• An RS packet length of 240 = 1 Sync Byte + 223 Payload Bytes + 16 RS Parity Bytes.

Supported by External Sync Mode only.

• An RS packet length of 255 = 1 Sync Byte + 238 Payload Bytes + 16 RS Parity Bytes.

Supported by Internal Sync Mode only.

FN8013.5

20

ISL837030, ISL83740

D a t a T i m i n g a n d P a c k e t D e f i n i t i o n

AGC Timing

Tper

AGC_CLK

/ /

Tsdly

/

AGC_SYNC

Tddly

Tupdate

/ /

D0

(LSB)

D11

(MSB)

Ignore First 4 Clock Cycles

D10

D1

AGC_DATA

FIGURE 13 AGC Timing

SYMBOL

Tper

DESCRIPTION

AGC_CLK Clock Period, 50%

MIN

200

0

MAX

N/A

5

UNITS

±

5% Duty Cycle

nsec

Tsdly

AGC_SYNC delay from AGC_CLK

AGC_DATA delay from AGC_CLK

Delay between updates

Tddly

0

10

Tupdate

3.2 Typical

µs

FN8013.5

21

ISL837030, ISL83740

Mechanical Drawings

Measurements are in inches.

SAMTEC P/N

TSW-140-07-T-D

.125 DIA.

NON-PLATED THRU HOLES

4 PLC'S

.125

.175

2

80

.000

79

1

MODEM PCBA

SAMTEC P/N

TSW-104-07-T-D

2

1

2

1

8

7

8

7

5.335

5.616

5.741

FIGURE 14 Modem PCBA Mechanical Dimensions (Top View)

FN8013.5

22

ISL837030, ISL83740

Applications

Suggested Baseband Interfaces to the Modem

I DAC

0mA to 20mA

1.8mf

+

0.42VDC

V bias

124

0.1%

143

0.1%

I-input

+

143

0.1%

124

0mA to 20mA

0.1%

12k

4x

2.43k*

2.2V p-p

max

-

0.42VDC

1.8mF

95k

1

3

5

7

2

4

6

8

-

Opt. TrimDACs

I level/bal

I offset

-Vr

AD8346

Direct U/C

V bias

Q offset

Q level/bal

Q-input

95k

+

Q DAC

12k

4x

2.43k*

2.2V p-p

max

0mA to 20mA

1.8mf

+

-

0.42VDC

124

143

0.1%

-

143

0.1%

124

0.1%

0mA to 20mA

0.42VDC

1.8mF

*Matched resistor networks recommended.

Modem PCBA

FIGURE 15 Modulator Baseband Interface to ISL83740EVAL/ISL83700EVAL Platform

This figure shows an IF interface to an L-band daughterboard (included with the Evaluation Platform).

FN8013.5

23

ISL837030, ISL83740

A p p l i c a t i o n s

.

1.00k

Modem PCBA

270nH, 5%

I Ch. ADC

AD8132

1.00k

56.2

-

1.30k

+

Direct Down Convert

Baseband Output Amplifiers

15pF

5%

2x 3.9pF

85Msps

68pF

2%

I Data

-

+

56.2

1.00k

49.9

I Ch.

270nH, 5%

1.00V p-p

1.05V p-p

49.9

1.00k

1

3

5

7

2

4

6

8

49.9

Q Ch.

1.05V p-p

1.00k

270nH, 5%

2x 3.9pF

Q Ch. ADC

AD8132

1.00k

56.2

-

For Shorter Runs

-

+

-

1.30k

68pF

2%

15pF

5%

85Msps

Q Data

+

270nH, 5%

1.00V p-p

1.00k

FIGURE 16 Unbalanced Demodulator Baseband Interface, Shorter Runs

1.00k

Modem PCBA

270nH, 5%

I Ch. ADC

AD8132

1.00k

56.2

-

1.30k

+

-

Direct Down Convert

Baseband Output Amplifiers

15pF

5%

2x 3.9pF

85Msps

68pF

2%

I Data

+

56.2

1.00k

49.9

2.00V p-p

I Ch.

270nH, 5%

1.00V p-p

1.00k

1

3

5

7

2

4

6

8

52.3

24.9

49.9

Q Ch.

2.00V p-p

52.3

1.00k

270nH, 5%

2x 3.9pF

24.9

Q Ch. ADC

AD8132

1.00K

56.2

-

1.30k

+

For Longer Runs

15pF

5%

68pF

2%

85Msps

Q Data

-

+

56.2

270nH, 5%

1.00V p-p

1.00k

FIGURE 17 Unbalanced Demodulator Baseband Interface, Longer Runs

FN8013.5

24

ISL837030, ISL83740

Support

Note: In some cases, users may enter parameters outside of ranges listed in this document; however, only

listed ranges are supported.


型号：	ISL87060MIK
厂家：	Intersil
描述：	Modem Reference Designs 调制解调器参考设计调制解调器
文件：	总25页 (文件大小：596K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL87060MIK [INTERSIL]

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