ISL9221IRZ-T [INTERSIL]
Dual Input Lithium Ion Battery Charger with OVP USB Bypass and 10mA LDO; 双输入锂离子电池充电器，带OVP USB绕道和10毫安LDO
| 型号： | ISL9221IRZ-T |
| 厂家： | 
Intersil |
| 描述： | Dual Input Lithium Ion Battery Charger with OVP USB Bypass and 10mA LDO |
| 文件： | 总11页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL9221
®
Data Sheet
April 3, 2008
FN6541.1
Dual Input Lithium Ion Battery Charger
with OVP USB Bypass and 10mA LDO
Features
• Lithium Ion/Polymer battery charging
• Dual input - USB host or car/wall adapter
• Input voltage withstanding up to 28V
The ISL9221 Lithium Ion charging IC is designed to meet the
charging requirements of most of today’s handheld devices.
The IC provides two inputs for either USB connection where
the current is limited by the USB standard or for
• 5.4V overvoltage protection on VUSB inputs
• Charging current up to 1.2A
powering/charging from a power adapter.
If the voltage at either VUSB or VDC pin is within the safe
allowable range, the PPR pin is pulled low indicating to the
system processor that external power is available.
• 4.9V/10mA linear regulator with input OVP
• Current limit on bypass path
• Programmable end-of-charge current
• Programmable charging current
• Programmable USB current limit
• Charging and power present indicator pins
• Charge enable pin
Charging can be enabled/disabled by controlling the state of
the EN pin. While charging, the CHG pin is pulled low
indicating the battery is being charged.
The battery is charged to 4.2V with only a 1% error across
the temperature range. USB charge current, Adapter charge
current and charge termination currents can be programmed
via external resistors.
• Reverse current protection
The ISL9221 adds an additional feature in providing a limited
amount of current to system architecture while protecting the
system from destructively high voltage.
• Pb-free (RoHS compliant)
Applications
The device contains Thermal regulation and protection to
provide additional safety features of this device. When the
temperature exceeds +125°C, the current will fold back to
reduce and control the die temperature.
• Smart Handheld Devices
• Cell Phones, PDAs, MP3 Players
• Digital Still Cameras
• Handheld Test Equipment
Ordering Information
PART
NUMBER
(Note)
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
PART
TEMP.
PACKAGE
(Pb-Free)
PKG.
DWG. #
MARKING RANGE (°C)
ISL9221IRZ
9221
-40°C to +85°C 12 Ld 4x3 DFN L12.4x3
-40°C to +85°C 12 Ld 4x3 DFN L12.4x3
ISL9221IRZ-T* 9221
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach materials
and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which
is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
Pinout
ISL9221
(12 LD DFN)
TOP VIEW
VDC
VUSB
PPR
CHG
EN
1
2
3
4
5
6
12 VDC_LDO
BAT
11
10
9
USB_BYP
IVDC
GND
8
7
IMIN
IUSB
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL9221
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDC, VUSB). . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V
Other Input Voltage (EN, IMIN, IUSB, IVDC). . . . . . . . . . -0.3V to 7V
Open Drain Pull Voltage (PPR, CHG) . . . . . . . . . . . . . . .-0.3V to 7V
Other Pin Voltage(VDC_LDO, USB_BYP, VBAT) . . . . . .-0.3V to 7V
Thermal Resistance (Typical, Notes 1, 2)
θ
JA (°C/W)
θ
JC (°C/W)
3.5
4x3 DFN Package . . . . . . . . . . . . . . . . . . . . 41
Maximum Junction Temperature (Plastic Package)+ . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VUSB) . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.3V
Supply Voltage (VDC). . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 6.7V
Typical Adapter Charge Current . . . . . . . . . . . . . . . . 100mA to 1.2A
Typical USB Charge Current . . . . . . . . . . . . . . . . 46.5mA to 465mA
Typical USB Bypass Current . . . . . . . . . . . . . . . . . . . 0mA to 200mA
Typical LDO Current . . . . . . . . . . . . . . . . . . . . . . . . . . 0mA to 10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
3. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
Electrical Specifications Typical Values are tested at USB = VDC = 5V and ambient temperature at +25°C, unless otherwise noted. All
maximum and minimum values are guaranteed under the recommended operating conditions.
MIN
MAX
PARAMETERS
SYMBOL
CONDITIONS
(Note 3)
TYP
(Note 3) UNITS
CHARGER POWER-ON THRESHOLDS
Rising VUSB/VDC Threshold
3.4
3.2
3.9
3.7
4.2
4.0
V
V
Falling VUSB/VDC Threshold
INPUT VOLTAGE OFFSET
Rising Edge of VDC or VUSB Relative to
VBAT
VOSHC
VOSLC
VBAT = 4.0V, use CHG pin to indicate the
comparator output
-
150
80
250
-
mV
mV
Falling Edge of VDC or VUSB Relative
to VBAT
20
STANDBY CURRENT
BAT Pin Sink Current
ISTANDBY EN = HIGH or both inputs are floating
-
-
-
-
0.05
365
300
0.63
0.5
420
360
0.85
µA
µA
µA
mA
VDC Pin Supply Current
VUSB Pin Supply Current
VDC/USB Pin Supply Current
VOLTAGE REGULATION
Output Voltage
IVDC
EN = HIGH, ILDO = 0
IVUSB
EN = HIGH, USB_BYP disconnected
EN = LOW, ILDO = 0, USB_BYP disconnected
VBAT
Load = 10mA
4.158
4.2
4.2
4.242
V
Load = 10mA (TJ = +25°C)
4.174
4.226
V
VDC Linear ON-resistance
USB Linear ON-resistance
CHARGE CURRENT
V
V
BAT =3.8V, IVDC = 0.3A, (TJ = +25°C)
BAT =3.8V, IUSB = 0.3A, (TJ = +25°C)
-
-
600
600
-
-
mΩ
mΩ
IVDC Pin Output Voltage
VDC Constant Current Accuracy
VDC Trickle Charge Current
VIVDC
VBAT = 3.8V
1.19
500
16
1.22
550
18
1.25
580
20
V
mA
%
IVDC
_
RIVDC = 12.4kΩ, VBAT = 2.7V to 3.8V
CHRG
IVDC_TRKL RIVDC = 12.4kΩ, VBAT = 2.2V, given as a % of the
IVDC
_
CHARGE
FN6541.1
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ISL9221
Electrical Specifications Typical Values are tested at USB = VDC = 5V and ambient temperature at +25°C, unless otherwise noted. All
maximum and minimum values are guaranteed under the recommended operating conditions. (Continued)
MIN
MAX
PARAMETERS
IUSB Pin Output Voltage
SYMBOL
CONDITIONS
(Note 3)
TYP
1.22
232
18
(Note 3) UNITS
VIUSB
VBAT = 3.8V
RIUSB = 29.4kΩ,VBAT = 2.7V to 3.8V
1.19
211
16
1.25
246
20
V
mA
%
VUSB Constant Current Accuracy
VUSB Trickle Charge Current
IUSB_
CHRG
IUSB_TRKL RIUSB = 29.4kΩ, VBAT = 2.2V and if IUSB_CHRG
≤ IVDC_TRKL, then given as a % of the IUSB
If IUSB_CHRG ≤ IVDC_TRKL
RMIN = 10kΩ
_
CHRG
-
IUSB_CHRG
55
-
%
DC and USB End-of-Charge Threshold
IMIN
46.5
63.5
mA
PRECONDITIONING CHARGE THRESHOLD
Preconditioning Charge Threshold
Voltage
VMIN
2.5
3.8
2.6
3.9
2.7
4.0
V
V
RECHARGE THRESHOLD
Recharge Threshold Voltage
PROTECTIONS
VRCH
VDC Overvoltage Level
OVP
6.7
6.8
90
1
6.9
130
-
V
VDC Overvoltage Hysteresis
VDC Overvoltage Protection Delay
VUSB Overvoltage Level
VUSB Overvoltage Hysteresis
VUSB Overvoltage Protection Delay
Short Circuit (USB_BYP)
BYPASS FETS
HOVP
-
mV
µs
-
5.3
5.4
60
1
5.5
90
-
V
-
-
-
mV
µs
IOCP
400
600
mA
Resistance VUSB to USB_BYP
USB_
rDS(ON)
Measured at 200mA, 4.3V < VDC < 5.3V
-
-
1.3
2.0
-
Ω
Drop Out VUSB to USB_BYP
INTERNAL TEMPERATURE MONITORING
Current Fold Back Threshold
LOGIC INPUT AND OUTPUT
EN Pin Logic Input HIGH
VUSBDO IOUT = 150mA, VUSB > 4.3V
200
mV
TFOLD
-
125
-
°C
VIH
VIL
1.3
-
-
-
0.4
850
-
V
V
EN Pin Logic Input LOW
-
600
-
EN Pin Internal Pull-down Resistance
CHG and PRR Sink Current
LINEAR REGULATOR
350
10
kΩ
mA
Pin Voltage = 0.8V
Output Voltage
VLDO
-
4.94
-
V
%
%
Voltage Regulation Accuracy
VREG
Initial accuracy, ILDO = 10mA; TJ = +25°C
Line/Load, ILDO = 10µA to 10mA,
-2.0
-2.8
-
-
+2.0
+2.8
VDC = VLDO + 0.5V to 6.5V; TJ = -40°C to +125°C
ILDO = 10mA, VLDO= 4.9V, VDC > VLDO+0.5V
For ILDO = 10mA option, VDC = 5.5V
Dropout (VDC to VLDO
Current Limit
)
VDO
-
30
-
50
-
mV
mA
ILIMIT
12
FN6541.1
April 3, 2008
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ISL9221
Pin Assignments
NAME
PIN
1
TYPE
AI
DESCRIPTION
VDC
Input pin from car adapter or AC/DC adapter
Input pin from USB host device
Output pin of Linear Regulator
Output pin from USB bypass circuitry
Battery current setting pin for adapter power
Current setting pin for USB power
End-of-charge current setting pin
Output pin to battery
VUSB
VDC_LDO
USB_BYP
IVDC
2
AI
12
10
9
AO
AO
AI
IUSB
7
AI
IMIN
6
AI
BAT
11
5
AO
DI
EN
Active low charge enable pin
PPR
3
OD
OD
G
Active low power present indicator pin
Active low charging indication pin
Ground pad
CHG
4
GND
8
TABLE 1. TYPE CHART
DESCRIPTION
The maximum current drawn from the VUSB pin is the
combination of the load at USB_BYP and the programmed
USB charging current.
SYMBOL
A
D
Analog Pin
Digital Pin
Input Pin
A 1µF bypass capacitor is recommended on the VUSB pin.
Higher values of bypass capacitance can be utilized but the
designer should refer to the maximum allowed bus capacitance
per USB application standard. When using ceramic capacitors,
a small resistance value, such as 1Ω in series with the
capacitor, is recommended to reduce voltage overshoot.
I
O
Output Pin
Open-Drain
Ground
OD
G
IVDC
Adapter charging current setting pin. A resistor on this pin
sets the maximum charging current to be delivered to the
BAT pin. The maximum current, however, may be reduced
by the adapter’s current limit or by the power dissipation
within the charging IC.
Functional Pin Descriptions
VDC
Adapter input pin. This pin is usually connected to adapter
power. The maximum input voltage is 28V. The charge
current from this pin is programmable up to 1.2A by selection
of the resistor on the IVDC pin. When this pin is connected to
a power source, no charge current is drawn from the USB
pin. A 1µF or larger value ceramic capacitor is
IUSB
USB charge current pin. This pin is connected internally to a
current source for setting the programmed charging current
delivered to the BAT pin.
recommended for decoupling.
BAT
VDC_LDO
Charger IC output pin. This pin is to be connected to the
positive (+) terminal of the battery. The charging IC monitors
this pin to determine the charge state of the battery.
Linear regulator output. A 0.1µF to 1µF ceramic capacitor
from this pin to ground is required.
USB_BYP
A 1µF bypass capacitor from the BAT pin to ground is
recommended. The charging IC relies on the battery to help
stabilize the circuitry and it is not recommended to operate
the charger IC without a battery connected to this pin.
USB input bypass pin. This is an output from the low current
bypass FET connected to the USB input pin. The USB_BYP
can be connected to the system to provide safe,
voltage-limited power from the USB input pin.
EN
VUSB
Enable charging pin. This pin is a logic level input to control
charging by the system processor. An external pull-up
resistor should be connected to processor’s I/O power
supply.
VUSB Input pin. This pin is usually connected to a USB port
power connector. The maximum input voltage is 28V.
However, the internal OVP circuitry will trip at 5.4V.
FN6541.1
April 3, 2008
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ISL9221
The USB_BYP and VDC_LDO stay on regardless of the
state of this pin. This ensures that the processor can be
powered up when an external source is connected to the
VDC or VUSB input pin.
CHG
Charge indication pin. This open-drain pin is pulled low to
indicate when the battery is being charged. If connected to
the processor, a pull-up resistor should be connected to the
processors I/O supply.
PPR
Power presence indication pin. This pin is used to notify the
system processor or enable the power circuitry when a
source is connected. The pin is an open drain output pin,
which pulls low when a valid voltage (above POR) is present
at either the VDC or VUSB pin. The PPR pin is held low
regardless of the state of the EN pin. If connected to the
processor, a pull-up resistor should be connected to the
processors I/O supply. If connected to power circuitry, a
pull-up should be tied to the appropriate bypass supply.
The CHG pin can also be used to drive an LED to indicate to
the user the battery is being charged.
GND
Ground pin. This provides the ground path for all internal
circuits.
Typical Application
OFF
LDO OUTPUT
ON
TO MCU
VDC INPUT
VDC
TO BATTERY
BAT
ISL9221
USB INPUT
VUSB
GND
USB_BYP
FN6541.1
April 3, 2008
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ISL9221
Block Diagram
LDO
LDO
BYPASS
USB_BYP
BAT
4.35V TO 6.5V
VDC
+
-
VMIN
VRCH
CC/CV
2.6V
3.9V
4.2V
+
-
4.35V TO 5.25V
VUSB
THERM
+
-
6.8VOVP
150/80mV
+
VOS
-
VOLTAGE/CURRENT CONTROLLER
5.4VOVP
+
VDC
VOS
-
+
VUSB
EN
IUSB
+
-
I/O CNTL
PPR
+
-
IDC
CHG
IMIN
+
-
1.22V
GND
FIGURE 1. SIMPLIFIED BLOCK DIAGRAM
Otherwise, the period to charge the battery may be
prolonged.
USB Charge Current
When the EN pin is pulled low and a valid USB voltage is
present at the USB pin, the IC will charge the battery at a
rate dependent on the IUSB setting. The charge current
maybe reduced by the USB source if it is set to a value
higher than the current limit of the USB source.
Adapter Charge Current
When the EN pin is pulled low and a valid adapter voltage is
present at the VDC pin, the IC will charge the battery at a
rate dependent on the IVDC setting; the charge on the
battery and the source connected to the VDC pin. An
example of this is while the IVDC is set for 1000mA, the
adapter supply may only provide 800mA and the battery is
limited to the 800mA.
Equation 1 for setting the IUSB current is as follows:
6820
-----------------
IUSB
IUSB =
(mA)
(EQ. 1)
R
Where RIUSB is in kΩ.
Typically the rDS(ON) across the charge path, VDC to BAT is
600mΩ. At a 1.0A charging rate, 600mV is dropped across
the charge path. Thus, the voltage at the VDC pin needs to
be maintained above ~4.80V. Otherwise the period to charge
the battery may be prolonged.
The current set by the IUSB pin for charging the battery is in
addition to current drawn by the load on the USB_BYP. The
system designer should consider the maximum expected
USB_BYP load current when selecting the USB charging
current so as not to exceed the current limits set by the USB
standards.
6820
-----------------
IVDC =
(mA)
(EQ. 2)
R
IVDC
Typically at room temperature, the rDS(ON) across the charge
path, VUSB to BAT is 600mΩ. If the entire USB current limit
of 465mA is being supplied to the battery, the drop across
the charging FET could be more than 300mV. Thus, the
voltage at the USB pin needs to be maintained above ~4.5V.
Where RIVDC is in kΩ.
It is recommended that the maximum charging current be
programmed to between 100mA and 1200mA.
FN6541.1
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ISL9221
Floating Charge Voltage
Power-Good Condition
The floating voltage during the constant voltage phase is
4.2V. The floating voltage has 1% accuracy over the ambient
temperature range of -40°C to +85°C.
Even if there is a power present at one of the power input
pins, the charger will not deliver power to the battery for
charging if three of the conditions below are not met:
• VDC or VUSB > V
POR
Trickle Charge Current
When the battery voltage is below 2.7V (VBATmin), the
charger operates in trickle/preconditioning mode, where the
charge current is typically 18% of the programmed current
set by RIVDC.
• VDC or VUSB - V
> VOS
BAT
• VDC or VUSB < V
OVP
Where VPOR is the power on reset voltage and VOS is the
offset voltage of the input-to-output comparator. All of these
voltages have hysteresis, as given in the “Electrical
Specifications” table on page 2.
End-of-Charge Indication
When an EOC condition (charge current falls below IMIN
during constant-voltage charging) is encountered, the
internal open-drain MOSFET at the CHG pin turn-off.
POR_DLY
6.8VOVP
OVP- HOVP
IMIN threshold is programmable by the resistor RIMIN at the
IMIN pin for both adapter and USB inputs. If the
programmed fast charge current is less than IMIN, then after
the de-bounce period for VBAT = VBATmax expires, EOC
occurs. Once EOC is reached, the status is latched and can
be reset by one of the following conditions:
POR
VDC
5.4V OVP
OVP- HOVP
POR
VUSB
• The part is disabled and re-enabled
• The selected input source is removed and reapplied
PPR
• The BAT pin voltage falls below the recharge threshold
(~3.9V)
ENABLE ACTIVE
EN
IMIN
IMIN sets the charge termination current for EOC (End-of-
CHG
Charge). IMIN can be calculated by Equation 3:
550
ILDO + ICHG
----------------
IMIN =
(mA)
(EQ. 3)
R
IMIN
ILDO
IVDC
Where RIMIN is in kΩ. IMIN is applicable for both adapter and
IUSB_BYP + ICHRG
USB charging.
IUSB_BYP
IVUSB
Power Presence Indication
When either the Adapter power or USB is above the POR
threshold, the PPR internal Open-Drain MOSFET pulls the
pin low indicating that there is a valid source on one of the
power input pins.
VBAT
If only one source is connected and it is above VOVP or both
sources are connected and both exceed VOVP, the PPR will
be released (HIGH) indicating that the voltage at the pin(s) is
invalid. If one input is valid while the other isn’t, the PPR pin
will be pulled low.
USB_BYP
4.94V
0V
VDC_LDO
™
FIGURE 2. . CHARGING PROFILE
Thermal Fold Back (Thermaguard )
The thermal fold back function reduces the charge current
when the internal temperature reaches the thermal foldback
threshold, which is typically +125°C. This protects the
charger from excessive thermal stress at high input voltages.
Input Bypass Capacitors
Due to the wall or car power adapter power lead inductance,
the VDC input capacitor type must be properly selected to
prevent high voltage transient during a hot-plug event. This
is also true for the USB input capacitor. A tantalum capacitor
is a good choice for its high ESR, providing damping to the
voltage transient. Multi-layer ceramic capacitors, however
FN6541.1
April 3, 2008
7
ISL9221
have a very low ESR and hence when chosen as input
capacitors, a 1Ω series resistor must be placed between the
capacitor and ground, as shown in the Typical Applications
Section, to provide adequate damping.
Fault Summary
If VDC is greater than 6.8V, then the VDC_LDO and
charging FETs are turned off until VDC < VOVP - HOVP
(Where HOVP is the OVP hysteresis). PPR will be asserted
high (off), unless VUSB is valid.
If VUSB is greater than 5.4V, then the VUSB bypass and
charging FETs are turned off until VUSB < VOVP - HOVP. PPR
will be asserted high (off), unless VDC is valid.
CHG
CHARGE
DISABLE
EN
CHARGE ENABLE
If the load on VUSB_BYP exceeds 400mA, the FET will be
current limited to protect the load and the IC.
VMAX
VRCH
IMAX
If VUSB_BYP > VUSB, USB Bypass FET is turned off.
VMIN
VBAT
State Diagram
The state diagram for the charger functions is shown in
Figure 4. The diagram starts with the Power-off state. When
at least one input voltage rises above the POR threshold, the
charger resets itself. If both input voltages are above the
POR threshold, the charger selects the VDC input as the
power source. Then if the EN pin is at a logic HIGH voltage,
the charger will stay in the disabled state. If the EN pin is
LOW or is brought LOW charging begins. Any time the EN
pin is asserted high, the charger returns to the disabled
state. When the EOC condition is reached, the CHG will turn
to a logic HIGH to indicate a charge complete status but
charging will continue.
0.18*IMAX
IMIN
ICHG
EOC
FIGURE 3. TIMING DIAGRAM
FN6541.1
April 3, 2008
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ISL9221
VDC BAD,
VUSB GOOD
VDC = GOOD, IF VPOR < VDC < 6.8V
VUSB = GOOD, IF VPOR < VUSB < 5.4V
POWER OFF
CHARGER: OFF
PPR: OFF
CHG: OFF
LDO: OFF
BYP: OFF
VOVP < VDC,
VUSB BAD
VDC BAD,
VOVP < VUSB
VDC GOOD,
VUSB GOOD
EN = HI
VDC GOOD,
VUSB BAD
EN = HI
VDC BAD,
VUSB GOOD
EN = HI
POR
VDC INPUT
CHARGER: OFF
PPR: ON
CHG: OFF
LDO: ON
NOT
ENABLED,
EN = HI
NOT
ENABLED,
EN = HI
POR
POR
VDC INPUT
CHARGER: OFF
PPR: ON
USB INPUT ONLY
CHARGER: OFF
PPR: ON
BYP: ON
CHG: OFF
LDO: OFF
CHG: OFF
LDO: ON
BYP: ON
BYP: OFF
VBAT < VMIN,
EN = LOW
VDC GOOD,
VOVP < VUSB
VOVP < VDC,
VUSB GOOD
TRICKLE CHARGE
CHARGER: ON
PPR: ON
CHG: ON
OVP
OVP
USB INPUT ONLY
CHARGER: OFF
PPR: OFF
VDC INPUT SELECTED
CHARGER: OFF
PPR: OFF
LDO: ON (IF VDC GOOD)
BYP: ON (IF VUSB GOOD)
CHG: OFF
CHG: OFF
LDO: OFF
LDO: OFF
BYP: OFF
BYP: OFF
VMIN < VBAT < VMAX,
EN = LOW
VMIN < VBAT < VMAX,
EN = LOW
VMIN < VBAT
VDC BAD
FAST CHARGE
FAST CHARGE
@ IUSB
CHARGER: ON
PPR: ON
@ IVDC
CHARGER: ON
PPR: ON
CHG: ON
CHG: ON
LDO: OFF
BYP: ON
LDO: ON
BYP: ON (IF VUSB GOOD)
VDC GOOD
RECHARGE
CONDITION MET,
VBAT < VRCH
VMAX = VBAT,
EN = LOW
CHARGE COMPLETE
CHARGER: ON
VMAX = VBAT,
EN = LOW
VMAX = VBAT,
VMAX = VBAT,
PPR: ON
EN = HI
EN = HI
CHG: OFF
LDO: ON (IF VDC GOOD)
BYP: ON (IF VUSB GOOD)
FIGURE 4. STATE DIAGRAM FOR CHARGER FUNCTIONS
FN6541.1
April 3, 2008
9
ISL9221
Logic Function State Table
VDC INPUT
USB INPUT
PGOOD,
PGOOD,
BAT
CHARGING
VDC_LDO
OUTPUT
V
< V
V
< VDC
V
> V
V
< V
V
<VUSB
V
> V
OVP
EN
PPR
CHG
USB_BYP
IN
POR
POR
IN
OVP
IN
POR
POR
IN
< V
< V
OVP
OVP
X
X
X
X
Don’t
Care
Hi Z
Hi Z
No,
Reverse
Blocked
No,
Reverse
Blocked
No,
Reverse
Blocked
X
X
Yes
Low
Low
Low
Low
Low
Low
Low
Yes, USB
Charging
No,
reverse
blocked
Yes
Yes
X
X
X
X
Yes, VDC
Charging
Yes
No,
Reverse
Blocked
Yes
Yes
Yes
Low
Low
Low
Hi Z
Yes, VDC
Charging
Yes
Yes
Yes
High
No,
No,
(Disables
Charging)
Reverse
Blocked
Reverse
Blocked
X
X
Yes
Yes
High
(Disables
Charging)
Low
Low
Hi Z
Hi Z
No,
Reverse
Blocked
No,
reverse
blocked
Yes
Yes
Yes
High
No,
Yes
(Disables
Charging)
Reverse
Blocked
NOTES:
4. ”X” denotes that the input is either less than VPOR or greater than VOVP
5. VDC_VOVP is a nominal 6.8V
6. VUSB_VOVP is a nominal 5.4V
FN6541.1
April 3, 2008
10
ISL9221
Dual Flat No-Lead Plastic Package (DFN)
L12.4x3
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-229-VGED-4 ISSUE C)
2X
0.15
C
A
A
D
MILLIMETERS
2X
SYMBOL
MIN
0.80
NOMINAL
0.90
MAX
1.00
NOTES
0.15
C B
A
A1
A3
b
-
-
0.18
3.15
1.55
-
0.05
-
0.20 REF
0.23
-
E
6
0.30
3.40
1.80
5,8
INDEX
AREA
D
4.00 BSC
3.30
-
D2
E
7,8
TOP VIEW
B
3.00 BSC
1.70
-
E2
e
7,8
0.50 BSC
-
-
// 0.10
0.08
C
k
0.20
0.30
-
-
A
L
0.40
0.50
8
C
N
12
2
SIDE VIEW
D2
A3
C
Nd
6
3
SEATING
PLANE
Rev. 1 2/05
NOTES:
7
8
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
(DATUM B)
D2/2
3. Nd refers to the number of terminals on D.
1
2
6
4. All dimensions are in millimeters. Angles are in degrees.
INDEX
AREA
NX k
E2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
(DATUM A)
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
E2/2
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
NX L
N
N-1
e
NX b
0.10
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
8
5
(Nd-1)Xe
REF.
M
C A B
BOTTOM VIEW
C
L
(A1)
NX (b)
5
L
e
SECTION "C-C"
TERMINAL TIP
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6541.1
April 3, 2008
11
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