IS61C256AL-12TLI [ISSI]
32K x 8 HIGH-SPEED CMOS STATIC RAM; 32K ×8高速CMOS静态RAM![IS61C256AL-12TLI](http://pdffile.icpdf.com/pdf1/p00113/img/icpdf/IS61C256AL_615505_icpdf.jpg)
型号: | IS61C256AL-12TLI |
厂家: | ![]() |
描述: | 32K x 8 HIGH-SPEED CMOS STATIC RAM |
文件: | 总12页 (文件大小:98K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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®
IS61C256AL
ISSI
32K x 8 HIGH-SPEED CMOS STATIC RAM
OCTOBER2006
DESCRIPTION
FEATURES
The ISSI IS61C256AL is a very high-speed, low power,
32,768 word by 8-bit static RAMs. It is fabricated using
ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques,yieldsaccesstimesasfastas10nsmaximum.
• High-speed access time: 10, 12 ns
• CMOS Low Power Operation
— 1 mW (typical) CMOS standby
— 125 mW (typical) operating
• Fully static operation: no clock or refresh
required
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 150 µW (typical) with CMOS input levels.
• TTL compatible inputs and outputs
• Single 5V power supply
• Lead-free available
Easy memory expansion is provided by using an active
LOW Chip Enable (CE) input and an active LOW Output
Enable (OE) input. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
TheIS61C256ALispincompatiblewithother32Kx8SRAMs
and are available in 28-pin SOJ and TSOP (Type I)
packages.
FUNCTIONAL BLOCK DIAGRAM
32K X 8
MEMORY ARRAY
A0-A14
DECODER
VDD
GND
I/O
DATA
CIRCUIT
COLUMN I/O
I/O0-I/O7
CE
CONTROL
CIRCUIT
OE
WE
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. B
10/23/06
®
IS61C256AL
ISSI
PIN CONFIGURATION
28-Pin SOJ
PIN CONFIGURATION
28-Pin TSOP
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
WE
A13
A8
OE
A11
A9
22
23
24
25
26
27
28
1
2
3
4
5
21
A10
CE
2
20
19
18
17
16
15
14
13
12
11
10
9
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
3
A8
A6
4
A13
WE
VDD
A14
A12
A7
A6
A5
A4
A3
A5
5
A9
A4
6
A11
OE
A3
7
A2
8
A10
CE
A1
9
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
6
7
A1
A2
I/O0
I/O1
I/O2
GND
8
PIN DESCRIPTIONS
TRUTH TABLE
Mode
WE
CE OE I/O Operation VDD Current
A0-A14
CE
Address Inputs
Not Selected
(Power-down)
X
H
X
High-Z
ISB1, ISB2
Chip Enable Input
Output Enable Input
Write Enable Input
Bidirectional Ports
Power
OE
Output Disabled H
L
L
L
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
WE
Read
Write
H
L
I/O0-I/O7
VDD
X
GND
Ground
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TSTG
PT
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Value
Unit
V
°C
–0.5 to +7.0
–65 to +150
1.5
Power Dissipation
W
IOUT
DC Output Current (LOW)
20
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
10/23/06
®
IS61C256AL
ISSI
OPERATING RANGE
Range
AmbientTemperature
Speed(ns)
VDD (V)
5V 5%
5V 10%
5V 10%
Commercial
Commercial
Industrial
0°C to +70°C
0°C to +70°C
–40°Cto+85°C
-10
-12
-12
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
TestConditions
Min.
2.4
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –4.0 mA
VDD = Min., IOL = 8.0 mA
—
0.4
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage(1)
InputLeakage
—
V
2.2
VDD + 0.5
0.8
V
–0.3
V
GND ≤ VIN ≤ VDD
Com.
Ind.
–1
–2
1
2
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD,
OutputsDisabled
Com.
Ind.
–1
–2
1
2
µA
Note: 1. VIL = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-10
-12
Symbol
Parameter
DDOperating
SupplyCurrent
DD DynamicOperating
TestConditions
DD =Max.,CE=VIL
OUT =0mA,f=0
DD =Max.,CE=VIL
IOUT =0mA,f=fMAX
Min. Max.
Min. Max.
Unit
I
CC
1
V
V
I
Com.
Ind.
—
—
20
—
—
—
20
25
mA
I
CC
2
V
V
Com.
Ind.
—
—
45
—
—
—
35
40
mA
SupplyCurrent
typ.(2)
25
I
SB
1
TTLStandbyCurrent
(TTLInputs)
V
V
CE
DD =Max.,
IN =VIH orVIL
IH,f=0
Com.
Ind.
—
—
1
—
—
—
1
2
mA
µA
≥ V
ISB
2
CMOSStandby
Current(CMOSInputs)
VDD =Max.,
Com.
Ind.
—
—
350
—
—
—
200
350
450
CE
≥
≥
V
DD –0.2V,
VIN
VDD –0.2V,or
typ.(2)
V
IN
≤
0.2V, f=0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 5V, TA = 25oC and not 100% tested.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
8
Unit
pF
Input Capacitance
Output Capacitance
COUT
VOUT = 0V
10
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
3
Rev. B
10/23/06
®
IS61C256AL
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-10 ns
-12 ns
Symbol
tRC
Parameter
Min. Max
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address Access Time
Output Hold Time
CE Access Time
OE Access Time
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
CE toPower-Up
10
—
2
—
10
—
10
6
12
—
2
—
12
—
12
6
tAA
tOHA
tACS
—
—
0
—
—
0
tDOE
(2)
tLZOE
—
5
—
6
(2)
tHZOE
—
2
—
3
(2)
tLZCS
—
5
—
7
(2)
tHZCS
—
0
—
0
(3)
tPU
—
10
—
12
(3)
tPD
CEtoPower-Down
—
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0V to 3.0V
3 ns
Input and Output Timing
andReferenceLevels
1.5V
OutputLoad
See Figures 1 and 2
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
255 Ω
5 pF
255 Ω
30 pF
Including
jig and
Including
jig and
scope
scope
Figure 2
Figure 1
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
10/23/06
®
IS61C256AL
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACS
CE
t
HZCS
t
LZCS
HIGH-Z
DOUT
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
5
Rev. B
10/23/06
®
IS61C256AL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-10ns
Min.
-12 ns
Min. Max.
Symbol
tWC
Parameter
Max
—
Unit
ns
Write Cycle Time
CE to Write End
10
9
12
10
10
—
—
—
tSCS
—
ns
tAW
Address Setup Time
to Write End
9
—
ns
tHA
AddressHold
from Write End
0
—
0
—
ns
tSA
Address Setup Time
0
9
—
—
—
—
—
6
0
9
—
—
—
—
—
6
ns
ns
ns
ns
ns
ns
ns
tPWE1
tPWE2
tSD
WE Pulse Width (OE LOW)
WE Pulse Width (OE HIGH)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
8
8
7
7
tHD
0
0
(2)
tHZWE
—
0
—
0
(2)
tLZWE
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t
WC
VALID ADDRESS
SCS
ADDRESS
t
SA
t
t
HA
CE
t
AW
t
tPPWWEE21
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR1.eps
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
10/23/06
®
IS61C256AL
ISSI
WRITE CYCLE NO. 2(OE is HIGH During Write Cycle) (1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR2.eps
WRITE CYCLE NO. 3(OE is LOW During Write Cycle) (1)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
LOW
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE
≥ VIH.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev. B
10/23/06
®
IS61C256AL
ISSI
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter
DD forDataRetention
TestCondition
Min. Typ.(1)
Max. Unit
VDR
V
SeeDataRetentionWaveform
2.0
5.5
V
IDR
DataRetentionCurrent
V
DD =2.0V,CE≥VDD –0.2V
Com.
Ind.
—
—
50
90
100
µA
VIN ≥ VDD – 0.2V, or VIN
≤
VSS + 0.2V
t
SDR
DataRetentionSetupTime
RecoveryTime
SeeDataRetentionWaveform
SeeDataRetentionWaveform
0
—
—
ns
ns
tRDR
t
RC
Note:
1. Typical Values are measured at VDD = 5V, T
= 25oC and not 100% tested.
A
DATA RETENTION WAVEFORM (CE Controlled)
t
Data Retention Mode
t
RDR
SDR
VDD
4.5V
2.2V
V
DR
CE ≥ VDD - 0.2V
CE
GND
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
10/23/06
®
IS61C256AL
ISSI
ORDERING INFORMATION: IS61C256AL
Commercial Range: 0°C to +70°C
Speed (ns)
Order Part Number
Package
10
IS61C256AL-10J
IS61C256AL-10JL
IS61C256AL-10T
IS61C256AL-10TL
300-mil Plastic SOJ
300-mil Plastic SOJ, Lead-free
TSOP (Type 1)
TSOP (Type 1), Lead-free
12
IS61C256AL-12J
IS61C256AL-12JL
IS61C256AL-12T
IS61C256AL-12TL
300-mil Plastic SOJ
300-mil Plastic SOJ, Lead-free
TSOP (Type 1)
TSOP (Type 1), Lead-free
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part Number
Package
12
IS61C256AL-12JI
IS61C256AL-12JLI
IS61C256AL-12TI
IS61C256AL-12TLI
300-mil Plastic SOJ
300-mil Plastic SOJ, Lead-free
TSOP (Type 1)
TSOP (Type 1), Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
9
Rev. B
10/23/06
®
PACKAGING INFORMATION
300-mil Plastic SOJ
Package Code: J
ISSI
N
E1
E
1
SEATING PLANE
D
A
A2
B
C
e
b
A1
E2
Notes:
1. Controlling dimension: inches, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash
protrusionsandshouldbemeasuredfromthebottomof
MILLIMETERS
INCHES
Min. Typ. Max.
Sym. Min. Typ. Max.
N0.
thepackage
.
4. Formed leads shall be planar with respect to one
another within 0.004 inches at the seating plane.
Leads
24/26
A
—
—
—
—
—
—
—
—
—
—
—
3.56
—
—
—
—
—
—
—
—
—
—
—
—
0.140
—
A1
A2
b
0.64
2.41
0.41
0.66
0.20
17.02
8.26
7.49
6.27
0.025
0.095
0.016
0.026
0.008
0.670
0.325
0.295
0.247
2.67
0.51
0.81
0.25
17.27
8.76
7.75
7.29
0.105
0.020
0.032
0.010
0.680
0.345
0.305
0.287
B
C
D
E
E1
E2
e
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/25/03
®
PACKAGING INFORMATION
300-mil Plastic SOJ
Package Code: J
ISSI
MILLIMETERS
INCHES
MILLIMETERS
INCHES
Sym. Min. Typ. Max.
Min. Typ. Max.
Sym. Min. Typ. Max.
Min. Typ. Max.
N0.
N0.
Leads
28
Leads
32
A
—
—
—
—
—
—
—
—
—
—
—
3.56
—
—
—
—
—
—
—
—
—
—
—
—
0.140
—
A
—
—
—
—
—
—
—
—
—
—
—
3.56
—
—
—
—
—
—
—
—
—
—
—
—
0.140
—
A1
A2
b
0.64
2.41
0.41
0.66
0.20
18.29
8.26
7.49
6.27
0.025
0.095
0.016
0.026
0.008
0.720
0.325
0.295
0.247
A1
A2
b
0.64
2.41
0.41
0.66
0.20
20.83
8.26
7.49
6.27
0.025
0.095
0.016
0.026
0.008
0.820
0.325
0.295
0.247
2.67
0.51
0.81
0.25
18.54
8.76
7.75
7.29
0.105
0.020
0.032
0.010
0.730
0.345
0.305
0.287
2.67
0.51
0.81
0.25
21.08
8.76
7.75
7.29
0.105
0.020
0.032
0.010
0.830
0.345
0.305
0.287
B
B
C
C
D
D
E
E
E1
E2
e
E1
E2
e
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.D
02/25/03
®
PACKAGINGINFORMATION
ISSI
Plastic TSOP - 28-pins
Package Code: T (Type I)
1
E
H
N
D
SEATING PLANE
A
S
L
α
e
B
C
A1
Plastic TSOP (T—Type I)
Millimeters
Inches
Symbol
Min
Max
Min
Max
Ref. Std.
No. Leads
Notes:
28
1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and
A
A1
B
C
D
E
H
e
1.00
0.05
0.16
0.10
7.90
11.70
13.20
0.55 BSC
1.20
0.20
0.27
0.20
8.10
0.037
0.002
0.006
0.004
0.308
0.456
0.515
0.047
0.008
0.011
0.008
0.316
0.465
0.531
should be measured from the bottom of the package
.
4. Formed leads shall be planar with respect to one another within
0.004 inches at the seating plane.
11.90
13.60
0.022 BSC
L
0.30
0.70
0.011
0.027
α
0°
5°
0°
5°
Integrated Silicon Solution, Inc.
PK13197T28 Rev. B 01/31/97
相关型号:
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