IS62VV25616LL-85TI [ISSI]
256K x 16 LOW VOLTAGE, 1.8V ULTRA LOW POWER CMOS STATIC RAM; 256K ×16低电压， 1.8V超低功耗CMOS静态RAM
| 型号： | IS62VV25616LL-85TI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 256K x 16 LOW VOLTAGE, 1.8V ULTRA LOW POWER CMOS STATIC RAM |
| 文件： | 总10页 (文件大小：56K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS62VV25616LL
ISSI
AUGUST2002
256K x 16 LOW VOLTAGE, 1.8V ULTRA
LOW POWER CMOS STATIC RAM
FEATURES
DESCRIPTION
The ISSI IS62VV25616LL is a high-speed, 4,194,304 bit
static RAMs organized as 262,144 words by 16 bits. They
are fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
• High-speed access time: 70, 85, ns
• CMOS low power operation
– 36 mW (typical) operating
– 9 µW (typical) CMOS standby
• Single 1.7V- 2.25 VDD power supply
For the IS62VV25616LL, when CE is HIGH (deselected)
or CE is low and both LB and UB are HIGH, the device
assumes a standby mode at which the power dissipation
can be reduced down with CMOS input levels.
• Fully static operation: no clock or refresh
required
• Three state outputs
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
• Data control for upper and lower bytes
• Industrialtemperatureavailable
• Available in the 44-pin TSOP (Type II) and
48-pin mini BGA (7.2mm x 8.7mm)
The IS62VV25616LL is packaged in the JEDEC standard
44-pin TSOP(Type II) and 48-pin mini BGA (7.2mm x 8.7mm).
FUNCTIONAL BLOCK DIAGRAM
256K x 16
MEMORY ARRAY
A0-A17
DECODER
VDD
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany
publishedinformationandbeforeplacingordersforproducts.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
1
08/07/02
®
IS62VV25616LL
ISSI
PIN CONFIGURATIONS
44-Pin TSOP (Type II)
48-Pin mini BGA (7.2mm x 8.7mm)
1
2
3
4
5
6
A4
A3
A2
A1
A0
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
2
3
4
5
CE
6
A0
A3
A1
A4
A2
LB
OE
UB
N/C
A
B
C
D
E
F
I/O0
I/O1
I/O2
I/O3
7
8
I/O
CE
I/O
0
8
9
I/O
I/O
A5
A6
I/O
I/O
2
9
10
1
10
11
12
13
14
15
16
17
18
19
20
21
22
VDD
GND
A17
NC
A14
A12
A9
A7
I/O
I/O
I/O
I/O
I/O
VDD
11
3
4
5
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
VDD
GND
V
DD
A16
A15
A13
A10
12
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A17
I/O
I/O
I/O
I/O
6
14
13
NC
A8
WE
I/O
7
15
G
H
NC
A11
NC
PIN DESCRIPTIONS
A0-A17
I/O0-I/O15
CE
Address Inputs
LB
Lower-byte Control (I/O0-I/O7)
Upper-byteControl(I/O8-I/O15)
NoConnection
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
UB
NC
OE
VDD
GND
Power
WE
Ground
TRUTH TABLE
I/O PIN
Mode
WE
CE
OE
LB
UB
I/O0-I/O7
I/O8-I/O15
VddCurrent
Not Selected
X
X
H
L
X
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
OutputDisabled
Read
H
X
L
L
H
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
ICC
ISB1, ISB2
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
Write
L
L
L
L
L
L
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
ICC
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/07/02
®
IS62VV25616LL
ISSI
OPERATING RANGE
Range
AmbientTemperature
VDD
Commercial
Industrial
0°C to +70°C
1.7V - 2.25V
1.7V - 2.25V
–40°Cto+85°C
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
VDD
Parameter
Value
–0.2 to VDD+0.25
–0.2 to +2.5
–65 to +150
1.0
Unit
V
Terminal Voltage with Respect to GND
Vdd Related to GND
V
TSTG
PT
StorageTemperature
°C
W
PowerDissipation
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
TestConditions
IOH = -0.1 mA
IOL = 0.1 mA
Min.
1.4
—
Max.
Unit
V
VOH
VOL
VIH
OutputHIGHVoltage
—
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage
InputLeakage
0.2
V
1.4
–0.3
–1
VDD + 0.2
V
(1)
VIL
ILI
0.4
1
V
GND ≤ VIN ≤ VDD
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
Notes:
1. VIL (min.) = –1.0V for pulse width less than 10 ns.
CAPACITANCE(1)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
8
Unit
Input Capacitance
Input/Output Capacitance
pF
pF
COUT
VOUT = 0V
10
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
3
08/07/02
®
IS62VV25616LL
ISSI
AC TEST CONDITIONS
Parameter
Unit
0.4V to VDD - 0.2V
5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
andReferenceLevel
0.9V
OutputLoad
See Figures 1 and 2
AC TEST LOADS
3070 Ω
3070 Ω
2.8V
2.8V
OUTPUT
OUTPUT
3150 Ω
3150 Ω
30 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figure 1
Figure 2
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/07/02
®
IS62VV25616LL
ISSI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-70
-85
Symbol
Parameter
Test Conditions
Min. Max.
Min. Max.
Unit
ICC
Vdd Dynamic Operating VDD = Max.,
Com.
Ind.
—
—
30
35
—
—
30
35
mA
Supply Current
I
OUT = 0 mA, f = fMAX
DD = Max.,
OUT = 0 mA, f = 1 MH
ICC1
ISB1
Operating Supply
Current
V
I
Com.
Ind.
—
—
3
3
—
—
3
3
mA
mA
Z
TTL Standby Current
(TTL Inputs)
V
V
DD = Max.,
IN = VIH or VIL
Com.
Ind.
—
—
0.3
0.3
—
—
0.3
0.3
CE
≥ VIH , f = 0
OR
ULBControl
Vdd = Max., VIN = VIH or VIL
CE = VIL, f = 0, UB = VIH, LB = VIH
ISB2
CMOS Standby
Current (CMOS Inputs) CE
V
DD = 1.95V.,
Com.
Ind.
—
—
10
10
—
—
10
10
µA
≥
≥
≤
V
V
DD – 0.2V,
DD – 0.2V, or
0.2V, f = 0
V
V
IN
IN
OR
ULBControl
VDD = 1.95V., CE = VIL
IN ≤ 0.2V, f = 0; UB / LB = VDD – 0.2V
V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-70
Min.
-85
Min.
Symbol
tRC
Parameter
Max.
—
Max.
Unit
Read Cycle Time
70
—
10
—
—
—
5
85
—
10
—
—
—
5
—
85
—
85
40
25
—
25
—
85
25
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
Output Hold Time
CE Access Time
70
—
tOHA
tACE
70
35
25
—
tDOE
OE Access Time
(2)
tHZOE
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
(2)
tLZOE
(2)
tHZCE
0
25
—
0
(2)
tLZCE
10
—
0
10
—
0
tBA
70
25
—
tHZB
tLZB
0
0
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V and
outputloadingspecifiedinFigure1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
5
08/07/02
®
IS62VV25616LL
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CE, OE, AND UB/LB Controlled)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
LZOE
ACE
t
CE
t
t
HZCE
t
LZCE
LB, UB
t
BA
t
HZB
t
LZB
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/07/02
®
IS62VV25616LL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-70
-85
Min. Max.
Symbol
tWC
Parameter
Min. Max.
Unit
1ns
ns
Write Cycle Time
70
65
65
0
—
—
—
—
—
—
—
—
—
30
—
85
70
70
0
—
—
—
—
—
—
—
—
—
30
—
tSCE
tAW
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
ns
tHA
ns
tSA
0
0
ns
tPWB
tPWE
tSD
LB, UB Valid to End of Write
WE Pulse Width
60
55
30
0
70
60
35
0
ns
ns
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
ns
tHD
ns
(3)
tHZWE
—
5
—
5
ns
(3)
tLZWE
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V and
outputloadingspecifiedinFigure1.
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
anyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfallingedgeofthesignalthatterminatesthewrite.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCS
ADDRESS
t
SA
t
t
HA
CE
t
AW
PWE1
PWE2
t
t
WE
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CSWR1.eps
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of
the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
7
08/07/02
®
IS62VV25616LL
ISSI
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CSWR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
LOW
CE
t
t
AW
t
PWE2
WE
t
SA
t
PBW
UB, LB
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CSWR3.eps
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/07/02
®
IS62VV25616LL
ISSI
WRITE CYCLE NO. 4 (UB/LB Controlled)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
CE
t
SA
LOW
t
HA
SA
t
HA
t
WE
t
PBW
t
PBW
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CSWR4.eps
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Test Condition
Min.
Max.
2.25
10
Unit
V
Vdd for Data Retention
Data Retention Current
See Data Retention Waveform
VDD = 1.0V, CE ≥ VDD – 0.2V
1.0
—
0
IDR
µA
ns
tSDR
Data Retention Setup Time See Data Retention Waveform
Recovery Time See Data Retention Waveform
—
tRDR
tRC
—
ns
DATA RETENTION WAVEFORM (CE Controlled)
t
SDR
Data Retention Mode
tRDR
V
DD
DR
2.3V
2.0V
V
CE ≥ VDD Ð 0.2V
CE
GND
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
9
08/07/02
®
IS62VV25616LL
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
(ns)
Order Part No.
Package
70
IS62VV25616LL-70T
IS62VV25616LL-70M
TSOP (Type II)
MiniBGA (7.2mmx8.7mm)
85
IS62VV25616LL-85T
IS62VV25616LL-85M
TSOP (Type II)
MiniBGA (7.2mmx8.7mm)
Industrial Range: –40°C to +85°C
Speed
(ns)
Order Part No.
Package
70
IS62VV25616LL-70TI
TSOP (Type II)
IS62VV25616LL-70MI MiniBGA (7.2mmx8.7mm)
IS62VV25616LL-85TI TSOP (Type II)
IS62VV25616LL-85MI MiniBGA (7.2mmx8.7mm)
85
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/07/02
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