IXDD408CI [IXYS]
8 Amp Low-Side Ultrafast MOSFET Driver; 8安培低端超快MOSFET驱动器
| 型号： | IXDD408CI |
| 厂家： | 
IXYS CORPORATION |
| 描述： | 8 Amp Low-Side Ultrafast MOSFET Driver |
| 文件： | 总10页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IXDD408PI / 408SI / 408YI / 408CI
8 Amp Low-Side Ultrafast MOSFET Driver
General Description
Features
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes.
• Latch Up Protected
TheIXDD408isahighspeedhighcurrentgatedriver
specifically designed to drive the largest MOSFETs and
IGBTs to their minimum switching time and maximum
practical frequency limits. The IXDD480 can source and
sink 8A of peak current while producing voltage rise and
fall times of less than 30ns. The input of the driver is
compatible with TTL or CMOS and is fully immune to
latch up over the entire operating range. Designed with
small internal delays, cross conduction/current shoot-
through is virtually eliminated in the IXDD408. Its features
and wide safety margin in operating voltage and power
maketheIXDD408unmatchedinperformanceandvalue.
• High Peak Output Current: 8A Peak
• Operates from 4.5V to 25V
• Ability to Disable Output under Faults
• High Capacitive Load
Drive Capability: 2500pF in <15ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• LowOutputImpedance
• LowSupplyCurrent
Applications
The IXDD408 incorporates a unique ability to disable the
output under fault conditions. When a logical low is
forced into the Enable input, both final output stage
MOSFETs (NMOS and PMOS) are turned off. As a
result, the output of the IXDD408 enters a tristate mode
andachievesaSoftTurn-OffoftheMOSFET/IGBTwhen
a short circuit is detected. This helps prevent damage
that could occur to the MOSFET/IGBT if it were to be
switchedoffabruptlyduetoadv/dtover-voltagetran-
sient.
• DrivingMOSFETsandIGBTs
• Limiting di/dt under Short Circuit
• MotorControls
• LineDrivers
• PulseGenerators
• Local Power ON/OFF Switch
• Switch Mode Power Supplies (SMPS)
• DCtoDCConverters
• PulseTransformerDriver
• Class D Switching Amplifiers
TheIXDD408isavailableinthestandard8-pinP-DIP(PI),
SOP-8 (SI), 5-pin TO-220 (CI) and in the TO-263 (YI)
surface-mountpackage.
Figure 1 - Functional Diagram
Copyright © IXYS CORPORATION 2001 Patent Pending
First Release
IXDD408PI/408SI//408YI/408CI
Absolute Maximum Ratings (Note 1)
Operating Ratings
Parameter
Value
Parameter
Value
Supply Voltage
All Other Pins
25 V
-0.3 V to V
Maximum Junction Temperature
o
150
C
+ 0.3 V
CC
Operating Temperature Range
o
o
-40 C to 85 C
o
Power Dissipation, TAMBIENT ≤25
8 Pin PDIP (PI)
C
Thermal Impedance (Junction To Case)
975mW
1055mW
17W
o
TO220 (CI), TO263 (YI) (θJC
)
0.95 C/W
8 Pin SOIC (SI)
TO220 (CI), TO263 (YI)
Derating Factors (to Ambient)
8 Pin PDIP (PI)
o
7.6mW/ C
8 Pin SOIC (SI)
o
8.2mW/ C
TO220 (CI), TO263 (YI)
Storage Temperature
Lead Temperature (10 sec)
o
0.14W/ C
o
o
C
-65 C to 150
o
300
C
Electrical Characteristics
Unless otherwise noted, TA = 25 oC, 4.5V ≤ VCC ≤ 25V .
All voltage measurements with respect to GND. IXDD408 configured as described in Test Conditions.
Symbol
VIH
Parameter
Test Conditions
Min
Typ
Max
Units
V
High input voltage
Low input voltage
Input voltage range
Input current
3.5
VIL
0.8
V
VIN
-5
VCC + 0.3
10
V
IIN
-10
0V ≤ VIN ≤ VCC
µA
VOH
VOL
ROH
High output voltage
Low output voltage
VCC - 0.025
V
V
Ω
0.025
1.5
Output resistance
@ Output high
Output resistance
@ Output Low
IOUT = 10mA, VCC = 18V
IOUT = 10mA, VCC = 18V
VCC is 18V
0.8
0.8
8
ROL
IPEAK
IDC
1.5
Ω
A
A
Peak output current
Continuous output
current
Limited by package power
dissipation
2
VEN
VENH
VENL
tR
Enable voltage range
- .3
Vcc + 0.3
V
V
High En Input Voltage
Low En Input Voltage
Rise time
2/3 Vcc
1/3 Vcc
18
V
CL=2500pF Vcc=18V
CL=2500pF Vcc=18V
CL=2500pF Vcc=18V
12
13
37
14
15
38
ns
ns
ns
tF
Fall time
19
tONDLY
On-time propagation
delay
42
tOFFDLY
tENOH
tDOLD
Off-time propagation
delay
Enable to output high
delay time
Disable to output low
Disable delay time
Power supply voltage
CL=2500pF Vcc=18V
Vcc=18V
32
34
38
52
30
25
ns
ns
ns
V
Vcc=18V
VCC
ICC
4.5
18
Power supply current
VIN = 3.5V
VIN = 0V
VIN = + VCC
1
0
3
10
10
mA
µA
µA
Specifications Subject To Change Without Notice
2
IXDD408PI/408SI/408YI/408CI
Pin Configurations
1 VCC
VCC 8
I
Vc c
OUT
GND
IN
1
2
3
4
X
D
D
4
0
8
2 IN
OUT
OUT
GND
7
6
5
3 EN
4 GND
EN
5
TO220(CI)
TO263(YI)
8 PIN DIP (PI)
SO8 (SI)
Pin Description
SYMBOL
VCC
IN
FUNCTION
DESCRIPTION
Positive power-supply voltage input. This pin provides power to the
entire chip. The range for this voltage is from 4.5V to 25V.
Input signal-TTL or CMOS compatible.
Supply Voltage
Input
The system enable pin. This pin, when driven low, disables the chip,
forcing high impedance state to the output.
EN
Enable
Driver Output. For application purposes, this pin is connected,
through a resistor, to Gate of a MOSFET/IGBT.
The system ground pin. Internally connected to all circuitry, this pin
provides ground reference for the entire chip. This pin should be
connected to a low noise analog ground plane for optimum
performance.
OUT
GND
Output
Ground
Note 1: Operating the device beyond parameters with listed “absolute maximum ratings” may cause permanent
damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not
guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures
when handling and assembling this component.
Figure 2 - Characteristics Test Diagram
V
IN
3
IXDD408PI/408SI//408YI/408CI
Typical Performance Characteristics
Fig. 4
100
Fall Time vs. Supply Voltage
Fig. 3
50
Rise Time vs. Supply Voltage
80
60
40
20
40
30
20
10
CL=10,000 pF
4700 pF
CL=10,000 pF
4700 pF
2200 pF
2200 pF
0
8
0
8
10
12
14
16
18
10
12
14
16
18
Supply Voltage (V)
SupplyVoltage(V)
Fig. 5
Rise And Fall Times vs. Junction Temperature
C = 2500pF, V = 18V
Fig. 6
50
Rise Time vs. Load Capacitance
L
CC
25
20
15
10
5
8V
40
30
20
10
10V
12V
tF
18V
14V
16V
tR
0
2k
0
4k
6k
8k
10k
-40
-20
0
20
40
60
80
100
120
Load Capacitance (pF)
Temperature (°C)
Fall Time vs. Load Capacitance
Max / Min Input vs. Junction Temperature
Fig. 8
Fig. 7
C =2500pF VCC = 18V
L
90
3.2
8V
80
70
60
50
40
30
20
10
3.0
2.8
2.6
2.4
2.2
2.0
1.8
Minimum Input High
10V
12V
18V
Maximum Input Low
16V
14V
1.6
-60
0
2k
4k
6k
8k
10k
-40
-20
0
20
40
60
80
100
Load Capacitance (pF)
o
Temperature ( C)
4
IXDD408PI/408SI/408YI/408CI
Fig. 9
Supply Current vs. Load Capacitance
Vcc=18V
Fig. 10
Supply Current vs. Frequency
Vcc=18V
100
10
1
100
CL= 5000 pF
1 MHz
2500 pF
10
1
1000 pF
500 KHz
100 kHz
50 kHz
0.1
10 kHz
0.1
1
10
100
1000
0.1k
1.0k
10.0k
10.0k
10.0k
Frequency (kHz)
Load Capacitance (pF)
Supply Current vs. Frequency
Vcc=12V
Fig. 11
Supply Current vs. Load Capacitance
Vcc=12V
Fig. 12
100
100
CL= 5000 pF
10
1
2500 pF
10
1
1 MHz
1000 pF
500 KHz
100 kHz
50 kHz
0.1
10 kHz
0.1
1
10
100
1000
0.1k
1.0k
Frequency (kHz)
Load Capacitance (pF)
Fig. 14
Fig. 13
Supply Current vs. Frequency
Vcc=8V
Supply Current vs. Load Capacitance
Vcc=8V
100
100
CL= 5000 pF
10
1
2 MHz
10
1
2500 pF
1 MHz
1000 pF
500 KHz
100 kHz
50 kHz
0.1
0.1
10 kHz
1
10
100
1000
0.1k
1.0k
Frequency (kHz)
Load Capacitance (pF)
5
IXDD408PI/408SI//408YI/408CI
Fig. 15
Fig. 16
Propagation Delay vs. Input Voltage
CL=2500pF VCC=15V
Propagation Delay vs. Supply Voltage
CL=2500pF V =5V@1kHz
IN
60
70
60
50
40
30
20
10
0
50
40
30
20
10
tONDLY
tONDLY
tOFFDLY
tOFFDLY
0
2
4
6
8
10
12
8
10
12
14
16
18
Input Voltage (V)
Supply Voltage (V)
Propagation Delay Times vs. Junction Temperature
Fig. 17
Quiescent Supply Current vs. Junction Temperature
Fig. 18
C = 2500pF VCC = 18V
L
VCC=18V V =5V@1kHz
IN
60
55
50
45
40
35
30
25
20
15
10
0.66
0.64
0.62
0.60
0.58
0.56
0.54
tONDLY
tOFFDLY
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
o
Temperature (°C)
Temperature ( C)
Fig. 19
P Channel Peak Output Current vs. Case Temperature
CI and YI Packages, CL=.1uF VCC=18V
Fig. 20
N Channel Peak Output Current vs. Case Temperature
CI and YI Packages, CL=.1uF VCC=18V
9
12
11
10
9
8
7
6
8
-40
-20
0
20
40
o
60
80
100
-40
-20
0
20
40
o
60
80
100
Temperature ( C)
Temperature ( C)
6
IXDD408PI/408SI/408YI/408CI
High State Output Resistance
vs. Supply Voltage
Fig. 22
Fig. 21
Enable Threshold vs. Supply Voltage
14
3
12
10
8
2
1
6
4
2
0
4
0
5
6
8
10
12
14
16
18
20
22
24
26
10
15
20
25
Supply Voltage (V)
Supply Voltage (V)
Fig. 23
Low-State Output Resistance
vs. Supply Voltage
Vcc vs. P Channel Output Current
Fig. 24
C =15nF
L
0
-2
3.0
-4
2.0
1.0
0.0
-6
-8
-10
-12
-14
-16
5
10
15
20
25
30
8
10
15
20
25
Supply Voltage (V)
Vcc
Fig. 25
Figure 26 - Typical Application Short Circuit di/dt Limit
Vcc vs. N Channel Output Current
C =15nF
L
10
8
6
4
2
0
5
10
15
20
25
30
Vcc
7
IXDD408PI/408SI//408YI/408CI
APPLICATIONS INFORMATION
Short Circuit di/dt Limit
A short circuit in a high-power MOSFET module such as the
VM0580-02F, (580A, 200V), as shown in Figure 26, can cause
the current through the module to flow in excess of 1500A for
10µs or more prior to self-destruction due to thermal runaway.
For this reason, some protection circuitry is needed to turn off
the MOSFET module. However, if the module is switched off
too fast, there is a danger of voltage transients occuring on the
drain due to Ldi/dt, (where L represents total inductance in
series with drain). If these voltage transients exceed the
MOSFET's voltage rating, this can cause an avalanche break-
down.
ground. (Those glitches might cause false triggering of the
comparator).
The comparator's output should be connected to a SRFF(Set
Reset Flip Flop). The flip-flop controls both the Enable signal,
andthelowpowerMOSFETgate. PleasenotethatCMOS4000-
series devices operate with a VCC range from 3 to 15 VDC, (with
18 VDC being the maximum allowable limit).
A low power MOSFET, such as the 2N7000, in series with a
resistor, will enable the VMO580-02F gate voltage to drop
gradually. The resistor should be chosen so that the RC time
constant will be 100us, where "C" is the Miller capacitance of
theVMO580-02F.
TheIXDD408hastheuniquecapabilitytosoftlyswitchoffthe
high-power MOSFET module, significantly reducing these
Ldi/dttransients.
For resuming normal operation, a Reset signal is needed at
the SRFF's input to enable the IXDD408 again. This Reset can
be generated by connecting a One Shot circuit between the
IXDD408 Input signal and the SRFF restart input. The One Shot
will create a pulse on the rise of the IXDD408 input, and this
pulse will reset the SRFF outputs to normal operation.
Thus, the IXDD408 helps to prevent device destruction from
both dangers; over-current, and avalanche breakdown due to
di/dt induced over-voltage transients.
The IXDD408 is designed to not only provide ±8A under normal
conditions, but also to allow it's output to go into a high
impedance state. This permits the IXDD408 output to control
a separate weak pull-down circuit during detected overcurrent
shutdown conditions to limit and separately control dVGS/dt gate
turnoff. This circuit is shown in Figure 27.
When a short circuit occurs, the voltage drop across the low-
value, current-sensing resistor, (Rs=0.005 Ohm), connected
between the MOSFET Source and ground, increases. This
triggers the comparator at a preset level. The SRFF drives a low
input into the Enable pin disabling the IXDD408 output. The
SRFF also turns on the low power MOSFET, (2N7000).
Referring to Figure 27, the protection circuitry should include
a comparator, whose positive input is connected to the source
of the VM0580-02. A low pass filter should be added to the input
of the comparator to eliminate any glitches in voltage caused
by the inductance of the wire connecting the source resistor to
In this way, the high-power MOSFET module is softly turned off
by the IXDD408, preventing its destruction.
Figure 27 - Application Test Diagram
+
VB
Ld
-
10uH
Rd
IXDD408
0.1ohm
VCC
VCCA
Rg
High_Power
VMO580-02F
OUT
IN
EN
1ohm
Rsh
1600ohm
+
-
+
-
VCC
VIN
GND
SUB
Rs
Low_Power
2N7002/PLP
Ls
R+
10kohm
20nH
One ShotCircuit
Rcomp
0
Comp
LM339
5kohm
+
V+
NAND
CD4011A
NOT2
CD4049A
C+
NOT1
CD4049A
V-
-
100pF
Ccomp
1pF
Ros
+
-
R
1Mohm
REF
Cos
1pF
Q
NOT3
CD4049A
NOR1
CD4001A
S
EN
NOR2
CD4001A
SR Flip-Flop
8
IXDD408PI/408SI/408YI/408CI
TTL to High Voltage CMOS Level Translation
Supply Bypassing and Grounding Practices,
Output Lead inductance
The enable (EN) input to the IXDD408 is a high voltage
CMOS logic level input where the EN input threshold is ½ VCC,
and may not be compatible with 5V CMOS or TTL input levels.
The IXDD408 EN input was intentionally designed for
enhanced noise immunity with the high voltage CMOS logic
levels. In a typical gate driver application, VCC =15V and the
EN input threshold at 7.5V, a 5V CMOS logical high input
applied to this typical IXDD408 application’s EN input will be
misinterpreted as a logical low, and may cause undesirable
or unexpected results. The note below is for optional
adaptation of TTL or 5V CMOS levels.
When designing a circuit to drive a high speed MOSFET
utilizing the IXDD408, it is very important to keep certain design
criteria in mind, in order to optimize performance of the driver.
Particular attention needs to be paid to Supply Bypassing,
Grounding, and minimizing the Output Lead Inductance.
Say, for example, we are using the IXDD408 to charge a
5000pF capacitive load from 0 to 25 volts in 25ns…
Using the formula: I= ∆V C / ∆t, where ∆V=25V C=5000pF &
∆t=25ns we can determine that to charge 5000pF to 25 volts
in25nswilltakeaconstantcurrentof5A. (Inreality,thecharging
current won’t be constant, and will peak somewhere around
8A).
The circuit in Figure 28 alleviates this potential logic level
misinterpretation by translating a TTL or 5V CMOS logic input
to high voltage CMOS logic levels needed by the IXDD408 EN
input. From the figure, VCC is the gate driver power supply,
typically set between 8V to 20V, and VDD is the logic power
supply, typically between 3.3V to 5.5V. Resistors R1 and R2
form a voltage divider network so that the Q1 base is
positioned at the midpoint of the expected TTL logic transition
levels.
SUPPLYBYPASSING
In order for our design to turn the load on properly, the IXDD408
must be able to draw this 5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the
power supply at the driver with a capacitance value that is a
magnitude larger than the load capacitance. Usually, this
would be achieved by placing two different types of bypassing
capacitors, with complementary impedance curves, very close
to the driver itself. (These capacitors should be carefully
selected, low inductance, low resistance, high-pulse current-
servicecapacitors). Leadlengthsmayradiateathighfrequency
due to inductance, so care should be taken to keep the lengths
oftheleadsbetweenthesebypasscapacitorsandtheIXDD408
to an absolute minimum.
A TTL or 5V CMOS logic low, VTTLLOW=~<0.8V, input applied to
the Q1 emitter will drive it on. This causes the level translator
output, the Q1 collector output to settle to VCESATQ1
+
VTTLLOW=<~2V, which is sufficiently low to be correctly
interpreted as a high voltage CMOS logic low (<1/3VCC=5V for
VCC =15V given in the IXDD408 data sheet.)
A TTL high, VTTLHIGH=>~2.4V, or a 5V CMOS high,
V5VCMOSHIGH=~>3.5V, applied to the EN input of the circuit in
Figure 28 will cause Q1 to be biased off. This results in Q1
collector being pulled up by R3 to VCC=15V, and provides a
high voltage CMOS logic high output. The high voltage CMOS
logical EN output applied to the IXDD408 EN input will enable
it, allowing the gate driver to fully function as an 8 Amp output
driver.
GROUNDING
In order for the design to turn the load off properly, the IXDD408
must be able to drain this 5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXDD408
and it’s load. Path #2 is between the IXDD408 and it’s power
supply. Path #3 is between the IXDD408 and whatever logic
is driving it. All three of these paths should be as low in
resistance and inductance as possible, and thus as short as
practical. Inaddition, everyeffortshouldbemadetokeepthese
three ground paths distinctly separate. Otherwise, (for
instance), the returning ground current from the load may
develop a voltage that would have a detrimental effect on the
logic line driving the IXDD408.
The total component cost of the circuit in Figure 28 is less
than $0.10 if purchased in quantities >1K pieces. It is
recommended that the physical placement of the level
translator circuit be placed close to the source of the TTL or
CMOS logic circuits to maximize noise rejection.
Figure 28 - TTL to High Voltage CMOS Level Translator
C C
OUTPUTLEADINDUCTANCE
(Fro m G a te Drive r
R3
10K
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and it’s
load as short and wide as possible. If the driver must be placed
farther than 2” from the load, then the output leads should be
treated as transmission lines. In this case, a twisted-pair
should be considered, and the return line of each twisted pair
should be placed as close as possible to the ground pin of the
driver, and connect directly to the ground terminal of the load.
Po we r Sup p ly)
Hig h Vo lta g e
V
DD
EN
C MOS
3.3K
(Fro m Lo g ic
Po we r Sup p ly)
R1
O utp ut
Q 1
2N3904
(To IXDD408
EN Inp ut)
3.3K R2
o r
TTL
Inp ut)
9
IXDD408PI/408SI//408YI/408CI
Package Information
NOTE: Mounting or solder tabs on all packages are connected to ground
IXYS Corporation
Ordering Information
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
e-mail: sales@ixys.net
Part N um ber Package T ype
Tem p. R ange
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
IX D D 408PI
IX D D 408SI
IX D D 408YI
IX D D 408C I
8-Pin PD IP
8-Pin SO IC
5-Pin TO -263
5-Pin TO -220
IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: marcom@ixys.de
Directed Energy, Inc.
An IXYS Company
2401 Research Blvd. Ste. 108
Ft. Collins, CO 80526
Tel: 970-493-1901; Fax: 970-493-1903
e-mail: deiinfo@directedenergy.com
Doc #9200-0227 R7
10
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