KK74HC165AD [KODENSHI]
8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS; 8位串行或并行输入/串行输出移位寄存器高性能硅栅CMOS
| 型号： | KK74HC165AD |
| 厂家： | 
KODENSHI KOREA CORP. |
| 描述： | 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS |
| 文件： | 总8页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL DATA
8-Bit Serial or Parallel-Input/
KK74HC165A
Serial-Output Shift Register
High-Performance Silicon-Gate CMOS
The KK74HC165A is identical in pinout to the LS/ALS165. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device is an 8-bit shift register with complementary outputs from
the last stage. Data may be loaded into the register either in parallel or in
serial form. When the Serial Shift/ Parallel Load input is low, the data is
loaded asynchronously in parallel. When the Serial Shift/Parallel Load
input is high, the data is loaded serially on the rising edge of either Clock
or Clock Inhibit (see the Function Table).
The 2-input NOR clock may be used either by combining two
independent clock sources or by designating one of the clock inputs to act
as a clock inhibit.
ORDERING INFORMATION
KK74HC165AN Plastic
KK74HC165AD SOIC
TA = -55° to 125° C for all packages
•
•
•
•
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 16=VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Clock
Internal Stages
Output
QH
Operation
Serial Shift/
Clock
S
A-H
QA
QB-QG
Parallel Load
Inhibit
A
L
H
H
H
X
L
L
X
L
a...h
X
a
L
H
b-g
h
Asynchronous Parallel Load
Serial Shift via Clock
QAn-QFn
QAn-QFn
QGn
QGn
H
X
H
H
L
L
L
X
X
L
QAn-QFn
QAn-QFn
QGn
QGn
Serial Shift via Clock
Inhibit
H
H
H
H
X
H
L
H
X
L
X
X
X
X
X
X
no change
Inhibited Clock
H
no change
No Clock
X = Don’t Care
QAn-QFn = Data shifted from the preceding stage
1
KK74HC165A
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
Unit
V
VCC
VIN
VOUT
IIN
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
V
mA
mA
mA
mW
IOUT
ICC
DC Output Current, per Pin
±25
DC Supply Current, VCC and GND Pins
±50
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
2.0
0
Max
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
VCC
VIN, VOUT
TA
V
-55
+125
°C
ns
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
V
OUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74HC165A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
VIH
Parameter
Test Conditions
Unit
V
25 °C
to
≤85 ≤125
°C
°C
-55°C
Minimum High-
Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
VIL
Maximum Low -
Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH
Minimum High-
Level Output Voltage
VIN=VIH or VIL
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH or VIL
⎢IOUT⎢ ≤ 4.0 mA
⎢IOUT⎢ ≤ 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum Low-
Level Output Voltage
VIN= VIL or VIH
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN= VIL or VIH
⎢IOUT⎢ ≤ 4.0 mA
⎢IOUT⎢ ≤ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0 ±1.0
µA
µA
ICC
Maximum Quiescent VIN=VCC or GND
Supply Current
(per Package)
6.0
8.0
80 160
I
OUT=0µA
3
KK74HC165A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
VCC
V
Guaranteed Limit
Symbol
fmax
Parameter
Unit
MHz
ns
25 °C
to
≤85°C ≤125°C
-55°C
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 8)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
tPLH, tPHL Maximum Propagation Delay, Clock (or Clock
Inhibit) to QH or QH (Figures 1 and 8)
2.0
4.5
6.0
150
30
190
38
225
45
26
33
38
tPLH, tPHL Maximum Propagation Delay ,
SerialShift./.Parallel Load to QH or QH
(Figures 2 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPLH, tPHL Maximum Propagation Delay, Input H to QH or
QH (Figures 3 and 8)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 8)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
CIN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Package)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
85
pF
PD=CPDVCC2f+ICCVCC
4
KK74HC165A
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
tSU
Parameter
V
Unit
ns
25 °C to
-55°C
≤85°C
≤125°C
Minimum Setup Time,
Parallel Data Inputs to Serial
Shift/Parallel Load (Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
tSU
tSU
tSU
th
Minimum Setup Time, Input
SA to Clock (or Clock Inhibit)
(Figure 5)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Minimum Setup Time, Serial
Shift/Parallel Load to Clock
(or Clock Inhibit) (Figure 6)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
Minimum Setup Time, Clock
to Clock Inhibit (Figure 7)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
Minimum Hold Time, Serial
Shift/Parallel Load to Parallel
Data Inputs (Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
th
Minimum Hold Time, Clock
(or Clock Inhibit) to Input SA
(Figure 5)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
th
Minimum Hold Time, Clock
(or Clock Inhibit) to Serial
Shift/Parallel Load (Figure 6)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
trec
Minimum Recovery Time,
Clock to Clock Inhibit
(Figure 7)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
tw
Minimum Pulse Width, Clock
(or Clock Inhibit) (Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tw
Minimum Pulse Width, Serial
Shift/Parallel Load (Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tr, tf
Maximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
5
KK74HC165A
SWITCHING WAVEFORMS
6
KK74HC165A
TIMING DIAGRAM
EXPANDED LOGIC DIAGRAM
7
KK74HC165A
N SUFFIX PLASTIC DIP
(MS - 001BB)
A
Dimension, mm
9
8
16
1
Symbol
MIN
18.67
6.1
MAX
19.69
7.11
B
A
B
C
D
F
5.33
0.36
1.14
0.56
F
L
1.78
C
2.54
7.62
G
H
J
SEATING
PLANE
-T-
N
M
0
°
10
°
J
G
K
H
D
2.92
7.62
0.2
3.81
8.26
0.36
K
L
M
N
0.25 (0.010) M
T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
0.38
D SUFFIX SOIC
(MS - 012AC)
Dimension, mm
A
16
Symbol
MIN
9.8
MAX
10
9
A
B
C
D
F
H
B
P
3.8
4
1.35
0.33
0.4
1.75
0.51
1.27
1
8
G
R x 45
C
1.27
5.72
G
H
J
-T-
SEATING
PLANE
K
M
D
J
F
0.25 (0.010) M T C
M
0
°
8
°
0.1
0.19
5.8
0.25
0.25
6.2
K
M
P
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
0.25
0.5
R
for A; for B 0.25 mm (0.010) per side.
‑
8
相关型号：
KK74HC165AN
8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS
KODENSHI
KK74HC166A
8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS
KODENSHI
KK74HC166AD
8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS
KODENSHI
KK74HC166AN
8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS
KODENSHI
KK74HC175AD
Quad D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS
KODENSHI
KK74HC175AN
Quad D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS
KODENSHI
©2020 ICPDF网 联系我们和版权申明