KK74HC166A [KODENSHI]
8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS; 8位串行或并行输入/串行输出移位寄存器高性能硅栅CMOS
| 型号： | KK74HC166A |
| 厂家： | 
KODENSHI KOREA CORP. |
| 描述： | 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS |
| 文件： | 总7页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL DATA
KK74HC166A
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High-Performance Silicon-Gate CMOS
The KK74HC166A is identical in pinout to the LS/ALS166. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device is a parallel-in or serial-in, serial-out shift register with
gated clock inputs and an overriding clear input. The shift/load input
establishes the parallel-in or serial-in mode. When high, this input enables
the serial data input and couples the eight flip-flops for serial shifting
with each clock pulse. Synchronous loading occurs on the next clock
pulse when this is low and the parallel data inputs are enabled. Serial data
flow is inhibited during parallel loading. Clocking is done on the low-to-
high level edge of the clock pulse via a two input positive NOR gate,
which permits one input to be used as a clock enable or clock inhibit
function. Clocking is inhibited when either of the clock inputs are held
high, holding either input low enables the other clock input. This will
allow the system clock to be free running and the register stopped on
command with the other clock input. A change from low-to-high on the
clock inhibit input should only be done when the clock input is high. A
buffered direct clear input overrides all other inputs, including the clock,
andsets all flip-flop to zero.
ORDERING INFORMATION
KK74HC166AN Plastic
KK74HC166AD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
•
•
•
•
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
1
KK74HC166A
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
Unit
V
VCC
VIN
VOUT
IIN
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
V
mA
mA
mA
mW
IOUT
ICC
DC Output Current, per Pin
±25
DC Supply Current, VCC and GND Pins
±50
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
2.0
0
Max
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
VCC
VIN, VOUT
TA
V
-55
+125
°C
ns
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
V
OUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74HC166A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
VIH
Parameter
Test Conditions
Unit
V
25 °C
to
≤85 ≤125
°C
°C
-55°C
Minimum High-
Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
VIL
Maximum Low -
Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH
Minimum High-
Level Output Voltage
VIN=VIH or VIL
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH or VIL
⎢IOUT⎢ ≤ 4.0 mA
⎢IOUT⎢ ≤ 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum Low-
Level Output Voltage
VIN=VIH or VIL
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN=VIH or VIL
⎢IOUT⎢ ≤ 4.0 mA
⎢IOUT⎢ ≤ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN
Maximum Input
Leakage Current
V =VCC or GND
6.0
±0.1
±1.0 ±1.0
µA
µA
ICC
Maximum Quiescent VIN=VCC or GND
Supply Current
(per Package)
6.0
8.0
80 160
I
OUT=0µA
FUNCTION TABLE
Inputs
Internal
Outputs
Output
QH
Clear
Shift/Load
Clock
Clock
X
SA
Parallel
A...H
QA QB
Inhibit
L
H
H
H
H
H
X
X
L
X
X
L
L
L
H
X
X
X
H
L
X
X
L
L
L
No change
a...h
X
a
H
L
b
h
H
H
X
QAn
QGn
QGn
X
QAn
X
X
X
No change
X = don’t care
a...h = the level of steady state input voltage at input A trough H respectively
3
KK74HC166A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
VCC
V
Guaranteed Limit
Symbol
fmax
Parameter
Unit
MHz
ns
25 °C
to
≤85°C ≤125°C
-55°C
Minimum Clock Frequency (50% Duty Cycle)
(Figures 2 and 4)
2.0
4.5
6.0
6.0
31
36
5.0
25
28
4.2
21
25
tPLH, tPHL Maximum Propagation Delay, Clock (or Clock
Inhibit) to QH (Figures 2,3 and 4)
2.0
4.5
6.0
140
28
175
35
210
42
24
30
36
tPHL
Maximum Propagation Delay , Clear to QH
(Figures 1 and 4)
2.0
4.5
6.0
150
30
26
200
40
34
230
48
40
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
16
14
95
20
18
110
25
20
ns
CIN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Package)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
140
pF
PD=CPDVCC2f+ICCVCC
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
tsu
Parameter
V
Unit
ns
25 °C to
-55°C
≤85°C
≤125°C
Minimum Setup Time, Shift/Load to
Clock (Figure 3)
2.0
4.5
6.0
80
16
14
100
20
18
120
24
20
tsu
Minimum Setup Time, Data before
Clock (or Clock Inhibit) (Figure 3)
2.0
4.5
6.0
80
16
14
100
20
18
120
24
20
ns
ns
tw
Minimum Pulse Width, Clock (or
Clock Inhibit) (Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
4
KK74HC166A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
5
KK74HC166A
TIMING DIAGRAM
EXPANDED LOGIC DIAGRAM
6
KK74HC166A
N SUFFIX PLASTIC DIP
(MS - 001BB)
A
Dimension, mm
9
8
16
1
Symbol
MIN
18.67
6.1
MAX
19.69
7.11
B
A
B
C
D
F
5.33
0.36
1.14
0.56
F
L
1.78
C
2.54
7.62
G
H
J
SEATING
PLANE
-T-
N
M
0
°
10
°
J
G
K
H
D
2.92
7.62
0.2
3.81
8.26
0.36
K
L
M
N
0.25 (0.010) M
T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
0.38
D SUFFIX SOIC
(MS - 012AC)
Dimension, mm
A
16
Symbol
MIN
9.8
MAX
10
9
A
B
C
D
F
H
B
P
3.8
4
1.35
0.33
0.4
1.75
0.51
1.27
1
8
G
R x 45
C
1.27
5.72
G
H
J
-T-
SEATING
PLANE
K
M
D
J
F
0.25 (0.010) M T C
M
0
°
8
°
0.1
0.19
5.8
0.25
0.25
6.2
K
M
P
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
0.25
0.5
R
for A; for B 0.25 mm (0.010) per side.
‑
7
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