KK74HC4053ADW [KODENSHI]
Analog Multiplexer/Demultiplexer High-Performance Silicon-Gate CMOS; 模拟多路复用器/多路解复用器高性能硅栅CMOS
| 型号： | KK74HC4053ADW |
| 厂家： | 
KODENSHI KOREA CORP. |
| 描述： | Analog Multiplexer/Demultiplexer High-Performance Silicon-Gate CMOS |
| 文件： | 总9页 (文件大小：421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL DATA
KK74HC4053A
Analog Multiplexer/Demultiplexer
High-Performance Silicon-Gate CMOS
The KK74HC4053A utilize silicon-gate CMOS technology to achieve
fast propagation delays, low ON resistances, and low OFF leakage
currents. These analog multiplexers/demultiplexers control analog
voltages that may vary across the complete power supply range (from VCC
to VEE).
The Channel-Select inputs determine which one of the Analog
Inputs/Outputs is to be connected, by means of an analog switch, to the
Common Output/Input.When the Enable pin is high, all analog switches
are turned off.
The Channel-Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LS/ALSTTL outputs.
ORDERING INFORMATION
KK74HC4053AN Plastic
KK74HC4053ADW SOIC
TA = -55° to 125° C for all packages
•
•
•
•
•
•
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Analog Power Supply Range (VCC-VEE)=2.0 to 12.0 V
Digital (Control) Power Supply Range (VCC-GND)=2.0 to 6.0 V
Low Noise
PIN ASSIGNMENT
LOGIC DIAGRAM
Triple Single-Pole, Double-Position
Plus Common Off
FUNCTION TABLE
Control Inputs
ON
Enable
Select
B
Channels
C
L
A
L
L
L
L
L
L
L
L
L
H
L
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
X0
X1
X0
X1
X0
X1
X0
X1
L
L
H
L
L
H
Y1
L
H
H
L
Y1
H
H
H
H
X
L
Y0
PIN 16 =VCC
PIN 7 = VEE
PIN 8 = GND
L
H
L
Y0
H
Y1
H
H
X
Y1
X
None
X = don’t care
1
KK74HC4053A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
VCC
Positive DC Supply Voltage (Referenced to GND)
(Referenced to VEE)
-0.5 to +7.0
-0.5 to +14.0
VEE
VIS
VIN
I
Negative DC Supply Voltage (Referenced to GND)
Analog Input Voltage
-7.0 to +0.5
VEE - 0.5 to VCC+0.5
-1.5 to VCC +1.5
±25
V
V
Digital Input Voltage (Referenced to GND)
DC Input Current Into or Out of Any Pin
V
mA
mW
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
Max
Unit
V
Positive Supply Voltage (Referenced to GND)
(Referenced to VEE)
2.0
2.0
6.0
12.0
VEE
VIS
VIN
Negative DC Supply Voltage (Referenced to GND)
Analog Input Voltage
- 6.0
VEE
GND
-
GND
VCC
VCC
1.2
V
V
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature, All Package Types
Input Rise and Fall Time (Channel Select VCC =2.0 V
V
*
VIO
V
TA
-55
+125
°C
ns
tr, tf
0
0
0
1000
500
400
or Enable Inputs)
VCC =4.5 V
VCC =6.0 V
*
For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn;
i. e., the current out of the switch may contain both VCC and switch input components. The reliability of the device
will be unaffected unless the Maximum Ratings are exceeded.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range indicated in the
Recommended Operating Conditions..
Unused digital input pins must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused Analog I/O pins may be left open or terminated.
2
KK74HC4053A
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE=GND,
Except Where Noted
VCC
V
Guaranteed Limit
Symbol
Parameter
Test Conditions
Unit
V
25 °C
to
≤85
°C
≤125
°C
-55°C
VIH
VIL
IIN
Minimum High-Level
Input Voltage,
Channel-Select or
Enable Inputs
RON = Per Spec
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
Maximum Low -Level
Input Voltage,
Channel-Select or
Enable Inputs
RON = Per Spec
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Maximum Input
Leakage Current,
Channel-Select or
Enable Inputs
VIN=VCC or GND,
VEE=-6.0 V
6.0
±0.1
±1.0
±1.0
µA
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
Channel Select = VCC or GND
Enable = VCC or GND
VIS = VCC or GND
VIO= 0 V
VEE = GND
VEE = -6.0
6.0
6.0
2
8
20
80
40
160
DC ELECTRICAL CHARACTERISTICS Analog Section
VCC VEE
Guaranteed Limit
Symbol
RON
Parameter
Test Conditions
V
V
Uni
t
25 °C ≤85 ≤125
to
°C
°C
-55°C
Maximum “ON” Resistance VIN=VIL or VIH
VIS = VCC or VEE
4.5
4.5
6.0
0.0
-4.5
-6.0
190
120
100
240 280
150 170
125 140
Ω
IS ≤ 2.0 mA(Figure 1)
VIN=VIL or VIH
VIS = VCC or VEE
(Endpoints)
4.5
4.5
0.0
-4.5
150
100
190 230
125 140
6.0
-6.0
80
100 115
IS ≤ 2.0 mA(Figure 1)
Maximum Difference in
“ON” Resistance Between
Any Two Channels in the
Same Package
VIN=VIL or VIH
VIS = 1/2 (VCC- VEE)
IS ≤ 2.0 mA
4.5
4.5
6.0
0.0
-4.5
-6.0
30
12
10
35
15
12
40
18
14
∆RON
Ω
IOFF
Maximum Off- Channel
Leakage Current, Any One
Channel
VIN=VIL or VIH
VIO = VCC- VEE
Switch Off (Figure 2)
6.0
6.0
6.0
-6.0
-6.0
-6.0
0.1
0.1
0.1
0.5
1.0
1.0
1.0
2.0
2.0
µA
Maximum Off- Channel
Leakage Current, Common
Channel
VIN=VIL or VIH
VIO= VCC- VEE
Switch Off (Figure 3)
ION
Maximum On- Channel
Leakage Current, Channel to Switch to Switch =
Channel VCC- VEE (Figure 5)
VIN=VIL or VIH
µA
3
KK74HC4053A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
VCC
V
Guaranteed Limit
Symbol
Parameter
Unit
ns
25 °C
to
≤85°C ≤125°C
-55°C
tPLH, tPHL Maximum Propagation Delay, Channel-Select to
Analog Output (Figures 8 and 9)
2.0
4.5
6.0
370
74
465
93
79
550
110
94
63
tPLH, tPHL Maximum Propagation Delay , Analog Input to
Analog Output (Figures 10 and 11)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tPLZ, tPHZ Maximum Propagation Delay , Enable to Analog
Output (Figures 12 and 13)
2.0
4.5
6.0
290
58
49
364
73
62
430
86
73
ns
tPZL, tPZH Maximum Propagation Delay , Enable to Analog
Output (Figures 12 and 13)
2.0
4.5
6.0
345
69
59
435
87
74
515
103
87
ns
CIN
Maximum Input Capacitance, Channel-Select or
Enable Inputs
-
10
35
10
35
10
pF
pF
CI/O
Maximum Capacitance
-
35
Analog I/O
Common O/I
Feedthrough
All Switches Off
-
-
50
50
50
1.0
1.0
1.0
Power Dissipation Capacitance (Per Package)
(Figure 15)
Typical @25°C,VCC=5.0 V, VEE=0
V
CPD
Used to determine the no-load dynamic power
consumption:
45
pF
PD=CPDVCC2f+ICCVCC
4
KK74HC4053A
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V)
VCC
VEE
V
Limit*
Symbol
BW
Parameter
Test Conditions
fin=1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VOS
Increase fin Frequence Until dB Meter
Reads -3 dB
V
Unit
25 °C
Maximum On-
Channel
Bandwidth or
Minimum
Frequency
Response
MHz
2.25
4.50
6.00
-2.25
-4.50
-6.00
120
120
120
RL =50 Ω, CL=10 pF
(Figure 5)
-
-
Off-Channel
Feedthrough
Isolation
fin= Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL =600 Ω, CL=50 pF
dB
2.25
4.50
6.00
-2.25
-4.50
-6.00
-50
-50
-50
(Figure 6)
2.25
4.50
6.00
-2.25
-4.50
-6.00
-40
-40
-40
fin = 1.0 MHz, RL =50 Ω, CL=10 pF
Feedthrough
Noise, Channel
Select Input to
Common O/I
(Figure 7)
mVpp
VIN≤ 1 MHz Square Wave (tr = tf = 6 ns)
Adjust RL at Setup so that IS= 0 A Enable
= GND
2.25
4.50
6.00
-2.25
-4.50
-6.00
25
105
135
RL =600 Ω, CL=50 pF
2.25
4.50
6.00
-2.25
-4.50
-6.00
35
145
190
RL =10 Ω, CL=10 pF
-
Crosstalk
fin= Sine Wave
dB
Between Any
Two Switches
(Figure 14)
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL =600 Ω, CL=50 pF
2.25
4.50
6.00
-2.25
-4.50
-6.00
-50
-50
-50
2.25
4.50
6.00
-2.25
-4.50
-6.00
-60
-60
-60
fin = 1 MHz, RL =50 Ω, CL=10 pF
THD
Total Harmonic
Distortion
(Figure 16)
%
fin= 1 kHz, RL =10 kΩ, CL=50 pF
THD = THDMeasured - THDSource
VIS =4.0 VPP sine wave
2.25
4.50
6.00
-2.25
-4.50
-6.00
0.10
0.08
0.05
VIS =8.0 VPP sine wave
VIS =11.0 VPP sine wave
* Limits not tested. Determined by design and verified by qualification.
5
KK74HC4053A
Figure 1. On Resistance Test Set-Up
Figure 2. Maximum Off Channel Leakage
Figure 3. Maximum Off Channel Leakage Current,
Current, Any One Channel, Test Set-UP
Common Channel, Test Set-UP
* Includes all probe and jig capacitance.
Figure 5. Maximum On Channel Bandwidth,
Test Set-UP
Figure 4. Maximum On Channel Leakage
Current, Channel to Channel, Test Set-UP
* Includes all probe and jig capacitance.
* Includes all probe and jig capacitance.
Figure 6. Off Channel Feedthrough Isolation, Figure 7.Feedthrough Noise, Channel Select to Common
Test Set-UP Out, Test Set-UP
6
KK74HC4053A
* Includes all probe and jig capacitance.
Figure 8. Switching Weveforms
Figure 9. Test Set-UP, Channel Select to Analog Out
* Includes all probe and jig capacitance.
Figure 10. Switching Weveforms
Figure 11. Test Set-UP, Analog In to Analog Out
Figure 12. Switching Weveforms
Figure 13. Test Set-UP, Enable to Analog Out
7
KK74HC4053A
* Includes all probe and jig capacitance.
Figure 14. Crosstalk Between Any Two
Switches, Test Set-Up
Figure 15. Power Dissipation Capacitance, Test Set-Up
Figure 16. Total Harmonic Distortion, Test Set-UP
EXPANDED LOGIC DIAGRAM
8
KK74HC4053A
N SUFFIX PLASTIC DIP
(MS - 001BB)
A
Dimension, mm
9
8
16
1
Symbol
MIN
18.67
6.1
MAX
19.69
7.11
B
A
B
C
D
F
5.33
0.36
1.14
0.56
F
L
1.78
C
2.54
7.62
G
H
J
SEATING
PLANE
-T-
N
M
0
°
10
°
J
G
K
H
D
2.92
7.62
0.2
3.81
8.26
0.36
K
L
M
N
0.25 (0.010) M
T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
0.38
D SUFFIX SOIC
(MS - 012AC)
Dimension, mm
A
16
Symbol
MIN
9.8
MAX
10
9
A
B
C
D
F
H
B
P
3.8
4
1.35
0.33
0.4
1.75
0.51
1.27
1
8
G
R x 45
C
1.27
5.72
G
H
J
-T-
SEATING
PLANE
K
M
D
J
F
0.25 (0.010) M T C
M
0
°
8
°
0.1
0.19
5.8
0.25
0.25
6.2
K
M
P
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
0.25
0.5
R
for A; for B 0.25 mm (0.010) per side.
‑
9
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