KK74HC4094A [KODENSHI]
8-Bit Serial-Input Shift Register With Latched 3-State Outputs High-Performance Silicon-Gate CMOS; 8位串行输入移位寄存器锁存三态输出的高性能硅栅CMOS
| 型号： | KK74HC4094A |
| 厂家： | 
KODENSHI KOREA CORP. |
| 描述： | 8-Bit Serial-Input Shift Register With Latched 3-State Outputs High-Performance Silicon-Gate CMOS |
| 文件： | 总8页 (文件大小：389K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL DATA
KK74HC4094A
8-Bit Serial-Input Shift Register
With Latched 3-State Outputs
High-Performance Silicon-Gate CMOS
The KK74HC4094A is identical in pinout to the LS/ALS4094. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of an 8-bit shift register and 8-bit D-type latch
with three-state parallel outputs. Data is shifted serially through the shift
register on the positive going transition of the clock input signal. The
output of the last stage SQH can be used to cascade several devices.
Data on the SQH output is transferred to a second output (SQH’) on the
following negative transition of the clock input signal. The data of each
stage of the shift register is provided with a latch, which latches data on
the negative going transition of the Strobe input signal. When the Strobe
input is held high, data propagates through the latch to a 3-state output
buffer.
ORDERING INFORMATION
KK74HC4094AN Plastic
KK74HC4094AD SOIC
TA = -55° to 125° C for all packages
This buffer is enabled when Output Enable input is taken high.
•
•
•
•
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
PIN ASSIGNMENT
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Parallel
Outputs
Serial
Outputs
Clock Output Strobe
Enable
A
QA QN SQH SQH’
L
L
X
X
L
X
X
X
L
Z
Z
Z
Z
Q6 NC
NC SQH
PIN 16 =VCC
PIN 8 = GND
H
H
H
H
NC NC Q6 NC
H
H
X
L
QN-1 Q6 NC
QN-1 Q6 NC
H
X
H
NC NC NC SQH
NC = No Change
Z = high impedance
X = don’t care
1
KK74HC4094A
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
Unit
V
VCC
VIN
VOUT
IIN
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
V
mA
mA
mA
mW
IOUT
ICC
DC Output Current, per Pin
±25
DC Supply Current, VCC and GND Pins
±50
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
2.0
0
Max
6.0
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
VIN, VOUT
TA
VCC
+125
V
-55
°C
ns
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
V
OUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74HC4094A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
VIH
Parameter
Test Conditions
Unit
V
25 °C
to
≤85 ≤125
°C
°C
-55°C
Minimum High-
Level Input Voltage
VOUT= 0.1 V or VCC-0.1 V
⎢IOUT⎢≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
VIL
Maximum Low -
Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VOH
Minimum High-
Level Output Voltage
VIN=VIH or VIL
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN= VIH or VIL
⎢IOUT⎢ ≤ 4.0 mA
⎢IOUT⎢ ≤ 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum Low-
Level Output Voltage
VIN=VIH or VIL
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN= VIH or VIL
⎢IOUT⎢ ≤ 4.0 mA
⎢IOUT⎢ ≤ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0 ±1.0
µA
µA
IOZ
Maximum Three-
State Leakage
Current
Output in High-Impedance
State
VIN= VIL or VIH
VOUT=VCC or GND
6.0
±0.5
±5.0
±10
ICC
Maximum Quiescent VIN=VCC or GND
6.0
4.0
40
160
µA
Supply Current
(per Package)
I
OUT=0µA
3
KK74HC4094A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
VCC
V
Guaranteed Limit
Symbol
fmax
Parameter
Unit
MHz
ns
25 °C
to
≤85°C ≤125°C
-55°C
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
2.0
4.5
6.0
6
30
35
5
25
28
4
20
23
tPLH, tPHL Maximum Propagation Delay, Clock to SQH
(Figures 1 and 5)
2.0
4.5
6.0
150
30
190
38
225
45
26
33
38
tPLH, tPHL Maximum Propagation Delay, Clock to QA-QH
(Figures 2 and 5)
2.0
4.5
6.0
195
40
33
245
50
42
295
60
50
ns
tPLZ, tPHZ Maximum Propagation Delay ,Output Enable to
QA-QH (Figures 3 and 6)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tPZL, tPZH Maximum Propagation Delay ,Output Enable to
QA-QH (Figures 3 and 6)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
CIN
Maximum Input Capacitance
-
-
10
15
10
15
10
15
pF
pF
COUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State), QA-QH
Power Dissipation Capacitance (Per Package)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
300
pF
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
tsu
Parameter
V
Unit
ns
25 °C to
-55°C
≤85°C
≤125°C
Minimum Setup Time, Serial Data
Input A to Clock (Figure 4)
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
th
Minimum Hold Time, Clock to Data
Input A (Figure 4)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
ns
ns
tw
Minimum Pulse Width, Strobe
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
4
KK74HC4094A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Test Circuit
Figure 6. Test Circuit
5
KK74HC4094A
EXPANDED LOGIC DIAGRAM
6
KK74HC4094A
TIMING DIAGRAM
7
KK74HC4094A
N SUFFIX PLASTIC DIP
(MS - 001BB)
A
Dimension, mm
9
8
16
1
Symbol
MIN
18.67
6.1
MAX
19.69
7.11
B
A
B
C
D
F
5.33
0.36
1.14
0.56
F
L
1.78
C
2.54
7.62
G
H
J
SEATING
PLANE
-T-
N
M
0
°
10
°
J
G
K
H
D
2.92
7.62
0.2
3.81
8.26
0.36
K
L
M
N
0.25 (0.010) M
T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
0.38
D SUFFIX SOIC
(MS - 012AC)
Dimension, mm
A
16
Symbol
MIN
9.8
MAX
10
9
A
B
C
D
F
H
B
P
3.8
4
1.35
0.33
0.4
1.75
0.51
1.27
1
8
G
R x 45
C
1.27
5.72
G
H
J
-T-
SEATING
PLANE
K
M
D
J
F
0.25 (0.010) M T C
M
0
°
8
°
0.1
0.19
5.8
0.25
0.25
6.2
K
M
P
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
0.25
0.5
R
for A; for B 0.25 mm (0.010) per side.
‑
8
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8-Bit Serial-Input Shift Register With Latched 3-State Outputs High-Performance Silicon-Gate CMOS
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KK74HC4094AN
8-Bit Serial-Input Shift Register With Latched 3-State Outputs High-Performance Silicon-Gate CMOS
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