ML145106-6P [LANSDALE]
PLL Frequency Synthesizer CMOS; PLL频率合成器的CMOS
| 型号： | ML145106-6P |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | PLL Frequency Synthesizer CMOS |
| 文件： | 总8页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML145106
PLL Frequency Synthesizer
CMOS
INTERFACES WITH DUAL–MODULUS PRESCALERS
Legacy Device: Motorola MC145106
The ML145106 is a phase–locked loop (PLL) frequency synthesizer
constructed in CMOS on a single monolithic structure. This synthesizer
finds applications in such areas as AM radio, shortwave, amateur radio,
CB and FM transceivers. The device contains an oscillator/amplifier, a
210 or 211 divider chain for the oscillator signal, a programmable
divider chain for the input signal, and a phase detector. The ML145106
has circuitry for a 10.24 MHz oscillator or may operate with an exter-
nal signal. The circuit provides a 5.12 MHz output signal, which can be
used for frequency tripling. A 29 programmable divider divides the
input signal frequency for channel selection. The inputs to the program-
mable divider are standard ground–to–supply binary signals. Pull–down
resistors on these inputs normally set these inputs to ground enabling
these programmable inputs to be controlled from a mechanical switch
or electronic circuitry.
P DIP 18 = VP
PLASTIC DIP
CASE 707
18
1
SOG 20W = -6P
SOG PACKAGE
CASE 751D
20
1
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 18
SOG 20W
MC145106P
ML145106VP
MC145106DW ML145106-6P
The phase detector may control a VCO and yields a high level signal
when input frequency is low, and a low level signal when input fre-
quency is high. An out–of–lock signal is provided from the on–chip
lock detector with a “0” level for the out–of–lock condition.
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
• Single Power Supply
• Wide Supply Range: 4.5 to 12 V
• Provision for 10.24 MHz Crystal Oscillator
• 5.12 MHz Output
• Programmable Division Binary Input Selects up to 29
• On–Chip Pull–Down Resistors on Programmable Divider Inputs
• Selectable Reference Divider, 210 or 211 (Including ÷ 2)
• Three–State Phase Detector
• See Application Note AN535 and Article Reprint AR254
• Chip Complexity: 880 FETs or 220 Equivalent Gates
BLOCK DIAGRAM
OSC
out
÷
2
FS
out
REFERENCE
DIVIDE 2 OR 2
φDet
÷
2
out
OSC
in
9
10
PHASE
DETECTOR
9
f
LD
DIVIDE–BY–N COUNTER 2 – 1
in
P0 P1 P2 P3 P4 P5 P6 P7 P8
Page 1 of 8
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Issue bBC
ML145106
LANSDALE Semiconductor, Inc.
PIN ASSIGNMENTS
PLASTIC DIP
V
1
2
3
4
5
6
18
17
16
15
14
13
V
SS
DD
f
P0
P1
P2
P3
P4
P5
P6
P7
in
in
OSC
OSC
out
÷2
out
FS
φ
Det
7
8
9
12
11
10
out
LD
P8
SOG PACKAGE
V
1
2
20
19
V
SS
DD
f
P0
in
OSC
3
4
18
17
NC
P1
in
OSC
out
÷2
5
6
16
15
P2
P3
out
FS
φDet
7
14
13
12
11
P4
NC
P5
P6
out
LD
8
P8
P7
9
10
NC = NO CONNECTION
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised that
normalprecautions betakentoavoid application
of any voltage higher than maximum rated
voltages to this high impedance circuit. For
Parameter
DC Supply Voltage
Symbol
Value
Unit
V
DD
– 0.5 to + 12
V
V
Input Voltage, All Inputs
V
in
– 0.5 to V + 0.5
DD
DC Input Current, per Pin
Operating Temperature Range
Storage Temperature Range
I
± ±10
mA
°C
°C
proper operation it is recommended that V and
in
T
A
– 40 to + 85
V
be constrained to the range V ° (V or
≤
SS in
out
V
)°≤±V
.
T
stg
– 65 to + 150
out DD
Page 2 of 8
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Issue Bb B
ML145106
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS (T = 25°C Unless Otherwise Stated, Voltages Referenced to V
)
A
SS
All Types
V
Vdc
DD
Characteristic
Power Supply Voltage Range
Symbol
Unit
V
Min
Typ*
Max
V
DD
–
4.5
–
12
Supply Current
I
5.0
10
12
–
–
–
6
20
28
10
35
50
mA
DD
Input Voltage
“0” Level
“1” Level
“0” Level
V
5.0
10
12
–
–
–
–
–
–
1.5
3.0
3.6
V
IL
IH
in
V
5.0
10
12
3.5
7.0
8.4
–
–
–
–
–
–
Input Current
FS, Pull–Up Resistor Source Current)
I
5.0
10
12
– 5.0
– 15
– 20
– 20
– 60
– 80
– 50
– 150
– 200
µA
(P0 – P8)
(FS)
5.0
10
12
–
–
–
–
–
–
– 0.3
– 0.3
– 0.3
“1” Level
5.0
10
12
–
–
–
–
–
–
0.3
0.3
0.3
(P0 – P8, Pull–Down Resistor Sink Current)
5.0
10
12
7.5
22.5
30
30
90
120
75
225
300
(OSC , f )
in in
“0” Level
“1” Level
5.0
10
12
– 2.0
– 6.0
– 9.0
– 6.0
– 25
– 37
– 15
– 62
– 92
(OSC , f )
in in
5.0
10
12
2.0
6.0
9.0
6.0
25
37
15
62
92
Output Drive Current
I
mA
OH
(V = 4.5 V)
Source
Sink
5.0
10
12
– 0.7
– 1.1
– 1.5
– 1.4
– 2.2
– 3.0
–
–
–
O
(V = 9.5 V)
O
(V = 11.5 V)
O
(V = 0.5 V)
I
5.0
10
12
0.9
1.4
2.0
1.8
2.8
4.0
–
–
–
O
OL
(V = 0.5 V)
O
(V = 0.5 V)
O
Input Amplitude
–
V p–p
Sine
(f @ 4.0 MHz)
–
–
1.0
1.5
0.2
0.3
–
–
in
(OSC @ 10.24 MHz)
in
Input Resistance
R
MΩ
in
(OSC , f )
5.0
10
12
–
–
–
1.0
0.5
–
–
–
–
in in
Input Capacitance
C
–
–
6.0
–
pF
in
(OSC , f )
in in
Three–State Leakage Current
I
5.0
10
12
–
–
–
–
–
–
1.0
1.0
1.0
µA
OZ
(φDet
)
out
Input Frequency
(– 40 to + 85°C)
f
4.5
12
0
0
–
–
4.0
4.0
MHz
MHz
in
Oscillator Frequency
(– 40 to + 85°C)
OSC
4.5
12
0.1
0.1
–
–
10.24
10.24
in
*Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC's potential performance.
Page 3 of 8
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Issue Bb
ML145106
LANSDALE Semiconductor, Inc.
TYPICAL CHARACTERISTICS*
25
20
25
20
15
+ 25°C
+ 25°C
15
+ 85°C
– 40°C
+ 85°C
– 40°C
10
5.0
0
10
5.0
0
0
10
20
30
40
50
0
10
20
30
40
50
f
, MAXIMUM FREQUENCY (MHz)
OSC , MAXIMUM FREQUENCY (MHz)
in
in
Figure 1. Maximum Divider Input Frequency
versus Supply Voltage
Figure 2. Maximum Oscillator Input Frequency
versus Supply Voltage
* Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC's potential performance.
LD
TRUTH TABLE
Lock Detector (PDIP, SOG – Pin 8)
LD is high when loop is locked, pulses low when
out–of–lock.
Selection
P8 P7 P6 P5 P4 P3 P2 P1 P0
Divide by N
0
0
0
0
0
•
•
•
0
0
0
0
0
•
•
•
0
0
0
0
0
•
•
•
0
0
0
0
0
•
•
•
0
0
0
0
0
•
•
•
0
0
0
0
0
•
•
•
0
0
0
0
1
•
•
•
0
0
1
1
0
•
•
•
0
1
0
1
0
•
•
•
2*
3*
2
3
4
•
•
•
255
•
•
•
φDet
(PDIP, SOG – Pin 7)
Signal for control of external VCO, output high when f /N
out
in
is less than the reference frequency; output low when f /N is
in
greater than the reference frequency. Reference frequency is
the divided down oscillator–input frequency typically 5.0 or 10
kHz.
0
1
1
1
1
1
1
1
1
•
•
•
•
•
•
•
•
•
NOTE
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Phase Detector Gain = VDD/4π.
1
1
1
1
1
1
1
1
1
511
1: Voltage level = V
DD
.
FS
0: Voltage level = 0 or open circuit input.
Reference Oscillator Frequency Division Select (PDIP,SOG
– Pin 6)
When using 10.24 MHz OSC frequency, this control selects
10 kHz, a “0” selects 5.0 kHz.
* The binary setting of 00000000 and 00000001 on P8 to P0 results
in a 2 and 3 division which is not in the 2 – 1 sequence. When pin
is not connected the logic signal on that pin can be treated as a “0”.
N
PIN DESCRIPTIONS
÷2
(PDIP, SOG – Pin 5)
P0 – P8
out
Reference OSC frequency divided by 2 output; when using
10.24 MHz OSC frequency, this output is 5.12 MHz for fre-
quency tripling applications.
Programmable Inputs (PDIP – Pins 17 – 9; SOG – Pins 19,
17 – 14, 12 – 9)
Programmable divider inputs (binary).
V
fin
DD
Positive Power Supply (PDIP, SOG – Pin 1)
Frequency Input (PDIP, SOG – Pin 2)
Frequency input to programmable divider (derived
fromVCO).
V
SS
Ground (PDIP – Pin 18, SOG – Pin 20)
OSC , OSC
in
out
Oscillator Input and Oscillator Output (PDIP, SOG –
Pins 3, 4)
Oscillator/amplifier input and output terminals.
Page 4 of 8
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Issue b
ML145106
LANSDALE Semiconductor, Inc.
Legacy Applications Information
PLL SYNTHESIZER APPLICATIONS
MHz (receive) frequencies are provided to mixer #1. When
these signals are provided with crystal oscillators, the result is
a three crystal 360 channel, 50 kHz step synthesizer. When
using the offset loop (bottom) in Figure 5 to provide the indi-
cated injection frequencies for mixer #1 (two for transmit and
two for receive) 360 additional channels are possible. This
results in a 720–channel, 25 kHz step synthesizer which
requires only two crystals and provides R/T offset capability.
The receive offset value is determined by the 11.31 MHz crys-
tal frequency and is 10.7 MHz for the example.
The VHF marine synthesizer in Figure 4 depicts a single
loop approach for FM transceivers. The VCO operates on fre-
quency during transmit and is offset downward during receive.
The offset corresponds to the receive IF (10.7 MHz) for chan-
nels having identical receive/transmit frequencies (simplex),
and is (10.7 – 4.6 = 6.1) MHz for duplex channels. Carrier
modulation is introduced in the loop during transmit.
The ML145106 is well suited for applications in CB radios
because of the channelized frequency requirements. A typical
40 channel CB transceiver synthesizer, using a single crystal
reference, is shown in Figure 3 for receiver IF values of 10.695
MHz and 455 kHz.
In addition to applications in CB radios, the MC145106 can
be used as a synthesizer for several other systems. Various fre-
quency spectrums can be achieved through the use of proper
offset, prescaling, and loop programming techniques. In gener-
al, 300 – 400 channels can be synthesized using a single loop,
with many additional channels available when multiple loop
approaches are employed. Figures 4 and 5 are examples of
some possibilities.
In the aircraft synthesizer of Figure 5, the VHF loop (top)
will provide a 50 kHz, 360 channel system with 10.7 MHz R/T
offset when only the 11.0500 MHz (transmit) and 12.1200
LD
9
10
2 /2
OSC
2
26.965 – 27.405 MHz
LOOP
FILTER
PHASE
DETECTOR
10.24
MHz
5.0 kHz
(TRANSMIT)
26.510 – 26.950 MHz
(RECEIVE)
VCO
BUFFER
ML145106
PROGRAMMABLE
DIVIDER
V
GND
DD
SWITCH WAFERS
R/T
BUFFER
MIXER
10.24 MHz
16.270 – 16.710 MHz
1.365 – 1.805 MHz (TRANSMIT)
0.91 – 1.35 MHz (RECEIVE)
TO RECEIVER
2ND MIXER
RECEIVER 1ST
LOCAL OSC SIGNAL
25.6 MHz
X 5
MIXER
Figure 3. Single Crystal CB Synthesizer Featuring On–Frequency VCO During Transmit
Page 5 of 8
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Issue b
ML145106
LANSDALE Semiconductor, Inc.
Legacy Applications Information
LOCK DETECT
V
GND
DD
9
10
REF
OSC
2 , 2
TRANSMIT RANGE
156.025 – 157.425 MHz
*157.4
2
DIVIDER
2.5 kHz
(5.0 kHz)
5.12 MHz
(10.24 MHz)
PHASE
DETECTOR
LOOP
FILTER
VCO AND
BUFFER
ML145106
RECEIVER L.O. RANGE
145.575 – 152.575 MHz
*151.3
9
N 2 – 1
TRANSMIT
MODULATION
CIRCUIT
MODULATION
PROGRAMMABLE INPUTS
N = 97 TO 153 *152
0.2425 – 0.3825
(0.4850 – 0.7650)
*0.3800
BUFFER
FILTER
10 ( 5)
MIXER
15.36 (30.72)
RECEIVE OFFSET
OSCILLATOR
TRIPLER
TRANSMIT
RECEIVE
SIMPLEX
14.29
DUPLEX
14.75#
NOTES:
• Receiver IF = 10.7 MHz.
(28.58)
(29.50)
• Low Side Injection.
• Duplex Offset = 4.6 MHz.
• Step Size = 25 kHz.
• Frequencies in MHz unless noted.
• Values in parentheses are for a 5.0 kHz reference frequency.
• Example frequencies for Channel 28 shown by *.
#Can be eliminated by adding 184 to N for Duplex Channels.
Figure 4. VHF Marine Transceiver Synthesizer
Page 6 of 8
www.lansdale.com
Issue b
ML145106
LANSDALE Semiconductor, Inc.
Legacy Applications Information
LOCK DETECT
9
10
TRANSMIT
118.000 – 135.975 MHz
(25 kHz STEPS)
2 , 2
REF
OSC
÷
2
DIVIDER
10.24 MHz
PHASE
DETECTOR
LOOP
FILTER
VCO AND
BUFFER
5.0 kHz
RECEIVE
128.700 – 146.675 MHz
MC145106
9
N 2 – 1
÷
VHF LOOP
V
GND
DD
PROGRAMMING
750 kHz – 2545 kHz
N = 150 – 509
MIXER
#1
÷
10
TRANSMIT
11.0500 MHz
11.0525 MHz
LOCK DETECT
RECEIVE
12.1200 MHz
12.1225 MHz
9
10
5.12 MHz
REF OSC
AND
2 , 2
÷
2
DIVIDER
PHASE
DETECTOR
LOOP
FILTER
VCO AND
BUFFER
2.5 kHz
MC145106
9
N 2 – 1
÷
1
0 1 0 0 0 1 0
OFFSET LOOP
PROGRAMMING
V
GND
DD
TRANSMIT
10.24 MHz
MIXER
#2
AMP
OSC
810 kHz – 812.5 kHz
N = 324 – 325
RECEIVE
11.31 MHz
(SELECT FREQUENCY TO
GIVE DESIRED R/T OFFSET)
Figure 5. VHF Aircraft 720 Channel Two Crystal Frequency Synthesizer
Page 7 of 8
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Issue b
ML145106
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 18 = VP
(ML145106VP)
CASE 707–02
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
18
10
9
B
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
1
MILLIMETERS
INCHES
DIM
A
B
C
D
F
MIN
22.22
6.10
3.56
0.36
1.27
MAX
23.24
6.60
4.57
0.56
1.78
MIN
MAX
A
0.875
0.240
0.140
0.014
0.050
0.915
0.260
0.180
0.022
0.070
L
C
G
H
J
K
L
M
N
2.54 BSC
1.02
0.20
2.92
1.52
0.30
3.43
K
N
J
F
D
M
SEATING
PLANE
7.62 BSC
H
G
0°
15°
0.51
1.02
SOG 20W = -6P
(ML145106-6P)
CASE 751D–04
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
10X P
–B–
M
M
0.010 (0.25)
B
1
10
MILLIMETERS
INCHES
20X D
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
0.010 (0.25)
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0°
0.32
0.25
7°
0.010
0.004
0°
0.012
0.009
7°
R X 45°
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabil-
ity, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the cus-
tomer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 8 of 8
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Issue b
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