LT1970CFE#TR_技术文档

LT1970

500mA Power Op Amp with

Adjustable Precision Current Limit

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FEATURES

DESCRIPTIO

The LT^®1970 is a ±500mA power op amp with precise

externally controlled current limiting. Separate control

voltages program the sourcing and sinking current limit

sense thresholds with 2% accuracy. Output current may

be boosted by adding external power transistors.

■

±500mA Minimum Output Current

■

Independent Adjustment of Source and

Sink Current Limits

2% Current Limit Accuracy

■

Operates with Single or Split Supplies

■

Shutdown/Enable Control Input

Thecircuitoperateswithsingleorsplitpowersuppliesfrom

5V to 36V total supply voltage. In normal operation, the

inputstagesuppliesandtheoutputstagesuppliesarecon-

nected (V_CCto V⁺and V_EEto V^–). To reduce power dissi-

pationitispossibletopowertheoutputstage(V⁺,V^–)from

independent,lowervoltagerails.Theamplifierisunity-gain

stable with a 3.6MHz gain bandwidth product and slews at

1.6V/µs. The current limit circuits operate with a 2MHz re-

sponse between the VC_SRCor VC_SNKcontrol inputs and

the amplifier output.

■

Open Collector Status Flags:

Sink Current Limit

Source Current Limit

Thermal Shutdown

■

Fail Safe Current Limit and Thermal Shutdown

1.6V/µs Slew Rate

3.6MHz Gain Bandwidth Product

Fast Current Limit Response: 2MHz Bandwidth

Specified Temperature Range: –40°C to 85°C

■

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Open collector status flags signal current limit circuit

activation,aswellasthermalshutdownoftheamplifier.An

enable logic input puts the amplifier into a low power, high

impedance output state when pulled low. Thermal shut-

down and a ±800mA fixed current limit protect the chip

under fault conditions.

APPLICATIO S

■

Automatic Test Equipment

Laboratory Power Supplies

■

Motor Drivers

■

Thermoelectric Cooler Driver

The LT1970 is packaged in a 20-lead TSSOP package with

a thermally conductive copper bottom plate to facilitate

heat sinking.

, LTC and LT are registered trademarks of Linear Technology Corporation.

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TYPICAL APPLICATIO

A_V= 2 Amplifier with Adjustable ±500mA Full-Scale

Current Limit and Fault indication

Current Limited Sinewave Into 10Ω Load

V

LIMIT

0V TO 5V

15V

3k

15V

V

LIMIT

10 • R

I

= ±

OUT(LIMIT)

4V

CS

V

CC

+

V

2V

VC

SRC

V_LOAD

V

IN

+IN

VC

SNK

0V

R

CS

ISNK

1Ω

I

ISRC

OUT

–2V

1/4W

TSD

+

OUT

LT1970

SENSE

–

SENSE

–

LOAD

V

R1

10k

–IN

V

EE

COMMON

VC_SRC= 4V

VC_SNK= 2V

R_CS= 1Ω

20µs/DIV

1970 TA02

R2

10k

–15V

1970 TA01

1970f

1

LT1970

W W

U W

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ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

TOP VIEW

ORDER PART

Supply Voltage (V_CCto V_EE).................................... 36V

Positive High Current Supply (V⁺) .................. V^–to V_CC

Negative High Current Supply(V^–) ................... V_EEto V⁺

Amplifier Output (OUT)..................................... V^–to V⁺

Current Sense Pins

NUMBER

V

1

2

20

19

18

17

16

15

14

13

12

11

V

EE

–

EE

+

V

LT1970CFE

OUT

3

TSD

+

SENSE

4

ISNK

FILTER

5

ISRC

(SENSE⁺, SENSE^–, FILTER) .......................... V^–to V⁺

Logic Outputs (ISRC, ISNK, TSD)....... COMMON to V_CC

Input Voltage (–IN, +IN).......... V_EE– 0.3V to V_EE+ 36V

Input Current ....................................................... 10mA

Current Control Inputs

–

+

–

SENSE

6

ENABLE

COMMON

V

7

CC

–IN

+IN

8

VC

SRC

9

VC

SNK

V

10

V

EE

(VC_SRC, VC_SNK) .............COMMON to COMMON + 7V

Enable Logic Input .............................. COMMON to V_CC

COMMON ..................................................... V_EEto V_CC

Output Short-Circuit Duration......................... Indefinite

Operating Temperature Range (Note 2) .. –40°C to 85°C

Specified Temperature Range (Note 3)... –40°C to 85°C

Maximum Junction Temperature ......................... 150°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

FE PACKAGE

20-LEAD PLASTIC TSSOP

T_JMAX= 150°C, θ_JA= 40°C/ W (NOTE 6)

UNDERSIDE METAL CONNECTED TO V_EE

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are T_A= 25°C. See Test Circuit for standard test conditions.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Power Op Amp Characteristics

V

Input Offset Voltage

200

600

800

1000

µV

OS

0°C < T < 70°C

●

A

–40°C < T < 85°C

A

Input Offset Voltage Drift (Note 4)

Input Offset Current

●

–10

–100

–600

–4

10

µV/°C

nA

I

V

= 0V

100

OS

CM

Input Bias Current

–160

3

nA

B

Input Noise Voltage

0.1Hz to 10Hz

1kHz

µV

P-P

e

Input Noise Voltage Density

Input Noise Current Density

Input Resistance

15

3

nV/√Hz

pA/√Hz

n

i

1kHz

n

R

Common Mode

Differential Mode

500

100

kΩ

IN

C

V

Input Capacitance

Pin 8 and Pin 9 to Ground

6

pF

IN

Input Voltage Range

Typical

Guaranteed by CMRR Test

–14.5

–12.0

13.6

12.0

V

CM

●

CMRR

PSRR

Common Mode Rejection Ratio

Power Supply Rejection Ratio

–12V < V < 12V

92

105

dB

CM

–

+

V

= V = –5V, V = V = 3V to 30V

●

90

110

90

100

130

100

130

dB

EE

CC

–

+

= V = –5V, V = 30V, V = 2.5V to 30V

CC

–

+

= V = –3V to –30V, V = V = 5V

CC

–

+

= –30V, V = –2.5V to –30V, V = V = 5V

110

CC

1970f

2

LT1970

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are T_A= 25°C. See Test Circuit for standard test conditions.

SYMBOL

PARAMETER

CONDITIONS

R = 1k, –12.5V < V < 12.5V

OUT

MIN

TYP

MAX

UNITS

A

Large-Signal Voltage Gain

100

75

150

V/mV

VOL

L

●

R = 100Ω, –12.5V < V

< 12.5V

80

40

120

60

V/mV

L

OUT

+

–

R = 10Ω, –5V < V

L

< 5V, V = –V = 8V

20

5

V/mV

OUT

–

V

Output Sat Voltage Low

Output Sat Voltage High

Output Short-Circuit Current

V

OL

= V

– V

OUT

OL

OH

+

–

R = 100, V = V = 15V, V = V = –15V

1.9

0.8

2.4

2.2

V

L

CC

EE

+

–

R = 10, V = –V = 15V, V = –V = 5V

L

CC

EE

+

V

OH

= V – V

OUT

+

–

R = 100, V = V = 15V, V = V = –15V

●

1.7

1.0

V

L

CC

EE

+

–

R = 10, V = –V = 15V, V = –V = 5V

L

CC

EE

I

Output Low, R

Output High, R

= 0Ω

500

–1000

800

–800

1200

–500

mA

SC

SENSE

SR

Slew Rate

–10V < V

< 10V, R = 1k

0.7

11

1.6

V/µs

kHz

MHz

µs

OUT

L

FPBW

GBW

Full Power Bandwidth

Gain Bandwidth Product

Settling Time

V

OUT

= 10V

(Note 5)

PEAK

f = 10kHz

0.01%, V

3.6

8

t

= 0V to 10V, A = –1, R = 1k

S

OUT

V

L

Current Sense Characteristics

V

Minimum Current Sense Voltage

VC

= VC

= 0V

0.1

4

7

10

mV

SENSE(MIN)

SRC

SNK

●

V

Current Sense Voltage 4% of Full Scale

Current Sense Voltage 10% of Full Scale

VC

SRC

VC

SRC

= VC

= 0.2V

= 0.5V

= 5V

15

45

20

50

25

55

mV

SENSE(4%)

SENSE(10%)

SENSE(FS)

SNK

Current Sense Voltage 100% of Full Scale VC

490

480

500

510

520

mV

●

I

Current Limit Control Input Bias Current

VC , VC Pins

SRC SNK

–1

–0.2

0.1

200

µA

nA

BI

SENSE

FILTER

–

SENSE Input Current

0V < (VC , VC ) < 5V

–200

SRC

SNK

FILTER Input Current

0V < (VC , VC ) < 5V

SRC SNK

+

SENSE Input Current

VC = VC

= 0V

●

–500

200

–300

500

300

–200

25

nA

µA

SENSE

SRC

SNK

= 5V, VC

VC

= 0V

= 5V

250

–250

SNK

VC = 0V, VC

SRC

VC

= VC

= 5V

–25

SRC

SNK

Current Sense Change with Output Voltage VC

= VC

= 5V, –12.5V < V

< 12.5V

●

–0.1

750

0.1

%

OUT

+

Current Sense Change with Supply Voltage VC

= VC

= 5V, 6V < (V , V ) < 18V

±0.05

±0.01

±0.05

±0.01

%

CC

+

2.5V < V < 18V, V = 18V

–18V < (V , V ) < –2.5V

–18V < V < –2.5V, V = –18V

CC

–

EE

–

EE

Current Sense Bandwidth

2

MHz

–

R

Resistance FILTER to SENSE

●

1000

1250

Ω

CSF

Logic I/O Characteristics

Logic Output Leakage ISRC, ISNK, TSD

Logic Low Output Level

V = 15V

I = 5mA

●

1

µA

V

0.2

25

0.4

Logic Output Current Limit

Enable Logic Threshold

mA

V

0.8

–1

1.6

2.4

1

ENABLE

I

Enable Pin Bias Current

µA

ENABLE

1970f

3

LT1970

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are T_A= 25°C. See Test Circuit for standard test conditions.

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

7

MAX

13

UNITS

mA

µs

+

–

I

t

Total Supply Current

Supply Current

V

, V and V , V Connected

●

SUPPLY

CC

EE

+

–

V

, V and V , V Separate

3

7

CC

EE

+

–

Supply Current Disabled

Turn-On Delay

, V and V , V Connected, V ≤ 0.8V

ENABLE

0.6

10

1.5

CC(STBY)

ON

EE

(Note 7)

Turn-Off Delay

µs

OFF

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 4: This parameter is not 100% tested.

Note 5: Full power bandwidth is calculated from slew rate measurements:

Note 2: The LT1970C is guaranteed functional over the operating

temperature range of –40°C and 85°C.

Note 3: The LT1970C is guaranteed to meet specified performance from

0°C to 70°C. The LT1970C is designed, characterized and expected to

meet specified performance from –40°C to 85°C but is not tested or QA

sampled at these temperatures.

FPBW = SR/(2 • π • V )

P

Note 6: Thermal resistance varies depending upon the amount of PC board

metal attached to the device. If the maximum dissipation of the package is

exceeded, the device will go into thermal shutdown and be protected.

Note 7: Turn-on and turn-off delay are measured from V

1.6V to the OUT pin at 90% of normal output voltage.

crossing

ENABLE

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Total Supply Current

vs Supply Voltage

Warm-Up Drift V_IOvs Time

Input Bias Current vs V_CM

14

12

10

8

6

4

–100

–120

–140

–160

–180

–200

–220

–240

–260

V

= ±15V

S

+

I

+ I

125°C

25°C

CC

V

–I

BIAS

+I

–55°C

2

0

BIAS

–

I

+ I

EE

V

–2

–4

–6

–8

–10

–12

–14

0V

25°C

TIME (100ms/DIV)

1970 G04

125°C

0

2

4

6

8

10 12 14 16 18

–15 –12 –9 –6 –3

0

3

6

9

12 15

SUPPLY VOLTAGE (±V)

COMMON MODE INPUT VOLTAGE (V)

1970 G15

1970 G05

1970f

4

LT1970

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Open-Loop Gain and Phase

Supply Current vs Supply Voltage

vs Frequency

Phase Margin vs Supply Voltage

70

60

50

40

100

90

60

58

56

54

52

50

48

46

44

42

40

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

+

A

= –1

V

F

I

V

R = R = 1k

G

–

I

V

T

= 25°C

A

80

V

= V /2

GAIN

PHASE

OUT

S

70

I

VCC

30

20

60

50

I

VEE

10

0

40

30

20

10

0

–10

–20

–30

T

= 25°C

CC

A

+

–

V

= V = –V = –V

EE

0

100

1k

10k 100k

1M

10M 100M

0

4

8

12 16 20 24 28 32 36

2

4

6

8

10 12

20

14 16 18

TOTAL SUPPLY VOLTAGE (V)

FREQUENCY (Hz)

SUPPLY VOLTAGE (±V)

1970 G18

1970 G21

1870 G16

Slew Rate vs Supply Voltage

Slew Rate vs Temperature

Large-Signal Response, A_V= 1

2.5

2.0

1.5

1.0

0.5

0

1.8

V

S

= ±15V

FALLING

1.7

1.6

FALLING

RISING

10V

0V

RISING

1.5

1.4

1.3

1.2

1.1

–10V

A

= –1

V

F

R

_L= 1k

20µs/DIV

1970 G39

R = R = 1k

G

T

= 25°C

A

1.0

–50 –25

0

25

50

75 100 125

6

8

12

14

16

18

4

10

TEMPERATURE (°C)

SUPPLY VOLTAGE (±V)

1970 G24

1970 G23

Large-Signal Response, A_V= –1

Small-Signal Response, A_V= 1

Small-Signal Response, A_V= –1

10V

0V

–10V

R

_L= 1k

20µs/DIV

1970 G40

R_L= 1k

500ns/DIV

1970 G41

R_L= 1k

C_L= 1000pF

2µs/DIV

1970 G42

C_L= 1000pF

1970f

5

LT1970

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Undistorted Output Swing

vs Frequency

Full Range Current Sense

Transfer Curve

% Overshoot vs C_LOAD

30

25

20

15

10

5

60

50

40

30

20

10

0

500

400

V

= ±15V

S

300

SOURCING

A

= 1

V

200

CURRENT

100

0

A

= –1

V

–100

–200

–300

–400

–500

SINKING

CURRENT

V

A

= ±15V

S

V

= –5

1% THD

0

100

1k

10k

100k

10

100

1k

10k

0

1

2

3

4

5

FREQUENCY (Hz)

C

(pF)

LOAD

V

= V

(V)

CSNK

CSRC

1970 G47

1970 G44

1970 G50

Low Level Current Sense

Transfer Curve

Output Stage Quiescent Current

vs Supply Voltage

10

8

25

20

15

10

5

+

125°C

I

V

6

SOURCING

CURRENT

25°C

4

–55°C

2

0

–

I

V

–55°C

–2

–4

–6

–8

–10

–5

SINKING

–10

–15

–20

–25

25°C

CURRENT

125°C

14 16

SUPPLY VOLTAGE (±V)

18

0

25 50 75 100 125 150 175 200 225 250

= V (mV)

0

2

4

6

8

10 12

V

CSNK

CSRR

1970 G80

1970 G51

Control Stage Quiescent Current

vs Supply Voltage

Supply Current vs Supply Voltage

in Shutdown

800

700

600

500

400

300

200

100

0

5

4

V

= 0V

I

ENABLE

CC

85°C

125°C

25°C

–55°C

3

25°C

2

–55°C

1

0

I

EE

–1

–2

–3

–4

–5

–55°C

25°C

125°C

8

10

0

2

4

6

12 14 16 18

0

2

4

6

8

10 12 14 16 18

SUPPLY VOLTAGE (V)

SUPPLY VOLTAGE (±V)

1970 G82

1970 G81

1970f

6

LT1970

U

PI FU CTIO S

V_EE(Pins 1, 10, 11, 20, Package Base): Minus Supply

Voltage. V_EEconnects to the substrate of the integrated

circuitdie,andthereforemustalwaysbethemostnegative

voltage applied to the part. Decouple V_EEto ground with a

low ESR capacitor. V_EEmay be a negative voltage or it may

equal ground potential. Any or all of the V_EEpins may be

used. Unused V_EEpins must remain open.

V^–(Pin 2): Output Stage Negative Supply. V^–may equal

V_EEor may be smaller in magnitude. Only output stage

current flows out of V^–, all other current flows out of V_EE.

V^–may be used to drive the base/gate of an external power

device to boost the amplifier’s output current to levels

above the rated 500mA of the on-chip output devices.

Unless used to drive boost transistors, V^–should be

decoupled to ground with a low ESR capacitor.

FILTER (Pin 5): Current Sense Filter Pin. This pin is

normally not used and should be left open in most appli-

cations. When very large capacitive loads are driven, a

filter capacitor connected between FILTER and SENSE⁺

will reduce overshoot as the amplifier enters current

limiting mode. The filter time constant is set by an internal

1k resistor and the external filter capacitor. Capacitor

values of 1nF to 100nF are most effective at reducing

overshoot.

SENSE^–(Pin 6): Negative Current Sense Pin. This pin is

normally connected to the load end of the external sense

resistor. Positive current limit operation is activated when

the voltage V_SENSE(V_SENSE+ – V_SENSE–) equals 1/10 of

the programming control voltage at VC_SRC(Pin 13).

Negative current limit operation is activated when the

voltage V_SENSEequals –1/10 of the programming control

voltage at VC_SNK(Pin 12).

OUT (Pin 3): Amplifier Output. The OUT pin provides the

force function as part of a Kelvin sensed load connection.

OUT is normally connected directly to an external load

current sense resistor and the SENSE⁺pin. Amplifier

feedback is directly connected to the load and the other

end of the current sense resistor. The load connection is

also wired directly to the SENSE^–pin to monitor the load

current.

V_CC(Pin 7): Positive Supply Voltage. All circuitry except

the output transistors draw power from V_CC. Total supply

voltage from V_CCto V_EEmust be between 3.5V and 36V.

V_CCmustalwaysbegreaterthanorequaltoV⁺. V_CCshould

always be decoupled to ground with a low ESR capacitor.

–IN (Pin 8): Inverting Input of Amplifier. –IN may be any

voltage from V_EE– 0.3V to V_EE+ 36V. –IN and +IN remain

The OUT pin is current limited to ±800mA typical. This

current limit protects the output transistor in the event highimpedanceatalltimestopreventcurrentflowintothe

thatconnectionstotheexternalsenseresistorareopened inputs when current limit mode is active. Care must be

or shorted which disables the precision current limit taken to insure that –IN or +IN can never go to a voltage

function.

below V_EE– 0.3V even during transient conditions or

damage to the circuit may result. A Schottky diode from

V_EEto –IN can provide clamping if other elements in the

circuit can allow –IN to go below V_EE.

SENSE⁺(Pin 4): Positive Current Sense Pin. This lead is

normally connected to the driven end of the external sense

resistor. Positive current limit operation is activated when

the voltage V_SENSE(V_SENSE+ – V_SENSE–) equals 1/10 of

theprogrammingcontrolvoltageatVC_SRC(Pin13). Nega-

tive current limit operation is activated when the voltage

V_SENSEequals –1/10 of the programming control voltage

at VC_SNK(Pin 12).

+IN (Pin 9): Noninverting Input of Amplifier. +IN may be

any voltage from V_EE– 0.3V to V_EE+ 36V. –IN and +IN

remain high impedance at all times to prevent current flow

into the inputs when current limit mode is active. Care

must be taken to insure that –IN or +IN can never go to a

voltage below V_EE– 0.3V even during transient conditions

or damage to the circuit may result. A Schottky diode from

V_EEto +IN can provide clamping if other elements in the

circuit can allow +IN to go below V_EE.

1970f

7

LT1970

U

PI FU CTIO S

VC_SNK(Pin 12): Sink Current Limit Control Voltage Input.

The current sink limit amplifier will activate when the

sense voltage between SENSE⁺and SENSE^–equals

–1.0 • V_VCSNK/10. VC_SNKmay be set between V_COMMON

and V_COMMON+ 6V. The transfer function between VC_SNK

and V_SENSEis linear except for very small input voltages at

VC_SNK< 60mV. V_SENSElimits at a minimum set point of

4mV typical to insure that the sink and source limit

amplifiers do not try to operate simultaneously. To force

zero output current, the ENABLE pin can be taken low.

current limit is not active. ISRC, ISNK and TSD may be

wired “OR” together if desired. ISRC may be left open if

this function is not monitored.

ISNK (Pin 17): Sinking Current Limit Digital Output Flag.

ISNK is an open collector digital output. ISNK pulls low

whenever the sinking current limit amplifier assumes

control of the output. This pin can sink up to 10mA of

current. The current limit flag is off when the source

current limit is not active. ISRC, ISNK and TSD may be

wired “OR” together if desired. ISNK may be left open if

this function is not monitored.

VC_SRC(Pin 13): Source Current Limit Control Voltage

Input. The current source limit amplifier will activate

when the sense voltage between SENSE⁺and SENSE^–

equals V_VCSRC/10. VC_SRCmay be set between V_COMMON

and V_COMMON+ 6V. The transfer function between VC_SRC

and V_SENSEis linear except for very small input voltages

at VC_SRC< 60mV. V_SENSElimits at a minimum set point

of 4mV typical to insure that the sink and source limit

amplifiers do not try to operate simultaneously. To force

zero output current, the ENABLE pin can be taken low.

TSD (Pin 18): Thermal Shutdown Digital Output Flag. TSD

isanopencollectordigitaloutput. TSDpullslowwhenever

theinternalthermalshutdowncircuitactivates, typicallyat

a die temperature of 160°C. This pin can sink up to 10mA

of output current. The TSD flag is off when the die

temperature is within normal operating temperatures.

ISRC, ISNK and TSD may be wired “OR” together if

desired. ISNK may be left open if this function is not

monitored. Thermal shutdown activation should prompt

the user to evaluate electrical loading or thermal environ-

mental conditions.

V⁺(Pin 19): Output Stage Positive Supply. V⁺may equal

V_CCor may be smaller in magnitude. Only output stage

current flows through V⁺, all other current flows into V_CC.

V⁺maybeusedtodrivethebase/gateofanexternalpower

device to boost the amplifier’s output current to levels

above the rated 500mA of the on-chip output devices.

Unless used to drive boost transistors, V⁺should be

decoupled to ground with a low ESR capacitor.

COMMON (Pin 14): Control and ENABLE inputs and flag

outputs are referenced to the COMMON pin. COMMON

may be at any potential between V_EEand V_CC– 3V. In

typical applications, COMMON is connected to ground.

ENABLE (Pin 15): ENABLE Digital Input Control. When

taken low this TTL-level digital input turns off the amplifier

output and drops supply current to less than 1mA. Use the

ENABLE pin to force zero output current. Setting VC_SNK

VC_SRC= 0V allows I_OUT= ±4mV/R_SENSEto flow in or out

of V_OUT

=

.

ISRC (Pin 16): Sourcing Current Limit Digital Output Flag.

ISRC is an open collector digital output. ISRC pulls low

whenever the sourcing current limit amplifier assumes

control of the output. This pin can sink up to 10mA of

current. The current limit flag is off when the source

Package Base: The exposed backside of the package is

electrically connected to the V_EEpins on the IC die. The

package base should be soldered to a heat spreading pad

on the PC board that is electrically connected to V_EE.

1970f

8

LT1970

W U

BLOCK DIAGRA A D TEST CIRCUIT

R

V

FB

CC

+

7

1k

V

15V

19

+IN

9

8

+

–

Q1

OUT

+

V

IN

1×

GM1

3

–

–IN

Q2

PS1

R

G

1k

10k

ISNK

ISRC

TSD

17

16

18

–

+

D1

D2

R

1Ω

CS

+

–

I

V

SINK

SNK

SRC

+

SENSE

FILTER

15V

4

5

6

ENABLE

+

–

V

ENABLE

15

12

–

SENSE

VC

SNK

5V

VC

SNK

–

+

R

FIL

1k

R

–

VC

SRC

LOAD

V

I

SRC

VC

1k

13

14

SRC

2

V

COMMON

EE

–15V

2, 10, 11, 20

1970TC

W U U

U

APPLICATIO S I FOR ATIO

The LT1970 power op amp with precision controllable

current limit is a flexible voltage and current source

module. The drawing on the front page of this data sheet

is representative of the basic application of the circuit,

however many alternate uses are possible with proper

understanding of the subcircuit capabilities.

between –IN and +IN. No current will flow at the inputs

when differential input voltage is present. This feature is

important when the precision current sense amplifiers

“I_SINK” and “I_SRC” become active.

Current Limit Amplifiers

Amplifierstages“I_SINK”and“I_SRC”areveryhightranscon-

ductance amplifier stages with independently controlled

offset voltages. These amplifiers monitor the voltage

between input pins SENSE⁺and SENSE^–which usually

sense the voltage across a small external current sense

resistor. The transconductance amplifiers outputs con-

nect to the same high impedance node as the main input

stage GM1 amplifier. Small voltage differences between

SENSE⁺and SENSE^–, smaller than the user set VC_SNK/10

and VC_SRC/10 in magnitude, cause the current limit ampli-

fiers to decouple from the signal path. This is functionally

indicatedbydiodesD1andD2intheBlockDiagram.When

the voltage V_SENSEincreases in magnitude sufficient to

equal or overcome one of the offset voltages VC_SNK/10 or

VC_SRC/10,theappropriatecurrentlimitamplifierbecomes

1970f

CIRCUIT DESCRIPTION

Main Operational Amplifier

Subcircuit block GM1, the 1X unity-gain current buffer

and output transistors Q1 and Q2 form a standard opera-

tionalamplifier.Thisamplifierhas±500mAcurrentoutput

capability and a 3.6MHz gain bandwidth product. Most

applicationsoftheLT1970willusethisopampinthemain

signalpath.Allconventionalopampcircuitconfigurations

are supported. Inverting, noninverting, filter, summation

or nonlinear circuits may be implemented in a conven-

tional manner. The output stage includes current limiting

at ±800mA to protect against fault conditions. The input

stage has high differential breakdown of 36V minimum

9

LT1970

W U U

U

APPLICATIO S I FOR ATIO

active and because of its very high transconductance,

ENABLE Control

takes control from the input stage, GM1. The output

The ENABLE input pin puts the LT1970 into a low supply

current, high impedance output state. The ENABLE pin

responds to TTL threshold levels with respect to the

COMMONpin.PullingtheENABLEpinlowisthebestway

toforcezerocurrentattheoutput.SettingVC_SNK=VC_SRC

= 0V allows the output current to remain as high as

current is regulated to a value of I_OUT= V_SENSE/R_SENSE

(VC_SRCor VC_SNK)/(10 • R_SENSE).

=

Most applications will connect pins SENSE⁺and OUT to-

gether, with the load on the opposite side of the external

sense resistor and pin SENSE^–. Feedback to the inverting

input of GM1 should be connected from SENSE^–to –IN.

±4mV/R_SENSE

.

The common mode range of stages “I_SINK” and “I_SRC

”

Operating Status Flags

allow other connections. Ground side sensing of load

current may be employed by connecting the load between

pinsOUTandSENSE⁺. PinSENSE^–wouldbeconnectedto

ground in this instance. Load current would be regulated

in exactly the same way as the conventional connection.

However, voltage mode accuracy would be degraded in

The LT1970 has three digital output indicators; TSD, ISRC

and ISNK. These outputs are open collector drivers re-

ferredtotheCOMMONpin.Theoutputshave36Vcapabili-

ties and can sink in excess of 10mA. ISRC and ISNK

indicate activation of the associated current limit ampli-

fier. The TSD output indicates excessive die temperature

has caused the circuit to enter thermal shutdown. The

three digital outputs may be wire “OR’d” together, moni-

tored individually or left open. These outputs do not affect

circuit operation, but provide an indication of the present

operational status of the chip.

this case due to the voltage across R_SENSE

.

Creative applications are possible where pins SENSE⁺and

SENSE^–monitor a parameter other than load current. The

operating principle that at most one of the current limit

stages may be active at one time, and that when active, the

current limit stages take control of the output from GM1,

can be used for many different signals.

THERMAL MANAGEMENT

Current Limit Threshold Control Buffers

Minimizing Power Dissipation

Input pins VC_SNKand VC_SRCare used to set the response

thresholds of current limit amplifiers “I_SINK” and “I_SRC”.

Each of these inputs may be independently driven by a

voltage of 0V to 5V above the COMMON reference pin. The

0V to 5V input voltage is attenuated by a factor of 10 and

applied as an offset to the appropriate current limit ampli-

fier. AC signals may be applied to these pins. The AC

bandwidth from a V_Cpin to the output is typically 2MHz.

The LT1970 can operate with up to 36V total supply

voltage with output currents up to ±500mA. The amount

ofpowerdissipatedinthechipcouldapproach18Wunder

worst-case conditions. This amount of power will cause

die temperature to rise until the circuit enters thermal

shutdown. While the thermal shutdown feature prevents

damage to the circuit, normal operation is impaired.

Thermal design of the LT1970 operating environment is

essential to getting maximum utility from the circuit.

The transfer function from V_Cto the associated V_OSis

linear from about 0.1V to 5V in, or 10mV to 500mV at the

currentlimitamplifierinputs. Anintentionalnonlinearityis

built into the transfer functions at low levels. This nonlin-

earityinsuresthatboththesinkandsourcelimitamplifiers

cannot become active simultaneously. Simultaneous acti-

vation of the limit amplifiers could result in uncontrolled

outputs. As shown in the Typical Performance Character-

istics curves, the control inputs have a “hockey stick”

shape, to keep the minimum limit threshold at 4mV for

each limit amplifier.

The first concern for thermal management is minimizing

the heat which must be dissipated. The separate power

pins V⁺and V^–can be a great aid in minimizing on-chip

power. The output pin can swing to within 1.0V of V⁺or V^–

even under maximum output current conditions. Using

separate power supplies, or off chip dissipative elements,

to set V⁺and V^–to their minimum values for the required

output swing will minimize power dissipation. The sup-

plies V_CCand V_EEmay also be reduced to a minimal value,

1970f

10

LT1970

W U U

APPLICATIO S I FOR ATIO

U

but these supply pins do not carry high currents, and the

power saving is much less. V_CCand V_EEmust be greater

than the maximum output swing by 2V or more.

and reducing peaking. The current sense resistor, usually

connected between the output pin and the load can serve

as a part of the decoupling resistance.

WhenV^–andV⁺areprovidedseparatelyfromV_CCandV_EE,

care must be taken to insure that V^–and V⁺are always less

than or equal to the main supplies in magnitude. Protec-

tion Schottky diodes may be required to insure this in all

cases, including power on/off transients.

OperationwithreducedV⁺andV^–suppliesdoesnotaffect

any performance parameters except maximum output

swing.AllDCaccuracyandACperformancespecifications

guaranteed with V_CC= V⁺and V_EE= V^–are still valid within

the reduced signal swing range.

Very large capacitive loads above 1µF can also cause

transient overshoots when the current limiting circuits

activate. TheFILTERpinisprovidedtoassistincontrolling

this problem. Should load capacitance cause transient

overshoot, a 1nF to 100nF capacitor between the FILTER

and SENSE^–pins will minimize the overshoot. The best

value of capacitor to use in this situation will likely require

some empirical evaluation, as the optimum is a complex

function of output current, load resistance, sense resistor

and load capacitance.

Inductive Loads

Heat Sinking

Load inductance is usually not a problem at the outputs of

operational amplifiers, but the LT1970 can be used as a

high output impedance current source. This condition

may be the main operating mode, or when the circuit

entersaprotectivecurrentlimitmode. Justasloadcapaci-

tance degrades the phase margin of normal op amps, load

inductance causes a peaking in the loop response of the

feedback controlled current source. The inductive load

maybecausedbylongleadlengthsattheamplifieroutput.

If the amplifier will be driving inductive loads or long lead

lengths (greater than 4 inches) a 500pF capacitor from the

SENSE^–pin to the ground plane will cancel the inductive

load and insure stability.

The power dissipated in the LT1970 die must have a path

to the environment. With 100°C/W thermal resistance in

free air with no heat sink, the package power dissipation is

limited to only 1W. The 20-pin TSSOP package with

exposed copper underside is an efficient heat conductor if

it is effectively mounted on a PC board. Thermal resis-

tances as low as 40°C/W can be obtained by soldering the

bottom of the package to a large copper pattern on the PC

board. For operation at 85°C, this allows up to 1.625W of

power to be dissipated on the LT1970. At 25°C operation,

up to 3.125W of power dissipation can be achieved. The

PC board heat spreading copper area must be connected

to V_EE.

Supply Bypassing

DRIVING REACTIVE LOADS

Capacitive Loads

The LT1970 can supply large currents from the power

suppliestoaloadatfrequenciesupto4MHz.Powersupply

impedance must be kept low enough to deliver these

currents without causing supply rails to droop. Low ESR

capacitors, such as 0.1µF or 1µF ceramics, located close

to the pins are essential in all applications. When large,

high speed transient currents are present additional ca-

pacitance may be needed near the chip. Check supply rails

with a scope and if signal related ripple is seen on the

supply rail, increase the decoupling capacitor as needed.

The LT1970 is much more tolerant of capacitive loading

thanmostoperationalamplifiers. Inaworst-caseconfigu-

ration as a voltage follower, the circuit is stable for capaci-

tive loads less than 2.5nF. Higher gain configurations

improve the C_LOADhandling. If very large capacitive loads

are to be driven, a resistive decoupling of the amplifier

fromthecapacitiveloadiseffectiveinmaintainingstability

1970f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.

11

LT1970

U

TYPICAL APPLICATIO

A_V= –1 Amplifier with Discrete Power Devices to Boost Output Current to 5A

V

CC

CURRENT LIMIT

CONTROL VOLTAGE

0V TO 5V

15V

10µF

0.1µF

100Ω

IRF9640

V

CC

ENABLE

+IN

1k

VC

SRC

VC

SNK

+

V

100Ω

OUT

LT1970

+

SENSE

–

SENSE

R

CS

COMMON

V

0.1Ω

–IN

–

5W

V

EE

LOAD

2.2k

V

IN

IRF9540

100Ω

V

EE

–15V

10µF

0.1µF

1970 TA03

U

PACKAGE DESCRIPTIO

FE Package

20-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663,

Exposed Pad Variation CA)

6.60 ±0.10

4.50 ±0.10

0.45 ±0.05

1.05 ±0.10

0.65 BSC

6.40 – 6.60*

(.252 – .260)

5.2

RECOMMENDED SOLDER PAD

1.15

(.0453)

MAX

(.205)

4.30 – 4.48*

(.169 – .176)

20 1918 17 16 15 14 1312 11

0° – 8°

EXPOSED

PAD HEAT SINK

ON BOTTOM OF

PACKAGE

0.65

(.0256)

BSC

0.50 – 0.70

(.020 – .028)

3.0

6.25 – 6.50

0.105 – 0.180

(.0041 – .0071)

0.05 – 0.15

(.002 – .006)

(.118) (.246 – .256)

0.195 – 0.30

(.0077 – .0118)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

FE20 TSSOP 1101

5

7

8

1

2

3

4

6

9 10

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .150mm (.006") PER SIDE

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LT1010

Fast ±150mA Power Buffer

LT1206

250mA/60MHz Current Feedback Amplifier

1.1A/35MHz Current Feedback Amplifier

Shutdown Mode, Adjustable Supply Current

Stable with C = 10,000pF

LT1210

L

1970f

LT/TP 0102 2K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

12

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

LINEAR TECHNOLOGY CORPORATION 2002


型号：	LT1970CFE#TR
厂家：	Linear
描述：	LT1970 - 500mA Power Op Amp with Adjustable Precision Current Limit; Package: TSSOP; Pins: 20; Temperature Range: 0°C to 70°C 运算放大器
文件：	总12页 (文件大小：234K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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