LT3800IFE#PBF [Linear]
LT3800 - High-Voltage Synchronous Current Mode Step-Down Controller; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LT3800IFE#PBF |
| 厂家： | 
Linear |
| 描述： | LT3800 - High-Voltage Synchronous Current Mode Step-Down Controller; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C 开关 光电二极管 输出元件 |
| 文件： | 总24页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3800
High-Voltage Synchronous
Current Mode Step-Down
Controller
FEATURES
DESCRIPTION
The LT®3800 is a 200kHz fixed frequency high voltage
synchronouscurrentmodestep-downswitchingregulator
controller. The IC drives standard gate N-channel power
MOSFETs and can operate with input voltages from 4V to
60V. AnonboardregulatorprovidesICpowerdirectlyfrom
n
Wide 4V to 60V Input Voltage Range
n
Output Voltages up to 36V
n
Adaptive Nonoverlap Circuitry Prevents Switch
Shoot-Through
n
Reverse Inductor Current Inhibit for Discontinuous
Operation Improves Efficiency with Light Loads
V
IN
and provides for output-derived power to minimize
IN
n
Output Slew Rate Controlled Soft-Start with
V quiescent current. MOSFET drivers employ an internal
Auto-Reset
dynamic bootstrap feature, maximizing gate-source “ON”
voltages during normal operation for improved operating
efficiencies. TheLT3800incorporatesBurstMode® opera-
tion, which reduces no load quiescent current to under
100μA. Light load efficiencies are also improved through
a reverse inductor current inhibit, allowing the controller
to support discontinuous operation. Both Burst Mode
operation and the reverse-current inhibit features can be
disabled if desired. The LT3800 incorporates a program-
mablesoft-startthatdirectlycontrolsthevoltageslewrate
of the converter output for reduced startup surge currents
and overshoot errors. The LT3800 is available in a 16-lead
thermally enhanced TSSOP package.
n
100μA No Load Quiescent Current
n
Low 10μA Current Shutdown
n
1% Regulation Accuracy
n
200kHz Operating Frequency
n
Standard Gate N-Channel Power MOSFETs
n
Current Limit Unaffected by Duty Cycle
n
Reverse Overcurrent Protection
n
16-Lead Thermally Enhanced TSSOP Package
APPLICATIONS
n
12V and 42V Automotive and Heavy Equipment
n
48V Telecom Power Supplies
L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks
n
Avionics and Industrial Control Systems
Distributed Power Converters
and No R
and ThinSOT are trademarks of Linear Technology Corporation. All other
SENSE
trademarks are the property of their respective owners. Protected by U.S. Patents including
5481178, 6611131, 6304066, 6498466, 6580258.
n
TYPICAL APPLICATION
12V 75W DC/DC Converter with Reverse Current Inhibit and Input UVLO
V
IN
20V TO 55V
Efficiency and Power Loss
+
1μF
100
95
90
85
80
75
70
6
5
4
3
2
1
0
56μF
×3
×2
V
IN
= 24V
V
BOOST
TG
IN
V
IN
= 36V
1μF
Si7850DP
Si7370DP
1M
V
= 60V
LT3800
IN
82.5k
SHDN
SW
1.5nF
V
= 48V
BAS19
1μF
200k
IN
C
SS
15μH
B160
1N4148
174k
1%
BURST_EN
V
CC
20k
1%
LOSS (48V)
V
FB
BG
V
C
PGND
100pF
82.5k
–
+
10
0.1
1
SENSE
SENSE
SGND
I
(A)
LOAD
680pF
0.015Ω
3800 TA01b
V
OUT
12V AT 75W
+
10μF
270μF
3800 TA01a
3800fc
1
LT3800
(Note 1)
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
Supply Voltages
TOP VIEW
Input Supply Pin (V )............................... –0.3V to 65V
IN
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BOOST
TG
IN
Boosted Supply Pin (BOOST).................... –0.3V to 80V
Boosted Supply Voltage (BOOST – SW)... –0.3V to 24V
Boosted Supply Reference Pin (SW)............ –2V to 65V
NC
SHDN
SW
C
SS
NC
17
Local Supply Pin (V ).............................. –0.3V to 24V
CC
BURST_EN
V
CC
Input Voltages
V
FB
BG
+
–
SENSE , SENSE ...................................... –0.3V to 40V
V
C
PGND
+
–
SENSE – SENSE ......................................... –1V to 1V
BURST_EN Pin.......................................... –0.3V to 24V
–
+
SENSE
SENSE
FE PACKAGE
16-LEAD PLASTIC TSSOP
Other Inputs (SHDN, C , V , V ) .......... –0.3V to 5.0V
SS FB
C
Input Currents
T
= 125°C, θ = 40°C/W, θ = 10°C/W
JMAX JA JC
EXPOSED PAD (PIN 17) IS SGND
MUST BE SOLDERED TO PCB
SHDN, C ............................................... –1mA to 1mA
SS
Maximum Temperatures
Operating Junction Temperature Range (Note 2)
LT3800E (Note 3).............................. –40°C to 125°C
LT3800I............................................. –40°C to 125°C
Storage Temperature Range.................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C
ORDER INFORMATION
LEAD FREE FINISH
LT3800EFE#PBF
LT3800IFE#PBF
TAPE AND REEL
LT3800EFE#TRPBF
LT3800IFE#TRPBF
PART MARKING
3800EFE
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
16-Lead Plastic TSSOP
16-Lead Plastic TSSOP
3800IFE
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V,
SENSE– = SENSE+ = 10V, SGND = PGND = SW = 0V, CTG = CBG = 3300pF, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Operating Voltage Range (Note 4)
Minimum Start Voltage
UVLO Threshold (Falling)
UVLO Hysteresis
●
●
●
4
60
V
V
IN
7.5
3.65
3.80
670
3.95
V
mV
I
V
V
V
Supply Current
Burst Mode Current
Shutdown Current
V
V
V
> 9V
●
20
20
8
μA
μA
μA
VIN
IN
IN
IN
CC
BURST_EN
= 0V, V = 1.35V
FB
= 0V
15
SHDN
V
Operating Voltage
●
●
75
20
V
V
V
V
BOOST
Operating Voltage Range (Note 5)
UVLO Threshold (Rising)
UVLO Hysteresis
V
V
V
– V
– V
– V
BOOST
BOOST
BOOST
SW
SW
SW
5
0.4
3800fc
2
LT3800
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V,
SENSE– = SENSE+ = 10V, SGND = PGND = SW = 0V, CTG = CBG = 3300pF, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
BOOST Supply Current (Note 6)
BOOST Burst Mode Current
BOOST Shutdown Current
1.4
0.1
0.1
mA
μA
μA
BOOST
V
V
= 0V
BURST_EN
SHDN
= 0V
V
Operating Voltage (Note 5)
Output Voltage
UVLO Threshold (Rising)
UVLO Hysteresis
●
●
20
8.3
V
V
CC
8.0
6.25
500
V
mV
I
V
V
V
Supply Current (Note 6)
Burst Mode Current
Shutdown Current
●
3
80
3.6
mA
μA
VCC
CC
CC
CC
V
V
= 0V
BURST_EN
SHDN
= 0V
20
μA
Short-Circuit Current
●
●
–40
–120
mA
V
V
Enable Threshold (Rising)
Threshold Hysteresis
1.30
1.35
120
1.40
V
mV
SHDN
Common Mode Range
●
●
0
140
36
175
SENSE
+
+
–
–
Current Limit Sense Voltage
Reverse Protect Sense Voltage
Reverse Current Offset
V
V
V
– V
– V
150
–150
10
mV
mV
mV
SENSE
SENSE
BURST_EN
SENSE
SENSE
, V
BURST_EN
BURST_EN
= V
CC
= V
FB
= 0V or V
I
f
Input Current
SENSE
V
V
V
= 0V
0.8
–20
–0.3
mA
μA
SENSE
SENSE(CM)
SENSE(CM)
SENSE(CM)
+
–
(I
+ I
)
SENSE
= 2.75V
> 4V
mA
Operating Frequency
190
175
200
1.231
25
210
220
kHz
kHz
O
●
●
V
Error Amp Reference Voltage
Feedback Input Current
Measured at V Pin
1.224
1.215
1.238
1.245
V
V
FB
FB
I
FB
nA
V
Soft-Start Disable Voltage
Soft-Start Disable Hysteresis
V
Rising
FB
1.185
300
V
mV
FB(SS)
I
Soft-Start Capacitor Control Current
Error Amp Transconductance
Error Amp DC Voltage Gain
Error Amp Output Range
2
μA
μmhos
dB
CSS
g
●
275
350
62
400
m
A
V
V
C
Zero Current to Current Limit
10% to 90% or 90% to 10%
1.2
30
V
I
Error Amp Sink/Source Current
μA
VC
V
Gate Drive Output On Voltage (Note 7)
Gate Drive Output Off Voltage
9.8
0.1
V
V
TG,BG
t
t
t
t
Gate Drive Rise/Fall Time
Minimum Off Time
50
ns
ns
ns
TG,BG
TG(OFF)
TG(ON)
NOL
450
300
Minimum On Time
●
500
Gate Drive Nonoverlap Time
TG Fall to BG Rise
BG Fall to TG Rise
200
150
ns
ns
3800fc
3
LT3800
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
LT3800I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 4: V voltages below the start-up threshold (7.5V) are only
IN
supported when V is externally driven above 6.5V.
CC
Note 2: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: The LT3800E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
Note 5: Operating range dictated by MOSFET absolute maximum gate-
source voltage ratings.
Note 6: Supply current specification does not include switch drive
currents. Actual supply currents will be higher.
Note 7: DC measurement of gate drive output “ON” voltage is typically
8.6V. Internal dynamic bootstrap operation yields typical gate “ON”
voltages of 9.8V during standard switching operation. Standard operation
gate “ON” voltage is not tested but guaranteed by design.
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Threshold (Rising)
vs Temperature
Shutdown Threshold (Falling)
vs Temperature
VCC vs Temperature
1.37
1.36
1.35
1.34
1.33
1.240
1.235
1.230
1.225
1.220
8.1
8.0
7.9
7.8
I
CC
= 0mA
I
= 20mA
CC
–50 –25
0
25
50
75
100 125
50
75
–50 –25
0
25
50
75
100 125
–50 –25
100 125
0
25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3800 G01
3800 G02
3800 G03
VCC vs ICC(LOAD)
VCC vs VIN
ICC Current Limit vs Temperature
8
7
6
5
4
3
200
8.05
8.00
7.95
7.90
7.85
I
= 20mA
= 25°C
T
= 25°C
CC
A
A
T
175
150
125
100
75
50
8
4
5
6
7
9
10 11 12
–50 –25
0
25
50
75
100 125
0
5
15 20 25 30
(mA)
40
10
35
V
(V)
TEMPERATURE (°C)
I
IN
CC(LOAD)
3800 G05
3800 G06
3800 G04
3800fc
4
LT3800
TYPICAL PERFORMANCE CHARACTERISTICS
VCC UVLO Threshold (Rising)
Error Amp Transconductance
vs Temperature
vs Temperature
ICC vs VCC (SHDN = 0V)
25
20
15
6.30
6.25
6.20
6.15
380
360
340
320
T
= 25°C
A
10
5
0
0
2
4
6
8
10 12 14 16 18 20
(V)
–50 –25
0
25
50
75
100 125
–50 –25
0
25
50
75
100 125
V
TEMPERATURE (°C)
TEMPERATURE (°C)
CC
3800 G12
3800 G07
3800 G08
Operating Frequency
vs Temperature
Error Amp Reference
vs Temperature
+
–
I(SENSE + SENSE ) vs VSENSE(CM)
800
600
400
200
0
1.232
1.231
1.230
1.229
1.228
1.227
220
210
200
190
180
T
= 25°C
A
–200
–400
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(V)
–50 –25
0
25
50
75
100 125
–50 –25
0
25
50
75
100 125
V
TEMPERATURE (°C)
SENSE(CM)
TEMPERATURE (°C)
3800 G09
3800 G11
3800 G10
PIN FUNCTIONS
IN
V (Pin 1): Converter Input Supply.
C
(Pin 4): Soft-Start AC Coupling Capacitor Input.
SS
Connect capacitor (C ) in series with a 200k resistor
SS
NC (Pin 2): No Connection.
from pin to converter output (V ). Controls converter
start-up output voltage slew rate (∆V /∆t). Slew rate
correspondsto2μAaveragecurrentthroughthesoft-start
couplingcapacitor.Thecapacitorvalueforadesiredoutput
startup slew rate follows the relation:
OUT
SHDN (Pin 3): Precision Shutdown Pin. Enable threshold
is 1.35V (rising) with 120mV of input hysteresis. When
in shutdown mode, all internal IC functions are disabled.
The precision threshold allows use of the SHDN pin to
incorporate UVLO functions. If the SHDN pin is pulled
below 0.7V, the IC enters a low current shutdown mode
OUT
C
= 2μA/(∆V /∆t)
OUT
SS
with I
< 10μA. In low-current shutdown, the IC will
Shorting this pin to SGND disables the soft-start function
VIN
sink 20μA from the V pin until that local supply has
CC
BURST_EN (Pin 5): Burst Mode Operation Enable Pin.
collapsed. Typical pin input bias current is <10nA and the
pin is internally clamped to 6V.
This pin also controls reverse-inhibit mode of operation.
When the pin voltage is below 0.5V, Burst Mode operation
3800fc
5
LT3800
PIN FUNCTIONS
and reverse-current inhibit functions are enabled. When
the pin voltage is above 0.5V, Burst Mode operation is dis-
abled, but reverse-current inhibit operation is maintained.
DC/DC converters operating with reverse-current inhibit
V pin is set at 100mV below the burst threshold, which
C
limits the negative excursion of the pin voltage. There-
fore, this pin cannot be pulled low with a low-impedance
source. If the V pin must be externally manipulated, do
C
operation (BURST_EN = V ) have a 1mA minimum load
so through a 1kꢀ series resistance.
FB
requirement. Reverse-current inhibit is disabled when the
pin voltage is above 2.5V. This pin is typically shorted to
groundtoenableBurstModeoperationandreverse-current
–
SENSE (Pin 8): Negative Input for Current Sense Ampli-
fier. Sensed inductor current limit set at 150mV across
SENSE inputs.
inhibit, shorted to V to disable Burst Mode operation
FB
+
SENSE (Pin 9): Positive Input for Current Sense Ampli-
while enabling reverse-current inhibit, and connected
fier. Sensed inductor current limit set at 150mV across
SENSE inputs.
to V pin to disable both functions. See Applications
CC
Information section.
PGND (Pin 10): High Current Ground Reference for Syn-
V (Pin6):ErrorAmplifierInvertingInput.Thenoninvert-
FB
chronousSwitch.Currentpathfrompintonegativeterminal
ing input of the error amplifier is connected to an internal
of V decoupling capacitor must not corrupt SGND.
1.231Vreference.Desiredconverteroutputvoltage(V
)
CC
OUT
is programmed by connecting a resistive divider from the
converter output to the V pin. Values for the resistor
BG (Pin 11): Synchronous Switch Gate Drive Output.
FB
V
(Pin 12): Internal Regulator Output. Most IC func-
CC
connected from V
to V (R2) and the resistor con-
OUT
FB
tions are powered from this pin. Driving this pin from
nected from V to ground (R1) can be calculated via the
FB
an external source reduces V pin current to 20μA.
IN
following relationship:
This pin is decoupled with a low ESR 1μF capacitor to
PGND. In shutdown mode, this pin sinks 20μA until the
pin voltage is discharged to 0V. See Typical Performance
Characteristics.
V
ꢀ
ꢃ
OUT
R2=R1•
–1
ꢅ
ꢂ
ꢁ
ꢄ
1.231
The V pin input bias current is 25nA, so use of extremely
FB
NC (Pin 13): No Connection.
high value feedback resistors could cause a converter
output that is slightly higher than expected. Bias current
error at the output can be estimated as:
SW (Pin 14): Reference for V
Supply and High Cur-
BOOST
rent Return for Bootstrapped Switch.
TG (Pin 15): Bootstrapped Switch Gate Drive Output.
∆V
= 25nA • R2
OUT(BIAS)
BOOST(Pin16):BootstrappedSupply–MaximumOperat-
ingVoltage(GroundReferred)to75V.Thispinisdecoupled
with a low ESR 1μF capacitor to pin SW. The voltage on
the decoupling capacitor is refreshed through a rectifier
V (Pin 7): Error Amplifier Output. The voltage on the V
C
C
pincorrespondstothemaximum(peak)switchcurrentper
oscillator cycle. The error amplifier is typically configured
as an integrator by connecting an RC network from this
pin to ground. This network creates the dominant pole for
the converter voltage regulation feedback loop. Specific
integrator characteristics can be configured to optimize
transient response. Connecting a 100pF or greater high
frequency bypass capacitor from this pin to ground is also
recommended.WhenBurstModeoperationisenabled(see
Pin5description),aninternallowimpedanceclamponthe
from either V or an external source.
CC
Exposed Package Backside (SGND) (Pin 17): Low Noise
Ground Reference. SGND connection is made through
the exposed lead frame on back of TSSOP package which
must be soldered to the PCB ground.
3800fc
6
LT3800
FUNCTIONAL DIAGRAM
V
IN
UVLO
(<4V)
BST
V
BOOST
16
15
CC
UVLO
1
V
IN
UVLO
(<6V)
8V
REG
BOOSTED
SWITCH
DRIVER
3.8V
REG
INTERNAL
SUPPLY RAIL
DRIVE
CONTROL
TG
FEEDBACK
SW
14
12
REFERENCE
NOL
–
+
1.231V
SWITCH
LOGIC
V
CC
+
–
3
5
SHDN
SYNCHRONOUS
SWITCH DRIVER
DRIVE
CONTROL
BG
11
10
PGND
+
–
BURST_EN
OSCILLATOR
+
–
Q
R
S
6
7
V
FB
SLOPE COMP
GENERATOR
–
+
g
m
Q
ERROR
AMP
R
0.5V
CURRENT
SENSE
–
+
COMPARATOR
V
S
C
SOFT-START
DISABLE/BURST
–
+
REVERSE
CURRENT
INHIBIT
ENABLE
+
1V
–
–
+
Burst Mode
OPERATION
1.185V
160mV
2μA
4
C
SS
–
+
+
SENSE
SENSE
9
8
10mV
–
GND
17
3800 FD
3800fc
7
LT3800
APPLICATIONS INFORMATION
Overview
threshold is not obtained for the entire oscillator cycle,
the switch driver is disabled at the end of the cycle for
450ns. This minimum off-time mode of operation assures
regeneration of the BOOST bootstrapped supply.
The LT3800 is a high input voltage range step-down
synchronous DC/DC converter controller IC that uses a
200kHz constant frequency, current mode architecture
with external N-channel MOSFET switches.
Power Requirements
The LT3800 has provisions for high efficiency, low load
operation for battery-powered applications. Burst Mode
operationreducestotalaverageinputquiescentcurrentsto
100μA during no load conditions. A low current shutdown
mode can also be activated, reducing quiescent current to
<10μA. Burst Mode operation can be disabled if desired.
The LT3800 is biased using a local linear regulator to
generate internal operational voltages from the V pin.
IN
Virtually all of the circuitry in the LT3800 is biased via an
internallinearregulatoroutput(V ).Thispinisdecoupled
CC
with a low ESR 1μF capacitor to PGND.
The V regulator generates an 8V output provided there
CC
TheLT3800alsoemploysareverse-currentinhibitfeature,
allowing increased efficiencies during light loads through
nonsynchronous operation. This feature disables the
synchronous switch if inductor current approaches zero.
If full time synchronous operation is desired, this feature
can be disabled.
is ample voltage on the V pin. The V regulator has
IN
CC
approximately 1V of dropout, and will follow the V pin
IN
with voltages below the dropout threshold.
The LT3800 has a start-up requirement of V > 7.5V. This
IN
assures that the onboard regulator has ample headroom
to bring the V pin above its UVLO threshold. The V
CC
CC
Much of the LT3800’s internal circuitry is biased from an
internal linear regulator. The output of this regulator is
regulator can only source current, so forcing the V pin
CC
above its 8V regulated voltage allows use of externally
derived power for the IC, minimizing power dissipation
in the IC. Using the onboard regulator for start-up, then
the V pin, allowing bypassing of the internal regulator.
CC
The associated internal circuitry can be powered from
the output of the converter, increasing overall converter
efficiency. Using externally derived power also eliminates
deriving power for V from the converter output maxi-
CC
mizes conversion efficiencies and is common practice. If
the IC’s power dissipation associated with the internal V
IN
V
is maintained above 6.5V using an external source,
CC
to V regulator.
CC
the LT3800 can continue to operate with V as low as 4V.
IN
Theory of Operation (See Block Diagram)
The LT3800 operates with 3mA quiescent current from
the V supply. This current is a fraction of the actual V
CC
CC
The LT3800 senses converter output voltage via the V
FB
quiescent currents during normal operation. Additional
current is produced from the MOSFET switching currents
for both the boosted and synchronous switches and are
pin. The difference between the voltage on this pin and
an internal 1.231V reference is amplified to generate an
error voltage on the V pin which is, in turn, used as a
C
typically derived from the V supply.
CC
threshold for the current sense comparator.
Because the LT3800 uses a linear regulator to generate
During normal operation, the LT3800 internal oscilla-
tor runs at 200kHz. At the beginning of each oscillator
cycle, the switch drive is enabled. The switch drive stays
V , power dissipation can become a concern with high
CC
V voltages. Gate drive currents are typically in the range
IN
of 5mA to 15mA per MOSFET, so gate drive currents can
enabled until the sensed switch current exceeds the V
C
create substantial power dissipation. It is advisable to
derivedthresholdforthecurrentsensecomparatorand,in
derive V and V
power from an external source
BOOST
CC
turn, disables the switch driver. If the current comparator
whenever possible.
3800fc
8
LT3800
APPLICATIONS INFORMATION
Charge Pump Doubler
The onboard V regulator will provide gate drive power
CC
for start-up under all conditions with total MOSFET gate
charge loads up to 180nC. The regulator can operate the
V
OUT
B0520
B0520
V
LT3800 continuously, provided the V voltage and/or
CC
IN
1μF
1μF
MOSFET gate charge currents do not create excessive
power dissipation in the IC. Safe operating conditions
for continuous regulator use are shown in Figure 1. In
LT3800
Si1555DL
BG
applications where these conditions are exceeded, V
CC
must be derived from an external source after start-up.
Charge Pump Tripler
70
V
OUT
1μF
60
B0520
B0520
50
40
1μF
B0520
1μF
V
CC
Si1555DL
Si1555DL
30
LT3800
SAFE
OPERATING
CONDITIONS
20
10
3800 AI01
BG
0
50
100
150
200
TOTAL FET GATE CHARGE (nC)
3800 F01
Inductor Auxiliary Winding
Figure 1. VCC Regulator Continuous Operating Conditions
In LT3800 converter applications with output voltages in
TG
the 9V to 20V range, back-feeding V and V
from
SW
CC
BOOST
LT3800
the converter output is trivial, accomplished by connect-
ing diodes from the output to these supply pins. Deriving
these supplies from output voltages greater than 20V will
requireadditionalregulationtoreducethefeedbackvoltage.
Outputs lower than 9V will require step-up techniques to
increase the feedback voltage to something greater than
N
•
V
V
OUT
CC
•
BG
3800 AI04
the 8V V regulated output. Low power boost switchers
CC
are sometimes used to provide the step-up function, but
a simple charge-pump can perform this function in many
instances.
3800fc
9
LT3800
APPLICATIONS INFORMATION
Burst Mode
During Burst Mode operation, V pin current is 20μA
IN
and V current is reduced to 80μA. If no external drive is
CC
The LT3800 employs low current Burst Mode functional-
ity to maximize efficiency during no load and low load
conditions. Burst Mode operation is enabled by shorting
the BURST_EN pin to SGND. Burst Mode operation can
provided for V , all V bias currents originate from the
CC
CC
V pin, giving a total V current of 100μA. Burst current
IN
IN
can be reduced further when V is driven using an output
CC
derived source, as the V component of V current is
CC
IN
be disabled by shorting BURST_EN to either V or V .
FB
CC
then reduced by the converter buck ratio.
When the required switch current, sensed via the V
C
Reverse-Current Inhibit
pin voltage, is below 15% of maximum, the Burst Mode
operation is employed and that level of sense current is
latchedontotheICcontrolpath. Iftheoutputloadrequires
less than this latched current level, the converter will
overdrive the output slightly during each switch cycle.
This overdrive condition is sensed internally and forces
The LT3800 contains a reverse-current inhibit feature to
maximize efficiency during light load conditions. This
mode of operation allows discontinuous operation, and
is sometimes referred to as “pulse-skipping” mode. Refer
to Figure 2.
the voltage on the V pin to continue to drop. When the
C
ThisfeatureisenabledwithBurstModeoperation,andcan
also be enabled while Burst Mode operation is disabled
voltage on V drops 150mV below the 15% load level,
C
switching is disabled and the LT3800 shuts down most
of its internal circuitry, reducing total quiescent current
to 100μA. When the converter output begins to fall, the
by shorting the BURST_EN pin to V .
FB
Whenreverse-currentinhibitisenabled, theLT3800sense
amplifier detects inductor currents approaching zero and
disables the synchronous switch for the remainder of
the switch cycle. If the inductor current is allowed to go
negative before the synchronous switch is disabled, the
switch node could inductively kick positive with a high
dv/dt. The LT3800 prevents this by incorporating a 10mV
positive offset at the sense inputs.
V pin voltage begins to climb. When the voltage on the
C
V pin climbs back to the 15% load level, the IC returns
C
to normal operation and switching resumes. An internal
clamp on the V pin is set at 100mV below the switch
C
disable threshold, which limits the negative excursion of
the pin voltage, minimizing the converter output ripple
during Burst Mode operation.
PULSE SKIP MODE
FORCED CONTINUOUS
I
L
I
L
DECREASING
LOAD
CURRENT
3800 F02
Figure 2. Inductor Current vs Mode
3800fc
10
LT3800
APPLICATIONS INFORMATION
Withthereverse-currentinhibitfeatureenabled,anLT3800
converter will operate much like a nonsynchronous
converter during light loads. Reverse-current inhibit
reduces resistive losses associated with inductor ripple
currents, which improves operating efficiencies during
light-load conditions.
responds to 2μA average current during the soft-start
interval. This capacitor value follows the relation:
2E–6 • tSS
CSS1
=
VOUT
is typically set to 200k for most applications.
R
SS
An LT3800 DC/DC converter that is operating in reverse-
inhibit mode has a minimum load requirement of 1mA
C
SS1
LT3800
R
SS
A
V
C
SS
OUT
(BURST_EN = V ). Since most applications use output-
FB
generated power for the LT3800, this requirement is met
by the bias currents of the IC, however, for applications
that do not derive power from the output, this require-
ment is easily accomplished by using a 1.2k resistor
3800 AI06
Considerations for Low Voltage Output Applications
connected from V to ground as one of the converter
The LT3800 C pin biases to 220mV during the soft-start
FB
SS
outputvoltageprogrammingresistors(R1). Thereareno
minimumloadrestrictionswheninBurstModeoperation
(BURST_EN < 0.5V) or continuous conduction mode
(BURST_EN > 2.5V).
cycle, and this voltage is increased at network node “A” by
the 2μA signal current through R , so the output has to
SS
reach this value before the soft-start function is engaged.
The value of this output soft-start start-up voltage offset
(V
) follows the relation:
OUT(SS)
Soft-Start
–6
V
= 220mV + R • 2E
SS
OUT(SS)
The LT3800 incorporates a programmable soft-start
function to control start-up surge currents, limit output
overshootandforuseinsupplysequencing.Thesoft-start
functiondirectlymonitorsandcontrolsoutputvoltageslew
rate during converter start-up.
which is typically 0.64V for R = 200k.
SS
In some low voltage output applications, it may be desir-
able to reduce the value of this soft-start start-up voltage
offset. This is possible by reducing the value of R . With
SS
reduced values of R , the signal component caused by
SS
As the output voltage of the converter rises, the soft-start
voltage ripple on the output must be minimized for proper
circuit monitors δV/δt current through a coupling capaci-
soft-start operation.
tor and adjusts the voltage on the V pin to maintain an
C
average value of 2μA. The soft-start function forces the
Peak-to-peakoutputvoltageripple(∆V )willbeimposed
OUT
programmed slew rate while the converter output rises to
on node “A” through the capacitor C . The value of R
SS1
SS
95% regulation, which corresponds to 1.185V on the V
can be set using the following equation:
FB
pin. Once 95% regulation is achieved, the soft-start circuit
ꢀVOUT
1.3E–6
RSS
=
is disabled. The soft-start circuit will re-enable when the
V pindropsbelow70%regulation,whichcorrespondsto
FB
ItisimportanttouselowESRoutputcapacitorsforLT3800
voltage converter designs to minimize this ripple voltage
component. A design with an excessive ripple component
300mV of control hysteresis on the V pin, which allows
FB
for a controlled recovery from a ‘brown-out’ condition.
The desired soft-start rise time (t ) is programmed via
SS
can be evidenced by observing the V pin during the start
C
a programming capacitor C , using a value that cor-
SS1
cycle.
3800fc
11
LT3800
APPLICATIONS INFORMATION
Soft-Start Characteristic Showing Excessive Ripple Component
Desirable Soft-Start Characteristic
V
V
OUT
OUT
V
V
OUT(SS)
OUT(SS)
V(V )
V(V )
C
C
3800 AI07
3800 AI08
250μs/DIV
250μs/DIV
The soft-start cycle should be evaluated to verify that the
Inductor current typically doesn’t reach I
in the few
MAX
reduced R value allows operation without excessive
cyclesthatoccurbeforesoft-startbecomesactive,butcan
with high input voltages or small inductors, so the above
relation is useful as a worst-case scenario.
SS
modulation of the V pin before finalizing the design.
C
If the V pin has an excessive ripple component during the
C
soft-startcycle, converteroutputrippleshouldbereduced
This energy transfer increase in output voltage is typically
small,butforsomelowvoltageapplicationswithrelatively
smalloutputcapacitors,itcanbecomesignificant.Thevolt-
age rise can be reduced by increasing output capacitance,
or R increased. Reduction in converter output ripple is
SS
typically accomplished by increasing output capacitance
and/or reducing output capacitor ESR.
which puts additional limitations on C
for these low
OUT
External Current Limit Foldback Circuit
voltage supplies. Another approach is to add an external
current limit foldback circuit which reduces the value of
An additional start-up voltage offset can occur during the
periodbeforetheLT3800soft-startcircuitbecomesactive.
I
during start-up.
MAX
Before the soft-start circuit throttles back the V pin in
An external current limit foldback circuit can be easily
incorporated into an LT3800 DC/DC converter application
by placing a 1N4148 diode and a 47k resistor from the
C
response to the rising output voltage, current as high as
the peak programmed current limit (I
) can flow in the
MAX
inductor.Switchingwillstoponcethesoft-startcircuittakes
converter output (V ) to the LT3800’s V pin. This limits
OUT
C
OUT
hold and reduces the voltage on the V pin, but the output
the peak current to 0.25 • I
when V
= 0V. A current
C
MAX
voltage will continue to increase as the stored energy in
limit foldback circuit also has the added advantage of
providingareducedoutputcurrentintheDC/DCconverter
during short-circuit fault conditions, so a foldback circuit
may be useful even if the soft-start function is disabled.
the inductor is transferred to the output capacitor. With
I
flowing in the inductor, the resulting leading-edge
MAX
rise on V
due to energy stored in the inductor follows
OUT
the relationship:
If the soft-start circuit is disabled by shorting the C pin
SS
ꢄ1/2
to ground, the external current limit fold-back circuit must
be modified by adding an additional diode and resistor.
The 2-diode, 2-resistor network shown also provides
ꢁ
L
ꢀVOUT =IMAX
•
ꢃ
ꢆ
C
ꢂ
OUT ꢅ
0.25 • I
when V
= 0V.
MAX
OUT
3800fc
12
LT3800
APPLICATIONS INFORMATION
Current Limit Foldback Circuit for
Applications That Use Soft-Start
Alternative Current Limit Foldback Circuit for Applications That
Have Soft-Start Disabled
V
C
V
C
1N4148
1N4148
39k
27k
1N4148
47k
V
OUT
3800 AI10
V
3800 AI09
OUT
Adaptive Nonoverlap (NOL) Output Stage
Shutdown
TheFETdriveroutputstagesimplementadaptivenonover-
lap control. This feature maintains a constant dead time,
preventing shoot-through switch currents, independent
of the type, size or operating conditions of the external
switch elements.
TheLT3800SHDNpinusesabandgapgeneratedreference
threshold of 1.35V. This precision threshold allows use of
the SHDN pin for both logic-level controlled applications
and analog monitoring applications such as power supply
sequencing.
Each of the two switch drivers contains a NOL control
circuit, which monitors the output gate drive signal of the
other switch driver. The NOL control circuits interrupt the
“turn on” command to their associated switch driver until
the other switch gate is fully discharged.
The LT3800 operational status is primarily controlled by
a UVLO circuit on the V regulator pin. When the IC is
CC
enabledviatheSHDNpin,onlytheV regulatorisenabled.
CC
Switching remains disabled until the UVLO threshold is
achieved at the V pin, when the remainder of the IC is
CC
enabled and switching commences.
Antislope Compensation
Because an LT3800 controlled converter is a power
transfer device, a voltage that is lower than expected on
the input supply could require currents that exceed the
sourcing capabilities of that supply, causing the system
to lock up in an undervoltage state. Input supply start-up
protection can be achieved by enabling the SHDN pin
Most current mode switching controllers use slope com-
pensation to prevent current mode instability. The LT3800
is no exception. A slope-compensation circuit imposes an
artificial ramp on the sensed current to increase the rising
slopeasdutycycleincreases.Unfortunately,thisadditional
ramp corrupts the sensed current value, reducing the
achievable current limit value by the same amount as the
added ramp represents. As such, current limit is typically
reduced as duty cycles increase. The LT3800 contains
circuitry to eliminate the current limit reduction typically
associated with slope compensation. As the slope-com-
pensation ramp is added to the sensed current, a similar
ramp is added to the current limit threshold reference.
The end result is that current limit is not compromised,
so a LT3800 converter can provide full power regardless
of required duty cycle.
using a resistive divider from the V supply to ground.
IN
Setting the divider output to 1.35V when that supply is at
an adequate voltage prevents an LT3800 converter from
drawing large currents until the input supply is able to
provide the required power. 120mV of input hysteresis
on the SHDN pin allows for almost 10% of input supply
droop before disabling the converter.
3800fc
13
LT3800
APPLICATIONS INFORMATION
Programming LT3800 VIN UVLO
Inductor Selection
TheprimarycriterionforinductorvalueselectioninLT3800
applicationsisripplecurrentcreatedinthatinductor.Basic
designconsiderationsforripplecurrentareoutputvoltage
ripple, and the ability of the internal slope compensation
waveform to prevent current mode instability. Once the
value is determined, an inductor must also have a satu-
ration current equal to or exceeding the maximum peak
current in the inductor.
V
IN
LT3800
R
R
B
A
3
SHDN
SGND
17
3800 AI02
Ripple current (∆I ) in an inductor for a given value (L)
L
The UVLO voltage, V
relation:
, is set using the following
can be approximated using the relation:
IN(UVLO)
ꢁ
OUT ꢄ
V
VOUT
fO •L
ꢀIL = 1–
•
ꢆ
VIN(UVLO) –1.35V
ꢃ
ꢂ
V
ꢅ
IN
RA =RB •
1.35V
The typical range of values for ∆I is 20% to 40% of
, where I is the maximum converter
output load current. Ripple currents in this range typically
yield a good design compromise between inductor perfor-
mance versus inductor size and cost, and values in this
range are generally a good starting point. A starting point
inductor value can thus be determined using the relation:
If additional hysteresis is desired for the enable function,
an external positive feedback resistor can be used from
the LT3800 regulator output.
I
OUT(MAX)
OUT(MAX)
The shutdown function can be disabled by connecting the
SHDNpintoV throughalargevaluepull-upresistor.This
IN
pin contains a low impedance clamp at 6V, so the SHDN
pin will sink current from the pull-up resistor (R ):
PU
ꢀ
OUT ꢃ
V
1–
ꢂ
ꢅ
V – 6V
RPU
VIN
IN
ꢁ
ꢄ
ISHDN
=
L = VOUT
•
fO •0.3•IOUT(MAX)
Because this arrangement will pull the SHDN pin to the
6V clamp voltage, it will violate the 5V absolute maximum
voltage rating of the pin. This is permitted, however, as
long as the absolute maximum input current rating of
1mA is not exceeded. Input SHDN pin currents of <100μA
are recommended; a 1Mꢀ or greater pull-up resistor is
typically used for this configuration.
Use of smaller inductors increase output ripple currents,
requiring more capacitance on the converter output. Also,
with converter operation with duty cycles greater than
50%, the slope compensation criterion, described later,
mustbemet.Designingforsmallerripplecurrentsrequires
larger inductor values, which can increase converter cost
and/or footprint.
3800fc
14
LT3800
APPLICATIONS INFORMATION
Some magnetics vendors specify a volt-second product
in their data sheet. If they do not, consult the vendor to
make sure the specification is not being exceeded by your
design. The required volt-second product is calculated as
follows:
duty cycle, to generate an equivalent slope of at least
5
1E • I
A/sec, where I
is the programmed con-
LIMIT
LIMIT
verter current limit. Current limit is programmed by using
a sense resistor (R ) such that I = 150mV/R , so the
S
LIMIT
S
equation for the minimum inductance to meet the current
mode instability criterion can be reduced to:
ꢁ
ꢃ
ꢂ
OUT ꢄ
V
VOUT
fO
–5
Volt-Secondꢀ
• 1–
L
MIN
= (5E )(V )(R )
ꢆ
OUT
S
V
ꢅ
IN
For example, with V
= 5V and R = 20mꢀ:
S
OUT
Magneticsvendorsspecifyeitherthesaturationcurrent,the
RMS current, or both. When selecting an inductor based
on inductor saturation current, the peak current through
–5
L
= (5E )(5)(0.02) = 5μH
MIN
After calculating the minimum inductance value, the volt-
secondproduct,thesaturationcurrentandtheRMScurrent
for your design, an off the shelf inductor can be selected
from a magnetics vendor. A list of magnetics vendors
can be found at http://www.linear.com/ezone/vlinks or by
contactingtheLinearTechnologyApplicationsdepartment.
the inductor, I
+ (∆I/2), is used. When selecting
OUT(MAX)
an inductor based on RMS current the maximum load
current, I , is used.
OUT(MAX)
The requirement for avoiding current mode instability is
keeping the rising slope of sensed inductor ripple current
(S1)greaterthanthefallingslope(S2).Duringcontinuous-
current switcher operation, the rising slope of the current
waveform in the switched inductor is less than the falling
slopewhenoperatingatdutycycles(DC)greaterthan50%.
To avoid the instability condition during this operation, a
false signal is added to the sensed current, increasing the
perceivedrisingslope.Topreventcurrentmodeinstability,
the slope of this false signal (Sx) must be sufficient such
that the sensed rising slope exceeds the falling slope, or
S1 + Sx ≥ S2. This leads to the following relations:
Output Voltage Programming
Outputvoltageisprogrammedthrougharesistorfeedback
networktoV (Pin6)ontheLT3800.Thispinistheinverting
FB
input of the error amplifier, which is internally referenced
to 1.231V. The divider is ratioed to provide 1.231V at the
V pin when the output is at its desired value. The output
FB
voltage is thus set following the relation:
V
ꢀ
ꢃ
OUT
R2=R1•
–1
ꢅ
ꢂ
ꢁ
ꢄ
1.231
Sx ≥ S2 (2DC – 1)/DC
where:
when an external resistor divider is connected to the
output as shown.
S2 ~ V /L
OUT
Programming LT3800 Output Voltage
Solving for L yields a relation for the minimum inductance
that will satisfy slope compensation requirements:
V
OUT
2DC – 1
DC • Sx
LT3800
R2
L
MIN = VOUT •
6
V
FB
The LT3800 maximizes available dynamic range using a
slopecompensationgeneratorthatcontinuouslyincreases
the additional signal slope as duty cycle increases. The
slope compensation waveform is calibrated at an 80%
R1
SGND
17
3800 AI03
3800fc
15
LT3800
APPLICATIONS INFORMATION
Power MOSFET Selection
The R
required for a given conduction loss can be
DS(ON)
calculated using the relation:
External N-channel MOSFET switches are used with the
LT3800. The positive gate-source drive voltage of the
LT3800 for both switches is roughly equivalent to the V
supply voltage, for use of standard threshold MOSFETs.
2
P
= I
• R
DS(ON)
LOSS
SWITCH
CC
In high voltage applications (V > 20V), the main switch
IN
is required to slew very large voltages. MOSFET transition
2
Selection criteria for the power MOSFETs include the
losses are proportional to V and can become the domi-
IN
“ON” resistance (R
), total gate charge (Q ), reverse
RSS
nant power loss term in the main switch. This transition
DS(ON)
G
transfer capacitance (C ), maximum drain-source volt-
loss takes the form:
age (V ) and maximum current.
2
DSS
P
≈ (k)(V ) (I
)(C )(f )
SWITCH RSS O
TR
IN
The power FETs selected must have a maximum operating
where k is a constant inversely related to the gate drive
current, approximated by k = 2 in LT3800 applications,
V
exceeding the maximum V . V voltage maximum
DSS
IN GS
must exceed the V supply voltage.
CC
and I
is the converter output current. The power
SWITCH
Total gate charge (Q ) is used to determine the FET gate
loss terms for the switches are thus:
G
drive currents required. Q increases with applied gate
2
G
P
MAIN
=(DC)(I
) (1+d)(R
) +
SWITCH
2
DS(ON)
voltage, so the Q for the maximum applied gate voltage
G
2(V ) (I
)(C )(f )
RSS O
IN
SWITCH
must be used. A graph of Q vs. V is typically provided
G
GS
2
in MOSFET data sheets.
P
= (1 – DC)(I
) (1 + d)(R
)
DS(ON)
SYNC
SWITCH
In a configuration where the LT3800 linear regulator is
The (1 + d) term in the above relations is the temperature
providing V and V
currents, the V 8V output
CC
dependency of R
normalized R
, typically given in the form of a
CC
BOOST
DS(ON)
voltage can be used to determine Q . Required drive cur-
vs Temperature curve in a MOSFET
G
DS(ON)
rent for a given FET follows the simple relation:
data sheet.
I
= Q
• f
The C term is typically smaller for higher voltage FETs,
GATE
G(8V) O
RSS
and it is often advantageous to use a FET with a higher
Q
is the total FET gate charge for V = 8V, and f =
GS 0
G(8V)
V
rating to minimize transition losses at the expense of
DS
operatingfrequency.Ifthesecurrentsareexternallyderived
additional R
losses.
DS(ON)
by backdriving V , use the backfeed voltage to determine
CC
Q . Be aware, however, that even in a backfeed configura-
In some applications, parasitic FET capacitances couple
the negative going switch node transient onto the bottom
gate drive pin of the LT3800, causing a negative voltage
in excess of the Absolute Maximum Rating to be imposed
on that pin. Connection of a catch Schottky diode from
this pin to ground will eliminate this effect. A 1A current
rating is typically sufficient for the diode.
G
tion, the drive currents for both boosted and synchronous
FETs are still typically supplied by the LT3800 internal V
CC
regulatorduringstart-up. TheLT3800canstartusingFETs
with a combined Q
up to 180nC.
G(8V)
Oncevoltagerequirementshavebeendetermined,R
DS(ON)
can be selected based on allowable power dissipation and
required output current.
Input Capacitor Selection
In an LT3800 buck converter, the average inductor cur-
rent is equal to the DC load current. The average cur-
rents through the main (bootstrapped) and synchronous
(ground-referred) switches are:
The large currents typical of LT3800 applications require
special consideration for the converter input and output
supply decoupling capacitors. Under normal steady state
buck operation, the source current of the main switch
I
I
= (I
= (I
)(DC)
MAIN
SYNC
LOAD
MOSFET is a square wave of duty cycle V /V . Most
OUT IN
of this current is provided by the input bypass capacitor.
)(1 – DC)
LOAD
3800fc
16
LT3800
APPLICATIONS INFORMATION
To prevent large input voltage transients and avoid bypass
capacitor heating, a low ESR input capacitor sized for the
maximum RMS current must be used. This maximum
capacitor RMS current follows the relation:
∆V
increases with input voltage, so the maximum
OUT
operating input voltage should be used for worst-case
calculations. Multiple capacitors are often paralleled to
meet ESR requirements. Typically, once the ESR require-
ment is satisfied, the capacitance is adequate for filtering
and has the required RMS current rating. An additional
ceramic capacitor in parallel is commonly used to reduce
the effect of parasitic inductance in the output capacitor,
which reduces high frequency switching noise on the
converter output.
1
2
IMAX
V
V – V
(
)
(
)
OUT IN OUT
IRMS
=
VIN
which peaks at a 50% duty cycle, when I
= I
/2.
RMS
MAX
The bulk capacitance is calculated based on an accept-
IncreasinginductanceisanoptiontoreduceESRrequire-
ments. For extremely low ∆VOUT, an additional LC filter
stagecanbeaddedtotheoutputofthesupply.Application
Note 44 has information on sizing an additional output
LC filter.
able maximum input ripple voltage, ∆V , which follows
IN
the relation:
VOUT
V
IN
CIN(BULK) =IOUT(MAX) •
ꢀV • fO
IN
Layout Considerations
∆Vistypicallyontheorderof100mVto200mV.Aluminum
electrolytic capacitors are a good choice for high voltage,
bulkcapacitanceduetotheirhighcapacitanceperunitarea.
The LT3800 is typically used in DC/DC converter designs
that involve substantial switching transients. The switch
drivers on the IC are designed to drive large capacitances
and,assuch,generatesignificanttransientcurrentsthem-
selves. Careful consideration must be made regarding
supply bypass capacitor locations to avoid corrupting the
ground reference used by IC.
The capacitor voltage rating must be rated greater than
V
. The combination of aluminum electrolytic ca-
IN(MAX)
pacitors and ceramic capacitors is a common approach
to meeting supply input capacitor requirements. Multiple
capacitors are also commonly paralleled to meet size or
height requirements in a design.
Typically, high current paths and transients from the input
supply and any local drive supplies must be kept isolated
from SGND, to which sensitive circuits such as the error
amp reference and the current sense circuits are referred.
Capacitor ripple current ratings are often based on only
2000hours(threemonths)lifetime;itisadvisabletoderate
either the ESR or temperature rating of the capacitor for
increased MTBF of the regulator.
Effectivegroundingcanbeachievedbyconsideringswitch
currentinthegroundplane,andthereturncurrentpathsof
each respective bypass capacitor. The V bypass return,
Output Capacitor Selection
IN
V
bypass return, and the source of the synchronous
CC
The output capacitor in a buck converter generally has
much less ripple current than the input capacitor. Peak-to-
FET carry PGND currents. SGND originates at the negative
terminal of the V
signal reference for the LT3800.
bypass capacitor, and is the small
OUT
peak ripple current is equal to that in the inductor (∆I ),
L
typically a fraction of the load current. C
is selected
OUT
Don’t be tempted to run small traces to separate ground
paths. A good ground plane is important as always, but
PGND referred bypass elements must be oriented such
thattransientcurrentsinthesereturnpathsdonotcorrupt
the SGND reference.
to reduce output voltage ripple to a desirable value given
an expected output ripple current. Output ripple (∆V
is approximated by:
)
OUT
–1
∆V
≈ ∆I (ESR + [(8)(f ) • C ] )
OUT
L
O
OUT
where f = operating frequency.
O
During the dead-time between switch conduction, the
body diode of the synchronous FET conducts inductor
3800fc
17
LT3800
APPLICATIONS INFORMATION
current. Commutating this diode requires a significant
charge contribution from the main switch. At the instant
the body diode commutates, a current discontinuity is
created and parasitic inductance causes the switch node
to fly up in response to this discontinuity. High cur-
rents and excessive parasitic inductance can generate
extremely fast dV/dt rise times. This phenomenon can
cause avalanche breakdown in the synchronous FET
body diode, significant inductive overshoot on the switch
node, and shoot-through currents via parasitic turn-on of
the synchronous FET. Layout practices and component
orientations that minimize parasitic inductance on this
node is critical for reducing these effects.
not corrupt the SGND reference. Problems caused by the
PGND return path are generally recognized during heavy
load conditions, and are typically evidenced as multiple
switch pulses occurring during a single 5μs switch cycle.
This behavior indicates that SGND is being corrupted and
grounding should be improved. SGND corruption can
often be eliminated, however, by adding a small capacitor
(100pF-200pF) across the synchronous switch FET from
drain to source.
The high di/dt loop formed by the switch MOSFETs and
the input capacitor (C ) should have short wide traces
IN
to minimize high frequency noise and voltage stress from
inductiveringing.Surfacemountcomponentsarepreferred
to reduce parasitic inductances from component leads.
Connect the drain of the main switch MOSFET directly to
Ringingwaveformsinaconvertercircuitcanleadtodevice
failure, excessive EMI, or instability. In many cases, you
can damp a ringing waveform with a series RC network
across the offending device. In LT3800 applications, any
ringing will typically occur on the switch node, which
can usually be reduced by placing a snubber across the
synchronous FET. Use of a snubber network, however,
shouldbeconsideredalastresort.Effectivelayoutpractices
typically reduce ringing and overshoot, and will eliminate
the need for such solutions.
the (+) plate of C , and connect the source of the syn-
IN
chronous switch MOSFET directly to the (–) terminal of
C . This capacitor provides the AC current to the switch
IN
MOSFETs. Switch path currents can be controlled by
orienting switch FETs, the switched inductor, and input
and output decoupling capacitors in close proximity to
each other.
Locate the V and BOOST decoupling capacitors in close
CC
proximity to the IC. These capacitors carry the MOSFET
drivers’ high peak currents. Locate the small-signal
components away from high frequency switching nodes
Effective grounding techniques are critical for successful
DC/DC converter layouts. Orient power path components
such that current paths in the ground plane do not cross
through signal ground areas. Signal ground refers to the
Exposed Pad on the backside of the LT3800 IC. SGND
(BOOST, SW, TG, V and BG). Small-signal nodes are
CC
oriented on the left side of the LT3800, while high current
switching nodes are oriented on the right side of the IC
to simplify layout. This also helps prevent corruption of
the SGND reference.
is referenced to the (–) terminal of the V
decoupling
OUT
capacitor and is used as the converter voltage feedback
reference. Power ground currents are controlled on the
LT3800 via the PGND pin, and this ground references
the high current synchronous switch drive components,
Connect the V pin directly to the feedback resistors
FB
–
independent of any other nodes, such as the SENSE pin.
as well as the local V supply. It is important to keep
CC
The feedback resistors should be connected between the
PGND and SGND voltages consistent with each other, so
separating these grounds with thin traces is not recom-
mended. When the synchronous FET is turned on, gate
drive surge currents return to the LT3800 PGND pin from
the FET source. The BOOST supply refresh surge currents
also return through this same path. The synchronous FET
must be oriented such that these PGND return currents do
(+) and (–) terminals of the output capacitor (C ).
OUT
Locate the feedback resistors in close proximity to the
LT3800 to minimize the length of the high impedance
V
FB
node.
TheSENSE– andSENSE+ tracesshouldberoutedtogether
and kept as short as possible.
3800fc
18
LT3800
APPLICATIONS INFORMATION
Orientation of Components Isolates Power Path and PGND
Currents, Preventing Corruption of SGND Reference
The LT3800 packaging has been designed to efficiently
remove heat from the IC via the Exposed Pad on the
backside of the package. The Exposed Pad is soldered to
a copper footprint on the PCB. This footprint should be
madeaslargeaspossibletoreducethethermalresistance
of the IC case to ambient air.
V
IN
BOOST
SW
+
TG
SW
SGND
REFERRED
COMPONENTS
LT3800
V
CC
+
BG
SGND PGND
3800 AI05
V
OUT
I
SENSE
TYPICAL APPLICATIONS
6.5V-55V to 5V 10A DC/DC Converter with Charge Pump Doubler VCC Refresh and Current Limit Foldback
V
IN
6.5V TO 55V
C2
C8
+
1μF
56μF
63V
×2
100V
X7R ×3
V
BOOST
TG
IN
C1 1μF
16V X7R
D1
BAS19
M1
Si7850DP
×2
R
A
NC
1M
LT3800
C7
1.5nF
SHDN
SW
NC
R4 75k
L1
C
SS
5.6μH
R2
309k
1%
R1
100k
1%
BURST_EN
V
CC
C3 1μF
16V X7R
M2
Si7370DP
×2
DS3
B160
×2
V
BG
FB
V
PGND
C
R3
R5
47k
C10
100pF
–
+
62k
SENSE
SENSE
C9
470pF
SGND
R
S
0.01Ω
D2
1N4148
V
OUT
5V AT 10A
DS1
C6
+
C5
M3
MBRO520L
10μF
6.3V
X7R
DS2
MBRO520L
220μF
1/2 Si1555DL
×2
Efficiency and Power Loss
3800 TA02a
M4
100
95
12
10
C4
1μF
1/2 Si1555DL
C5: SANYO POSCAP 6TP220M
L1: IHLP-5050FD-01
V
= 24V
IN
V
= 13.8V
IN
V
= 48V
IN
90
85
8
6
V
= 55V
IN
POWER LOSS
= 48V
80
75
70
4
2
0
V
IN
POWER LOSS
IN
V
= 13.8V
0
2
4
6
8
10
I
(A)
OUT
3800 TA02b
3800fc
19
LT3800
TYPICAL APPLICATIONS
9V-38V to 3.3V 10A DC/DC Converter with Input UVLO and Burst Mode Operation
No Load I(VIN) = 100μA
V
IN
9V TO 38V
C8
C9
+
100μF
50V
×2
4.7μF
50V
X7R ×3
V
BOOST
TG
IN
C5 1μF
16V X7R
M1
Si7884DP
R
A
NC
R
B
1M
LT3800
187k
SHDN
SW
NC
C1 1nF
R4 39k
D1
L1
C
SS
MBR520
3.3μH
R1
100k
1%
R2
BURST_EN
V
C10
CC
169k
1%
C4 1μF
16V X7R
100pF
DS1
SS14
×2
M2
Si7884DP
V
BG
FB
V
PGND
C
R3
82k
C2
C3
100pF
–
+
SENSE
SENSE
SGND
R
S
330pF
0.01Ω
V
OUT
3.3V AT 10A
C7
+
C6
10μF
6.3V
X7R
C6: SANYO POSCAP 4TPD470M
L1: IHLP-5050FD-01
470μF
×2
3800 TA03a
Efficiency and Power Loss
92
90
88
86
84
82
80
78
7
6
5
4
3
2
1
0
V
= 13.8V
IN
0.1
10
1
I
(A)
LOAD
3800 TA03b
3800fc
20
LT3800
TYPICAL APPLICATIONS
9V-38V to 5V 6A DC/DC Converter with All Ceramic Capacitors, Input UVLO,
Burst Mode Operation and Current Limit Foldback
V
IN
9V TO 38V
C8
22μF
×3
V
BOOST
TG
IN
C5 1μF
R
A
10V X7R
M1
C9 1nF
187k
1M
NC
Si7884DP
LT3800
R
B
SHDN
SW
NC
C1 3.9nF
R4 51k
D1
L1
C
SS
BAS19
10μH
R2
154k
1%
R1
49.9k
1%
C6
47pF
BURST_EN
V
CC
C4 1μF
10V X7R
DS1
SS14
M2
Si7884DP
V
V
BG
FB
C
PGND
R3
27k
C2
1nF
C3
100pF
R5
47k
D2
1N4148
–
+
SENSE
SENSE
SGND
R
S
0.02Ω
V
OUT
5V AT 6A
C7
100μF
×2
3800 TA05a
C7: TDK C4532X5R0J107MT
C8: TDK C5750X7R1E226MT
L1: IHLP-5050FD-01
Efficiency and Power Loss
100
3.20
V
= 13.8V
IN
95
90
85
80
75
70
65
60
2.80
2.40
2.00
1.60
1.20
0.80
0.40
0
0.001
0.01
0.1
1
10
I
(A)
LOAD
3800 TA05b
3800fc
21
LT3800
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev I)
Exposed Pad Variation BC
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
0.48
(.019)
REF
3.58
(.141)
16 1514 13 12 11 109
6.60 t0.10
4.50 t0.10
0.51
(.020)
REF
2.94
DETAIL B
(.116)
6.40
(.252)
BSC
SEE NOTE 4
2.94
(.116)
DETAIL B IS THE PART OF
THE LEAD FRAME FEATURE
FOR REFERENCE ONLY
0.45 t0.05
1.05 t0.10
NO MEASUREMENT PURPOSE
0.65 BSC
5
7
8
1
2
3
4
6
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0s – 8s
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE16 (BC) TSSOP REV I 1210
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3800fc
22
LT3800
REVISION HISTORY (Revision history begins at Rev C)
REV
DATE
DESCRIPTION
PAGE NUMBER
C
9/11
Minor correction to TA04a schematic
24
3800fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT3800
TYPICAL APPLICATION
24V-48V to –12V 75W Inverting DC/DC Converter with VIN UVLO
V
IN
24V TO 48V
C10
1μF
100V
X7R
w4
C9
+
56μF
63V
w2
R7
D2
1N4148
D1
BAS19
1M
R8
V
BOOST
TG
IN
1M
M1
2N3906
NC
FDD3570
C2 1μF
16V X7R
LT3800
R3
1M
L1
15μH
R
S
SHDN
SW
NC
0.01Ω
C1 1nF
R1 200k
R2
R6
130k
C
SS
174k
1%
C6
1μF
16V
X7R
BURST_EN
V
CC
C7
DS1
B180
150pF
100V
M2
FDD3570
V
V
BG
FB
R5
20k
1%
PGND
C
R4
39k
–
+
SENSE
SENSE
SGND
C3
470pF
C5
270μF
16V
C8
+
4.7μF
16V
C4
100pF
SPRAGUE SP
V
–12V
75W
X7R
OUT
3800 TA04a
L1: COEV MGPWL-00099
Efficiency and Power Loss
100
12
90
80
70
60
50
40
10
8
V
IN
= 24V
V
= 48V
IN
V
= 36V
IN
6
4
V
= 36V LOSS
IN
2
0
0.1
1
10
I
(A)
LOAD
3800 TA04b
RELATED PARTS
PART NUMBER
LTC1735
DESCRIPTION
Synchronous Step-Down Controller
No R ™ Synchronous Step-Down Controller
COMMENTS
4V ≤ V ≤ 36V, 0.8V ≤ V
≤ 6V, I ≤ 20A
OUT
IN
OUT
LTC1778
Current Mode Without Using Sense Resistor, 4V ≤ V ≤ 36V
SENSE
IN
LT®1934
Micropower Step-Down Switching Regulator
Synchronous Single Switch Forward Converter
60V Switching Regulator
3.2V ≤ V ≤ 34V, 300mA Switch, ThinSOT™ Package
IN
LT1952
25W to 500W Isolated Power Supplies, Small Size, High Efficiency
LT1976
3.2V ≤ V ≤ 60V, 1.5A Switch, 16-Lead TSSOP
IN
LT3010
3V to 80V LDO
50mA Output Current, 1.275V ≤ V
≤ 60V
OUT
LT3430/LT3431
LTC3703
3A, 60V Switching Regulators
5.5V ≤ V ≤ 60V, 200kHz, 16-Lead TSSOP
IN
100V Synchronous Step-Down Controller
60V Synchronous Step-Down Controller
Large 1ꢀ Gate Drivers, No R
Large 1ꢀ Gate Drivers, No R
SENSE
SENSE
LTC3703-5
LTC3727-1
LTC3728L
High V
2-Phase Dual Step-Down Controller
0.8V ≤ V
≤ 14V, PLL: 250kHz to 550kHz
OUT
OUT
2-Phase, Dual Synchronous Step-Down Controller
550kHz, PLL: 250kHz to 550kHz, 4V ≤ V ≤ 36V
IN
3800fc
LT 0911 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2005
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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