LT3800 [Linear]
High Voltage, Current Mode Switching Regulator Controller; 高电压，电流模式开关稳压控制器
| 型号： | LT3800 |
| 厂家： | 
Linear |
| 描述： | High Voltage, Current Mode Switching Regulator Controller |
| 文件： | 总24页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3724
High Voltage, Current Mode
Switching Regulator Controller
U
FEATURES
DESCRIPTIO
The LT®3724 is a DC/DC controller used for medium
power, low part count, low cost, high efficiency supplies.
Itoffersawide4V-60Vinputrange(7.5Vminimumstartup
voltage)andcanimplementstep-down, step-up, inverting
and SEPIC topologies.
■
Wide Input Range: 4V to 60V
■
Output Voltages up to 36V (Step-Down)
Burst Mode® Operation: <100µA Supply Current
■
■
<10µA Shutdown Supply Current
■
±1.3% Reference Accuracy
■
200kHz Fixed Frequency
The LT3724 includes Burst Mode operation, which re-
duces quiescent current below 100µA and maintains high
efficiency at light loads. An internal high voltage bias
regulator allows for simple biasing and can be back driven
to increase efficiency.
■
Drives N-Channel MOSFET
■
Programmable Soft-Start
■
Programmable Undervoltage Lockout
■
Internal High Voltage Regulator for Gate Drive
■
Thermal Shutdown
■
Additional features include fixed frequency current mode
control for fast line and load transient response; a gate
driver capable of driving large N-channel MOSFETs; a
precision undervoltage lockout function; 10µA shutdown
current; short-circuit protection; and a programmable
soft-start function that directly controls output voltage
slew rates at startup which limits inrush current, mini-
mizes overshoot and facilitates supply sequencing.
Current Limit Unaffected by Duty Cycle
■
16-Pin Thermally Enhanced TSSOP Package
U
APPLICATIO S
■
Industrial Power Distribution
■
12V and 42V Automotive and Heavy Equipment
■
High Voltage Single Board Systems
Distributed Power Systems
Avionics
Telecom Power
■
The LT3724 is available in a 16-lead thermally enhanced
TSSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5731694, 6498466, 6611131.
■
■
U
TYPICAL APPLICATIO
Efficiency and Power Loss
vs Load Current
High Voltage Step-Down Regulator
V
IN
30V TO
60V
C
95
90
85
80
75
70
65
12
10
8
V
BOOST
TG
IN
68µF
IN
0.22µF
1M
Si7852
EFFICIENCY
LT3724
0.025Ω
V
OUT
SHDN
SW
24V
47µH
75W
68.1k
200k
SS3H9
+
C
C
SS
6
OUT
330µF
Burst_EN
V
CC
4
1µF
V
PGND
LOSS
FB
2
40.2k
+
V
C
SENSE
V
= 48V
IN
680pF
120pF
1000pF
0
10
–
SGND
SENSE
0.1
1
4.99k
93.1k
LOAD CURRENT (A)
3724 TA01a
3724 TA01b
3724f
1
LT3724
W W
U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
TOP VIEW
Input Supply Voltage (VIN).........................65V to –0.3V
Boosted Supply Voltage (BOOST)..............80V to –0.3V
Switch Voltage (SW) ....................................65V to –1V
Differential Boost Voltage
NUMBER
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BOOST
TG
IN
NC
LT3724EFE
LT3724IFE
SHDN
SW
C
NC
SS
(BOOST to SW) .....................................24V to –0.3V
Bias Supply Voltage (VCC) .........................24V to –0.3V
SENSE+ and SENSE– Voltages ...................40V to –0.3V
Differential Sense Voltage
17
BURST_EN
V
CC
V
PGND
FB
FE PART
MARKING
+
V
C
SENSE
SENSE
–
SGND
(SENSE+ to SENSE–) ..................................1V to –1V
BURST_EN Voltage....................................24V to –0.3V
VC, VFB, CSS, and SHDN Voltages ................5V to –0.3V
3724EFE
3724IFE
FE PACKAGE
16-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 40°C/W, θJC = 10°C/W
EXPOSED PAD IS SGND (PIN 17)
MUST BE SOLDERED TO PCB
C
SS and SHDN Pin Currents .................... 1mA to –1mA
Operating Junction Temperature Range (Note 2)
LT3724E (Note 3) ..............................–40°C to 125°C
LT3724I .............................................–40°C to 125°C
Storage Temperature .............................–65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V,
SENSE– = SENSE+ = 10V, SGND = PGND = SW = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Operating Voltage Range (Note 4)
Minimum Start Voltage
UVLO Threshold (Falling)
UVLO Threshold Hysteresis
●
●
●
4
7.5
3.65
60
V
V
V
IN
3.8
670
3.95
mV
I
V
V
V
Supply Current
Burst Mode Current
Shutdown Current
V
V
V
> 9V
20
20
9
µA
µA
µA
VIN
IN
IN
IN
CC
BURST_EN
= 0V, V = 1.35V
FB
= 0V
●
15
SHDN
V
Operating Voltage Range
Operating Voltage Range (Note 5)
UVLO Threshold (Rising)
●
●
75
20
V
V
V
BOOST
V
V
V
- V
SW
- V
SW
- V
SW
BOOST
BOOST
BOOST
5
400
UVLO Threshold Hysteresis
mV
I
BOOST Supply Current (Note 6)
BOOST Burst Mode Current
BOOST Shutdown Current
1.4
0.1
0.1
mA
µA
µA
BOOST
V
V
= 0V
= 0V
BURST_EN
SHDN
V
Operating Voltage Range (Note 5)
Output Voltage
●
●
20
8.3
V
V
CC
Over Full Line and Load Range
8
UVLO Threshold (Rising)
UVLO Threshold Hysteresis
6.25
500
V
mV
I
V
V
V
Supply Current (Note 6)
Burst Mode Current
Shutdown Current
●
●
1.7
80
20
2.1
mA
µA
µA
VCC
CC
CC
CC
V
V
= 0V
= 0V
BURST_EN
SHDN
Short-Circuit Current
–30
–55
mA
3724f
2
LT3724
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V,
SENSE– = SENSE+ = 10V, SGND = PGND = SW = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
Measured at V Pin
MIN
TYP
MAX
UNITS
V
Error Amp Reference Voltage
1.224
1.215
1.231
1.238
1.245
V
V
FB
FB
●
●
I
Feedback Input Current
25
nA
FB
V
Enable Threshold (Rising)
Threshold Hysteresis
1.3
1.35
120
1.4
V
mV
SHDN
SENSE
SENSE
V
Common Mode Range
Current Limit Sense Voltage
●
●
0
140
36
175
V
mV
+
–
V
V
– V
150
SENSE
SENSE
I
f
Input Current
= 0V
400
2
–150
µA
µA
µA
SENSE(CM)
+
–
(I
+ I
)
2V < V
< 3.5V
SENSE
SENSE
SENSE(CM)
V
> 4V
SENSE(CM)
Operating Frequency
190
175
200
210
220
kHz
kHz
SW
●
●
V
Soft-Start Disable Voltage
Soft-Start Disable Hysteresis
V
Rising
FB
1.185
300
V
mV
FB(SS)
I
Soft-Start Capacitor Control Current
Error Amp Transconductance
Error Amp DC Voltage Gain
2
µA
µmhos
dB
SS
g
275
340
62
400
m
A
V
V
C
Error Amp Output Range
Zero Current to Current Limit
1.2
±30
V
I
Error Amp Sink/Source Current
µA
VC
V
Gate Drive Output On Voltage (Note 7) C
= 3300pF
= 3300pF
9.8
0.1
V
V
TG
LOAD
LOAD
Gate Drive Output Off Voltage
Gate Drive Rise/Fall Time
Minimum Switch Off Time
Minimum Switch On Time
SW Pin Sink Current
C
t
t
t
I
10% to 90% or 90% to 10%, C
= 3300pF
LOAD
60
ns
ns
TG
350
300
300
TG(OFF)
TG(ON)
SW
●
500
ns
V
= 2V
mA
SW
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 4: V voltages below the start-up threshold (7.5V) are only
IN
supported when the V is externally driven above 6.5V.
CC
Note 2: The LT3724 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 5: Operating range is dictated by MOSFET absolute maximum V .
GS
Note 6: Supply current specification does not include switch drive
currents. Actual supply currents will be higher.
Note 7: DC measurement of gate drive output “ON” voltage is typically
8.6V. Internal dynamic bootstrap operation yields typical gate “ON”
Note 3: The LT3724E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3724I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
voltages of 9.8V during standard switching operation. Standard operation
gate “ON” voltage is not tested but guaranteed by design.
3724f
3
LT3724
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Threshold (Falling)
vs Temperature
Shutdown Threshold (Rising)
vs Temperature
V
CC vs Temperature
1.38
1.37
1.36
1.35
1.34
1.33
1.32
1.26
1.25
1.24
1.23
1.22
1.21
1.20
8.2
8.1
8.0
7.9
7.8
7.7
7.6
7.5
I
= 20mA
CC
–50 –25
0
25
50
75
100 125
–50 –25
0
25
50
75
100 125
–50 –25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3724 G01
3724 G03
3724 G02
VCC vs ICC(LOAD)
ICC Current Limit vs Temperature
VCC vs VIN
70
60
50
40
30
20
8.2
8.1
8.0
7.9
7.8
7.7
7.6
7.5
9
8
7
6
5
4
3
T
= 25°C
I
= 20mA
= 25°C
A
CC
A
T
20
(mA)
30
35
4
11
12
–50 –25
0
25
50
75
100 125
0
5
10
15
25
8
10
5
6
7
9
V
(V)
TEMPERATURE (°C)
I
IN
CC (LOAD)
3724 G04
3724 G05
3724 G06
Error Amp Transconductance
vs Temperature
VCC UVLO Threshold (Rising)
vs Temperature
ICC vs VCC (SHDN = 0V)
6.5
6.4
6.3
6.2
6.1
6.0
350
345
340
335
330
325
320
25
20
15
T
A
= 25°C
10
5
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
50
75
100 125
0
2
4
6
12 14 16 18
20
–50 –25
0
25
75
8
10
TEMPERATURE (°C)
V
CC
(V)
3724 G09
3724 G07
3724 G08
3724f
4
LT3724
U W
TYPICAL PERFOR A CE CHARACTERISTICS
+
–
Error Amp Reference
vs Temperature
I(SENSE + SENSE ) vs
VSENSE (CM)
Operating Frequency
vs Temperature
400
300
200
100
0
230
220
210
200
190
180
170
1.234
1.233
1.232
1.231
1.230
1.229
1.228
1.227
T
= 25°C
A
–100
–200
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
0.5
–50 –25
0
25
75
–50 –25
0
25
75
V
(V)
SENSE (CM)
3724 G10
3724 G11
3724 G12
VIN UVLO Threshold (Falling)
vs Temperature
Maximum Current Sense
Threshold vs Temperature
VIN UVLO Threshold (Rising)
vs Temperature
160
158
156
154
152
150
148
146
144
142
140
3.86
3.84
3.82
3.80
3.78
3.76
4.54
4.52
4.50
4.48
4.46
4.44
4.42
4.40
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
–50 –25
0
25
75
3724 G13
3724 G14
3724 G15
3724f
5
LT3724
U
U
U
PI FU CTIO S
VIN (Pin 1): The VIN pin is the main supply pin and should
be decoupled to SGND with a low ESR capacitor located
close to the pin.
optimizetransientresponse.Connectinga100pForgreater
high frequency bypass capacitor from this pin to ground
is recommended. When Burst Mode operation is enabled
(see Pin 5 description), an internal low impedance clamp
on the VC pin is set at 100mV below the burst threshold,
which limits the negative excursion of the pin voltage.
Therefore, this pin cannot be pulled low with a low imped-
ance source. If the VC pin must be externally manipulated,
do so through a 1kΩ series resistance.
NC (Pin 2): No Connection.
SHDN (Pin 3): The SHDN pin has a precision IC enable
threshold of 1.35V (rising) with 120mV of hysteresis. It is
used to implement an undervoltage lockout (UVLO) cir-
cuit. See Application Information section for implement-
ing a UVLO function. When the SHDN pin is pulled below
a transistor VBE (0.7V), a low current shutdown mode is
entered, all internal circuitry is disabled and the VIN supply
current is reduced to approximately 9µA. Typical pin input
bias current is <10µA and the pin is internally clamped to
6V.
SGND (Pin 8, 17): The SGND pin is the low noise ground
reference. It should be connected to the –VOUT side of the
output capacitors. Careful layout of the PCB is necessary
to keep high currents away from this SGND connection.
See the Application Information section for helpful hints
on PCB layout of grounds.
CSS (Pin 4): The soft-start pin is used to program the
supplysoft-startfunction.ThepinisconnectedtoVOUT via
a ceramic capacitor (CSS) and 200kΩ series resistor.
During start-up, the supply output voltage slew rate is
controlled to produce a 2µA average current through the
soft-start coupling capacitor. Use the following formula to
calculate CSS for a given output voltage slew rate:
SENSE– (Pin 9): The SENSE– pin is the negative input for
the current sense amplifier and is connected to the VOUT
side of the sense resistor for step-down applications. The
sensed inductor current limit is set to 150mV across the
SENSE inputs.
SENSE+ (Pin 10): The SENSE+ pin is the positive input for
the current sense amplifier and is connected to the induc-
tor side of the sense resistor for step-down applications.
The sensed inductor current limit is set to 150mV across
the SENSE inputs.
CSS = 2µA(tSS/VOUT
)
See the application section for more information on set-
ting the rise time of the output voltage during start-up.
Shorting this pin to SGND disables the soft-start function.
PGND (Pin 11): The PGND pin is the high-current ground
referenceforinternallowsideswitchandtheVCC regulator
circuit. Connect the pin directly to the negative terminal of
the VCC decoupling capacitor. See the Application Infor-
mation section for helpful hints on PCB layout of grounds.
BURST_EN (Pin 5): The BURST_EN pin is used to enable
or disable Burst Mode operation. Connect the BURST_EN
pin to ground to enable the burst mode function. Connect
the pin to VCC to disable the burst mode function.
VFB (Pin 6): The output voltage feedback pin, VFB, is
externally connected to the supply output voltage via a
resistive divider. The VFB pin is internally connected to the
inverting input of the error amplifier. In regulation, VFB is
1.231V.
VCC (Pin 12): The VCC pin is the internal bias supply
decoupling node. Use low ESR 1µF ceramic capacitor to
decouple this node to PGND. Most internal IC functions
are powered from this bias supply. An external diode
connected from VCC to the BOOST pin charges the
bootstrapped capacitor during the off-time of the main
powerswitch.BackdrivingtheVCC pinfromanexternalDC
voltage source, such as the VOUT output of the buck
regulator supply, increases overall efficiency and reduces
power dissipation in the IC. In shutdown mode this pin
sinks 20µA until the pin voltage is discharged to 0V.
VC (Pin 7): The VC pin is the output of the error amplifier
whosevoltagecorrespondstothemaximum(peak)switch
current per oscillator cycle. The error amplifier is typically
configured as an integrator circuit by connecting an RC
network from the VC pin to SGND. This circuit creates the
dominant pole for the converter regulation control loop.
Specific integrator characteristics can be configured to
NC (Pin 13): No Connection.
3724f
6
LT3724
U
U
U
PI FU CTIO S
SW (Pin 14): In step-down applications the SW pin is
connectedtothecathodeofanexternalclampingSchottky
diode, the drain of the power MOSFET and the inductor.
TheSWnodevoltageswingisfromVIN duringtheon-time
of the power MOSFET, to a Schottky voltage drop below
ground during the off-time of the power MOSFET. In start-
up and in operating modes where there is insufficient
inductor current to freewheel the Schottky diode, an
internal switch is turned on to pull the SW pin to ground
so that the BOOST pin capacitor can be charged. Give
careful consideration in choosing the Schottky diode to
limit the negative voltage swing on the SW pin.
MOSFET with a short and wide, typically 0.02” width, PCB
trace to minimize inductance.
BOOST (Pin 16): The BOOST pin is the supply for the
bootstrapped gate drive and is externally connected to a
low ESR ceramic boost capacitor referenced to SW pin.
The recommended value of the BOOST capacitor,CBOOST
,
is 50 times greater that the total input capacitance of the
topside MOSFET. In most applications 0.1µF is adequate.
The maximum voltage that this pin sees is VIN + VCC,
ground referred, and is limited to 75V.
Exposed Pad (SGND) (Pin 17): The exposed leadframe is
internally connected to the SGND pin. Solder the exposed
pad to the PCB ground for electrical contact and optimal
thermal performance.
TG (Pin 15): The TG pin is the bootstrapped gate drive for
the top N-Channel MOSFET. Since very fast high currents
are driven from this pin, connect it to the gate of the power
3724f
7
LT3724
U
U
W
FU CTIO AL DIAGRA
V
IN
UVLO
(<4V)
8V V
CC
REGULATOR
V
IN
BOOST
16
V
CC
BST
UVLO
1
V
IN
UVLO
(<6V)
C
IN
C
BOOST
3.8V
REGULATOR
INTERNAL
SUPPLY RAIL
BOOSTED
SWITCH
DRIVER
TG
15
DRIVE
M1
D1
CONTROL
RA
RB
FEEDBACK
REFERENCE
–
+
SW
14
L1
R
SENSE
1.231V
V
OUT
NOL
SWITCH
LOGIC
C
OUT
D2
V
CC
SHDN
+
–
3
12
C
VCC
D3
(OPTIONAL)
DRIVE
CONTROL
BURST_EN
PGND
11
–
+
5
6
V
FB
–
+
R2
R1
g
m
0.5V
OSCILLATOR
ERROR
AMP
Q
R
S
–
+
V
C
SLOPE COMP
GENERATOR
7
SOFT-START
CURRENT
C
C2
DISABLE/BURST
SENSE
R
C
ENABLE
COMPARATOR
+
~1V
C
C1
–
–
+
BURST MODE
OPERATION
1.185V
2µA
C
SS
4
8
+
SENSE
10
–
+
C
SS
–
SENSE
SGND
9
3724 FD
3724f
8
LT3724
U
(Refer to Functional Diagram)
OPERATIO
The LT3724 is a PWM controller with a constant fre-
quency, current mode control architecture. It is designed
for low to medium power, switching regulator applica-
tions.Itshighoperatingvoltagecapabilityallowsittostep-
up or down input voltages up to 60V without the need for
a transformer. The LT3724 is used in nonsynchronous
applications, meaning that a freewheeling rectifier diode
(D1 of Function Diagram) is used instead of a bottom side
MOSFET. For circuit operation, please refer to the Func-
tional Diagram of the IC and Typical Application on the
front page of the data sheet. The LT3800 is a similar part
that uses synchronous rectification, replacing the diode
with a MOSFET in a step-down application.
VCC/Boosted Supply
An internal VCC regulator provides VIN derived gate-drive
power for start-up under all operating conditions with
MOSFET gate charge loads up to 90nC. The regulator can
operate continuously in applications with VIN voltages up
to 60V, provided the VIN voltage and/or MOSFET gate
chargecurrentsdonotcreateexcessivepowerdissipation
in the IC. Safe operating conditions for continuous regu-
lator use are shown in Figure 1. In applications where
these conditions are exceeded, VCC must be derived from
an external source after start-up. The LT3724 regulator
can, however, be used for “full time” use in applications
whereshort-durationVIN transientsexceedallowablecon-
tinuous voltages.
Main Control Loop
70
60
50
40
During normal operation, the external N-channel MOSFET
switch is turned on at the beginning of each cycle. The
switch stays on until the current in the inductor exceeds a
current threshold set by the DC control voltage, VC, which
is the output of the voltage control loop. The voltage
control loop monitors the output voltage, via the VFB pin
voltage, and compares it to an internal 1.231V reference.
It increases the current threshold when the VFB voltage is
below the reference voltage and decreases the current
threshold when the VFB voltage is above the reference
voltage. For instance, when an increase in the load current
occurs, the output voltage drops causing the VFB voltage
to drop relative to the 1.231V reference. The voltage
control loop senses the drop and increases the current
threshold. The peak inductor current is increased until the
average inductor current equals the new load current and
the output voltage returns to regulation.
30
SAFE
OPERATING
AREA
20
10
0
20
40
60
80
100
MOSFET TOTAL GATE CHARGE (nC)
3724 F01
Figure 1. VCC Regulator Continuous Operating Conditions
For higher converter efficiency and less power dissipation
in the IC, VCC can also be supplied from an external supply
such as the converter output. When an external supply
back drives the internal VCC regulator through an external
diode and the VCC voltage is pulled to a diode above its
regulation voltage, the internal regulator is disabled and
goes into a low current mode. VCC is the bias supply for
mostoftheinternalICfunctionsandisalsousedtocharge
thebootstrappedcapacitor(CBOOST)viaanexternaldiode.
The external MOSFET switch is biased from the
bootstrappedcapacitor.WhiletheexternalMOSFETswitch
isoff, aninternalBJTswitch, whosecollectorisconnected
to the SW pin and emitter is connected to the PGND pin,
is turned on to pull the SW node to PGND and recharge the
Current Limit/Short-Circuit
The inductor current is measured with a series sense
resistor (see the Typical Application on the front page).
When the voltage across the sense resistor reaches the
maximum current sense threshold, typically 150mV, the
TG MOSFET driver is disabled for the remainder of that
cycle. If the maximum current sense threshold is still
exceededatthebeginningofthenextcycle,theentirecycle
is skipped. Cycle skipping keeps the inductor currents to
a reasonable value during a short-circuit, particularly
when VIN is high. Setting the sense resistor value is
discussed in the “Application Information” section.
bootstrap capacitor. The switch stays on until either the
3724f
9
LT3724
U
(Refer to Functional Diagram)
OPERATIO
switching resumes. An internal clamp on the VC pin is set
at100mVbelowtheoutputdisablethreshold, whichlimits
the negative excursion of the pin voltage, minimizing the
converter output ripple during Burst Mode operation.
start of the next cycle or until the bootstrapped capacitor
is fully charged.
MOSFET Driver
The LT3724 contains a high speed boosted driver to turn
on and off an external N-channel MOSFET switch. The
MOSFET driver derives its power from the boost capacitor
which is referenced to the SW pin and the source of the
MOSFET. The driver provides a large pulse of current to
turn on the MOSFET fast to minimize transition times.
Multiple MOSFETs can be paralleled for higher current
operation.
During Burst Mode operation, the VIN pin current is 20µA
andtheVCC currentisreducedto80µA. Ifnoexternaldrive
isprovidedforVCC, allVCC biascurrentsoriginatefromthe
VIN pin, giving a total VIN current of 100µA. Burst current
can be reduced further when VCC is driven using an output
derived source, as the VCC component of VIN current is
then reduced by the converter duty cycle ratio.
Start-Up
To eliminate the possibility of shoot through between the
MOSFET and the internal SW pull-down switch, an adap-
tive nonoverlap circuit ensures that the internal pull-down
switch does not turn on until the gate of the MOSFET is
below its turn on threshold.
The following section describes the start-up of the supply
andoperationdownto4Voncethestep-downsupplyisup
and running. For the protection of the LT3724 and the
switching supply, there are internal undervoltage lockout
(UVLO)circuitswithhysteresisonVIN, VCC andVBOOST, as
shown in the Electrical Characteristics table. Start-up and
continuous operation require that all three of these
undervoltage lockout conditions be satisfied because the
TG MOSFET driver is disabled during any UVLO fault
condition. In startup, for most applications, VCC is pow-
ered from VIN through the high voltage linear regulator of
the LT3724. This requires VIN to be high enough to drive
the VCC voltage above its undervoltage lockout threshold.
VCC, in turn, has to be high enough to charge the BOOST
capacitor through an external diode so that the BOOST
voltage is above its undervoltage lockout threshold. There
is an NPN switch that pulls the SW node to ground each
cycle during the TG power MOSFET off-time, ensuring the
BOOST capacitor is kept fully charged. Once the supply is
up and running, the output voltage of the supply can
backdrive VCC throughanexternaldiode.Internalcircuitry
disables the high voltage regulator to conserve VIN supply
current. Output voltages that are too low or too high to
backdriveVCC requireadditionalcircuitrysuchasavoltage
doubler or linear regulator. Once VCC is backdriven from a
supply other than VIN, VIN can be reduced to 4V with
normal operation maintained.
Low Current Operation (Burst Mode Operation)
To increase low current load efficiency, the LT3724 is
capable of operating in Linear Technology’s proprietary
Burst Mode operation where the external MOSFET oper-
ates intermittently based on load current demand. The
Burst Mode function is disabled by connecting the
BURST_EN pin to VCC and enabled by connecting the pin
to SGND.
When the required switch current, sensed via the VC pin
voltage, isbelow15%ofmaximum, BurstModeoperation
is employed and that level of sense current is latched onto
the IC control path. If the output load requires less than
this latched current level, the converter will overdrive the
output slightly during each switch cycle. This overdrive
conditionissensedinternallyandforcesthevoltageonthe
VC pin to continue to drop. When the voltage on VC drops
150mV below the 15% load level, switching is disabled,
and the LT3724 shuts down most of its internal circuitry,
reducing total quiescent current to 100µA. When the
converter output begins to fall, the VC pin voltage begins
toclimb. WhenthevoltageontheVC pinclimbsbacktothe
15% load level, the IC returns to normal operation and
3724f
10
LT3724
U
(Refer to Functional Diagram)
OPERATIO
Soft-Start
artificial ramp on the sensed current to increase the rising
slope as duty cycle increases.
The soft-start function controls the slew rate of the power
supply output voltage during start-up. A controlled output
voltage ramp minimizes output voltage overshoot, re-
duces inrush current from the VIN supply, and facilitates
supply sequencing. A capacitor, CSS, connected between
VOUT of the supply and the CSS pin of the IC, programs the
slew rate. The capacitor provides a current to the CSS pin
which is proportional to the dV/dt of the output voltage.
The soft-start circuit overrides the control loop and ad-
juststheinductorcurrentuntiltheoutputvoltageslewrate
yields a 2µA current through the soft-start capacitor. If the
current is greater than 2µA, then the current threshold set
by the DC control voltage, VC, is decreased and the
inductor current is lowered. This in turn lowers the output
currentandtheoutputvoltageslewrateisdecreased.Ifthe
current is less than 2µA, then the current threshold set by
the DC control voltage, VC, is increased and the inductor
current is raised. This in turn increases the output current
and the output voltage slew rate is increased. Once the
output voltage is within 5% of its regulation voltage, the
soft-startcircuitisdisabledandthemaincontrolregulates
the output. The soft-start circuit is reactivated when the
output voltage drops below 70% of its regulation voltage.
Unfortunately, this additional ramp typically affects the
sensed current value, thereby reducing the achievable
current limit value by the same amount as the added ramp
represents. As such, the current limit is typically reduced
as the duty cycle increases. The LT3724, however, con-
tains antislope compensation circuitry to eliminate the
current limit reduction associated with slope compensa-
tion. As the slope compensation ramp is added to the
sensedcurrent, asimilarrampisaddedtothecurrentlimit
threshold. The end result is that the current limit is not
compromised so the LT3724 can provide full power re-
gardless of required duty cycle.
Shutdown
The LT3724 includes a shutdown mode where all the
internal IC functions are disabled and the VIN current is
reduced to less than 10µA. The shutdown pin can be used
for undervoltage lockout with hysteresis, micropower
shutdown or as a general purpose on/off control of the
converter output. The shutdown function has two thresh-
olds. The first threshold, a precision 1.23V threshold with
120mV of hysteresis, disables the converter from switch-
ing. The second threshold, approximately a 0.7V refer-
enced to SGND, completely disables all internal circuitry
and reduces the VIN current to less than 10µA. See the
Application Information section for more information.
Slope/Antislope Compensation
The IC incorporates slope compensation to eliminate
potential subharmonic oscillations in the current control
loop. The IC’s slope compensation circuit imposes an
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ThebasicLT3724step-down(buck)application, shownin
the Typical Application on the front page, converts a larger
positive input voltage to a lower positive or negative
output voltage. This Application Information section as-
sists selection of external components for the require-
ments of the power supply.
compensation circuit is ineffective and current mode
instability may occur at duty cycles greater than 50%.
Lower values of ∆IL require larger and more costly mag-
netics. A value of ∆IL = 0.3 • IOUT(MAX) produces a ±15%
ofIOUT(MAX) ripplecurrentaroundtheDCoutputcurrentof
the supply.
Somemagneticsvendorsspecifyavolt-secondproductin
their datasheet. If they do not, consult the magnetics
vendor to make sure the specification is not being ex-
ceeded by your design. The volt-second product is calcu-
lated as follows:
RSENSE Selection
The current sense resistor, RSENSE, monitors the inductor
current of the supply (See Typical Application on front
page). Itsvalueischosenbasedonthemaximumrequired
output load current. The LT3724 current sense amplifier
has a maximum voltage threshold of, typically, 150mV.
(VIN(MAX) – VOUT )•VOUT
Therefore, the peak inductor current is 150mV/RSENSE
.
Volt-second (µsec) =
VIN(MAX) • fSW
The maximum output load current, IOUT(MAX), is the peak
inductor current minus half the peak-to-peak ripple cur-
rent, ∆IL.
The magnetics vendors specify either the saturation cur-
rent, the RMS current or both. When selecting an inductor
based on inductor saturation current, use the peak current
through the inductor, IOUT(MAX) + ∆IL/2. The inductor
saturation current specification is the current at which the
inductance, measured at zero current, decreases by a
specified amount, typically 30%.
Allowing adequate margin for ripple current and external
component tolerances, RSENSE can be calculated as
follows:
100mV
IOUT(MAX)
RSENSE
=
When selecting an inductor based on RMS current rating,
use the average current through the inductor, IOUT(MAX)
.
Typical values for RSENSE are in the range of 0.005Ω
to 0.05Ω.
TheRMScurrentspecificationistheRMScurrentatwhich
the part has a specific temperature rise, typically 40°C,
above 25°C ambient.
Inductor Selection
After calculating the minimum inductance value, the volt-
second product, the saturation current and the RMS
current for your design, select an off-the-shelf inductor. A
listofmagneticsvendorscanbefoundat www.linear.com,
or contact the Linear Technology Application Department.
The critical parameters for selection of an inductor are
minimum inductance value, volt-second product, satura-
tion current and/or RMS current.
The minimum inductance value is calculated as follows:
V
IN(MAX) – VOUT
For more detailed information on selecting an inductor,
please see the “Inductor Selection” section of Linear
Technology Application Note 44.
L ≥ VOUT
•
fSW •VIN(MAX) • ∆IL
fSW is the switch frequency (200kHz).
Step-Down Converter: MOSFET Selection
The typical range of values for ∆IL is (0.2 • IOUT(MAX)) to
(0.5 • IOUT(MAX)), where IOUT(MAX) is the maximum load
current of the supply. Using ∆IL = 0.3 • IOUT(MAX) yields a
good design compromise between inductor performance
versus inductor size and cost. Higher values of ∆IL will
increase the peak currents, requiring more filtering on the
input and output of the supply. If ∆IL is too high, the slope
The selection criteria of the external N-channel standard
level power MOSFET include on resistance(RDS(ON)), re-
versetransfercapacitance(CRSS), maximumdrainsource
voltage (VDSS), total gate charge (QG), and maximum
continuous drain current.
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LT3724
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U
Formaximumefficiency, minimizeRDS(ON) andCRSS. Low
RDS(ON) minimizes conduction losses while low CRSS
minimizes transition losses. The problem is that RDS(ON)
isinverselyrelatedtoCRSS.Balancingthetransitionlosses
with the conduction losses is a good idea in sizing the
MOSFET. Select the MOSFET to balance the two losses.
The internal VCC regulator operating range limits the
maximum total MOSFET gate charge, QG, to 90nC. The QG
vs VGS specification is typically provided in the MOSFET
data sheet. Use QG at VGS of 8V. If VCC is back driven from
an external supply, the MOSFET drive current is not
sourced from the internal regulator of the LT3724 and the
QG of the MOSFET is not limited by the IC. However, note
that the MOSFET drive current is supplied by the internal
regulator when the external supply back driving VCC is not
available such as during startup or short-circuit.
CalculatethemaximumconductionlossesoftheMOSFET:
2⎛ VOUT
⎞
P
COND
= (IOUT(MAX)
)
(R
DS(ON)
)
⎜
⎟
⎝ V
⎠
IN
The manufacturer’s maximum continuous drain current
specification should exceed the peak switch current,
IOUT(MAX) + ∆IL/2.
Note that RDS(ON) has a large positive temperature depen-
dence. The MOSFET manufacturer’s data sheet contains a
curve, RDS(ON) vs Temperature.
During the supply startup, the gate drive levels are set by
the VCC voltage regulator, which is approximately 8V.
Once the supply is up and running, the VCC can be back
driven by an auxiliary supply such as VOUT. It is important
nottoexceedthemanufacturer’smaximumVGS specifica-
tion. A standard level threshold MOSFET typically has a
VGS maximum of 20V.
Calculate the maximum transition losses:
PTRAN = (k)(VIN)2 (IOUT(MAX))(CRSS)(fSW
)
where k is a constant inversely related to the gate driver
current, approximated by k = 2 for LT3724 applications.
The total maximum power dissipation of the MOSFET is
the sum of these two loss terms:
Step-Down Converter: Rectifier Selection
PFET(TOTAL) = PCOND + PTRAN
The rectifier diode (D1 on the Functional Diagram) in a
buck converter generates a current path for the inductor
current when the main power switch is turned off. The
rectifier is selected based upon the forward voltage, re-
verse voltage and maximum current. A Schottky diode is
recommended. Its low forward voltage yields the lowest
power loss and highest efficiency. The maximum reverse
To achieve high supply efficiency, keep the PFET(TOTAL) to
less than 3% of the total output power. Also, complete a
thermal analysis to ensure that the MOSFET junction
temperature is not exceeded.
TJ = TA + PFET(TOTAL) • θJA
where θJA is the package thermal resistance and TA is the
ambient temperature. Keep the calculated TJ below the
maximumspecifiedjunctiontemperature,typically150°C.
voltage that the diode will see is VIN(MAX)
.
In continuous mode operation, the average diode current
is calculated at maximum output load current and maxi-
mum VIN:
Note that when VIN is high, the transition losses may
dominate. A MOSFET with higher RDS(ON) and lower CRSS
may provide higher efficiency. MOSFETs with higher volt-
age VDSS specification usually have higher RDS(ON) and
V
IN(MAX) − VOUT
IDIODE(AVG) = IOUT(MAX)
V
IN(MAX)
lower CRSS
.
Choose the MOSFET VDSS specification to exceed the
maximum voltage across the drain to the source of the
MOSFET, which is VIN(MAX) plus any additional ringing on
theswitchnode.Ringingontheswitchnodecanbegreatly
reduced with good PCB layout and, if necessary, an RC
snubber.
To improve efficiency and to provide adequate margin
for short-circuit operation, a diode rated at 1.5 to 2 times
the maximum average diode current, IDIODE(AVG), is
recommended.
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Step-Down Converter: Input Capacitor Selection
Step-Down Converter: Output Capacitor Selection
A local input bypass capacitor is required for buck con-
verters because the input current is pulsed with fast rise
and fall times. The input capacitor selection criteria are
basedonthebulkcapacitanceandRMScurrentcapability.
Thebulkcapacitancewilldeterminethesupplyinputripple
voltage. The RMS current capability is used to keep from
overheating the capacitor.
The output capacitance, COUT, selection is based on the
design’s output voltage ripple, ∆VOUT, and transient load
requirements. ∆VOUT is a function of ∆IL and the COUT
ESR. It is calculated by:
⎛
⎞
⎟
1
∆VOUT = ∆IL • ESR +
⎜
⎝
(8• fSW •COUT )⎠
The bulk capacitance is calculated based on maximum
input ripple, ∆VIN:
The maximum ESR required to meet a ∆VOUT design
requirement can be calculated by:
I
OUT(MAX) •VOUT
(∆VOUT )(L)(fSW
)
CIN(BULK)
=
ESR(MAX) =
∆V • fSW •V
⎛
⎞
IN
IN(MIN)
VOUT
VOUT • 1–
⎜
⎟
V
⎝
⎠
IN(MAX)
∆VIN is typically chosen at a level acceptable to the user.
100mV-200mV is a good starting point. Aluminum elec-
trolytic capacitors are a good choice for high voltage, bulk
capacitance due to their high capacitance per unit area.
Worst-case ∆VOUT occurs at highest input voltage. Use
paralleled multiple capacitors to meet the ESR require-
ments. Increasing the inductance is an option to lower the
ESRrequirements.Forextremelylow∆VOUT,anadditional
LC filter stage can be added to the output of the supply.
Application Note 44 has some good tips on sizing an
additional output filter.
The capacitor’s RMS current is:
VOUT (V – VOUT
)
IN
ICIN(RMS) = IOUT
(V )2
IN
If applicable, calculate it at the worst case condition, VIN =
2VOUT.TheRMScurrentratingofthecapacitorisspecified
by the manufacturer and should exceed the calculated
ICIN(RMS). Due to their low ESR (Equivalent Series Resis-
tance), ceramic capacitors are a good choice for high
voltage, high RMS current handling. Note that the ripple
currentratingsfromaluminumelectrolyticcapacitormanu-
facturers are based on 2000 hours of life. This makes it
advisable to further derate the capacitor or to choose a
capacitor rated at a higher temperature than required.
Output Voltage Programming
A resistive divider sets the DC output voltage according to
the following formula:
VOUT
1.231V
⎛
⎝
⎞
⎠
R2 = R1
– 1
⎟
⎜
The external resistor divider is connected to the output of
the converter as shown in Figure 2. Tolerance of the
feedback resistors will add additional error to the output
voltage.
The combination of aluminum electrolytic capacitors and
ceramic capacitors is an economical approach to meeting
the input capacitor requirements. The capacitor voltage
rating must be rated greater than VIN(MAX). Multiple ca-
pacitors may also be paralleled to meet size or height
requirements in the design. Locate the capacitor very
close to the MOSFET switch and use short, wide PCB
traces to minimize parasitic inductance.
Example: VOUT = 12V; R1 = 10kΩ
12V
1.231V
⎛
⎜
⎝
⎞
⎠
R2 = 10kΩ
− 1 = 87.48kΩ − use 86.6kΩ1%
⎟
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14
LT3724
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U
L1
V
SUPPLY
V
OUT
RA
RB
C
R2
R1
OUT
SHDN PIN
V
FB
PIN
3724 F03
3724 F02
Figure 3. Undervoltage Lockout Circuit
Figure 2. Output Voltage Feedback Divider
The VFB pin input bias current is typically 25nA, so use of
extremely high value feedback resistors could cause a
converter output that is slightly higher than expected. Bias
current error at the output can be estimated as:
If additional hysteresis is desired for the enable function,
anexternalpositivefeedbackresistorcanbeusedfromthe
LT3724 regulator output.
The shutdown function can be disabled by connecting the
SHDN pin to the VIN through a large value pull-up resistor.
This pin contains a low impedance clamp at 6V, so the
SHDN pin will sink current from the pull-up resistor(RPU):
∆VOUT(BIAS) = 25nA • R2
Supply UVLO and Shutdown
The SHDN pin has a precision voltage threshold with
hysteresis which can be used as an undervoltage lockout
threshold (UVLO) for the power supply. Undervoltage
lockout keeps the LT3724 in shutdown until the supply
input voltage is above a certain voltage programmed by
the user. The hysteresis voltage prevents noise from
falsely tripping UVLO.
V – 6V
RPU
IN
ISHDN
=
Because this arrangement will clamp the SHDN pin to the
6V, it will violate the 5V absolute maximum voltage rating
of the pin. This is permitted, however, as long as the
absolute maximum input current rating of 1mA is not
exceeded. Input SHDN pin currents of <100µA are recom-
mended: a 1MΩ or greater pull-up resistor is typically
used for this configuration.
Resistors are chosen by first selecting RB. Then
V
⎛
⎞
SUPPLY(ON)
RA = RB •
– 1
⎟
⎜
⎝
1.35V
⎠
Soft-Start
VSUPPLY(ON) is the input voltage at which the undervoltage
lockout is disabled and the supply turns on.
The soft-start function forces the programmed slew rate
while the converter output rises to 95% of regulation,
which corresponds to 1.185V on the VFB pin. Once 95%
regulation is achieved, the soft-start circuit is disabled.
The soft-start circuit will re-enable when the VFB pin drops
below 70% of regulation, which corresponds to 300mV of
control hysteresis on the VFB pin. This allows for a con-
trolled recovery from a “brown-out” condition.
Example: Select RB = 49.9kΩ, VSUPPLY(ON) = 14.5V
(based on a 15V minimum input voltage)
14.5V
1.35V
⎛
⎜
⎝
⎞
⎠
RA = 49.9kΩ •
– 1
⎟
= 486.1kΩ (499kΩ resistor is selected)
LT3724
If low supply current in standby mode is required, select
a higher value of RB.
C
SS1
R
SS
A
V
OUT
C
SS
The supply turn off voltage is 9% below turn on. In the
example the VSUPPLY(OFF) would be 13.2V.
3724 F04
Figure 4.Soft-Start Circuit
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The desired soft-start rise time (tSS) is programmed via a
programming capacitor CSS1, using a value that corre-
sponds to 2µA average current during the soft-start inter-
val. This capacitor value follows the relation:
V
OUT
2•10–6 • tSS
V
OUT(SS)
C
CSS1
=
V(V )
VOUT
TIME, 250µs/DIV
RSS is typically set to 200k for most applications.
3724F05
Considerations for Low-Voltage Output Applications
Figure 5. Soft-Start Characteristic
Showing Excessive Ripple Component
The LT3724 CSS pin biases to 220mV during the soft-start
cycle, and this voltage is increased at Figure 4 node “A” by
the 2µA signal current through RSS, so the output has to
reach this value before the soft-start function is engaged.
The value of this output soft-start startup voltage offset
(VOUT(SS)) follows the relation:
V
OUT
VOUT(SS) = 220mV + RSS • 2 • 10– 6
V
OUT(SS)
V(V )
C
Which is typically 0.64V for RSS = 200k.
TIME, 250 s/DIV
In some low voltage output applications, it may be desir-
able to reduce the value of this soft-start startup voltage
offset. This is possible by reducing the value of RSS. With
reduced values of RSS, the signal component caused by
voltage ripple on the output must be minimized for proper
soft-start operation.
3724F06
Figure 6. Desirable Soft-Start Characteristic
reduced. This is typically accomplished by increasing
outputcapacitanceand/orreducingoutputcapacitorESR.
Peak-to-peak output voltage ripple (∆VOUT) will be im-
posed on node “A” through the capacitor CSS1. The value
of RSS can be set using the following equation:
External Current Limit Foldback Circuit
An additional startup voltage offset can occur during the
period before the LT3724 soft-start circuit becomes ac-
tive. Before the soft-start circuit throttles back the VC pin
in response to the rising output voltage, current as high as
the peak programmed current limit (IMAX) can flow in the
switched inductor. Switching will stop once the soft-start
circuit takes hold and reduces the voltage on the VC pin,
but the output voltage will continue to increase as the
stored energy in the inductor is transferred to the output
capacitor. WithIMAX intheinductor, theresultingleading-
edge rise on VOUT due to energy stored in the inductor
follows the relation:
∆VOUT
1.3 •10–6
RSS
=
It is important to use low ESR output capacitors for
LT3724 voltage converter designs to minimize this ripple
voltage component. A design with an excessive ripple
component can be evidenced by observing the VC pin
during the start cycle.
The soft-start cycle should be evaluated to verify that the
reduced RSS value allows operation without excessive
modulation of the VC pin before finalizing the design.
⎛ L ⎞1/2
If VC pin has an excessive ripple component during
the soft-start cycle, converter output ripple should be
∆VOUT = IMAX
•
⎜
⎟
⎝ COUT
⎠
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Inductor current typically doesn’t reach IMAX in the few
cyclesthatoccurbeforesoft-startbecomesactive,butcan
with high input voltages or small inductors, so the above
relation is useful as a worst-case scenario.
U
V
C
1N4148
1N4148
27k
This energy transfer increase in output voltage is typically
small,butforsomelowvoltageapplicationswithrelatively
small output capacitors, it can become significant. The
voltage rise can be reduced by increasing output capaci-
tance, which puts additional limitations on COUT for these
low voltage supplies. Another approach is to add an
external current limit foldback circuit which reduces the
value of IMAX during start-up.
39k
V
OUT
3724 F07
Figure 8. Current Limit Foldback Circuit for Applications
that have Soft-Start Disabled (CSS Pin Shorted to SGND)
Efficiency Considerations
An external current limit foldback circuit can be easily
incorporated into an LT3724 DC/DC converter application
by placing a 1N4148 diode and a 47kΩ resistor from the
converteroutput(VOUT)totheLT3724’sVC pin. Thislimits
the peak current to 0.25 • IMAX when VOUT = 0V. A current
limit foldback circuit also has the added advantage of
providing reduced output current in the DC/DC converter
during short-circuit fault conditions, so a foldback circuit
may be useful even if the soft-start function is disabled.
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%.
Express percent efficiency as:
% Efficiency = 100% - (L1 + L2 + L3 + ...)
whereL1,L2,etc.areindividuallosstermsasapercentage
of input power.
Although all dissipative elements in the circuit produce
losses, fourmaincontributorsusually account for most of
the losses in LT3724 circuits:
If the soft-start circuit is disabled by shorting the CSS pin
to ground, the external current limit foldback circuit must
be modified by adding an additional diode and resistor.
The 2-diode, 2-resistor network shown also provides 0.25
• IMAX when VOUT = 0V.
1. LT3724 VIN and VCC current loss
2. I2R conduction losses
3. MOSFET transition loss
V
C
4. Schottky diode conduction loss
1N4148
47k
1. The VIN and VCC currents are the sum of the quiescent
currents of the LT3724 and the MOSFET drive currents.
The quiescent currents are in the LT3724 Electrical Char-
acteristics table. The MOSFET drive current is a result of
charging the gate capacitance of the power MOSFET each
cycle with a packet of charge, QG. QG is found in the
MOSFET data sheet. The average charging current is
calculated as QG • fSW. The power loss term due to these
currents can be reduced by backdriving VCC with a lower
3724 F03
V
OUT
Figure 7. Current Limit Foldback Circuit
for Applications that use Soft-Start
voltage than VIN such as VOUT
.
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2. I2R losses are calculated from the DC resistances of the
MOSFET, the inductor, the sense resistor, and the input
and output capacitors. In continuous conduction mode
the average output current flows through the inductor and
RSENSE but is chopped between the MOSFET and the
input capacitor, and the ground return of the VCC capaci-
tor. This ground has very fast high currents and is consid-
ered the noisy ground. The two grounds are connected to
each other only at the (–) terminal of VOUT
.
2. Use short wide traces in the loop formed by the
MOSFET, the Schottky diode and the input capacitor to
minimize high frequency noise and voltage stress from
parasitic inductance. Surface mount components are pre-
ferred.
Schottky diode. The resistances of the MOSFET (RDS(ON)
)
andtheRSENSE multipliedbythedutycyclecanbesummed
with the resistances of the inductor and RSENSE to obtain
the total series resistance of the circuit. The total conduc-
tion power loss is proportional to this resistance and
usually accounts for between 2% to 5% loss in efficiency.
3. Connect the VFB pin directly to the feedback resistors
independent of any other nodes, such as the SENSE– pin.
Connect the feedback resistors between the (+) and (–)
terminals of COUT. Locate the feedback resistors in close
proximity to the LT3724 to keep the high impedance node,
VFB, as short as possible.
3. TransitionlossesoftheMOSFETcanbesubstantialwith
input voltages greater than 20V. See MOSFET Selection
section.
4. The Schottky diode can be a major contributor of power
loss especially at high input to output voltage ratios (low
duty cycles) where the diode conducts for the majority of
the switch period. Lower Vf reduces the losses. Note that
oversizing the diode does not always help because as the
diode heats up the Vf is reduced and the diode loss term
is decreased.
I2R losses and the Schottky diode loss dominate at high
load currents. Other losses including CIN and COUT ESR
dissipative losses and inductor core losses generally
account for less than 2% total additional loss in efficiency.
4.RoutetheSENSE– andSENSE+ tracestogetherandkeep
as short as possible.
5. LocatetheVCC andBOOSTcapacitorsincloseproximity
to the IC. These capacitors carry the MOSFET driver’s high
peak currents. Place the small signal components away
from high frequency switching nodes (BOOST, SW, and
TG). In the layout shown in Figure 9, place all the small
signal components on one side of the IC and all the power
componentsontheother.Thishelpstokeepthesignaland
power grounds separate.
PCB Layout Checklist
6. A small decoupling capacitor (100pF) is sometimes
useful for filtering high frequency noise on the feedback
and sense nodes. If used, locate as close to the IC as
possible.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation.
These items are illustrated graphically in the layout dia-
gram of Figure 9.
7. The LT3724 packaging will efficiently remove heat from
theICthroughtheexposedpadonthebacksideofthepart.
The exposed pad is soldered to a copper footprint on the
PCB. Make this footprint as large as possible to improve
the thermal resistance of the IC case to ambient air. This
helps to keep the LT3724 at a lower temperature.
1. Keepthesignalandpowergroundsseparate. Thesignal
groundconsistsoftheLT3724SGNDpin,theexposedpad
on the backside of the LT3724 IC and the (–) terminal of
VOUT. The signal ground is the quiet ground and does not
contain any high, fast currents. The power ground con-
sists of the Schottky diode anode, the (–) terminal of the
8.MakethetraceconnectingthegateofMOSFETM1tothe
TG pin of the LT3724 short and wide.
3724f
18
LT3724
W U U
APPLICATIO S I FOR ATIO
U
+
V
IN
R
C
A
BOOST
C
IN
V
16
15
14
1
V
BOOST
TG
IN
–
IN
M1
LT3724
L1
R
R
SENSE
B
3
4
+
SHDN
SW
C
D2
D3
SS
17
R
CSS
C
12
11
10
9
5
6
7
SS
V
BURST_EN
CC
C
OUT
C
V
OUT
VCC
V
PGND
FB
D1
+
V
C
SENSE
R2
R
8
C
–
SGND
SENSE
C
–
C1
R1
C
C2
3724 F06
Figure 9. LT3724 Layout Diagram (See PCB Layout Checklist).
Minimum On-Time Considerations
(Step-Down Converters)
therefore, the minimum duty cycle of the MOSFET switch
is 6%. When the duty cycle needs to be less than 6% the
output will stay regulated, but cycle skipping may occur.
Cycle skipping results in an increase in inductor ripple
current. If it is important that cycle skipping does not
occur, follow this guideline which takes into account
Minimumon-time(tTG(ON))istheleastamountoftimethat
the LT3724 is capable of turning the MOSFET on and then
offagain. Itisdeterminedbyinternaltimingdelaysandthe
gate charge of the MOSFET. Applications with high input
to output differential voltages operate at low duty cycles
andmayapproachthisminimumon-time,typically300nS.
TheLT3724switchingfrequencyisinternallysetto200kHz,
worst case fSW and tTG(ON)
IN(MAX) ≤ 9 • VOUT
This is only an issue for supplies with VOUT < 7V.
:
V
3724f
19
LT3724
U
TYPICAL APPLICATIO S
12V to 24V/50W Boost (Step-Up) Converter
D1
BAV99
R
SENSE
0.015Ω
16
15
14
1
V
IN
8V TO16V
V
BOOST
TG
IN
C
IN
0.1µF
L1
R3
4.7M
33µF ×2
25V
10µH
D2
25V
LT3724
V
OUT
24V AT 50W
3
C1
1500pF
SHDN
SW
SBM540
R
CSS
200k
4
C
SS
M1
12
11
10
9
5
6
7
R2
C
C
OUT2
OUT1
330µF
V
BURST_EN
CC
187k
2.2µF x3
C4
1µF
25V
35V
50V
V
PGND
FB
+
V
C
SENSE
R1
10k
R6
8
–
40.2k
C2
120pF
SGND
SENSE
C
= SANYO, 25SVP33M
L1 = VISHAY, IHLP-5050FD-011
M1 = SILICONIX, Si7370DP
IN
C3
4700pF
C
C
= SANYO, 35CV330AXA
= TDK, C4532X7R1H225K
OUT1
OUT2
D2 = DIODESINC., SBM540
3724 TA02
R
= IRC LRF2512-01-R0I5-F
SENSE
Efficiency and Power Loss vs Load Current
100
98
96
94
92
90
88
6
5
4
3
2
1
0
0.1
1
10
LOAD CURRENT (A)
3724 F08
3724f
20
LT3724
U
TYPICAL APPLICATIO S
300mA LumiLED High Voltage Constant
Current Driver with Dimmer Control
LumiLED
L1
300µH
V
IN
8V TO 60V
C
IN
D1
B170
2.2µF
16
15
14
1
100V
V
BOOST
TG
IN
M1
R1
ZXMN10A07F
4.7M
OPTIONAL
DIMMER
LT3724
3
4
SHDN
SW
CONTROL
C
VCC
M2
2N7002
1µF
C
SS
16V
1kHz
12
11
10
9
5
6
7
V
BURST_EN
CC
ADJUST I
:
LED
0.15V
V
FB
PGND
I
=
LED
R
SENSE
+
V
C
SENSE
C
= TDK, C4532X7R2A225K
R
IN
SENSE
0.5Ω
8
–
D1 = DIODESINC., B170
SGND
SENSE
C1
100pF
M1 = ZETEX, ZXMN10A07F
R
= VISHAY, WSL2010R0150FEA
SENSE
L1 = COILTRONICS, CTX300-4
3724 TA03
3724f
21
LT3724
U
TYPICAL APPLICATIO S
12V Step-Down with VCC Back Driven
from VOUT and Ceramic Capacitor in Output Filter
V
IN
15V TO 60V
C6
0.1F
16V
+
C
IN
2.2F x2
100V
100F
100V
R2
499k
16
1
3
V
BOOST
IN
R3
49.9k
R7
20Ω
15
14
M1
Si7852DP
SHDN
TG
C1
3300pF
SW
LT3724
R
CSS
4
V
C
OUT
D2A
SS
12V AT 50W
200k
BAV99
12
11
10
9
5
6
7
8
L1
47H
R4
130k
R
SENSE
V
CC
BURST_EN
C4
0.020
1F
V
PGND
FB
D2B
BAV99
16V
C
OUT
D1
33F x3
16V
+
V
C
SENSE
R6
15k
R5
14.7k
–
SGND
C2
120pF
SENSE
C3
680pF
3724 TA04
C
C
: TDK, C4532X7R2A225MT
OUT
IN
: TDK, C4532X7R1C336MT
D1: DIODESINC., PDS5100H
L1: COEV DU1971-470M
M1: VISHAY Si7852DP
3724f
22
LT3724
U
PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BC
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
3.58
(.141)
16 1514 13 12 1110
9
6.60 ±0.10
4.50 ±0.10
2.94
(.116)
6.40
(.252)
BSC
SEE NOTE 4
2.94
(.116)
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE16 (BC) TSSOP 0204
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3724f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LT3724
U
TYPICAL APPLICATIO S
Inverting –12V 1.5A Converter
V
IN
18V TO 36V
R3
0.1 F
16V
2M
16
15
14
1
V
BOOST
TG
IN
0.1 F
M1
L1
47 H
+
C
IN1
LT3724
220 F
50V
3
4
SHDN
SW
D1A
C
SS
D1B
D2
12
C
R
CSS
200k
SS
V
CC
1000pF
R1
88.7k
1 F
16V
V
OUT
–12V
1.5A
11
10
9
6
7
V
V
PGND
FB
C
R6, 40.2k
+
R2
10.2k
SENSE
R
C
C
SENSE
C2
C1
C
OUT1
0.040
680pF
120pF
8
330 F
–
+
GND
SENSE
16V
D1 = BAV99
3724 TA05
D2 = ON SEMI, MBRD350
L1 = COEV, DU1311-470M
M1 = VISHAY, Si7370DP
C
C
= SANYO, 50CV220KX
OUT1
IN1
= SANYO, 16SVP330M
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
up to 60V, Drivers 10000pF Gate Capacitance, I
LT1339
High Power Synchronous DC/DC Controller
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LTC1624
LTC1702A
LTC1735
LTC1778
LT3010
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LT3800
High Voltage Synchronous Regulator Controller
V
up to 60V, I
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OUT
IN
16-Lead TSSOP FE Package
3724f
LT/TP 0305 1K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2005
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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