LT5506 [Linear]
40MHz to 500MHz Quadrature Demodulator with VGA; 40MHz至500MHz的正交解调器与VGA
| 型号： | LT5506 |
| 厂家： | 
Linear |
| 描述： | 40MHz to 500MHz Quadrature Demodulator with VGA |
| 文件： | 总12页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT5506
40MHz to 500MHz
Quadrature Demodulator
with VGA
U
FEATURES
DESCRIPTIO
TheLT®5506isa40MHzto500MHzmonolithicintegrated
quadraturedemodulatorwithvariablegainamplifier(VGA),
designed for low voltage operation. It supports standards
that use a linear modulation format. The chip consists of
a VGA, quadrature down-converting mixers and lowpass
noise filters. The LO port consists of a divide-by-two stage
and LO buffers. The IC provides all building blocks for IF
down-conversionto IandQbasebandsignalswithasingle
supplyvoltageof1.8Vto5.25V. TheVGAgainhasalinear-
in-dB relationship to the control input voltage. Hard-clip-
ping amplifiers at the mixer outputs reduce the recovery
time from a signal overload condition. The lowpass filters
reduce the out-of-band noise and spurious frequency
components. The cut-off frequency of the noise filters is
approximately 8.8MHz. The external 2xLO frequency is
required to be twice the IF input frequency for the mixers.
The standby mode provides reduced supply current and
fast transient response into the normal operating mode
when the I/Q outputs are AC-coupled to a baseband chip.
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Wide Range 1.8V to 5.25V Supply
■
Frequency Range: 40MHz to 500MHz
■
–4dB to 59dB Variable Power Gain
■
THD < 0.12% (–58dBc)
at 800mVP-P Differential Output Level
■
8.8MHz I/Q Lowpass Output Noise Filters
■
IF Overload Detector
■
Baseband I/Q Amplitude Imbalance: 0.2dB
■
Baseband I/Q Phase Imbalance: 0.6°
■
6.8dB Noise Figure at Max Gain
■
Input IP3 at Low Gain: –0.5dBm
■
Low Supply Current: 27mA
■
Low Delay Shift Over Gain Control Range: 2ps/dB
■
Outputs Biased Up While in Standby
■
16-Lead QFN 4mUm x 4mm Package with Exposed Pad
APPLICATIO S
■
IEEE802.11
High Speed Wireless LAN
■
■
Wireless Local Loop
U
TYPICAL APPLICATIO
Total Harmonic Distortion vs
IF Input Level at 1.8V Supply
–30
1.8V
280MHz
IF INPUT
C2
C1
f
f
f
= 280MHz
= 280.1MHz
= 570MHz
IF, 1
IF, 2
2xLO
+
1µF
1nF
IF
L1
15nH
C3
10pF
L2
15nH
–35
–40
–45
–50
–55
–60
800mV DIFFERENTIAL OUT
P-P
V
CC
+
–
I
I
OUT
–
IF
OUT
IF DET
+
V
CTRL
C3
1.8pF
GAIN CONTROL
+
2xLO
Q
OUT
2xLO
C4
L3
39nH
560MHz
3.3pF
–
÷2
Q
OUT
INPUT
–
2xLO
–60
–40
–30
–20
–10
–50
LT5506
EN
ENABLE
STBY
STANDBY
GND
C5
3.3pF
IF INPUT POWER EACH TONE (dBm)
5506 TA01
5506 TA01b
5506fa
1
LT5506
W W
U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
ORDER PART
Supply Voltage ....................................................... 5.5V
Differential Voltage Between 2xLO+ and 2xLO–.......... 4V
IF+, IF– ............................................. –500mV to 500mV
IOUT+, IOUT–, QOUT+, QOUT– ..................VCC – 1.8V to VCC
Operating Ambient Temperature
NUMBER
16 15 14 13
GND
1
2
3
4
12 STBY
LT5506EUF
+
+
IF
11 2xLO
17
–
–
IF
2xLO
EN
10
9
(Note 2) ...................................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
Voltage on Any Pin
GND
5
6
7
8
Not to Exceed ........................ –500mV to VCC + 500mV
UF PACKAGE
16-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 17) IS GROUND
MUST BE SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
VCC = 3V. f2xLO = 570MHz, P2xLO = –5dBm (Note 5), fIF = 284MHz,
PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3)
SYMBOL
IF Input
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
Frequency Range
Nominal Input Level
Input Impedance
40 to 500
MHz
dBm
IF
R
= 200Ω Differential
–79 to –22
SOURCE
+
–
IF , IF to GND, EN = V
IF , IF to GND, EN = GND
100Ω//1.2pF
CC
+
–
1pF
NF
Noise Figure at Max Gain
Min Gain (Note 4)
V
V
V
P
P
V
= 1.7V
= 0.2V
= 1.7V
6.8
0.9
59
dB
dB
CTRL
CTRL
CTRL
G
G
8
L
Max Gain (Note 4)
Input IP3, Min Gain
Input IP3, Max Gain
Input IP2, Max Gain
50
dB
H
IIP3
= –22.5dBm (Note 7)
= –75dBm (Note 7)
–0.5
–49
–8
dBm
dBm
dBm
IF
IF
IIP2
= 1.7V
CTRL
Demodulator I/Q Output
Nominal Voltage Swing
(Note 6)
(Note 6)
0.8
V
V
P-P
Clipping Level
1.25
P-P
DC Common Mode Voltage
I/Q Amplitude Imbalance
I/Q Phase Imbalance
DC Offset
V
– 1.19
0.2
V
CC
(Note 8)
0.5
3
dB
(Note 8)
0.6
Deg
mV
kΩ
(Notes 6, 8)
Single Ended, C
28
Output Driving Capability
STBY to Turn-On Delay
I/Q Output 1dB Compression
I/Q Output IM3
≤ 10pF
2
1.5
LOAD
0.3
µs
–11.5
–50
dBm
dBc
P
P
= –25.5dBm, 280MHz
= –25.5dBm, 280.1MHz (Note 7)
IF, 1
IF, 2
5506fa
2
LT5506
ELECTRICAL CHARACTERISTICS
VCC = 3V. f2×LO = 570MHz, P2×LO = –5dBm (Note 5), fIF = 284MHz,
PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3)
SYMBOL
Variable Gain Amplifier (VGA)
Gain Slope Linearity Error
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
CTRL
= 0V to 1.4V
±0.5
±0.3
100
0 to 1.7
43
dB
dB
Temperature Gain Shift
T = –40°C to 85°C, V
= 0V to 1.4V
CTRL
Gain Control Response Time
Gain Control Voltage Range
Gain Control Slope
Settled within 10% of Final Value
ns
V
dB/V
kΩ
Gain Control Input Impedance
Delay Shift Over Gain Control
To Internal 0.2V
25
Measured Over 10dB Step
2
ps/dB
Baseband Lowpass Filter
–3dB Cutoff Frequency
Group Delay Ripple
7.2
8.8
5
10.4
MHz
ns
2xLO Input
f
Frequency Range
Input Power
80 to 1000
–5
MHz
dBm
dBm
2xLO
P
1:2 Transformer with 240Ω Shunt Resistor (Note 5)
–20
2xLO
Input Power
LC Balun (Note 5)
–10
+
–
Input Impedance
DC Common Mode Voltage
Differential Between 2xLO and 2xLO
800Ω//0.4pF
V
CC
– 0.4
V
IF Detector
IF Detector Range
Referred to IF Input
–30 to 8
0.3 to 1.2
100
dBm
V
Output Voltage Range
Detector Response Time
For P = –30dBm to 8dBm
IF
With External 1.8pF Load,
ns
Settling within 10% of Final Value
Power Supply
V
Supply Voltage
Supply Current
Shutdown Current
Standby Current
1.8
5.25
36
V
mA
µA
CC
I
I
I
EN = High, STBY = Low or High
EN, STBY < 350mV
26.5
0.2
CC
30
OFF
EN = Low; STBY = High
3.6
5.5
mA
STBY
Mode
Enable
Enable Pin Voltage
Enable Pin Voltage
Standby Pin Voltage
Standby Pin Voltage
EN = High
1
1
V
V
V
V
Disable
Standby
No Standby
EN = Low
0.5
0.5
STBY = High
STBY = Low
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Specifications over the –40°C to 85°C temperature range are
assured by design, characterization and correlation with statistical process
controls.
Note 5: If a narrow-band match is used in the 2xLO path instead of a 1:2
transformer with 240Ω shunt resistor, 2xLO input power can be reduced
to –10dBm, without degrading the phase imbalance. See Figure 11 and
Figure 6.
+
–
Note 6: Differential between I
and I
(or differential between
OUT
OUT
+
–
Q
OUT
and Q
).
OUT
Note 3: Tests are performed as shown in the configuration of Figure 6. The
IF input transformer loss is substracted from the measured values.
Note 7: The gain control voltage V
is set in such a way that the
CTRL
+
–
differential output voltage between I
and I
(or differential between
OUT
OUT
Note 4: Power gain is defined here as the I (or Q) output power into a 4kΩ
differential load, divided by the IF input power in dB. To calculate the
voltage gain between the differential I output (or Q output) and the IF
input, including ideal matching network, 10 • log(4kΩ/50) = 19dB has to
be added to this power gain.
+
–
Q
OUT
and Q
) is 800mV , with the given input power P .
OUT P-P IF
Note 8: The typical parameter is defined as the mean of the absolute
values of the data distribution.
5506fa
3
LT5506
U W
VCC = 3V. f2×LO = 570MHz, P2×LO = –5dBm
TYPICAL PERFOR A CE CHARACTERISTICS
unless otherwise noted. (Note 3)
(Note 5), fIF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC
,
Gain and Noise Figure
vs Control Voltage at 3V Supply
Supply Current vs Supply Voltage
32
30
28
26
24
22
20
60
50
40
30
20
10
0
85°C
25°C
–40°C
NF
GAIN AT 25°C
NF AT 25°C
GAIN AT –40°C
NF AT –40°C
GAIN AT 85°C
NF AT 85°C
GAIN
f
f
= 284MHz
IF
2xLO
= 570MHz
–10
1.75
2.75 3.25 3.75 4.25 4.75 5.25
SUPPLY VOLTAGE (V)
2.25
0.3
0.6
0.9
1.2
1.8
0
1.5
V
(V)
CTRL
5506 G01
5506 G02
Gain and Noise Figure
vs Control Voltage at 1.8V Supply
Gain Flatness
vs Control Voltage at 1.8V Supply
60
50
40
30
20
10
0
0.5
0.4
0.3
0.2
25°C
85°C
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
NF
GAIN AT –40°C
NF AT –40°C
GAIN AT 25°C
NF AT 25°C
GAIN AT 85°C
NF AT 85°C
–40°C
GAIN
f
f
= 284MHz
IF
2xLO
= 570MHz
–10
0.3
0.6
0.9
1.2
1.8
0
1.5
0
0.3
0.9
(V)
1.2
1.5
0.6
V
V
(V)
CTRL
CTRL
5506 G03
5506 G04
Gain and Noise Figure
vs IF Frequency
Gain and Noise Figure
vs Control Voltage and VCC
60
50
40
30
20
10
0
60
50
40
30
20
10
0
GAIN, V
= 1.6V
CTRL
NF, V
= 0.2V
CTRL
GAIN, V
= 0.9V
CTRL
NF, V
= 0.9V
CTRL
NF
GAIN AT 1.8V
NF AT 1.8V
GAIN AT 3V
NF AT 3V
GAIN AT 5.25V
NF AT 5.25V
NF, V
= 1.6V
CTRL
GAIN
f
f
= 284MHz
GAIN, V
= 0.2V
IF
2xLO
CTRL
100
= 570MHz
–10
–10
0.3
0.6
0.9
1.5
0
1.8
1.2
10
1000
IF FREQUENCY (MHz)
V
(V)
CTRL
5506 G06
5506 G05
5506fa
4
LT5506
U W
VCC = 3V. f2×LO = 570MHz, P2×LO = –5dBm
TYPICAL PERFOR A CE CHARACTERISTICS
(Note 5), fIF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC
unless otherwise noted. (Note 3)
,
Total Harmonic Distortion
vs IF Input Power at 3V Supply
and 800mVP-P Differential Out
Total Harmonic Distortion
vs IF Input Power at 1.8V Supply
and 800mVP-P Differential Out
Total Harmonic Distortion
vs IF Input Power and IF
Frequency
–30
–35
–40
–45
–50
–55
–60
–65
–30
–35
–40
–45
–50
–55
–60
–30
–35
–40
–45
–50
–55
–60
f
f
f
= 280MHz
= 280.1MHz
= 570MHz
800mV DIFFERENTIAL OUT
P-P
f
f
f
= 280MHz
= 280.1MHz
= 570MHz
IF,1
IF,2
2xLO
IF,1
IF,2
2xLO
3V SUPPLY
–40°C
–40°C
f
= 280MHz
= 550MHz
IF
f
IF
25°C
25°C
85°C
85°C
f
IF
= 40MHz
–50
–40
–20
–60
–30
–50
–40
–20
–50
–40
–20
–60
–60
–30
–30
IF INPUT POWER EACH TONE (dBm)
IF INPUT POWER EACH TONE (dBm)
IF INPUT POWER EACH TONE (dBm)
5506 G07
5506 G08
5506 G09
LPF Frequency Response
vs Baseband Frequency
and Temperature
Total Harmonic Distortion
vs IF Input Power at 500mVP-P
Differential Out
Total Harmonic Distortion vs IF
Input Power and Supply Voltage
–40
–45
0
–5
–30
–35
–40
–45
–50
–55
–60
f
f
f
= 280MHz
= 280.1MHz
= 570MHz
V
= 3V
800mV DIFFERENTIAL OUT
P-P
IF,1
IF,2
2xLO
CC
f
f
f
= 280MHz
IF,1
IF,2
= 280.1MHz
= 570MHz
2xLO
25°C
85°C
–40°C
–50
–55
–10
–15
3V
–40°C
25°C
1.8V
–60
–65
–70
5.25V
–20
85°C
–20
–25
–45
–40
–35
–30
–25
–20
0
10
15
20
25
5
–50
–40
–60
–30
IF INPUT POWER EACH TONE (dBm)
BASEBAND FREQUENCY (MHz)
IF INPUT POWER EACH TONE (dBm)
5506 G11
5505 G12
5506 G10
LPF Frequency Response
vs Baseband Frequency and
Supply Voltage
IF Detector Output Voltage vs
IF Input CW Power at 3V Supply
IF Detector Output Voltage vs
IF Input CW Power at 1.8V Supply
1.4
1.2
1.4
1.2
0
–5
f
IF
= 280MHz
f
IF
= 280MHz
3V
1.8V
5.25V
1.0
0.8
1.0
0.8
–10
–15
–40°C 85°C
25°C
–40°C 85°C
25°C
0.6
0.4
0.2
0.6
0.4
0.2
–20
–25
–40
–30
–20
–10
0
10
–40
–30
–20
–10
0
10
0
10
15
20
25
5
IF INPUT CW POWER (dBm)
IF INPUT CW POWER (dBm)
BASEBAND FREQUENCY (MHz)
5506 G15
5506 G14
5505 G13
5506fa
5
LT5506
U W
VCC = 3V. f2×LO = 570MHz, P2×LO = –5dBm
TYPICAL PERFOR A CE CHARACTERISTICS
unless otherwise noted. (Note 3)
(Note 5), fIF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC
,
IF Detector Output Voltage
vs IF Input CW Power and
Supply Voltage
IF Detector Output Voltage vs IF
Input CW Power and IF Frequency
Phase Relation Between I and Q
Outputs vs LO Input Power
95
94
93
92
91
90
89
88
1.4
1.6
1.4
f
IF
f
IF
f
IF
f
IF
f
IF
= 284MHz, 25°C
= 284MHz, –40°C
= 284MHz, 85°C
= 40MHz, 25°C
= 550MHz, 25°C
f
IF
= 280MHz
V
CC
= 3V
1.2
f
= 280MHz
= 550MHz
IF
5.25V
1.8V
3V
1.2
1.0
0.8
0.6
0.4
0.2
1.0
0.8
f
IF
f
IF
= 40MHz
0.6
0.4
0.2
–30
–20
–10
10
–20
–5
0
5
10
–40
0
–15
–10
–40
–30
–20
–10
0
10
IF INPUT CW POWER (dBm)
IF INPUT CW POWER (dBm)
LO INPUT POWER (dBm)
5506 G17
5506 G18
5506 G16
U
U
U
PI FU CTIO S
GND (Pins 1, 4, 17): Ground. Pins 1 and 4 are connected
to each other internally. The Exposed Pad (Pin 17) is not
connectedinternallytoPins1and4.Forchipfunctionality,
the Exposed Pad and either Pin 1 or Pin 4 must be
connected to ground. For best RF performance, Pin 1,
Pin 4 and the Exposed Pad should be connected to RF
ground.
IF+, IF– (Pins 2, 3): Differential Inputs for the IF Signal.
Each pin must be DC grounded through an external
inductor or RF transformer with central ground tap. This
pathshouldhaveaDCresistancelowerthan2Ωtoground.
EN (Pin 9): Enable Input. When the enable pin voltage is
higher than 1V, the IC is completely turned on. When the
input voltage is less than 0.5V, the IC is turned off, except
the part of the circuit associated with standby mode.
2xLO–, 2xLO+ (Pins 10, 11): Differential Inputs for the
2xLO Input. The 2xLO input frequency must be twice that
of the IF frequency. The internal bias voltage is VCC – 0.4V.
STBY (Pin 12): Standby Input. When the STBY pin is
higher than 1V, the standby mode circuit is turned on to
prebias the I/Q buffers. When the STBY pin is less than
0.5V, the standby mode circuit is turned off.
VCC (Pins 5 and 8): Power Supply. These pins should be
decoupled to ground using 1000pF and 0.1µF capacitors.
+
QOUT–, QOUT (Pins 13, 14): Differential Baseband Out-
puts of the Q Channel. Internally biased at VCC – 1.19V.
VCTRL (Pin 6): VGA Gain Control Input. This pin controls
the IF gain and its typical input voltage range is 0.2V to
1.7V. It is internally biased via a 25k resistor to 0.2V,
setting a low gain if the VCTRL pin is left floating.
IOUT–, IOUT+ (Pins 15, 16): Differential Baseband Outputs
of the I Channel. Internally biased at VCC – 1.19V.
IF DET (Pin 7): IF Detector Output. For strong IF input
signals, the DC level at this pin is a function of the IF input
signal level.
5506fa
6
LT5506
W
BLOCK DIAGRA
+
+
CLIPPER
VGA
16 I
2
3
IF
OUT
I-MIXER
LPF
LPF
–
–
I
15
7
IF
OUT
90°
IF DET
V
6
CTRL
+
2×LO
Q-MIXER
11
+
Q
14
13
OUT
÷2
–
Q
0°
OUT
CLIPPER
–
2×LO 10
9
12
STBY
5506 BD
EN
U
W
U U
APPLICATIO S I FOR ATIO
The LT5506 consists of variable gain amplifier (VGA),
I/Q demodulator, quadrature LO generator, hard clipping
amplifiers (clippers), lowpass filters (LPFs) and bias
circuitry.
differential AC input impedance of the LT5506 is about
200Ω, thus a 1:4 (impedance ratio) RF transformer with
central tap can be used. In Figure 6, the evaluation board
schematic is shown using a 1:4 transformer. The mea-
suredinputsensitivityofthisboardisabout–82.6dBmfor
a10dBsignal-to-noiseratio. InthecaseofanLCmatching
circuit, the circuit of Figure 1 can be used. In Table 1 the
values are given for a range of IF frequencies. The match-
ing circuit of Figure 1 approaches 180° phase shift be-
tween IF+ and IF– in a broad range around its center
frequency. However, some amplitude mismatch occurs if
the circuit is not tuned to the center frequency. This leads
to reduced circuit linearity performance, because one of
theinputscarriesahighersignalcomparedtotheperfectly
balanced case. A 10% frequency shift from the center
frequency results in about a 2dB gain difference between
the IF+ and IF– inputs. This results in a 1.5dB higher IM3
contribution from the input stage which leads to a 0.75dB
drop in IIP3. Moreover, the IIP2 of the circuit is also
reducedwhichcanleadtoahighersecondorderharmonic
contribution. The circuit can be driven single ended, but
this is not recommended because it leads to a 3dB drop in
gain and a considerable increase in IM5 and IM7 compo-
nents. The single-ended noise figure increases by 4dB if
one IF input is directly grounded and increases by 1.5dB
if one IF input is grounded via a 1µH inductor. An IF input
cannot be left open or connected via a resistor to ground
because this will disturb the internal biasing, reducing the
gain, noise and linearity performance. For optimal perfor-
mance,itisimportanttokeeptheDCimpedancetoground
The IF signal is fed to the inputs of the VGA. The VGA gain
is typically set by an external signal in such a way that the
amplified IF signal delivered to the I/Q mixers is constant.
The IF signal is then converted into I/Q baseband signals
using the I/Q down-converting mixers. The quadrature LO
signals that drive the mixers are internally generated from
the on-chip divide-by-two circuit. The I/Q signals are
passed through a pair of hard-clipping amplifiers (clip-
pers), which protect the subsequent lowpass filters from
overloading. After externally setting the required gain,
these amplifiers should not clip. However, in the event of
overload, they reduce the settling time of the (optional)
externalACcouplingcapacitorsbypreventingasymmetri-
cal charging and discharging effects. The second order
baseband lowpass filters remove the out-of-band noise
and harmonic content generated by the mixers and the
clippers. The I/Q baseband outputs are buffered by output
drivers.
VGA and Input Matching
The VGA has a nominal 60dB gain control range with a
frequency range of 40MHz to 500MHz. The inputs of the
VGA must have a DC return to ground. This can be done
usingatransformerwithacentraltap(onsecondary)oran
LC matching circuit with a matched impedance at the
frequency of interest and near zero impedance at DC. The
5506fa
7
LT5506
U
W
U U
APPLICATIO S I FOR ATIO
C3
L1
IF
INPUT
56pF
+
–
V
TO IF
C1
10pF
TO IF
BIAS
56nH
IF
INPUT
+
–
TO IF
TO IF
75Ω
1mA
1mA
75Ω
L1
15nH
L2
15nH
C1
5.6pF
L3
120nH
L2
56nH
C2
5.6pF
+
–
IF
IF
5506 F02
5506 F01
(2a)
(2b)
Figure 2a. Simplified IF Input Matching Network at 280MHz
and Figure 2b. Simplified Circuit Schematic of the IF Inputs
Figure 1. IF Input Matching Network at 280MHz
Thismatchingnetworkcandeliverequalamplitudestothe
IF+ and IF– inputs for a narrow frequency region, but the
phasedifferencebetweentheinputswillnotbeexactly180
degrees. In practice, the phase shift will be around 145
degrees, depending on the quality factor of the network.
This will result in a reduction in the gain. The higher the
chosen quality factor, the closer the phase difference will
approach 180 degrees. However, a higher quality factor
will reduce bandwidth and create more loss in the match-
ing network. For minimum board space, 0402 compo-
nents are used. The measured noise figure for maximum
gain with this matching network is about 8dB, and the
maximum gain about 57dB. Assuming 0402 inductors
with Q = 35, the insertion loss of this network is about
2.5dB. The tolerance for the components in Figure 2a can
be 10% for a return loss higher than 10dB and a gain
reductionduetomismatchlessthan0.5dB. Themeasured
input sensitivity for this matching network (see also Fig-
ure 11) is about –82.7dBm for a 10dB signal-to-noise
ratio.
Table 1. The Component Values of Matching Network L1, L2, L3,
C1, C2 and C3.
f (MHz)
L1, L2(nH)
C1, C2(pF)
34
L3(nH)
1800
470
C3(pF)
820
220
220
220
56
IF
50
340
159
106
80
100
150
200
250
300
350
400
450
500
15.9
10.6
8.0
470
470
64
6.4
120
53
5.3
120
56
45
4.5
120
56
40
4.0
120
56
35
3.5
120
56
32
3.2
120
56
of both IF inputs lower than 2Ω. In the matching network
of Figure 1, inductor L3 is used for supplying the DC bias
current to the IF+ input. To keep the DC resistance of L3
below 2Ω, 120nH is used. This disturbs the matching
network slightly by causing the frequency where the S11
is minimal to be lower than the frequency where the
amplitudes of IF+ and IF– are equal. To compensate for
this, the value of coupling capacitor C3 is lowered and will
contribute some correcting reactance. For low frequen-
cies, it might not be possible to find any practical inductor
value for L3 with DC resistance smaller than 2Ω. In that
case it is recommended to use a transformer with central
tap. The tolerance for the components in Figure 1 can be
10% for a return loss higher than 16dB and a gain
reduction due to mismatch less than 0.3dB.
The gain of the VGA is set by the voltage at the VCTRL pin.
For high gain settings, both the noise figure and the input
IP3 will be low. From a noise figure point of view, it is
advantageous to work as closely as possible to the maxi-
mum gain point. However, if the voltage at the VCTRL pin
is increased beyond the maximum gain point (where
additional increase in control voltage does not give an
increase in gain), the response time of the gain control
circuit is increased. If control speed is crucial, a few dB of
gain margin should be allowed from the highest gain point
to be sure that at all temperatures, the maximum gain
settingisnotcrossed.Atlowgainsettings,thenoisefigure
and the input IP3 will be high. Optionally, the control
5506fa
It is possible to simplify the input matching circuit and
compromise the performance. In Figure 2a, the simplified
matching network is given.
8
LT5506
W U U
APPLICATIO S I FOR ATIO
U
V
V
CC
CC
voltage VCTRL can be set lower than 0.2V. The normal
range is from VCTRL = 0.2V to 1.7V, which results in a
nominal gain range from 0.9dB to 59dB. The linear-in-dB
gain relation with the VCTRL voltage still holds for control
voltages as low as –0.4 V. This results in an extended gain
control range of –19.7dB to 59dB. The VCTRL pin is a very
sensitive input because of its high input impedance and
therefore should be well shielded. Signal pickup on the
+
400mV
–
+
–
8k
8k
2xLO
2xLO
IF DET
1k
3.8k
V
CTRL pincanleadtospursandincreasednoisefloorinthe
5506 F03
(3b)
(3a)
I/Q baseband outputs. It can degrade the linearity perfor-
mance and it can cause asymmetry in the two-tone test. If
control speed is not important, 1µF bypass capacitors are
recommended between VCTRL and ground.
Figure 3a. Simplified Circuit Schematic of the
IF DET Output and Figure 3b. The 2xLO Inputs
3.3pF
100pF
A fast responding peak detector is connected to the VGA
input, sensitive to signal levels above the signal levels
where the VGA is operating in the linear range. It is active
from –22dBm up to 5dBm IF input signal levels. The DC
output voltage of this detector (IF DET) can be used by the
baseband controller to quickly determine the presence of
a strong input level at the desired channel, and adjust gain
accordingly. Figure 3a shows the simplified circuit sche-
matic of the IF DET output.
2xLO
2xLO
+
+
–
TO 2xLO
TO 2xLO
INPUT
INPUT
56Ω
39nH
1:4
2xLO
INPUT
+
TO 2xLO
TO 2xLO
100pF
–
TO 2xLO
240Ω
3.3pF
–
TO 2xLO
5506 F04
(4b)
(4c)
(4a)
Figure 4. 2xLO Input Matching Networks for 4a) Narrow Band
Tuned to 570MHz, 4b) Wide Band, 4c) Single-Ended Wide Band
I/Q Demodulators
minimized. Figure 3b shows the simplified circuit sche-
matic of the 2xLO inputs. Depending on the application,
different2xLOinputmatchingnetworkscanbechosen.In
Figure 4, three examples are given. The first network pro-
vides the best 2xLO input sensitivity because it can boost
up the 2xLO differential input signal using a narrow-band
resonantapproach.Thesecondnetworkgivesawide-band
match, but the 2xLO input sensitivity is about 2dB lower.
Thethirdnetworkgivesasimpleandlessexpensivewide-
bandmatch,but2xLOinputsensitivitydropsbyabout9dB.
The IF input sensitivity doesn’t change significantly using
either of the three 2xLO matching networks.
The quadrature demodulators are double balanced mix-
ers, down-converting the amplified IF signal from the VGA
into I/Q baseband signals. The quadrature LO signals are
generated internally from a double frequency external CW
signal. The nominal output voltage of the differential I/Q
baseband signals should be set to 0.8VP-P or lower,
depending on the linearity requirements. The magnitudes
of I and Q are well matched and their phases are 90° apart.
Quadrature LO Generator
The quadrature LO generator consists of a divide-by-two
circuit and LO buffers. An input signal (2xLO) with twice
the desired IF signal frequency is used as the clock for the
divide-by-twocircuit,producingthequadratureLOsignals
for the demodulators. The outputs are buffered and then
drivethedown-convertingmixers. Withafullydifferential
approach, the quadrature LO signals are well matched.
Second harmonic content (or higher order even harmon-
ics)intheexternal2xLOsignalcandegradethe90° phase
shift between I and Q. Therefore, such content should be
Baseband Circuit
The baseband circuit consists of I/Q hard limiters (clip-
pers), I/Q lowpass filters and I/Q output buffers. The hard
limiter operates as a linear amplifier normally. However, if
a high level input temporarily overloads the linear ampli-
fier, then the circuit will limit symmetrically, which will
help to prevent the filter and output buffer from overload-
ing. This speeds up recovery from an overload event,
5506fa
9
LT5506
W U U
U
APPLICATIO S I FOR ATIO
Table 2. The Logic of Different Operating Modes
which can occur during the gain settling. It also helps to
reduce the high frequency spectral content at the I/Q
outputs during overload. The second order integrated
lowpass filters are used for filtering the down-converted
baseband signals for both the I channel and the Q channel.
They serve as antialiasing and pulse-shaping filters. The
I/Q filters are well matched in gain response and group
delay. The 3dB corner frequency is typically 8.8MHz with
a group delay ripple of 5ns. The I/Q outputs can drive 2kΩ
in parallel with a maximum capacitive loading of 10pF,
from all four pins to ground. The outputs are internally
biased at VCC – 1.19V. Figure 5 shows the simplified
output circuit schematic of the I channel or Q channel.
EN
STBY
Comments
Low
Low
High
Low
Shutdown Mode
Standby Mode
High
Low or High
Normal Operation Mode
the EN pin and STBY pin. In both normal operating mode
and standby mode, the maximum discharging current is
about 300µA, and the maximum charging current is more
than 4mA. In Figure 5 the simplified circuit schematic of
the STBY (or EN) input is shown.
V
CC
V
CC
+
TheI/QbasebandoutputscanbeDC-coupledtotheinputs
ofabasebandchip.ForAC-coupledapplicationswithlarge
capacitors, the STBY pin can be used to pre-bias the
outputs to nominal VCC – 1.19V at much reduced current.
Thismodedrawsonly3.6mAsupplycurrent. WhentheEN
pin is then driven high (>1V), the chip is quickly switched
to normal operating mode, avoiding the introduction of
large charging time constants. Table 2 shows the logic of
I CHANNEL (OR
Q CHANNEL):
DIFFERENTIAL
SIGNALS
I
OUT
+
–
(OR Q
)
OUT
–
I
OUT
(OR Q
)
OUT
22k
FROM LPF
STBY
(OR EN)
300µA
300µA
5506 F05
Figure 5. Simplified Circuit Schematic of I Channel
(or Q Channel) Outputs and STBY (or EN) Input
+
–
+
–
I
I
Q
OUT
Q
OUT
OUT OUT
V
CC3
C37
0.1µF
C35
4.7µF
C36
4.7µF
C38
0.1µF
R43
2k
R50
2k
C34
0.1µF
C27
0.1µF
R45
1k
R41
1k
C31
1µF
C30
1µF
3
2
3
2
7
7
R47
49.9Ω
R44
49.9Ω
+
+
J1
J2
U3
U2
6
6
R46
R39
Q
OUT
I
OUT
LT1809CS
LT1809CS
3.09k
3.09k
–
–
4
4
R49
2k
R42
2k
C33
0.1µF
C28
0.1µF
C32
2.2pF
C29
2.2pF
R48
R40
3.09k
3.09k
16 15 14
13
V
CC2
R35
20k
+
–
+
–
I
I
Q
Q
OUT OUT
OUT OUT
T1, 1:4,TR-R
JTX-4-10T
C43
22nF
T2, 1:4, TR-R C45
JTX-4-10T
22nF J4
MINI-CIRCUITS
1
2
3
4
12
J3
GND
STBY
+
MINI-CIRCUITS
IF
IN
2XLO
11
10
9
+
1
6
IF
2XLO
2XLO
U1
LT5506
R52
240Ω
–
–
IF
6
1
GND
EN
R36
20k
IF
DET
7
V
V
V
CC CTRL
CC
1 = EN
2 = STBY
5
6
8
0
GND
V
CC1
C15
1nF
C22
1µF
C16
1nF
C39
1µF
5506 F04
SW1
V
CTRL
OVERLOAD
R51
100Ω
C25
1.5pF
C26
1.8pF
NOTE: OUTPUT BUFFERS U2 AND U3 WITH ASSOCIATED
COMPONENTS ARE INCLUDED FOR MEASUREMENT PURPOSES ONLY.
BOARD NUMBER: DC468A (NARROW-BAND VERSION: DC535A)
C43, C45, C22, R51, C25, C26 AND C39 ARE OPTIONAL
Figure 6. Evaluation Circuit Schematic with I/Q Output Buffers
5506fa
10
LT5506
W U U
APPLICATIO S I FOR ATIO
U
Figure 8. Component Side Layout of Evaluation Board
Figure 7. Component Side Silkscreen of Evaluation Board
Figure 10. Bottom Side Layout of Evaluation Board
Figure 9. Bottom Side Silkscreen of Evaluation Board
5506fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LT5506
W U U
U
APPLICATIO S I FOR ATIO
15nH
1.8V
5, 8
RX INPUT:
1µF
1nF
2.4GHz TO 2.5GHz
10pF
280MHz
V
2
CC
IF SAW BP FILTER
BASEBAND
HARD
CLIPPER
VGA
RX
PROCESSOR
I-MIXER
LPF
FRONT END
16
15
15nH
3
A/D
I-OUTPUTS
IF DET
1ST LO,
2.12GHz
0°
TO 2.22GHz
7
A/D
D/A
MAIN
V
CTRL
6
SYNTHESIZER
Q-MIXER
14
2ND LO,
560MHz
–10dBm
A/D
13 Q-OUTPUTS
90°
11
AUX
SYNTHESIZER
LPF
HARD
CLIPPER
3.3pF
3.3pF
39nH
10
f/2
12
9
STBY
LT5506
EN
5506 F11
0,1,4
Figure 11. 2.4GHz to 2.5GHz Receiver Application (RX IF = 280MHz)
U
PACKAGE DESCRIPTIO
UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692)
BOTTOM VIEW—EXPOSED PAD
0.75 ± 0.05
R = 0.115
TYP
0.55 ± 0.20
4.00 ± 0.10
(4 SIDES)
15
16
0.72 ±0.05
PIN 1
TOP MARK
1
2
4.35 ± 0.05
2.90 ± 0.05
2.15 ± 0.05
(4 SIDES)
2.15 ± 0.10
(4-SIDES)
PACKAGE
OUTLINE
(UF) QFN 0503
0.30 ± 0.05
0.65 BSC
0.200 REF
0.30 ±0.05
0.65 BSC
0.00 – 0.05
NOTE:
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT5500
LT5502
LT5503
LT5504
LTC5505
LTC5507
LT5511
LT5512
1.8GHz to 2.7GHz Receiver Front End
400MHz Quadrature IF Demodulator with RSSI
1.2GHz to 2.7GHz Direct IQ Modulator and Mixer 1.8V to 5.25V Supply, Four Step RF Power Control, 120MHz Modulation Bandwidth
800MHz to 2.7GHz RF Measuring Receiver 2.7V to 5.25V Supply, 80dB Dynamic Range, Temperature Compensated
RF Power Detectors with >40dB Dynamic Range 2.7V to 6V Supply, 300MHz to 3.5GHz, Temperature Compensated
1.8V to 5.25V Supply, Dual-Gain LNA, Mixer
1.8V to 5.25V Supply, 70MHz to 400MHz IF, 84dBm Limiting Gain, 90dB RSSI Range
100kHz to 1000MHz RF Power Detector
High Signal Level Upconverting Mixer
High Signal Level Downconverting Mixer
2.7V to 6V Supply, 40dB Dynamic Range, Temperature Compensated
RF Output to 3GHz, 17dBm IIP3, Integrated LO Buffer
DC-3GHz, 21dBm IIP3, Integrated LO Buffer
5506fa
LT/TP 1003 1K REV A • PRINTED IN USA
12 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002
相关型号：
LT5506EUF#TR
LT5506 - 40MHz to 500MHz Quadrature Demodulator with VGA; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LT5511EFE#TR
LT5511 - High Signal Level Upconverting Mixer; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LT5512EUF#TR
LT5512 - 1kHz-3GHz High Signal Level Active Mixer; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明