LT5554IUH-PBF [Linear]
Broadband Ultra Low Distortion 7-Bit Digitally Controlled VGA; 宽带超低失真7位数字控制VGA
| 型号： | LT5554IUH-PBF |
| 厂家： | 
Linear |
| 描述： | Broadband Ultra Low Distortion 7-Bit Digitally Controlled VGA |
| 文件： | 总32页 (文件大小：602K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT5554
Broadband Ultra Low
Distortion 7-Bit Digitally
Controlled VGA
FEATURES
DESCRIPTION
The LT®5554 is a 7-bit digitally controlled programmable
gain (PG) amplifier with 16dB gain control range. It
consists of a 50Ω input variable attenuator, followed by
a high linearity variable transconductance amplifier. The
coarse4dBinputattenuatorstepisimplementedvia2-bits
of digital control (PG5, PG6). The fine transconductance
amplifier 0.125dB step within 3.875dB gain control range
is set via 5-bits digital control (PG0 to PG4). The LT5554
gain control inputs (PGx) and the STROBE input can be
directly coupled to TTL or ECL drivers. The seven parallel
gain control inputs time skew can be eliminated by using
the STROBE input positive transition.
n
1GHz Bandwidth at all Gains
n
48dBm OIP3 at 200MHz, 2V into 50Ω,
P-P
R
= 100Ω
OUT
n
–88dBc IMD3 at 200MHz, 2V into 50Ω,
OUT
P-P
R
= 100Ω
n
n
n
n
n
n
n
n
1.4nV/√Hz Input-Referred-Noise (RTI)
20dBm Output P1dB at 70MHz, R
= 130Ω
OUT
= 50Ω)
2dB to 18dB Gain Range (R
0.125dB Gain Step Size
OUT
30ps Group Delay Variation
5ns Fast Gain Settling Time
5ns Fast Overdrive Recovery
–80dB Reverse Isolation
The internal output resistor R = 400Ω limits the maxi-
O
mum overall gain to 36dB for open outputs. The internal
circuitry of open output collectors enables the LT5554 to
be unconditionally stable over any loading conditions (in-
cluding external SAW filters) and provides –80dB reverse
isolation at 300MHz.
APPLICATIONS
n
Differential ADC Driver
n
IF Sampling Receivers
n
VGA IF Power Amplifier
50Ω Driver
n
The LT5554 is internally protected during overdrive and
has an on-chip power supply regulator.
n
Instrumentation
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
With 0.125dB step resolution and 5ns settling time, the
LT5554 is suitable in applications where continuous gain
control is required.
TYPICAL APPLICATION
OIP3 and SFDR vs Frequency
132
130
128
126
49
46
43
40
R
OUT
= 50Ω
5V
V
MODE
CC
0.1μF
+
IN
OIP3
–
IF
IF
BPF
RF
INPUT
DEC
LT5554
BPF
ADC
AMPLIFIER
+
–
IN
7 BITS
0.1μF
DEC
LO
5554 TA01
PGx GAIN CONTROL
STROBE
SFDR
C
0.1μF
0
50
100
FREQUENCY (MHz)
150
200
5554 TA01b
5554f
1
LT5554
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
TOP VIEW
Supply Voltage
V ..........................................................................6V
CC
32 31 30 29 28 27 26 25
Pin Voltages and Currents
GND
GND
DEC
1
2
3
4
5
6
7
8
24
V
CC
+
–
OUT , OUT ............................................................7V
23 ENB
STROBE, PGx..........................................–0.5V to V
GND
22
21
CC
CC
+
–
ENB, MODE.............................................–0.5V to V
IN
OUT
33
–
+
+
–
IN
20 OUT
GND
IN , IN , DEC ........................................... –0.5V to 4V
DEC
GND
GND
19
18 MODE
17
Operating Ambient Temperature Range
LT5554............................................... –40°C to +85°C
Junction Temperature ........................................... 125°C
Storage Temperature Range................. –65°C to +150°C
V
CC
9
10 11 12 13 14 15 16
UH PACKAGE
32-LEAD (5mm s 5mm) PLASTIC QFN
= 150°C, θ = 34°C/W, θ = 3°C/W
T
JMAX
JA
JC
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
32-Lead (5mm × 5mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 85°C
LT5554IUH#PBF
LT5554IUH#TRPBF
5554
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
5554f
2
LT5554
AC ELECTRICAL CHARACTERISTICS (ROUT = 50Ω) Specifications are at TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 2.2V, VIH = 2.2V, VIL = 0.6V, maximum gain (Notes 3, 6), (Test circuits shown in Figure 16), unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Dynamic Performance
BW
Large Signal –3dB Bandwidth
All Gain Settings (Note 7)
LF – 1000
20
MHz
dBm
S
OP1dB
Output 1dB Compression Point
Amplifier Transconductance at G
All Gain Settings, R
= 130Ω, 70MHz
OUT
G
F
IN
F
IN
= 100MHz
0.15
–6
M
MAX
CMRR
Common Mode Gain to Single-Ended
Output
= 100MHz, Figure 19
dB
S12
Reverse Isolation
F
IN
F
IN
= 100MHz
= 400MHz
–86
–78
dB
dB
Overdrive Recovery Time
5ns Input Pulse, V
within 10ꢀ
5
ns
OUT
Noise/Linearity Performance Two Tones, P
= 4dBm/Tone (2V into 50Ω), Δf = 200kHz
P-P
OUT
IIP3
Input Third Order Intercept Point
G
G
, F = 200MHz
27
30
dBm
dBm
MAX IN
–3.875dB, F = 200MHz
MAX
IN
OIP3
IMD3
OIP3
OIP3
HD3
Output Third Order Intercept Point for
Max-Gain
F
F
= 100MHz
= 200MHz
45
46
dBm
dBm
IN
IN
Intermodulation Product for Max-Gain
F
IN
F
IN
= 100MHz
= 200MHz
–82
–84
dBc
dBc
Output Third Order Intercept Point for
–3.875dB STEP
F
IN
F
IN
= 100MHz
= 200MHz
44
40
dBm
dBm
Output Third Order Intercept Point
G
G
, F1 = 88MHz, F2 = 112MHz
40.5
38
47
44
dBm
dBm
MAX
MAX
–3.875dB, F1 = 88MHz, F2 = 112MHz
Third Harmonic Distortion
Pout = 10dBm, F = 100MHz, G
–62
dBc
IN
MAX
V
Output Noise Noise Spectral Density
G
MAX
, F = 200MHz
MAX IN
10.7
7.3
nV/√Hz
nV/√Hz
ONOISE
G
–3.875dB, F = 200MHz
IN
NF
Noise Figure
G
G
, F = 200MHz
10
10.5
dB
dB
MAX IN
–3.875dB, F = 200MHz
MAX
IN
RTI
Input Referred Noise Spectral Density
(RMS) (Note 5)
G
G
, F = 200MHz
1.34
1.42
nV/√Hz
nV/√Hz
MAX IN
–3.875dB, F = 200MHz
MAX
IN
SFDR
Spurious Free Dynamic Range in 1Hz
BW.
G
G
, F = 200MHz
128
129
dBm/Hz
dBm/Hz
MAX IN
–3.875dB, F = 200MHz
MAX
IN
Amplifier Voltage Gain and Gain Step
G
G
G
Maximum Voltage and Power Gain
Minimum Voltage and Power Gain
Gain Step Size (Note 9)
F
F
= 112MHz
15.3
17.6
1.725
0.125
19.7
dB
dB
MAX
MIN
IN
= 100MHz
IN
Except For –4dB, –8dB, –12dB Steps
For –4dB, –8dB, –12dB Steps
0.25
0.35
dB
dB
STEP
GD
Group Delay Step Accuracy
F
IN
= 100MHz
10
ps
ERROR
AMPLIFIER I/O Differential IMPEDANCE
R
Input Resistance
F
IN
F
IN
= 100MHz, G
= 100MHz, G
to G –3.875dB
MAX
43
47
ꢁ
ꢁ
IN
MAX
MAX
–4dB to G
MIN
C
Input Capacitance
Output Resistance
Output Capacitance
F
IN
F
IN
F
IN
= 100MHz
= 100MHz
= 100MHz
2.8
400
1.9
pF
ꢁ
IN
R
O
O
C
pF
5554f
3
LT5554
AC ELECTRICAL CHARACTERISTICS (ROUT = 100Ω) Specifications are at TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 2.2V, VIH = 2.2V, VIL = 0.6V, maximum gain (Notes 3, 8), (Test circuits shown in Figure 16), unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
= 4dBm/Tone (2V into 50Ω), Δf = 200kHz
MIN
TYP
MAX
UNIT
Noise/Linearity Performance Two Tones, P
OUT
P-P
IIP3
Input Third Order Intercept Point
G
G
, F = 200MHz
27
27
dBm
dBm
MAX IN
–3.875dB, F = 200MHz
MAX
IN
OIP3
IMD3
Output Third Order Intercept Point for
Max-Gain
F
F
= 100MHz
= 200MHz
48
48
dBm
dBm
IN
IN
Intermodulation Product for Max-Gain
Output Noise Noise Spectral Density
Noise Figure
F
IN
F
IN
= 100MHz
= 200MHz
–88
–88
dBc
dBc
V
G
G
, F = 200MHz
MAX IN
21.4
14.5
nV/√Hz
nV/√Hz
ONOISE
–3.875dB, F = 200MHz
MAX
IN
NF
G
G
, F = 200MHz
10
10.5
dB
dB
MAX IN
–3.875dB, F = 200MHz
MAX
IN
RTI
Input Referred Noise Spectral Density
(RMS) (Note 5)
G
G
, F = 200MHz
1.34
1.42
nV/√Hz
nV/√Hz
MAX IN
–3.875dB, F = 200MHz
MAX
IN
SFDR
Spurious Free Dynamic Range in
1Hz BW.
G , F = 200MHz
MAX IN
128
dBm/Hz
G
G
Maximum Voltage Gain
Maximum Power Gain
F
F
= 100MHz
23.6
20.6
dB
dB
VMAX
IN
= 100MHz
PMAX
IN
AC ELECTRICAL CHARACTERISTICS (Timing Diagram) (ROUT = 50Ω) Specifications are
at TA = 25°C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V, maximum gain (Test circuit shown in
Figure 16), unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
PGx and Strobe Timing Characteristics
T
T
T
T
T
T
Setup Time PGx vs STROBE
Hold Time PGx vs STROBE
STROBE Pulse Width
0
1
2
4
4
5
ns
ns
ns
ns
ns
ns
SU
HOLD
PW
STROBE Period
R
Latency Time of the Previous Gain State
Output Settles within 1ꢀ
LATENCY
GLITCH
Time Between Previous Stable Gain State Output Settles within 1ꢀ
to Next Stable State
A
Max Glitch Amplitude
V
= 0 (No Signal or STROBE Transition During
1
3
mV
dB
GLITCH
IN
Output Signal Zero Crossing)
STROBE Transition when Output Power is at
Peak + 10dBm Power
5554f
4
LT5554
AC ELECTRICAL CHARACTERISTICS (Timing Diagram)
Timing Diagram
PG0, 1, 2, 3, 4, 5, 6
INPUTS
T
T
T
PW
SU
HOLD
STROBE
INPUTS
DATA
TRANSPARENT
DATA
LATCH
T
GLITCH
T
LATENCY
STATE (i)
STATE (i + 1)
STATE (i + 2)
OUT SIGNAL
5554 TD01
DC ELECTRICAL CHARACTERISTICS Specifications are at TA = 25°C. VCC = 5V, VCCO = 5V, ENB = 3V,
MODE = 5V, unless otherwise noted. (Note 3) (Test circuit shown in Figure 16), unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Normal Operating Conditions
V
V
Supply Voltage
4.75
5
5
5.25
6
V
V
CC
+
–
OUT , OUT Output Pin DC Common Mode (Note 4)
Voltage
CCO
Shutdown DC Characteristics, ENB = 0.6V
+
–
V
DEC, IN , IN Bias Voltage
PGx, STR Input Current
PGx, STR Input Current
2
0
2.15
V
μA
IN(BIAS)
IL(PG)
IH(PG)
OUT
I
I
I
I
V
V
= 0.6V
= 5V
IN
210
μA
IN
+
–
OUT , OUT Current
Supply Current
20
μA
V
CC
4
5.1
mA
CC
Enable Input DC Characteristics
V
V
ENB Input LOW Voltage
ENB Input HIGH Voltage
ENB Input Current
Disable
Enable
0.6
V
V
IL(EN)
IH(EN)
IL(EN)
IH(EN)
IH(EN)
3
V
CC
I
I
I
V
IN
V
IN
V
IN
= 0.6V
= 3V
20
μA
μA
μA
ENB Input Current
70
ENB Input Current
= 5V
220
300
5554f
5
LT5554
DC ELECTRICAL CHARACTERISTICS Specifications are at TA = 25°C. VCC = 5V, VCCO = 5V, ENB = 3V,
MODE = 5V, unless otherwise noted. (Note 3) (Test circuit shown in Figure 16), unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
DEC External Capacitor Charge/Discharge CURRENT
I
I
DEC Pin Source Current
DEC Pin Sink Current
V
V
= 4V
27
50
70
mA
mA
IH(DEC)
IL(DEC)
DEC
= 1.8V
–70
–38
–14
DEC
Mode Input Three-State DC Characteristics
V
V
V
MODE Input LOW Voltage for AC-Couple
MODE Input OPEN
PGx AC-Coupled, STROBE AC-Coupled
PGx AC-Coupled, STROBE DC-Coupled
PGx DC-Coupled, STROBE DC-Coupled
0
0.6
2.3
V
V
IL(MODE)
OPEN(MODE)
IH(MODE)
IL(MODE)
1.7
OPEN
MODE Input HIGH Voltage
MODE Input Current
V
CC
– 0.4
V
V
CC
I
I
V
MODE
V
MODE
= 0V
= 5V
–42
43
–31
72
–23
100
μA
μA
MODE Input Current
IH(MODE)
PGx (MODE = V ) and STROBE (MODE = OPEN or MODE = V ) INPUTS for DC-Coupled
CC
CC
V
V
Input LOW Voltage
0.6
V
V
IL
Input HIGH Voltage
Input Current
2.2
125
0
IH
I
I
V
V
= 0.6V
30
μA
μA
IL(DC)
IH(DC)
IN
Input Current
= 5V
170
220
IN
PGx (MODE = 0V or MODE = OPEN) and STROBE (MODE = 0V) INPUTS for AC-Coupled
V
V
Input Pulse Range
Instantaneous Input Voltage
4.6
V
IN(AC)
Input Pulse Amplitude
Rise and Fall Time <5ns
Rise and Fall Time >80ns
600
300
mV
mV
IN(AC)P-P
P-P
P-P
V
Maximum Input Noise Amplitude
Input Current
No LT5554 Gain Update
100
–155
420
mV
IN(AC)MAX
P-P
I
I
V
IN
V
IN
= 0V
= 5V
–210
310
–100
530
μA
IL(AC)
Input Current
μA
IH(AC)
Amplifier DC Characteristics
V
V
DEC
G
G
1.85
1.8
2
2.25
2.2
V
V
IN(DEC)
IN(BIAS)
MAX
+
–
IN , IN Bias Voltage
2.04
MAX
R
IN
INPUT Differential Resistance
G
MAX
G
MIN
48
50
ꢁ
ꢁ
G
Amplifier Transconductance
G
0.15
47
S
M
MAX
+
–
I
I
I
OUT , OUT Quiescent Current
Output Current Mismatch
V
= 5V
–
33
57
mA
μA
ODC
OUT
+
IN , IN Open
200
OUT(OFFSET)
CC
V
CC
Supply Current
G
G
G
G
, MODE = 0V
78
77
75
75
110
109
106
106
132
131
127
127
mA
mA
mA
mA
MAX
MIN
MAX
MIN
, MODE = 0V
, MODE = 5V
, MODE = 5V
I
Total Supply Current
I
CC
+ 2 • I (G )
ODC MAX
200
mA
CC(TOTAL)
+
–
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
load resistance as seen at OUT , OUT pins.
All dBm figures are with respect to 50Ω. Specifications refer to differential
inputs and differential outputs.
Note 4: An external power supply equal to V
inductors or center-tap transformer output interfaces. Whenever OUT ,
OUT pins are biased via resistors, the voltage drop produced by the DC-
is used for choke
CCO
+
Note 2: All voltage values are with respect to GND ground.
–
Note 3: R = R = 50Ω Input matching is assumed. P is the available
S
IN
IN
input power. P
is the power into R . R
= R || R
is the total
output current (I
= 45mA typical) may require a larger output external
OUT
OUT OUT
O
LOAD
ODC
+
output resistance at amplifier open-collectors outputs (used in G G gain
calculation). R = 400Ω is LT5554 internal output impedance. R
power supply. However, care must be taken not to exceed the OUT ,
V,
P
–
is
OUT absolute maximum rating when the LT5554 is disabled.
O
LOAD
5554f
6
LT5554
ELECTRICAL CHARACTERISTICS
+
–
Note 5: RTI (Referred-To-Input) stands for the total input-referred noise
voltage source. RTI is close to output noise voltage divided by voltage gain
(the exact equation is given in Definition of Specification section). The
Note 8: The external loading at OUT /OUT pins is R
= 133Ω.
LOAD
R
= R || R = 100Ω.
LOAD O
OUT
Note 9: Depending on the actual input matching conditions and frequency
of operation, the LT5554 steps involving the input attenuator tap change
may show less than 0.125dB change. These steps are G
equivalent noise source e is twice the RTI value.
Note 6: The external loading at LT5554 OUT /OUT pins is R
N
+
–
= 57Ω.
–4dB, G
MAX MAX
LOAD
R
= R
|| R = 50Ω.
–8dB, G
–12dB, and the code is given in the Programmable Gain Table.
OUT
LOAD
O
MAX
+
–
The LT5554 monotonic operation for 0.125dB step resolution can still be
obtained by skipping any such code with a gain error excedding 0.125dB.
Note 7: The IN , IN , DEC pins are internally biased. The time-constant
of input coupling capacitor sets the low frequency corner (LF) at input.
The output coupling capacitors or the transformer sets the low frequency
corner (LF) at the output. The LT5554 operates internally down to DC.
TYPICAL PERFORMANCE CHARACTERISTICS (ROUT = 50Ω) TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), unless otherwise noted.
Gain vs Frequency for
0.5dB Steps, Figure 17
Differential Gain Error vs
Frequency at –40°C
Differential Gain Error vs
Frequency at 85°C
20
18
16
14
12
10
8
0.3
0.2
0.1
0
0.3
0.2
0.1
0
12dB
12dB
4dB
8dB
4dB
8dB
6
4
–0.1
–0.2
–0.1
–0.2
2
0
0
100 200 300 400 500 600 700 800 9001000
50
75
100
125
150
175
200
50
75
100
125
150
175
200
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
5554 G01
5554 G02
5554 G03
Differential Gain Error vs
Attenuation at 50MHz
Differential Gain Error vs
Attenuation at 100MHz
Differential Gain Error vs
Attenuation at 200MHz
0.3
0.2
0.1
0
0.3
0.2
0.1
0
0.3
0.2
0.1
0
–40°C
25°C
85°C
–40°C
25°C
85°C
–40°C
25°C
85°C
–0.1
–0.2
–0.1
–0.2
–0.1
–0.2
0
–4
–8
–12
–16
0
–4
–8
–12
–16
0
–4
–8
–12
–16
ATTENUATION (dB)
ATTENUATION (dB)
ATTENUATION (dB)
5554 G04
5554 G05
5554 G06
5554f
7
LT5554
TYPICAL PERFORMANCE CHARACTERISTICS (ROUT = 50Ω) TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), unless otherwise noted.
Integral Gain Error vs
Attenuation at 50MHz
Integral Gain Error vs
Attenuation at 100MHz
Integral Gain Error vs
Attenuation at 200MHz
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
–40°C
25°C
85°C
–40°C
25°C
85°C
–40°C
25°C
85°C
–0.1
–0.1
–0.1
0
–4
–8
–12
–16
0
–4
–8
–12
–16
0
–4
–8
–12
–16
ATTENUATION (dB)
ATTENUATION (dB)
ATTENUATION (dB)
5554 G07
5554 G08
5554 G09
Maximum Gain vs Temperature
P
OUT vs PIN at Maximum Gain
POUT vs PIN at GMAX – 3.875dB
18.0
17.8
17.6
17.4
17.2
17.0
24
16
8
24
16
8
70MHz
140MHz
200MHz
70MHz
140MHz
200MHz
50MHz
100MHz
200MHz
0
0
–8
–8
–16
–16
–40 –20
0
20
40
60
80
–35
–25
–15
–5
5
15
–35
–25
–15
–5
5
15
TEMPERATURE (°C)
PIN (dBm)
PIN (dBm)
5554 G10
5554 G11
5554 G12
(ROUT = 50Ω) TA = 25°C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure
16) POUT = 4dBm/tone (2VP-P into 50ꢀ), Δf = 200kHz, unless otherwise noted.
Two-Tone OIP3 vs Frequency at
Max Gain, Three Temperatures
Two-Tone IMD3 vs Frequency at
Max Gain, Three Temperatures
IIP3 vs Frequency at Max Gain,
Three Temperatures
49
46
43
40
–76
–79
–82
–85
–88
32
30
28
26
24
85°C
85°C
25°C
25°C
–40°C
25°C
–40°C
–40°C
85°C
0
50
100
150
200
0
50
100
150
200
0
50
100
150
200
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
5554 G13
5554 G14
5554 G15
5554f
8
LT5554
TYPICAL PERFORMANCE CHARACTERISTICS (ROUT = 50Ω) TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50ꢀ),
Δf = 200kHz, unless otherwise noted.
Two-Tone OIP3 vs Frequency for
GMAX and Critical Gain Steps
Two-Tone IMD3 vs Frequency for
GMAX and Critical Gain Steps
IIP3 vs Frequency for GMAX and
GMAX –3.875dB
32
30
28
26
24
49
46
43
40
–70
–76
–82
–88
G
– 3.875dB
MAX
G
MAX
– 12dB
G
MAX
G
MAX
G
MAX
– 3.875dB
G
– 15.875dB
MAX
G
– 15.875dB
MAX
G
MAX
– 3.875dB
G
MAX
G
– 12dB
100
MAX
50
100
150
200
50
100
150
200
50
150
200
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
5554 G18
5554 G16
5554 G17
Two-Tone IMD3 and OIP3 vs
Attenuation at 50MHz
Two-Tone IMD3 and OIP3 vs
Attenuation at 70MHz
–70
–74
–78
–82
–86
48
46
44
42
40
–70
48
46
44
42
OIP3
OIP3
–74
–78
–82
–86
IMD3
IMD3
40
0
–4
–8
–12
–16
0
–4
–8
–12
–16
ATTENUATION (dB)
ATTENUATION (dB)
5554 G19
5554 G20
Two-Tone IMD3 and OIP3 vs
Attenuation at 100MHz
Two-Tone IMD3 and OIP3 vs
Attenuation at 140MHz
–70
–74
–78
–82
–86
48
–70
–74
–78
–82
–86
48
46
44
42
OIP3
46
44
42
40
OIP3
IMD3
IMD3
40
0
–4
–8
–12
–16
0
–4
–8
–12
–16
ATTENUATION (dB)
ATTENUATION (dB)
5554 G21
5554 G22
5554f
9
LT5554
TYPICAL PERFORMANCE CHARACTERISTICS (ROUT = 50Ω) TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50ꢀ),
Δf = 200kHz, unless otherwise noted.
Two-Tone IMD3 and OIP3 vs
Attenuation at 200MHz
Two-Tone OIP3 vs Tone Power at
Max-Gain
Two-Tone OIP3 vs Tone Power at
Min-Gain
–70
–74
–78
–82
–86
48
46
44
42
40
47
44
41
38
47
44
41
38
IMD3
50MHz
70MHz
100MHz
140MHz
200MHz
OIP3
50MHz
70MHz
100MHz
140MHz
200MHz
0
–4
–8
–12
–16
0
3
6
9
12
0
3
6
9
12
ATTENUATION (dB)
OUTPUT TONE POWER (dBm)
OUTPUT TONE POWER (dBm)
5554 G23
5554 G25
5554 G24
Two-Tone OIP3 vs VCCO, for GMAX
–3.875dB
Two-Tone OIP3 vs ROUT, for GMAX
Two-Tone OIP3 vs VCCO, for GMAX
48
45
42
39
36
48
45
42
39
36
50
48
46
44
25MHz
70MHz
140MHz
200MHz
25MHz
70MHz
140MHz
200MHz
25MHz
70MHz
140MHz
200MHz
2
3
4
5
6
2
3
4
5
6
50
75
(Ω)
100
OUTPUT COMMON MODE VOLTAGE (V)
OUTPUT COMMON MODE VOLTAGE (V)
R
OUT
5554 G28
5554 G30
5554 G52
Harmonic Distortion vs
Attenuation, 50MHz,
POUT = 10dBm, Figure 17
OIP3 vs Frequency for GMAX and
GMIN, POUT = 10dBm
50
45
40
35
–70
–75
–80
HD3
–85
–90
G
MIN
–95
G
MAX
–100
–105
HD5
50
100
150
200
0
–4
–8
–12
–16
FREQUENCY (MHz)
ATTENUATION (dB)
5554 G29
5554 G27
5554f
10
LT5554
TYPICAL PERFORMANCE CHARACTERISTICS (ROUT = 50Ω) TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50ꢀ),
Δf = 200kHz, unless otherwise noted.
HD3 vs Frequency for GMAX and
GMIN, POUT = 10dBm, Figure 17
HD5 vs Frequency for GMAX and
GMIN, POUT = 10dBm, Figure 17
–50
–56
–62
–68
–74
–80
–70
–76
G
MAX
G
MAX
–82
G
MIN
G
MIN
–88
–94
–100
50
100
150
200
50
100
150
200
FREQUENCY (MHz)
FREQUENCY (MHz)
5554 G31
5554 G32
(ROUT = 50Ω) TA = 25°C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16),
maximum gain, unless otherwise noted.
HD3 and HD5 vs POUT
for GMAX, Figure 17
Single-Ended Output NF vs
Frequency, Figure 18
Noise Figure vs Frequency
–40
–45
–50
–55
–60
–65
–70
–75
–80
20
15
10
5
20
15
10
5
70MHz
140MHz
G
–3.875
MAX
G
–3.875
G
MAX
HD3
HD3
HD5
G
MAX
MAX
HD5
0
0
7
10
13
16
0
200
400
FREQUENCY (MHz)
600
800
0
200
400
FREQUENCY (MHz)
600
800
OUTPUT POWER (dBm)
5554 G33
5554 G34
5554 G35
Noise Figure vs Attenuation,
140MHz
Input Referred Noise vs
Attenuation, 140MHz
Output Noise Density vs
Attenuation, 140MHz
25
20
15
10
5
6
4
2
0
12
9
6
3
0
0
0
–4
–8
–12
–16
0
–4
–8
–12
–16
0
–4
–8
–12
–16
ATTENUATION (dB)
ATTENUATION (dB)
ATTENUATION (dB)
5554 G36
5554 G37
5554 G38
5554f
11
LT5554
TYPICAL PERFORMANCE CHARACTERISTICS ( ROUT = 50Ω) TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), maximum gain, unless otherwise noted.
Single-Ended Output Current vs
Attenuation
Total ICC Current vs Attenuation
98
96
94
92
215
208
200
193
185
85°C
25°C
–40°C
25°C
85°C
–40°C
0
–4
–8
ATTENUATION (dB)
–12
–16
0
–4
–8
–12
–16
ATTENUATION (dB)
5554 G39
5554 G40
I
CC Shutdown Current vs VCC,
VIN(BIAS) vs Attenuation
ENB = 0.6V
5
4
3
2
1
0
2.2
2.1
2.0
85°C
–40°C
–40°C
25°C
85°C
25°C
4.7
4.9
5.1
(V)
5.3
5.5
0
–4
–8
–12
–16
V
ATTENUATION (dB)
CC
5554 G41
5554 G42
5554f
12
LT5554
TYPICAL PERFORMANCE CHARACTERISTICS (ROUT = 50Ω) TA = 25°C. VCC = 5V, VCCO = 5V,
ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), maximum gain, unless otherwise noted.
2dB-Step Response (PG4)
120MHz Signal
8dB-Step Response (PG6)
120MHz Signal
8dB-Step Response (PG6)
120MHz Pulse Signal
0.1V/DIV
0.1V/DIV
0.2V/DIV
5554 G46
5554 G47
5554 G48
10ns/DIV
10ns/DIV
5ns/DIV
MODE = HIGH
MODE = HIGH
MODE = HIGH
8dB-Step (PG6) 120MHz
Sinusoidal Signal for 2dB
Overdrive
8dB-Step (PG6) 120MHz
Sinusoidal Signal for 8dB
Overdrive
8dB-Step (PG6) 120MHz Pulse
Signal for 8dB Overdrive
1V/DIV
1V/DIV
1V/DIV
5554 G49
5554 G50
5554 G51
5ns/DIV
5ns/DIV
10ns/DIV
MODE = HIGH
MODE = HIGH
MODE = HIGH
PIN FUNCTIONS
GND (Pins 1, 2, 7, 8, 10, 13, 15, 16, 19, 22, 25, 26, 28,
31): Ground Pins.
PG0 (Pin 12): 0.125dB Step Amplifier Programmable
Gain Control Input Pin. Input levels are controlled by
MODE pin.
DEC (Pins 3, 6): Decoupling Pin for the Internal DC Bias
+
–
Voltage for the Differential Inputs, IN and IN . It is also
connected to the ‘virtual ground’ of the input resistive
attenuator. Capacitive de-coupling to ground is recom-
mended in order to preserve linearity performance when
STROBE (Pin 14): Strobe Pin for the Programmable Gain
Control Inputs (PGx). With STROBE in Low-state, the
Amplifier Gain is not changed by PGx state changes (latch
mode). With STROBE in High-state, the Amplifier Gain is
asynchronously set by PGx inputs transitions (transpar-
ent-mode). A positive STROBE transition updates the
PGx state. Low-state and High-state depends on MODE
pin level (Table1).
+
–
IN , IN inputs are driven with up to 3dB imbalance.
+
IN (Pin 4): Positive Signal Input Pin with Internal DC
Bias to 2V.
–
IN (Pin 5): Negative Signal Input Pin with Internal DC
V
(Pins 17, 24): Power Supply Pins. These pins are
CC
Bias to 2V.
internally connected together.
PG5 (Pin 9): 4dB Step Amplifier Programmable Gain Con-
trol Input Pin. Input levels are controlled by MODE pin.
MODE (Pin 18): PGx and STROBE Functionality and Level
Control Pin. When MODE is higher than V – 0.4V, the
CC
PG6 (Pin 11): 8dB Step Amplifier Programmable Gain
Control Input Pin. Input levels are controlled by the
MODE pin.
PGx and STROBE are DC-coupled. When the MODE pin
is lower than 0.6V, the PGx and STROBE are AC-coupled.
5554f
13
LT5554
PIN FUNCTIONS
When the MODE pin is left open, the PGx inputs are AC-
couple and the STROBE input is DC-coupled.
When the ENB input voltage is less than or equal to 0.6V,
the amplifier is turned off.
InDC-coupledmode,thePGxandSTROBEinputslevelsare
0.6V and 2.2V. In AC-coupled mode, the PGx and STROBE
PG4 (Pin 27): 2dB Step Amplifier Programmable Gain Con-
trol Input Pin. Input levels are controlled by MODE pin.
inputs are driven with 0.6V minimum amplitude (with
P-P
PG3 (Pin 29): 1dB Step Amplifier Programmable Gain Con-
trol Input Pin. Input levels are controlled by MODE pin.
rise and fall time <5ns) regardless the DC voltage level. A
positive transition sets a High-state. A negative transition
sets a Low-state (for PGx and STROBE inputs).
PG2(Pin30):0.5dBStepAmplifierProgrammableGainCon-
trol Input Pin. Input levels are controlled by MODE pin.
+
OUT (Pin20):PositiveAmplifierOutputPin.Atransformer
PG1 (Pin 32): 0.25dB Step Amplifier Programmable
Gain Control Input Pin. Input levels are controlled by
MODE pin.
with a center tap tied to V or a choke inductor is recom-
CC
mended to conduct the DC quiescent current.
–
OUT (Pin21):NegativeAmplifierOutputPin.Atransformer
EXPOSED PAD (Pin 33): Ground. This pin must be sol-
dered to the printed circuit board ground plane for good
heat dissipation.
with a center tap tied to V or a choke inductor is recom-
CC
mended to conduct the DC quiescent current.
ENB (Pin 23): Enable Pin for Amplifier. When the ENB
input voltage is higher than 3V, the amplifier is turned on.
BLOCK DIAGRAM
17
24
23
GND
(15 PINS)
V
V
ENB
CC
CC
VOLTAGE
REGULATOR
AND BIAS
ENABLE
CONTROL
DEC
3
4
+
ATTENUATOR
R
+
IN
IN
–
OUT
25Ω
21
R
O
+
AMPLIFIER
–
OUT
400Ω
IN
20
5
6
–
R
IN
DEC
25Ω
ATTENUATOR
GAIN LOGIC
4dB STEPS
TRANSCONDUCTANCE
MODE
STROBE
LOGIC
GAIN LOGIC
0.125dB STEPS
3.875dB RANGE
12dB RANGE
PG6
PG5
MODE
STROBE
PG4
PG3
PG2
PG1
PG0
11
9
18
14
27
29
30
32
12
5554 BD
Figure 1. Functional Block Diagram
5554f
14
LT5554
FUNCTIONAL CHARACTERISTICS
Programmable Gain Table
ATTENUATION
STATE
N
PG0
PG1
PG2
PG3
PG4
PG5
PG6
Step Relative to Max Gain GAIN STATE NAME
Step Size in dB
dB
0.125
0.25
H
0.5
H
H
H
H
L
1
H
H
H
H
H
H
H
H
L
2
H
H
H
H
H
H
H
H
H
H
4
H
H
H
H
H
H
H
H
H
H
8
H
H
H
H
H
H
H
H
H
H
(N – 127) • 0.125dB
127
126
125
124
123
122
121
120
119
118
…
112
111
…
104
103
…
96
95
…
64
63
…
32
31
…
8
H
L
0.00dB
G
(Max Gain)
–0.125dB
MAX
H
–0.125dB
–0.250dB
–0.375dB
–0.500dB
–0.625dB
–0.750dB
–0.875dB
–1.00dB
G
MAX
H
L
L
G
–0.25dB
MAX
MAX
L
G
–0.375dB
H
L
H
G
–0.5dB
MAX
H
L
G
–0.625dB
–0.75dB
MAX
H
L
L
L
G
MAX
L
L
H
L
H
H
H
G
–1dB
MAX
H
L
–1.125dB
G
–1.125dB
MAX
L
L
L
L
H
L
H
H
H
H
–1.875dB
–2.00dB
G
G
G
G
–1.875dB
MAX
H
H
H
H
G
–2dB
MAX
L
L
L
H
L
L
L
H
H
H
H
–2.875dB
–3.00dB
–2.875dB
MAX
H
H
H
G
–3dB
MAX
L
L
L
L
L
H
L
H
H
–3.875dB
–4.00dB
–3.875dB
MAX
H
H
H
H
H
G
–4dB
MAX
L
L
L
L
L
L
H
L
–7.875dB
–8.00dB
–7.875dB
MAX
H
H
H
H
H
H
G
–8dB
MAX
L
L
L
L
L
H
L
L
L
–11.875dB
–12.000dB
G
–11.875dB
MAX
H
H
H
H
H
G
–12dB
MAX
L
H
L
L
H
H
L
L
H
H
H
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
–14.875dB
–15.000dB
–15.125dB
–15.250dB
–15.375dB
–15.500dB
–15.625dB
–15.750dB
–15.875dB
G
G
G
–14.875dB
MAX
7
G
–15dB
MAX
6
–15.125dB
–15.25dB
–15.375dB
MAX
5
H
L
G
MAX
MAX
4
L
3
H
L
H
H
L
G
–15.5dB
MAX
2
L
G
–15.625dB
–15.75dB
(Min Gain)
MAX
1
H
L
L
G
MAX
MIN
0
L
L
G
5554f
15
LT5554
DEFINITION OF SPECIFICATIONS
Amplifier Impedance and Gain Definitions
(Differential)
G
G
LT5554 differential voltage gain:
V
⎛
⎞
VOUT
GV = 20log
= 20log G •R
in dB
OUT
(
)
M
R
S
Input source resistor. Input matching is assumed:
R = R
⎜
⎟
V
⎝
⎠
IN
S
IN
LT5554 differential power gain:
P
R
LT5554 input resistance (internal, 50Ω)
LT5554 input capacitance (internal)
LT5554 output resistance (internal, 400Ω)
LT5554 output capacitance (internal)
IN
IN
2
G = 10log(R • G • R ) in dB
P
IN
M
OUT
C
P
IN
Power available at LT5554 input, R = R =
50Ω input matching:
S
IN
R
O
O
C
2
⎛
⎞
⎛
⎞
V
2
IN
R
Load resistance as seen by LT5554
output pins
⎜
⎜
⎜
⎜
⎟
⎟
⎟
⎟
LOAD
⎜
⎟
⎝
⎠
P =10log
in dBm,
IN
R •1mW
(
)
IN
C
Load capacitance as seen by LT5554
output pins
LOAD
⎜
⎟
⎠
⎝
R
Total output resistance at LT5554 open-collec-
OUT
V is peak -value
IN
tors outputs (used in G G gain calculation):
V,
P
P
OUT
Total power delivered by LT5554 open-collec-
tor outputs:
R
= R || R
O LOAD
OUT
C
Total output capacitance at LT5554 output
(used in gain calculation):
OUT
2
⎛
⎞
⎛
⎞
VOUT
2
⎜
⎜
⎜
⎜
⎟
⎟
⎟
⎟
⎜
⎟
⎝
⎠
C
= C + C
LOAD O
OUT
POUT =10log
in dBm,
R
•1mW
(
)
OUT
G
LT5554 differential transconductance:
M
⎜
⎟
⎠
⎝
IOUT
GM =
V
VOUT is peak -value
IN
INTERNAL
EXTERNAL
+
OUT
OUT
I
= G • V
M IN
OUT
R
O
R
400Ω
LOAD
C
O
V
= I
• R
C
IDC
OUT OUT OUT
LOAD
1.9pF
5554 F02
–
R
R
R
R
OUT
OUT
O
LOAD
400Ω
Figure 2. Output Equivalent Circuit and Impedance Definitions
5554f
16
LT5554
DEFINITION OF SPECIFICATIONS
Noise Definitions for 50Ω Matched Input
NF
Noise figure in dB according to any of the fol-
lowing equations:
e
RS
Source resistor RMS noise voltage:
2
2
⎛
⎞
⎟
e
2 +iN •RS
eRS2 = 4•k • T •RS; for RS = 50Ω,
(
)
N
⎜
NF =10log 1+
=
⎞
2
⎜
⎝
⎟
⎠
eRS
0.9nV
eRS
=
Hz
⎛
⎜
⎟
⎟
2
1+RTI2
e
i
Equivalentshort-circuitinputRMSnoisevoltage
source
⎛
⎞
N
1+ VN
⎜
⎜
⎜
⎝
10log
=10log
⎟
⎜
2
2
⎟
⎟
⎠
eRS
⎝
⎠
e
⎛
⎞
RS
Equivalent open-circuit input RMS noise current
source
⎜
⎝
⎟
⎠
N
2
v
Equivalent total input RMS noise voltage
source:
N
Linearity Definitions for 50Ω Matched Input
IMD3[dBc]
Third-order intermodulation product
(negative value)
2
2
2
2
v
= e + i • R (R = 50Ω)
N N S S
N
RTI
Referred-to-input LT5554 noise voltage:
IMD3
2
IIP3[dBm]
IIP3 = P (per-tone) –
IN
2
2
2
(eRS2+ eN + iN • RS )
vN
2
RTI =
=
2
2
⎝ ⎠
3
⎛ ⎞
SFDR[dBm/Hz] SFDR =
• 174 + IIP3 – NF
(
)
⎜ ⎟
V
LT5554 output noise voltage:
ONOISE
GV
20
⎛
⎜
⎞
2
IMD3
2
⎛
⎞
⎟
⎟
⎠
e
⎛
⎞
OIP3[dBm]
OIP3=POUT
–
=IIP3+GP
VONOISE
=
RTI2 +
• 10⎝
RS
2
⎜
⎜
⎝
⎟
⎠
⎜
⎝
⎟
⎠
APPLICATIONS INFORMATION
Circuit Operation
Sincenointernalfeedbacknetworkisusedbetweenampli-
fier outputs and inputs, the LT5554 is able to offer:
The LT5554 is a high dynamic range programmable-gain
amplifier. It consists of the following sections:
• Unconditional stability for I/O reactive loading such
as filters (no isolation output resistors required)
• An input variable attenuator with 50ꢁ input imped-
ance (four 4dB steps, controlled by PG5, PG6 inputs)
• High reverse isolation
• A differential programmable transconductance ampli-
fier (32 steps, 0.125dB each controlled by PG0, PG1,
PG2, PG3, PG4 inputs)
The LT5554 is a class-A transconductance amplifier. An
input signal voltage is first converted to an output cur-
rent via the LT5554 internal G . And then, the output load
M
(R ) converts the output current into an output voltage.
OUT
• Programmable logic blocks
• Internal bias (voltage regulators)
• Enable/disable circuit
R
setstheLT5554gainandoutputnoisefloor.However,
OUT
the SFDR performance is almost independent of R
values of 25ꢁ to 100ꢁ.
for
OUT
• Overdrive protection circuit
5554f
17
LT5554
APPLICATIONS INFORMATION
The PGx gain control inputs and STROBE input can be
configured to be either DC coupled or AC coupled depend-
ing on MODE pin level. The LT5554 gain control inputs
can be connected without external components to a wide
range of user control interfaces.
Thisbufferisalsoconnectedtotheinputresistiveattenua-
tor network. The DEC pin is a ‘virtual ground’ and typically
connected to an external capacitor C
(Figures 3 and
DEC
4). When C
is used, the LT5554 will have same input
DEC
attenuation for both differential mode and common mode
signals. The DEC pin de-coupling capacitor improves the
commonmodeACperformanceevenwhenthedifferential
The LT5554 has internal overdrive protection circuitry.
The recovery time from a short duration (less than 5ns)
overdrive pulse is 5ns.
+
–
IN , IN inputs are imbalanced by 3dB.
TheDECpincanbeusedasavoltagereferenceforexternal
circuitry when DC input coupling is desired.
Input Interface
+
–
The DC voltage level at the IN , IN inputs are internally
biased to about 2V when the part is either enabled or
disabled. The best linearity performance is achieved when
an input imbalance is less than 2dB.
Output Interface
TheoutputinterfacemustconducttheDCcurrentofabout
+
–
45mA to the amplifier outputs (OUT OUT ). Two interface
examples are shown in Figures 5 and 6.
Two typical Input connection circuits are shown in Figures
3 and 4.
A wide band ADC voltage interface is shown in Figure
5 where L1 and L2 are choke inductors. For a narrow
band application, a band pass filter can be placed at the
LT5554’s outputs.
An input source with 50ꢁ (5ꢀ) is required for best gain
error performance.
R
5V
SRC/2
25Ω
C1
V
CCO
+
IN
L1
CHOKE
L2
–
+
C5
MAX GAIN:
OUT
25Ω
ADC
INDUCTORS
DEC
C
BIAS
DEC
G
G
= 24dB
LT5554
V
P
V
SRC
R1
66.5Ω
R2
66.5Ω
C6
0.1μF
= 18dB
R
SRC/2
25Ω
25Ω
C2
–
+
IN
LT5554
IN
OUT
–
+
C3
OUT
5554 F03
R
O
DEC
400Ω
ADC
Figure 3. Input Capacitively-Coupled to a Differential Source
–
IN
OUT
C4
5554 F05
+
IN
R
R
R
R
SADC
100Ω
OUT
O
LOAD
–
OUT
100Ω
400Ω 133Ω
R
SRC
25Ω
LT5554
25Ω
50Ω
•
•
C
DEC
Figure 5. Differential Output Interface
DEC
0.1μF
V
SRC
5V
V
–
IN
+
OUT
MAX GAIN:
CCO
G
G
= 24dB
= 21dB
C5
V
P
5554 F04
MAX GAIN INTO Z :
P
O
G
= 18dB
+
R5
205Ω
LT5554
Figure 4. Input Transformer-Coupled to Single-Ended Source
IN
–
+
T2
4:1
OUT
R
O
•
•
•
Decouple (DEC) Input
DEC
400Ω
Z
O
50Ω
The DEC pin provides the DC voltage level for differential
–
IN
+
–
OUT
R6
205Ω
inputs IN , IN via an internal buffer, which is able to fast
charge/discharge the LT5554 input coupling capacitors
with about 30mA sourcing or sinking current capability.
5554 F06
R
R
R
LOAD
133Ω
OUT
O
100Ω
400Ω
Figure 6. Single-Ended Matched Output Interface
5554f
18
LT5554
APPLICATIONS INFORMATION
The differential outputs can also be converted to single-
ended 50ꢁ load using a center-tap transformer interface
shown in Figure 6 and Figure 16.
VoltageclippingwilloccurwithR >140ꢁ,inwhichcase
OUT
the instantaneous voltage at each OUT and OUT outputs
is either <2V or >8V.
+
–
Theinternal400ꢁdifferentialresistor(R )setstheoutput
The output OP1dB = 20dBm can be achieved when R
130ꢁ. In this case, the LT5554 outputs reach both current
and voltage limiting for maximum output power.
=
O
OUT
impedanceandthemaximumvoltagegain(G
)to36dB
MAX
+
–
when outputs OUT , OUT are open.
Figure 7 shows the Voltage and Power Gains as a func-
Gain Control Interface
tion of R , which is the total output loading at the open
OUT
The MODE pin selects the interface to the LT5554 gain
control pins.
collector amplifier output including the internal resistor
R = 400ꢁ.
O
The PGx and STROBE control inputs can be configured
to be either DC-coupled (for TTL interface) or AC-coupled
(for ECL or low-voltage CMOS interfaces).
36
VOLTAGE GAIN
30
24
18
12
6
In addition, the STROBE input can be driven such that the
LT5554 gain state is updated asynchronously (PGx latch
control in transparent-mode) or controlled by positive
STROBE transition (PGx latch control in strobed-mode).
POWER GAIN
There are several options available for coupling type and
latch control which are given in the following tables:
0
Table1. MODE Input Options
10
50
100
(Ω)
400
1000
R
OUT
COUPLING TYPE
5554 F07
MODE
(State)
STROBE
PGx
PGx (Latch Control)
Figure 7. Maximum Voltage and Power Gain vs ROUT
AC Positive
Transition
LOW
OPEN
OPEN
HIGH
HIGH
AC
AC
AC
DC
DC
Strobe
Transparent
Strobe
The gain vs R
equations:
relationship is given by the following
OUT
DC >2.2V
0.6 to 2.2V
DC >2.2V
G = 20log(G • R ) in dB
V
M
OUT
Transparent
Strobe
0.6 to 2.2V
G = 10log(R • G • R ) in dB
P
IN
M2
OUT
Where R = 50Ω and G = 0.15 siemens at G
MAX
IN
M
Table2. MODE Input Levels
For wide band applications, the amplifier bandwidth can
be extended by inductive peaking technique. The inductor
MODE
(State)
MODE
(Min Level)
MODE
(Max Level)
+
–
in series with the LT5554 outputs (OUT OUT ) can have
LOW
OPEN
HIGH
0
0.6V
2.5V
a value up to some tens of nH depending on R
and board capacitance.
value
OUT
1.5V
V
– 0.4V
V
CC
CC
The current limiting will occur with R
<140ꢁ, in which
OUT
casetheinstantaneoussignalcurrentattheoutputexceeds
= 45mA.
Alternatively, the MODE pin can be left open (2V
internal).
I
ODC
5554f
19
LT5554
APPLICATIONS INFORMATION
All seven PGx gain control inputs and STROBE input can
be configured as DC-coupled or ac-coupled. Accordingly,
therearetwobasicequivalentschematics(showninFigures
8 and 9) depending on MODE input choice (Table1).
The AC-coupled interface is shown in Figure 9. The PGx
inputs and STROBE input state is decided by a signal
transition rather than signal level.
A HIGH-state is set by positive transitions. A LOW-state is
set by negative transitions. The PGx and STROBE inputs
appear as capacitive coupled inputs. The DC voltage (0V
Each PGx input circuit shown in Figures 8 and 9 is fol-
lowed by a transparent latch controlled by the STROBE
input level (Table 1).
to V range) presented on any PGx or STROBE input is
CC
shifted to the internal 1.4V level by the additional circuit
shown in Figure 9. Each PGx and STROBE input has an
independent shift circuit such that each input can have a
different DC voltage.
TheDC-coupledinterfaceisshowninFigure8.DClevelsfor
PGx inputs and STROBE input are V <0.6V, V >2.2V.
IL
IH
V
CC
R2
1.5k
R3
1.5k
Each PGx input has a parallel R-C (R1 = 20k, C1 = 2pF)
with a 40ns time constant. The STROBE input circuit has
R1 = 20k C1 = 3pF and 60ns time constant. An minimum
+
OUT
OUT
–
R1
20k
Q1
R4
20k
amplitudeof0.6V isrequiredtotripthePGxandSTROBE
P-P
INPUT
Q2
Q3
inputs to an appropriate state when the signal period is
lessthaninputtimeconstant.ThecircuitshowninFigure 8
converts the single-ended external signal to an internal
differential signal. Consequently, when the input is idle for
V1
C1
2pF
1.4V
I1
200μA
IDC
DC-COUPLED
5554 F08
more than the input time constant, a 0.3V transition
P-P
will still trigger the gain control state change. All control
Figure 8. DC-Coupled PGx and STROBE Equivalent Inputs
(Simplified Schematic)
inputs have 200mV hysteresis to insure stable logic levels
when the input noise level is less than 100mV
.
P-P
V
CC
For transparent latch control, the amplifier gain will be
updated directly with any PGx input state changes. If
different PGx inputs have an (external) time skew greater
than 1ns, then a noticeable amplifier output glitch can
occur. The strobe latch control is recommended to avoid
this amplifier output glitch.
R2
1.5k
R3
1.5k
+
–
OUT
OUT
I3
IDC
R1
20k
Q1
R4
20k
INPUT
Q2
Q3
C1
It is not necessary to double buffer the PGx inputs since
theLT5554hasgoodinternalisolationfromthePGxinputs
to the amplifier output to any type of external gain control
circuit without external components.
2pF
AC-COUPLED
IDC
I2
V1
1.4V
I1
200μA
IDC
If LT5554 is powered up or enabled in latch mode, the
LT5554 gain initial gain is indeterminate. If the minimum
gain state is desired at power up, it is recommended to
set the transparent-mode with all PGx inputs low.
5554 F09
Figure 9. AC-Coupled PGx and STROBE Equivalent Inputs
(Simplified Schematic)
5554f
20
LT5554
APPLICATIONS INFORMATION
Gain Step Accuracy
code whenever PG5, PG6 transitions are involved in or-
der to preserve high-frequency monotonic behavior for
0.125dB steps.
LT5554 internal input signal coupling to the transcon-
ductance amplifier inputs across the 4dB step attenuator
increases with frequency. The gain step error is higher
when the LT5554 gain update changes the input attenua-
tor tap (PG5, PG6 transitions) and this error is frequency
dependent.
Linearity and Noise Performance Throughout the
Gain Range
The LT5554’s Noise and Linearity performance across
the 16dB gain range at 100MHz with R
SADC
= 100 and
OUT
Gain error is ‘compressive’, effectively reducing LT5554
gain range. Therefore, it is possible to skip one gain
R
= 50Ω is shown in Figures 10 through 13.
12
9
24
18
12
6
44
39
34
29
24
136
V
ONOISE
132
128
124
120
SFDR
6
NF
3
IIP3
RTI
0
0
0
–4
–8
–12
–16
0
–4
–8
–12
–16
ATTENUATION (dB)
ATTENUATION (dB)
5554 F10
5554 F11
Figure 10. Noise, 140MHz, ROUT = 50Ω
Figure 11. Noise, 140MHz, ROUT = 50Ω
–70
–74
–78
–82
–86
48
–70
–74
–78
–82
–86
48
OIP3
OIP3
46
44
42
40
46
44
42
40
IMD3
IMD3
0
–4
–8
ATTENUATION (dB)
–12
–16
0
–4
–8
ATTENUATION (dB)
–12
–16
5554 F12
5554 F12
Figure 12. Linearity, 70MHz, ROUT = 50Ω, 4dBm/Tone
Figure 13. Linearity, 140MHz, ROUT = 50Ω, 4dBm/Tone
5554f
21
LT5554
APPLICATIONS INFORMATION
The LT5554 Noise and Linearity performance throughout
the 16dB gain range has an obvious discontinuity at every
4dB gain step. The noise figure is fairly constant from 0dB
(MaximumGain)to–3.875dBattenuationwhenthegainis
decreasedbyloweringtheamplifiertransconductance.And
then, the NF increases by 4dB when the input attenuator
is switched to –4dB attenuation while the amplifier gain
is switched back to maximum transconductance. This
pattern repeats for each 4dB gain step change.
than 1ꢀ or use these two resistors with 1ꢀ component
tolerance. In this case, the HD2 can be as good as -80dBc
when the output power is 10dBm at 140MHz.
When the single-ended input is not converted into well
balanced inputs to LT5554, the HD2 performance will
be degraded. For instance, when the T1 transformer is
improperly rotated by 90 degrees as shown in Figure 15,
the imbalance of the differential input signals will result in
14dB degradation in HD2. It is also important to split the
differential R7 resistor into two single-ended R5 and R6
resistors at the outputs to reduce the imbalance of the T2
transformer. If not, 3dB degradation in HD2 performance
can also be observed.
SECOND ORDER HARMONIC DISTORTION
Balanced differential inputs and outputs are important
for achieving excellent second order harmonic distortion
(HD2) of the LT5554. When configured in single-ended
input and output interfaces, therefore, the single-ended
to differential conversion at the input and differential to
single-endedconversionattheoutputwillhavesignificant
impact on the HD2 performance.
V
CC
= 5V
C4
V
= 5V
CCO
0.1μF
+
IN
T2
TC2-1T
–
OUT
OUT
T1
1:1
DEC
50Ω
C1
47nF
LT5554
•
•
•
R7
134Ω
R
O
Figure 14, for example, shows the desirable singe-ended
inputandoutputconfigurationusingexternaltransformers
for the single-ended to differential conversion and differ-
ential to single-ended conversion. To assure a good HD2
performance, R5 and R6 should also be matched to better
ETC1-1-13
400Ω
–
IN
+
C3
0.1μF
C5
5554 F15
C2
47nF
1μF
Figure 15. Not Recommended Single-Ended Input and Output
Configuration, HD2 = –63dBc at 10dBm, 140MHz
V
= 5V
CC
C4
V
= 5V
CCO
R5
0.1μF
68.1Ω
+
IN
TheHD2performancecanbefurtherimprovedbymounting
T1
1:1
T2
TC2-1T
–
OUT
OUT
+
a capacitor from IN to ground (a few pF) and a capaci-
DEC
50Ω
LT5554
R6
68.1Ω
•
•
•
•
•
–
tor from OUT to ground. For narrow band applications,
R
O
these capacitors cancels to some degree the T1 and T2
imbalance as shown in Figure 15.
400Ω
–
ETC1-1-13
IN
+
C3
0.1μF
C5
5554 F14
1μF
ForoptimumHD2performance, fullydifferentialinputand
output interfaces to the LT5554 part are recommended.
Figure 14. Recommended Single-Ended Input and Output
Configuration, HD2 = –80dBc at 10dBm, 140MHz
5554f
22
LT5554
APPLICATIONS INFORMATION
Layout Considerations
The transformer board from Figure 16 was used for char-
acterization as a function of R . For each R
option,
OUT
OUT
Attention must be paid to the printed circuit board layout
to avoid output pin to input pin signal coupling (external
feedback). The evaluation board layout is a good example.
The exposed backside pad on the LT5554 package must be
soldered to PCB ground plane for thermal considerations.
The T2 transformer model and the matching resistors R5,
R6 values are given in Table 3. The T2 transformer total
matching resistance is R
= R || (R5 + R6) (part
O
MATCH
LT5554 internal, and part on board R5 and R6).
Table 3. Transformer Board ROUT Options
Characterization Test Circuits
R
(ꢀ)
50
TC2-1T
2
75
TC3-1T
3
100
TC4-1W
4
OUT
T2 (Mini-Circuits)
The LT5554’s typical performance data are on the test
circuits shown in Figures 16, 17 and 18 which are simpli-
fied schematics of the evaluation board schematic from
Figure 21.
N
LOAD
R
LOAD
Ratio
(ꢀ)
57.1
68.1
13.2
92.3
124
16
133.3
205
R5, R6 (ꢀ)
(dB)
G
17.2
P_BOARD
IL(T2) at
200MHz (dB)
–0.6
–0.65
–1
J5, 40 PINS
SMT-TB
1, 3, 5, 7
9
11
13
15
17
19
21
23
25
27
29
PG
31
MODE
33, 35, 37, 38
2, 4, ...40
V
V
ENB PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE
V
V
CCO
CC
DEC
R20
10k
R21
10k
R22
10k
R23
10k
R24
10k
R25
10k
R26
10k
C4
0.1μF
C8
0.1μF
PG0
PG1
PG2
PG3
PG4
PG5
PG6
C3
C19
4.7μF
R5
+
0.1μF
IN
68.1Ω
J1
50
T1
1:1
–
OUT
R
IN
J3
50
50Ω
LT5554
•
•
•
•
•
OUTPUT
MATCHING
R
O
400Ω
–
T2
IN
+
OUT
TC2-1T
2:1
C18
0.1μF
C9
0.1μF
R6
68.1Ω
C5
1μF
ETC1-1-13
MACOM
R
R
LOAD
400Ω 57.1Ω
O
R
= 50Ω
OUT
5554 F16
V
V
= 5V
CCO
CC
= 5V
Figure 16. Single-Ended Transformer Test Board (Simplified Schematic)
5554f
23
LT5554
APPLICATIONS INFORMATION
The LT5554 output power P
was obtained by adding
OUT
Table 4. Balun Board ROUT Options
3dB for matching-loss and the transformer loss IL(T2) in
Table 3 to the board output power at J3 connector. The
transformer insertion loss (frequency and temperature
dependent) has been included in characterization.
R
(Ω)
25
0
36
50
71
100
53.6
28
OUT
R3, R4 (Ω)
R5, R6 (Ω)
6.49
28.7
1.88
6.57
15.4
28
30.1
28
28.7
0
IL
V
3.66
6.96
5.76
7.61
8.08
8.66
PAD
(V)
6.29
The output power matching is required when LT5554
drives a 50Ω transmission line as shown on the evalua-
tion board.
CCO
The differential-output board from Figure 18 was used
for R
= 50Ω wide-band characterization of the LT5554
When LT5554 drives local (on-board) loads such that
an ADC part, output power matching is not required and
OUT
single-ended outputs.
OIP3 is defined based on P , total power at LT5554
OUT
Both Figure 17 and Figure 18 boards V
was shifted
CCO
open collector outputs.
up with the voltage drop on R5, R6 produced by 45mA
+
–
output DC current such that OUT , OUT DC bias voltage
Figure 17 shows the evaluation board for wide-band
is still 5V. The LT5554 part should be always enabled when
characterization at R
= 50Ω, where the insertion loss
OUT
+
V
>6V. If disabled, the V
will be applied at OUT ,
of the output balun is about –1dB at 1GHz. Several R
CCO
CCO
OUT
–
OUT exceeding the absolute maximum 6V limit with
possible LT5554 failure.
options are given in Table 4 as well as the output padding
insertion-lossandrequiredV for5VonLT5554outputs.
CCO
The LT5554 output power at open collector outputs is:
P
= P (J3) + IL(T2) + 3dB + IL
WR PAD
OUT
J5, 40 PINS
SMT-TB
1, 3, 5, 7
9
11
13
15
17
19
21
23
25
27
29
PG
31
MODE
33, 35, 37, 38
2, 4, ...40
V
V
ENB PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE
V
V
CCO
CC
DEC
R20
10k
R21
10k
R22
10k
R23
10k
R24
10k
R25
10k
R26
10k
PG0
PG1
PG2
PG3
PG4
PG5
PG6
C4
0.1μF
C8
0.1μF
C3
0.1μF
C9
0.1μF
C18
0.1μF
C19
4.7μF
+
R3
IN
J3
50
J1
50
T1
T2
–
15.4Ω
OUT
1:1
1:1
R
IN
R5
50Ω
LT5554
28Ω
•
•
•
•
50Ω
MATCHING
R
R6
28Ω
O
400Ω
–
IN
+
OUT
R4
15.4Ω
C5
1μF
ETC1-1-13
MACOM
ETC1-1-13
R
R
LOAD
O
400Ω 57.1Ω
R
= 50Ω
OUT
5554 F17
V
V
= 5V
CCO
CC
= 7V
Figure 17. Single Ended Test Board (Simplified Schematic)
5554f
24
LT5554
APPLICATIONS INFORMATION
J5, 40 PINS
SMT-TB
1, 3, 5, 7
9
11
13
15
17
19
21
23
25
27
29
PG
31
MODE
33, 35, 37, 38
2, 4, ...40
V
CC
V
ENB PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE
V
V
CCO
DEC
R20
10k
R21
10k
R22
10k
R23
10k
R24
10k
R25
10k
R26
10k
PG0
PG1
PG2
PG3
PG4
PG5
PG6
C4
0.1μF
C8
0.1μF
C3
0.1μF
C9
0.1μF
C18
0.1μF
C19
4.7μF
+
IN
J3
50
J1
50
T1
–
OUT
OUT
1:1
R
IN
R5
C10
50Ω
LT5554
66.5Ω
•
•
47nF
100Ω
MATCHING
R
R6
66.5Ω
O
400Ω
–
IN
+
J33
50
C5
1μF
C12
47nF
ETC1-1-13
MACOM
R
R
LOAD
57Ω
O
400Ω
R
= 50Ω
OUT
5554 F18
V
V
= 5V
CCO
ENB = 5V
CC
= 8V
Figure 18. Wideband Differential Output Test Board (Simplified Schematic)
Common mode characterization for the LT5554 was per-
formed with input circuit shown in Figure 19.
source is applied at J6 connector and 50ꢁ terminated by
R16 and R33 resistors. C66 decouple R33 to ground while
C16providesDC-decouplingbetweenreferencedtoground
pulse source and the PG6 DC-voltage. A supply connected
toPG6turretwillsetthePG6DC-voltagein0Vto5Vrange.
All other (untested) PGx DC-voltage can be independently
–
25Ω
C1
47nF
OUT
–
+
IN
25Ω
J1
50
DEC
LT5554
+
25Ω
+
–
IN
OUT
be applied at V turret decoupled by C88.
PG
C
DEC
5554 F19
47nF
Strobe-mode operation is tested with a pulse source ap-
plied at J7 connector as shown in Figure 20.
Figure 19. Common Mode Input Interface
Applying similar modifications around J2 and J4 connec-
torsshowninFigure21,otherPGxinputscanbeevaluated.
As described in Table 1 and Table 2, the MODE pin will
select the desired state.
TimingcharacterizationandAC-coupledgaincontrolinputs
are tested on evaluation board. The required circuit modi-
fications are shown in the Figure 20 simplified schematic
and detailed below for PG6 (8dB step). The PG6 pulse
5554f
25
LT5554
APPLICATIONS INFORMATION
V
PG
C88
47nF
R21
10k
R22
R23 R24
10k 10k
10k
PG1
PG2
R28
0Ω
PG4
PG3
R29
0Ω
R30 R31
C4
0.1μF
0Ω
0Ω
32
31
30
29
28
27
26
25
R8
0Ω
PG1 GND PG2 PG3 GND PG4 GND GND
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
GND
DEC
V
V
CC
V
CC
DEC
ENB
GND
ENABLE
+
–
IN
OUT
LT5554
–
+
IN
OUT
DEC
GND
GND
GND
MODE
MODE
C6
47nF
V
CC
C8
0.1μF
PG5 GND PG6 PG0 GND STROBE GND GND
C5
1μF
9
10
11
12
13
14
15
16
R16
100Ω
R17
100Ω
C16
47nF
C17
47nF
R32
0Ω
R33
100Ω
R27 R34
0Ω 100Ω
J6
J7
PG5
PG6
C27
47nF
PG0
C28
47nF
5554 F20
STROBE
R25
10k
R26
10k
R20
10k
Figure 20. Timing Test for PG6 and STROBE (Simplified Schematic)
Evaluation Board
V
supply enables the LT5554 part. PGx gain control
CC
and STROBE inputs will have TTL levels (DC-coupled)
when MODE = 5V (same power supply). To set LT5554 for
Figure 21 shows the schematic of the LT5554 evaluation
board. Transformer T2 is TC2-1T and resistor R5 + R6 =
maximumgain(G
)intransparent-mode,allsevenPGx
MAX
134Ω (R
= 50Ω G (J3) = 13.2dB). The silkscreen and
OUT
P
and STROBE can be connected to 5V supply. Alternatively,
a 2.2V power supply at V pin and STROBE turret will
layout are shown in Figures 22 through Figure 27. The
boardcontrolJ5edgeconnector(40PINSSMT-TB)allows
easy access to LT5554 component pins. Alternatively or
combined with J5, 14 test points (turrets) for signals and
two for GND are also available. The board is powered with
PG
set same G
state.
MAX
J1 (input) and J3 (output) are the default board signal
portsforevaluationwith50ꢁsingleendedtestsystem.For
differential evaluation, the board J11 and J33 connectors
must be reconfigured.
a single supply in 4.75V to 5.25V at V and V
J5 connector or turrets). Connecting the ENABLE pin to
(either
CC
CCO
5554f
26
LT5554
APPLICATIONS INFORMATION
J5, 40 PINS
SMT-TB
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
V
V
V
V
V
9
ENB PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE
V
MODE
31
V
V V V
CC
CC
CC
CC
DEC
PG
PG
CCO CCO CCO CCO
1
3
5
7
11
13
15
17
19
21
23
25
27
29
33
35
37
39
V
DEC
ENB PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE
V
MODE
V
CC
V
CCO
V
PG
PG1
PG4
R20
10k
R21
10k
R22
10k
R23
10k
R24
10k
R25
10k
R26
10k
C11
C14
R28
0Ω
R31
0Ω
47nF
47nF
NOT MOUNTED
J2
NOT MOUNTED
J4
PG0
PG1
PG2
PG3
PG4
PG5
PG6
C21
0.1μF
C22
0.1μF
C23
0.1μF
C24
0.1μF
C25
0.1μF
C26
0.1μF
C27
0.1μF
PG2 PG3
R30
NOT MOUNTED
NOT MOUNTED
C12
C13
47nF
R29
0Ω
47nF
0Ω
C21 THROUGH C27 ARE NOT MOUNTED
NOT MOUNTED
R12
NOT MOUNTED
R14
NOT MOUNTED
NOT MOUNTED
V
CCO
C3
0.1μF
C19
32
31
30
29
28
27
26
25
4.7μF
R8
PG1 GND PG2 PG3 GND PG4 GND GND
C4
0Ω
R5
1
24
GND
GND
DEC
V
V
68.1Ω
V
CC
CC
DEC
R3
2
3
4
5
6
7
8
23
22
21
20
19
18
17
T2
TC2-1T
2:1
•
•
ENB
ENABLE
+
–
0Ω
–
+
IN
T1
OUT
J1
J3
1:1
GND
+
–
•
•
•
IN
OUT
R7
NC
LT5554
–
+
IN
OUT
IN
OUT
DEC
GND
GND
GND
ETC1-1-13
MACOM
J11
J33
R4
0Ω
MINI-
CIRCUITS
MODE
MODE
R6
681Ω
C6
47nF
R1
0Ω
V
CC
NOT
MOUNTED
NOT
MOUNTED
C8
0.1μF
PG5 GND PG6 PG0 GND STROBE GND GND
C5
1μF
R2
C18
0.1μF
C9
0.1μF
0Ω
9
10
11
12
13
14
15
16
5554 F21
NOT MOUNTED
NOT MOUNTED
NOT MOUNTED
R16
R17
NOT MOUNTED
NOT MOUNTED
R33
0Ω
R27 R34
0Ω 0Ω
C16
47nF
C17
47nF
J7
NOT MOUNTED
NOT MOUNTED
J6
PG6 PG0
STROBE
R32
0Ω
C15
47nF
PG5
Figure 21. Evaluation Circuit Schematic
5554f
27
LT5554
APPLICATIONS INFORMATION
Figure 22. Top Side
Figure 23. Inner Layer 2 GND
5554f
28
LT5554
APPLICATIONS INFORMATION
Figure 24. Inner Layer 3 Power
Figure 25. Bottom Side
5554f
29
LT5554
APPLICATIONS INFORMATION
Figure 26. Silkscreen Top
Figure 27. Silkscreen Bottom
5554f
30
LT5554
PACKAGE DESCRIPTION
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 0.05
5.50 0.05
4.10 0.05
3.45 0.05
3.50 REF
(4 SIDES)
3.45 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
0.75 0.05
5.00 0.10
(4 SIDES)
31 32
0.40 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.45 0.10
3.50 REF
(4-SIDES)
3.45 0.10
(UH32) QFN 0406 REV D
0.200 REF
0.25 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
5554f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LT5554
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
Infrastructure
LT5514
Ultralow Distortion, IF Amplifier/ADC Driver with
850MHz Bandwidth, 47 dBm OIP3 at 100MHz, 10.5dB to 33dB Gain
Control Range
Digitally Controlled Gain
LT5517
LT5518
40MHz to 900MHz Quadrature Demodulator
21dBm IIP3, Integrated LO Quadrature Generator
1.5GHz to 2.4GHz High Linearity Direct Quadrature
Modulator
22.8dBm OIP3 at 2GHz, –158.2dBm/Hz Noise Floor, 50Ω Single-Ended RF and
LO Ports, 4-Channel W-CDMA ACPR = –64dBc at 2.14GHz
LT5519
LT5520
LT5521
LT5522
LT5524
0.7GHz to 1.4GHz High Linearity Upconverting Mixer
1.3GHz to 2.3GHz High Linearity Upconverting Mixer
10MHz to 3700MHz High Linearity Upconverting Mixer
17.1dBm IIP3 at 1GHz, Integrated RF Output Transformer with 50Ω Matching,
Single-Ended LO and RF Ports Operation
15.9dBm IIP3 at 1.9GHz, Integrated RF Output Transformer with 50Ω Matching,
Single-Ended LO and RF Ports Operation
24.2dBm IIP3 at 1.95GHz, NF = 12.5dB, 3.15V to 5.25V Supply, Single-Ended LO
Port Operation
600 MHz to 2.7GHz High Signal Level
Downconverting Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50Ω Single-Ended
RF and LO Ports
Low Power, Low Distortion ADC Driver with Digitally
Programmable Gain
450MHz Bandwidth, 40dBm OIP3, 4.5dB to 27dB Gain Control
LT5525
LT5526
High Linearity, Low Power Downconverting Mixer
High Linearity, Low Power Downconverting Mixer
Single-Ended 50Ω RF and LO Ports, 17.6dBm IIP3 at 1900MHz, I = 28A
CC
3V to 5.3V Supply, 16.5dBm IIP3, 100kHz to 2GHz RF, NF = 11dB,
I
CC
= 28mA, –65dBm LO-RF Leakage
LT5527
LT5528
LT5557
400MHz to 3.7GHz High Signal Level
Downconverting Mixer
IIP3 = 23.5dBm and NF = 12.5dBm at 1900MHz, 4.5V to 5.25V Supply,
= 78mA, Conversion Gain = 2dB
I
CC
1.5GHz to 2.4GHz High Linearity Direct Quadrature
Modulator
21.8dBm OIP3 at 2GHz, –159.3dBm/Hz Noise Floor, 50Ω, 0.5V Baseband
DC
Interface, 4-Channel W-CDMA ACPR = –66dBc at 2.14GHz
400MHz to 3.8GHz, 3.3V High Signal Level
Downconverting Mixer
IIP3 = 23.7dBm at 2600MHz, 23.5dBm at 3600MHz, I = 82A at 3.3V
CC
LT5560
LT5568
Ultra-Low Power Active Mixer
10mA Supply Current, 10dBm IIP3, 10dB NF, Usable as Up- or Down-Converter.
700MHz to 1050MHz High Linearity Direct Quadrature 22.9dBm OIP3 at 850MHz, –160.3dBm/Hz Noise Floor, 50Ω, 0.5V Baseband
DC
Modulator
Interface, 3-Ch CDMA2000 ACPR = –71.4dBc at 850MHz
LT5572
LT5575
LT5579
1.5GHz to 2.5GHz High Linearity Direct Quadrature
Modulator
21.6dBm OIP3 at 2GHz, –158.6dBm/Hz Noise Floor, High-Ohmic 0.5V
Baseband Interface, 4-Ch W-CDMA ACPR = –67.7dBc at 2.14GHz
DC
800MHz to 2.7GHz High Linearity Direct Conversion
I/Q Demodulator
50Ω, Single-Ended RF and LO Inputs. 28dBm IIP3 at 900MHz, 13.2dBm P1dB,
0.04dB I/Q Gain Mismatch, 0.4° I/Q Phase Mismatch
1.5GHz to 3.8GHz High Linearity Upconverting Mixer
27.3dBm OIP3 at 2.14GHz, 9.9dB Noise Floor, 2.6dB Conversion Gain, –35dBm
LO Leakage
RF Power Detectors
LTC®5505
LTC5507
LTC5508
LTC5509
LTC5530
LTC5531
LTC5532
LT5534
RF Power Detectors with >40dB Dynamic Range
300MHz to 3GHz, Temperature Compensated, 2.7V to 6V Supply
100kHz to 1GHz, Temperature Compensated, 2.7 to 6V Supply
44dB Dynamic Range, Temperature Compensated, SC70 Package
36dB Dynamic Range, Low Power Consumption, SC70 Package
100kHz to 1000MHz RF Power Detector
300MHz to 7GHz RF Power Detector
300MHz to 3GHz RF Power Detector
300MHz to 7GHz Precision RF Power Detector
300MHz to 7GHz Precision RF Power Detector
300MHz to 7GHz Precision RF Power Detector
Precision V
Precision V
Precision V
Offset Control, Shutdown, Adjustable Gain
Offset Control, Shutdown, Adjustable Offset
Offset Control, Adjustable Gain and Offset
OUT
OUT
OUT
50MHz to 3GHz Log RF Power Detector with 60dB
Dynamic Range
1dB Output Variation over Temperature, 38ns Response Time, Log Linear
Response
LTC5536
Precision 600Mhz to 7GHz RF Power Detector with
Fast Comparator Output
25ns Response Time, Comparator Reference Input, Latch Enable Input, –26dBm
to 12dBm Input Range
LT5537
LT5538
LT5570
Wide Dynamic Range Log RF/IF Detector
3.8GHz Wide Dynamic Range Log Detector
2.7GHz RMS Power Detector
Low Frequency to 1GHz, 83dB Log Linear Dynamic Range
75dB Dynamic Range, 1dB Output Variation Over Temperature
Fast Responding, up to 60dB Dynamic Range, 0.3dB Accuracy Over
Temperature
5554f
LT 0708 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LT5557EUF#PBF
LT5557 - 400MHz to 3.8GHz 3.3V Active Downconverting Mixer; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LT5557EUF#TR
IC SPECIALTY TELECOM CIRCUIT, PQCC16, 4 X 4 MM, PLASTIC, MO-220, QFN-20, Telecom IC:Other
Linear
LT5557EUF#TRPBF
LT5557 - 400MHz to 3.8GHz 3.3V Active Downconverting Mixer; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LT5558EUF#PBF
LT5558 - 600MHz to 1100MHz High Linearity Direct Quadrature Modulator; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LT5558EUF#TR
LT5558 - 600MHz to 1100MHz High Linearity Direct Quadrature Modulator; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LT5558EUF#TRBPF
IC TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PQCC16, 4 X 4 MM, LEAD FREE, PLASTIC, MO-220WGGC, QFN-16, Cellular Telephone Circuit
Linear
LT5558EUF#TRPBF
LT5558 - 600MHz to 1100MHz High Linearity Direct Quadrature Modulator; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明