LTC2308CUFXTRPBF [Linear]
Low Noise, 500ksps, 8-Channel, 12-Bit ADC; 低噪声， 500KSPS ， 8通道， 12位ADC
| 型号： | LTC2308CUFXTRPBF |
| 厂家： | 
Linear |
| 描述： | Low Noise, 500ksps, 8-Channel, 12-Bit ADC |
| 文件： | 总20页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2308
Low Noise, 500ksps,
8-Channel, 12-Bit ADC
FEATURES
DESCRIPTION
The LTC®2308 is a low noise, 500ksps, 8-channel, 12-bit
ADC with an SPI/MICROWIRE compatible serial interface.
This ADC includes an internal reference and a fully differ-
ential sample-and-hold circuit to reduce common-mode
noise. The internal conversion clock allows the external
serial output data clock (SCK) to operate at any frequency
up to 40MHz.
■
12-Bit Resolution
■
500ksps Sampling Rate
■
Low Noise: SINAD = 73.3dB
■
Guaranteed No Missing Codes
■
Single 5V Supply
■
Auto-Shutdown Scales Supply Current with Sample
Rate
■
Low Power: 17.5mW at 500ksps
The LTC2308 operates from a single 5V supply and draws
just3.5mAatasamplerateof500ksps.Theauto-shutdown
feature reduces the supply current to 200μA at a sample
rate of 1ksps.
0.9mW Nap Mode
35μW Sleep Mode
■
Internal Reference
■
Internal 8-Channel Multiplexer
■
The LTC2308 is packaged in a small 24-pin 4mm × 4mm
QFN.Theinternal2.5Vreferenceand8-channelmultiplexer
further reduce PCB board space requirements.
Internal Conversion Clock
SPI/MICROWIRETM Compatible Serial Interface
■
■
Unipolar or Bipolar Input Ranges (Software Selectable)
■
Separate Output Supply OV (2.7V to 5.25V)
DD
The low power consumption and small size make the
LTC2308 ideal for battery operated and portable appli-
cations, while the 4-wire SPI compatible serial interface
makes this ADC a good match for isolated or remote data
acquisition systems.
■
24-Pin 4mm × 4mm QFN Package
APPLICATIONS
■
High Speed Data Acquisition
■
Industrial Process Control
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■
Motor Control
■
Accelerometer Measurements
■
Battery Operated Instruments
■
Isolated and/or Remote Data Acquisition
TYPICAL APPLICATION
5V
8192 Point FFT, f = 1kHz
IN
0
–10
–20
–30
–40
–50
–60
–70
–80
0.1μF
10μF
10μF
0.1μF
f
= 500kHz
SMPL
SINAD = 73.6dB
THD = –89.5dB
OV
2.7V TO 5.25 V
AV
DV
DD
DD
DD
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
0.1μF
LTC2308
SDI
ANALOG
INPUT
MUX
12-BIT
500ksps
ADC
+
–
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTER
SDO
SERIAL
PORT
CH0-CH7
ANALOG INPUTS
0V TO 4.096V UNIPOLAR
p2.048V BIPOLAR
–90
SCK
–100
–110
–120
–130
–140
CONVST
V
REF
INTERNAL
2.5V REF
2.2μF
0
50
100
150
200
250
FREQUENCY (kHz)
2308 G03
REFCOMP
10μF
GND
0.1μF
2308 TA01
2308f
1
LTC2308
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
TOP VIEW
Supply Voltage (AV , DV , OV )...........................6V
DD
DD
DD
Analog Input Voltage (Note 3)
CH0 - CH7, COM, REF,
24 23 22 21 20 19
REFCOMP....................(GND –0.3V) to (AV + 0.3V)
DD
CH3
CH4
CH5
CH6
CH7
COM
1
2
3
4
5
6
18 GND
Digital Input Voltage
SD0
SCK
17
16
(Note 3) ...................... (GND –0.3V) to (DV + 0.3V)
DD
25
Digital Output Voltage ..... (GND –0.3V) to (OV + 0.3V)
15 SDI
DD
14
CONVST
Power Dissipation...............................................500mW
13 AV
DD
Operating Temperature Range
7
8
9 10 11 12
LTC2308C ................................................ 0°C to 70°C
LTC2308I ............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
= 150°C, θ = 37°C/W
T
JMAX
JA
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
24-Lead (4mm × 4mm) Plastic QFN
24-Lead (4mm × 4mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
LTC2308CUF#PBF
LTC2308IUF#PBF
LTC2308CUF#TRPBF
LTC2308IUF#TRPBF
2308
2308
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER AND MULTIPLEXER CHARACTERISTICS The
●
denotes the specifications
which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Notes 4, 5)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
●
●
●
●
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Bipolar Zero Error
12
(Note 6)
0.3
0.25
1
1
1
6
LSB
LSB
(Note 7)
LSB
Bipolar Zero Error Drift
Bipolar Zero Error Match
Unipolar Zero Error
0.002
0.3
LSB/°C
LSB
●
●
3
3
(Note 7)
0.5
LSB
Unipolar Zero Error Drift
Unipolar Zero Error Match
0.002
0.3
LSB/°C
LSB
●
2
2308f
2
LTC2308
CONVERTER AND MULTIPLEXER CHARACTERISTICS The
●
denotes the specifications
which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Notes 4, 5)
A
PARAMETER
CONDITIONS
MIN
TYP
1
MAX
UNITS
LSB
●
Bipolar Full-Scale Error
External Reference (Note 8)
External Reference
9
Bipolar Full-Scale Error Drift
Bipolar Full-Scale Error Match
Unipolar Full-Scale Error
Unipolar Full-Scale Error Drift
Unipolar Full-Scale Error Match
0.05
0.5
1.5
0.05
0.4
LSB/°C
LSB
●
●
3
8
External Reference (Note 8)
External Reference
LSB
LSB/°C
LSB
●
3
ANALOG INPUT The
●
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
AV
UNITS
+
●
V
Absolute Input Range (CH0 to CH7)
(Note 9)
–0.05
V
IN
IN
DD
–
+
●
●
V
Absolute Input Range (CH0 to CH7,
COM)
Unipolar (Note 9)
Bipolar (Note 9)
–0.05
–0.05
AV /2
V
V
DD
AV
DD
–
+
+
–
–
●
●
V
– V
Input Differential Voltage Range
V
IN
V
IN
= V – V (Unipolar)
0 to REFCOMP
REFCOMP/2
V
V
IN
IN
IN
IN
IN
= V – V (Bipolar)
IN
●
I
Analog Input Leakage Current
Analog Input Capacitance
1
μA
IN
C
Sample Mode
Hold Mode
55
5
pF
pF
IN
CMRR
Input Common Mode Rejection Ratio
70
dB
DYNAMIC ACCURACY The
●
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T = 25°C and A = –1dBFS. (Notes 4, 10)
A
IN
SYMBOL
SINAD
SNR
PARAMETER
CONDITIONS
MIN
71
TYP
73.3
73.4
–90
–90
–109
700
25
MAX
UNITS
dB
●
●
●
●
Signal-to-(Noise + Distortion) Ratio
Signal-to-Noise Ratio
f
IN
f
IN
f
IN
f
IN
f
IN
= 1kHz
= 1kHz
71
dB
THD
Total Harmonic Distortion
Spurious Free Dynamic Range
Channel-to-Channel Isolation
Full Linear Bandwidth
= 1kHz, First 5 Harmonics
–78
–80
dB
SFDR
= 1kHz
= 1kHz
dB
dB
(Note 11)
kHz
MHz
ns
–3dB Input Linear Bandwidth
Aperture Delay
13
Transient Reponse
Full-Scale Step
240
ns
2308f
3
LTC2308
INTERNAL REFERENCE CHARACTERISTICS The
●
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
PARAMETER
CONDITIONS
MIN
TYP
2.50
25
MAX
UNITS
V
●
V
V
V
V
V
Output Voltage
Output Tempco
Output Impedance
I
= 0
= 0
2.47
2.53
REF
OUT
OUT
I
ppm/°C
kΩ
REF
–0.1mA ≤ I
≤ 0.1mA
8
REF
OUT
Output Voltage
I
= 0
4.096
0.8
V
REFCOMP
OUT
Line Regulation
AV = 4.75V to 5.25V
DD
mV/V
REF
DIGITAL INPUTS AND DIGITAL OUTPUTS The
●
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
DV = 5.25V
MIN
TYP
MAX
UNITS
V
●
●
●
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Digital Input Capacitance
High Level Output Voltage
2.4
IH
IL
DD
V
DV = 4.75V
DD
0.8
10
V
I
IN
V
IN
= V
DD
μA
pF
C
V
5
IN
OV = 4.75V, I
= –10μA
= –200μA
4.74
V
V
OH
DD
OUT
OUT
●
OV = 4.75V, I
4
DD
V
Low Level Input Voltage
OV = 4.75V, I
DD
= 160μA
= 1.6mA
0.05
V
V
OL
DD
OUT
OUT
●
●
OV = 4.75V, I
0.4
10
I
OZ
Hi-Z Output Leakage
Hi-Z Output Capacitance
Output Source Current
Output Sink Current
V
OUT
= 0V to OV , CONVST High
μA
pF
DD
C
CONVST High
15
–10
10
OZ
I
I
V
OUT
V
OUT
= 0V
= OV
mA
mA
SOURCE
SINK
DD
POWER REQUIREMENTS The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
AV
PARAMETER
CONDITIONS
MIN
4.75
4.75
2.7
TYP
5
MAX
5.25
5.25
5.25
UNITS
Analog Supply Voltage
Digital Supply Voltage
Output Driver Supply Voltage
V
V
V
DD
DV
OV
5
DD
DD
●
●
●
I
DD
Supply Current
Nap Mode
Sleep Mode
C = 25pF
3.5
180
7
4.2
400
20
mA
μA
μA
L
CONVST = 5V, Conversion Done
CONVST = 5V, Conversion Done
P
Power Dissipation
Nap Mode
Sleep Mode
17.5
0.9
35
mW
mW
μW
D
2308f
4
LTC2308
TIMING CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
500
40
UNITS
kHz
MHz
ns
●
●
●
●
●
●
●
●
●
●
●
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Shift Clock Frequency
CONVST High Time
SMPL(MAX)
SCK
(Note 9)
20
2.5
0
WHCONV
HD
Hold Time SDI After SCK↑
Setup Time SDI Valid Before SCK↑
SCK High Time
ns
ns
SUDI
f
f
= f
= f
10
10
410
20
ns
WHCLK
WLCLK
WLCONVST
HCONVST
CONV
ACQ
SCK
SCK
SCK(MAX)
SCK(MAX)
SCK Low Time
ns
CONVST Low Time During Data Transfer
Hold Time CONVST Low After Last SCK↓
Conversion Time
(Note 9)
(Note 9)
ns
ns
1.3
1.6
μs
Acquisition Time
240
4
ns
7th SCK↑ to CONVST↑ (Note 9)
REFCOMP Wakeup Time (Note 12)
SDO Data Valid After SCK↓
SDO Hold Time After SCK↓
SDO Valid After CONVST↓
Bus Relinquish Time
C
= 10μF, C = 2.2μF
200
ms
ns
REFWAKE
dDO
REFCOMP
REF
●
●
●
●
C = 25pF (Note 9)
L
10.8
12.5
C = 25pF
L
ns
hDO
C = 25pF
L
11
11
4
15
15
ns
en
C = 25pF
L
ns
dis
SDO Rise Time
C = 25pF
L
ns
r
SDO Fall Time
C = 25pF
L
4
ns
f
Total Cycle Time
2
μs
CYC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 and 1111 1111
1111. Unipolar zero error is the offset voltage measured from +0.5LSB
when the output code flickers between 0000 0000 0000 and
0000 0000 0001.
Note 2: All voltage values are with respect to ground with AV , DV and
DD
DD
OV wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above V
they will be clamped by internal diodes. These products can handle input
currents greater than 100mA below ground or above V without latchup.
Note 8: Full-scale bipolar error is the worst-case of –FS or +FS untrimmed
deviation from ideal first and last code transitions and includes the effect
of offset error. Unipolar full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
DD
,
DD
DD
Note 9: Guaranteed by design, not subject to test.
Note 4: AV = 5V, DV = 5V, OV = 5V, f = 500kHz, internal
DD
DD
DD
SMPL
reference unless otherwise specified.
Note 5: Linearity, offset and full-scale specifications apply for a single-
Note 10: All specifications in dB are referred to a full-scale 2.048V input
with a 2.5V reference voltage.
ended analog input with respect to COM.
Note 11: Full linear bandwidth is defined as the full-scale input frequency
at which the SINAD degrades to 60dB or 10 bits of accuracy.
Note 12: REFCOMP wakeup time is the time required for the REFCOMP pin
to settle within 0.5LSB at 12-bit resolution of its final value after waking up
from SLEEP mode.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
2308f
5
LTC2308
T = 25°C, AV = DV = OV = 5V,
TYPICAL PERFORMANCE CHARACTERISTICS
A
DD
DD
DD
f
= 500ksps, Internal Reference, unless otherwise noted.
SMPL
Integral Nonlinearity vs
Output Code
Differential Nonlinearity vs
Output Code
1kHz Sine Wave
8192 Point FFt Plot
1.00
0
–10
–20
–30
–40
–50
–60
–70
1.00
0.75
0.50
0.25
0
SNR = 73.7dB
SINAD = 73.6dB
THD = –89.5dB
0.75
0.50
0.25
0
–80
–90
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
–100
–110
–120
–130
–140
2048
0
1024
3072
4096
2048
0
50
100
150
200
250
0
1024
3072
4096
OUTPUT CODE
FREQUENCY (kHz)
OUTPUT CODE
2308 G01
2308 G03
2308 G02
Crosstalk vs Frequency for
an Adjacent Pair
SNR vs Input Frequency
SINAD vs Input Frequency
–60
–70
80
75
70
65
60
55
50
80
75
70
65
60
55
50
–80
–90
–100
–110
–120
–130
–140
0.1
1
10
100
1000
1
10
100
1000
1
10
100
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
3208 G04
3208 G05
3208 G06
Supply Current vs
Sampling Frequency
THD vs Input Frequency
Supply Current vs Temperature
5
4
3
2
1
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–60
–65
–70
–75
–80
–85
–90
–95
–100
1
10
100
1000
50
TEMPERATURE (oC)
125
–50 –25
0
25
75 100
1
10
100
1000
SAMPLING FREQUENCY (ksps)
FREQUENCY (kHz)
3208 G08
3208 G07
3208 G09
2308f
6
LTC2308
T = 25°C, AV = DV = OV = 5V,
TYPICAL PERFORMANCE CHARACTERISTICS
A
DD
DD
DD
f
= 500ksps, Internal Reference, unless otherwise noted.
SMPL
Analog Input Leakage Current vs
Temperature
Sleep Current vs Temperature
10
1000
800
600
400
200
0
f
= 0ksps
SMPL
8
6
4
2
0
CH (ON)
CH (OFF)
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (oC)
TEMPERATURE (oC)
3208 G10
3208 G11
Offset vs Temperature
Full-Scale Error vs Temperature
1.5
1.0
0.5
0
4
2
BIPOLAR
BIPOLAR
0
UNIPOLAR
UNIPOLAR
–2
–4
–6
EXTERNAL REFERENCE
50 75 100 125
TEMPERATURE (°C)
EXTERNAL REFERENCE
–50 –25
0
25
TEMPERATURE (oC)
50
75 100
125
–50 –25
0
25
2308 G12
2308 G13
2308f
7
LTC2308
PIN FUNCTIONS
CH3-CH7 (Pins 1, 2, 3, 4, 5): Channel 3 to Channel 7
Analog Inputs. CH3 – CH7 can be configured as single-
ended or differential input channels. See the Analog Input
Multiplexer section.
SDI (Pin 15): Serial Data Input. The SDI serial bit stream
configures the ADC and is latched on the rising edge of
the first 6 SCK pulses.
SCK (Pin 16): Serial Data Clock. SCK synchronizes the
serial data transfer. The serial data input at SDI is latched
on the rising edge of SCK. The serial data output at SDO
transitions on the falling edge of SCK.
COM (Pin 6): Common Input. This is the reference point
for all single-ended inputs. It must be free of noise and
connectedtogroundforunipolarconversionsandmidway
between GND and REFCOMP for bipolar conversions.
SDO (Pin 17): Serial Data Out. SDO outputs the data from
the previous conversion. SDO is shifted out serially on the
falling edge of each SCK pulse.
V
REF
(Pin 7): 2.5V Reference Output. Bypass to GND with
a minimum 2.2μF tantalum capacitor or low ESR ceramic
capacitor. The internal reference may be over driven by an
external 2.5V reference at this pin.
OV (Pin 19): Output Driver Supply. Bypass OV to
DD
DD
GND with a 0.1μF ceramic capacitor close to the pin. The
REFCOMP (Pin 8): Reference Buffer Output. Bypass to
GND with a 10μF tantalum and 0.1μF ceramic capacitor
in parallel. Nominal output voltage is 4.096V.
range of OV is 2.7V to 5.25V.
DD
DV (Pin 21): 5V Digital Supply. The range of DV is
DD
DD
4.75Vto5.25V. BypassDV toGNDwitha0.1μFceramic
DD
GND (Pins 9, 10, 11, 18, 20): Ground. All GND pins must
be connected to a solid ground plane.
and a 10μF tantalum capacitor in parallel.
CH0-CH2 (Pins 22, 23, 24): Channel 0 to Channel 2
Analog Inputs. CH0 – CH2 can be configured as single-
ended or differential input channels. See the Analog Input
Multiplexer section.
AV (Pins12,13):5VAnalogSupply.TherangeofAV is
DD
DD
4.75V to 5.25V. Bypass AV to GND with a 0.1μF ceramic
DD
and a 10μF tantalum capacitor in parallel.
CONVST (Pin 14): Conversion Start. A rising edge at
CONVSTbeginsaconversion.Forbestperformance,ensure
that CONVST returns low within 40ns after the conversion
starts or after the conversion ends.
GND (Pin 25): Exposed Pad Ground. Must be soldered
directly to ground plane.
2308f
8
LTC2308
BLOCK DIAGRAM
AV
DD
DV
DD
OV
DD
LTC2308
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SDI
ANALOG
INPUT
MUX
12-BIT
500ksps
ADC
+
–
SDO
SERIAL
PORT
SCK
CONVST
V
REF
8k
INTERNAL
2.5V REF
GAIN = 1.6384x
REFCOMP
2308 BD
GND
TEST CIRCUIT
Load Circuit for t WAVEFORM 1
Load Circuit for t WAVEFORM 2, t
dis en
dis
V
DD
3k
SDO
TEST POINT
SDO
TEST POINT
C
3k
L
C
L
2308 TC02
2308 TC01
2308f
9
LTC2308
TIMING DIAGRAM
Voltage Waveforms for SDO Delay Times, t
and t
t
WLCLK
WHCLK
(SCK Low Time)
(SCK High Time)
dDO
hDO
t
t
(Hold Time SDI After SCK↑)
(Setup Time SDI Stable Before SCK↑)
HD
SCK
t
SUDI
V
IL
t
dDO
t
t
WHCLK
WLCLK
t
hDO
V
V
OH
OL
SCK
SDO
t
HD
2308 TD01
SDI
2308 TD03
t
SUDI
Voltage Waveforms for t
dis
Voltage Waveforms for t
en
V
CONVST
IH
CONVST
SDO
SDO
WAVEFORM 1
(SEE NOTE 1)
90%
2308 TD04
t
dis
SDO
WAVEFORM 2
(SEE NOTE 2)
t
en
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
Voltage Waveforms for SDO Rise and Fall Times t , t
r
f
2308 TD02
V
OH
SDO
V
OL
t
t
f
2308 TD05
r
2308f
10
LTC2308
APPLICATIONS INFORMATION
Overview
bit (LSB). The sampled input is successively compared
with binary weighted charges supplied by the capacitive
DACusingadifferentialcomparator.Attheendofaconver-
sion, the DAC output balances the analog input. The SAR
contents (a 12-bit data word) that represent the sampled
analog input are loaded into 12 output latches that allow
the data to be shifted out.
The LTC2308 is a low noise, 500ksps, 8-channel, 12-bit
successive approximation register (SAR) A/D converter.
The LTC2308 includes a precision internal reference, a
configurable 8-channel analog input multiplexer (MUX)
and an SPI-compatible serial port for easy data transfers.
The ADC may be configured to accept single-ended or
differential signals and can operate in either unipolar or
bipolar mode. A sleep mode option is also provided to
save power during inactive periods.
Programming the LTC2308
The various modes of operation of the LTC2308 are
programmed by a 6-bit D word. The SDI data bits are
IN
Conversions are initiated by a rising edge on the CONVST
input. Once a conversion cycle has begun, it cannot be
loaded on the rising edge of SCK, with the S/D bit loaded
on the first rising edge and the SLP bit on the sixth rising
edge (see Figure 8 in the Timing and Control section). The
input data word is defined as follows:
restarted. Between conversions, a 6-bit input word (D )
IN
at the SDI input configures the MUX and programs vari-
ous modes of operation. As the D bits are shifted in,
IN
data from the previous conversion is shifted out on SDO.
S/D
O/S
S1
S0
UNI
SLP
After the 6 bits of the D word have been shifted in, the
IN
ADC begins acquiring the analog input in preparation for
the next conversion as the rest of the data is shifted out.
The acquire phase requires a minimum time of 240ns
for the sample-and-hold capacitors to acquire the analog
input signal.
S/D = SINGLE-ENDED/DIFFERENTIAL BIT
O/S = ODD/SIGN BIT
S1 = ADDRESS SELECT BIT 1
S0 = ADDRESS SELECT BIT 0
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
During the conversion, the internal 12-bit capacitive
charge-redistribution DAC output is sequenced through a
successive approximation algorithm by the SAR starting
from the most significant bit (MSB) to the least significant
2308f
11
LTC2308
APPLICATIONS INFORMATION
Analog Input Multiplexer
4 Differential
8 Single-Ended
CH0
CH1
+ (
)
)
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
+
+
+
+
+
+
+
+
–
The analog input MUX is programmed by the S/D, O/S,
{
{
{
{
(
+
–
S1 and S0 bits of the D word. Table 1 lists the MUX
IN
+ (
)
)
CH2
CH3
–
configurations for all combinations of the configuration
bits.Figure1ashowsseveralpossibleMUXconfigurations
and Figure 1b shows how the MUX can be reconfigured
from one conversion to the next.
(
+
–
+ (
)
)
CH4
CH5
–
(
+
–
CH6
CH7
+ (
)
)
–
(
+
COM (
)
–
–
Driving the Analog Inputs
Combinations of Differential
and Single-Ended
The analog inputs of the LTC2308 are easy to drive. Each
of the analog inputs can be used as a single-ended input
relative to the COM pin (CH0-COM, CH1-COM, etc.) or in
differential input pairs (CH0 and CH1, CH2 and CH3, CH4
andCH5,CH6andCH7).Figure2showshowtodriveCOM
for single-ended inputs in unipolar and bipolar modes.
Regardless of the MUX configuration, the “+” and “–“
inputs are sampled at the same instant. Any unwanted
signal that is common to both inputs will be reduced by
thecommonmoderejectionofthesample-and-holdcircuit.
The inputs draw only one small current spike while charg-
ing the sample-and-hold capacitors during the acquire
mode. In conversion mode, the analog inputs draw only
a small leakage current. If the source impedance of the
CH0
+
{
CH1
–
CH2
CH3
–
{
+
+
+
+
+
CH4
CH5
CH6
CH7
COM (
)
–
2308 F01a
Figure 1a. Example MUX Configurations
1st Conversion
2nd Conversion
+
CH2
CH3
–
+
CH2
CH3
{
{
{
{
–
Table 1. Channel Configuration
+
–
CH4
CH5
+
+
CH4
CH5
S/D O/S S1 S0
0
1
2
3
4
5
6
+
–
+
7
–
+
COM
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
+
–
COM
(UNUSED)
COM (
)
–
+
–
2308 F01b
+
–
Figure 1b. Changing the MUX Assignment “On the Fly”
–
+
+
Unipolar Mode
Bipolar Mode
–
+
+
–
+
+
–
–
–
–
–
–
–
–
COM
COM
+
REFCOMP/2
–
2308 F02
+
Figure 2. Driving COM in UNIPOLAR and BIPOLAR Modes
+
+
+
2308f
12
LTC2308
APPLICATIONS INFORMATION
drivingcircuitislow, theADCinputscanbedrivendirectly.
Otherwise, more acquisition time should be allowed for a
source with higher impedance.
equivalent resistance (R = 1/(f
• C )) in series with
SMPL IN
EQ
an ideal voltage source (V
/2) as shown in Figure
REFCOMP
3b. ThemagnitudeoftheDCcurrentisthenapproximately
= (V - V /2)/R , which is roughly propor-
I
DC
IN
IN
REFCOMP
EQ
Input Filtering
tional to V . To prevent large DC drops across the resistor
FILTER
R
, a filter with a small resistor and large capacitor
The noise and distortion of the input amplifier and other
circuitry must be considered since they will add to the
ADC noise and distortion. Therefore, noisy input circuitry
should be filtered prior to the analog inputs to minimize
noise. A simple 1-pole RC filter is sufficient for many
applications.
should be chosen. When running at the minimum cycle
time of 2μs, the input current equals 106μA at V = 5V,
IN
whichamountstoafull-scaleerrorof0.5LSBswhenusing
a filter resistor (R
) of 4.7Ω. Applications requiring
FILTER
lower sample rates can tolerate a larger filter resistor for
the same amount of full-scale error.
The analog inputs of the LTC2308 can be modeled as
Figures 4a and 4b show respective examples of input
filtering for single-ended and differential inputs. For the
single-ended case in Figure 4a, a 50Ω source resistor
and a 2000pF capacitor to ground on the input will limit
the input bandwidth to 1.6MHz. High quality capacitors
and resistors should be used in the RC filter since these
components can add distortion. NPO and silver mica type
dielectriccapacitorshaveexcellentlinearity.Carbonsurface
mount resistors can generate distortion from self heating
and from damage that may occur during soldering. Metal
film surface mount resistors are much less susceptible
to both problems.
a 55pF capacitor (C ) in series with a 100Ω resistor
IN
(R ) as shown in Figure 3a. C gets switched to the
ON
IN
selected input once during each conversion. Large filter
RC time constants will slow the settling of the inputs. It
is important that the overall RC time constants be short
enough to allow the analog inputs to completely settle to
12-bit resolution within the acquisition time (t ) if DC
ACQ
accuracy is important.
When using a filter with a large C
value (e.g. 1μF),
FILTER
theinputsdonotcompletelysettleandthecapacitiveinput
switching currents are averaged into a net DC current
(I ). In this case, the analog input can be modeled by an
DC
50Ω
ANALOG
INPUT
CH0
LTC2308
INPUT
CH0-CH7
2000pF
COM
LTC2308
R
R
= 100Ω
ON
SOURCE
V
IN
C
C
= 55pF
IN
1
REFCOMP
10μF
0.1μF
2308 F04a
2308 F03a
Figure 3a. Analog Input Equivalent Circuit
Figure 4a. Optional RC Input Filtering for Single-Ended Input
1000pF
50Ω
CH0
INPUT
I
DIFFERENTIAL
LTC2308
DC
CH0-CH7
FILTER
R
ANALOG
INPUTS
1000pF
LTC2308
• C
V
IN
50Ω
CH1
R
EQ
= 1/(f
)
IN
SMPL
C
FILTER
1000pF
+
V
/2
REFCOMP
–
REFCOMP
10μF
0.1μF
2308 F04b
2308 F03b
Figure 3b. Analog Input Equivalent Circuit
for Large Filter Capacitances
Figure 4b. Optional RC Input Filtering for Differential Inputs
2308f
13
LTC2308
APPLICATIONS INFORMATION
Dynamic Performance
where V is the RMS amplitude of the fundamental fre-
1
quencyandV throughV aretheamplitudesofthesecond
2
N
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental.
through Nth harmonics.
Internal Reference
The LTC2308 has an on-chip, temperature compensated
bandgap reference that is factory trimmed to 2.5V (Refer
to Figure 6a). It is internally connected to a reference
Signal-to-Noise and Distortion Ratio (SINAD)
amplifier and is available at V
(Pin 7). V
should
REF
REF
be bypassed to GND with a 2.2μF tantalum capacitor for
stability and to minimize noise. An 8k resistor is in series
with the output so that it can be easily overdriven by an
external reference if more accuracy and/or lower drift are
required as shown in Figure 6b. The reference amplifier
The signal-to-noise and distortion ratio (SINAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure 5 shows a typical SINAD of 73.3dB with
a500kHzsamplingrateanda1kHzinput. ASNRof73.4dB
can be achieved with the LTC2308.
gains the V
voltage by 1.638 to 4.096V at REFCOMP
REF
(Pin 8). To compensate the reference amplifier, bypass
REFCOMP with a 10μF ceramic or tantalum capacitor
in parallel with a 0.1μF ceramic capacitor for best noise
performance.
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
Internal Conversion Clock
The internal conversion clock is factory trimmed to
achieve a typical conversion time (t
maximum conversion time of 1.6μs over the full operat-
ing temperature range. With a typical acquisition time of
240ns, a throughput sampling rate of 500ksps is tested
and guaranteed.
) of 1.3μs and a
CONV
band between DC and half the sampling frequency(f
/2). THD is expressed as:
SMPL
V 2 + V 2 + V42...+ V 2
2
3
N
THD= 20log
V
1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
0
50
100
150
200
250
FREQUENCY (kHz)
2308 F05
Figure 5. 1kHz Sine Wave 8192 Point FFT Plot
2308f
14
LTC2308
APPLICATIONS INFORMATION
Digital Interface
after the t
period, the LTC2308 enters NAP or SLEEP
CONV
mode, depending on the setting of SLP bit from the D
IN
The LTC2308 communicates via a standard 4-wire SPI
compatible digital interface. The rising edge of CONVST
initiatesaconversion. Aftertheconversionisfinished, pull
CONVST low to enable the serial output (SDO). The ADC
shifts out the digital data in 2’s complement format when
operatinginbipolarmodeorinstraightbinaryformatwhen
in unipolar mode, based on the setting of the UNI bit.
word that was shifted in after the previous conversion.
(see Nap Mode and Sleep Mode for more detail).
When CONVST returns low, the ADC wakes up and the
most significant bit (MSB) of the output data sequence
at SDO becomes valid after the serial data bus is enabled.
All other data bits from SDO transition on the falling edge
of each SCK pulse. Configuration data (D ) is loaded into
IN
For best performance, ensure that CONVST returns low
within40nsaftertheconversionstarts(i.e.,beforethefirst
bit decision) or after the conversion ends. If CONVST is
low when the conversion ends, the MSB bit will appear at
SDO at the end of the conversion and the ADC will remain
powered up.
the LTC2308 at SDI, starting with the first SCK rising edge
after CONVST returns low. The S/D bit is loaded on the
first SCK rising edge.
Example 2 (Figure 9) shows CONVST returning low be-
fore the conversion ends. In this mode, the ADC and all
internal circuitry remain powered up. When the conver-
sion is complete, the MSB of the output data sequence at
SDO becomes valid after the data bus is enabled. At this
Timing and Control
The start of a conversion is triggered by a rising edge at
CONVST. Once initiated, a new conversion cannot be re-
started until the current conversion is complete. Figures 8
and9showthetimingdiagramsfortwodifferentexamples
of CONVST pulses. Example 1 (Figure 8) shows CONVST
staying HIGH after the conversion ends. If CONVST is high
point(t
1.3μs after the rising edge of CONVST), puls-
CONV
ing SCK will shift data out at SDO and load configuration
data (D ) into the LTC2308 at SDI. The first SCK rising
IN
edge loads the S/D bit into the LTC2308. SDO transitions
on the falling edge of each SCK pulse.
R1
8k
V
REF
5V
BANDGAP
REFERENCE
2.5V
2.2μF
0.1MF
V
IN
LT1790A-2.5
V
REFCOMP
4.096V
10μF
REFERENCE
AMP
V
OUT
REF
LTC2308
2.2μF
0.1μF
R2
REFCOMP
GND
0.1μF
+
10μF
R3
GND
LTC2308
2308 F06b
2308 F06a
Figure 6a. LTC2308 Reference Circuit
Figure 6b. Using the LT1790A-2.5 as an External Reference
2308f
15
LTC2308
APPLICATIONS INFORMATION
Figures 8 and 9 are the transfer characteristics for the
bipolar and unipolar modes. Data is output at SDO in 2’s
complement format for bipolar readings and in straight
binary for unipolar readings.
Board Layout and Bypassing
Toobtainthebestperformance,aprintedcircuitboardwith
a solid ground plane is required. Layout for the printed
circuit board should ensure digital and analog signal lines
are separated as much as possible. Care should be taken
not to run any digital signal alongside an analog signal. All
Nap Mode
The ADC enters nap mode when CONVST is held high
analoginputsshouldbeshieldedbyGND. V , REFCOMP
REF
after the conversion is complete (t ) if the SLP bit is
CONV
and AV should be bypassed to the ground plane as
DD
set to a logic 0. The supply current decreases to 180μA
in nap mode between conversions, thereby reducing the
average power dissipation as the sample rate decreases.
For example, the LTC2308 draws an average of 200μA
with a 1ksps sampling rate. The LTC2308 keeps only the
close to the pin as possible. Maintaining a low impedance
path for the common return of these bypass capacitors
is essential to the low noise operation of the ADC. These
traces should be as wide as possible. See Figure 7 for a
suggested layout.
reference(V )andreferencebuffer(REFCOMP)circuitry
REF
DV , BYPASS
DD
10μF, 0603
active when in nap mode.
Sleep Mode
0V , BYPASS
DD
10μF, 0603
The ADC enters sleep mode when CONVST is held high
after the conversion is complete (t
) if the SLP bit is
CONV
set to a logic 1. The ADC draws only 7μA in sleep mode,
providedthatnoneofthedigitalinputsareswitching.When
CONVST returns low, the LTC2308 is released from the
SLEEP mode and requires 200ms to wake up and charge
the respective 2.2μF and 10μF bypass capacitors on the
V
and REFCOMP pins.
REF
AV , BYPASS
DD
10μF || 0.1μF, 0603
V
, BYPASS
REF
2.2μF, 1206
REFCOMP, BYPASS
10μF || 0.1μF, 0603
NOTE: SECOND LAYER OF BOARD IS A SOLID GROUND PLANE.
Figure 7. Suggested Layout
2308f
16
LTC2308
APPLICATIONS INFORMATION
t
WLCONVST
t
ACQ
CONVST
NAP OR
SLEEP
t
CONV
t
CYC
1
2
3
4
5
6
7
8
9
10 11 12
SCK
SDI
S/D O/S S1 S0 UNI SLP
MSB
LSB
Hi-Z
Hi-Z
SDO
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
2308 F08
Figure 8. LTC2308 Timing with a Long CONVST Pulse
t
t
HCONVST
WHCONV
t
ACQ
CONVST
t
CYC
t
CONV
1
2
3
4
5
6
7
8
9
10 11 12
SCK
SDI
S/D O/S S1 S0 UNI SLP
MSB
LSB
B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Hi-Z
Hi-Z
SDO
B11
2308 F09
Figure 9. LTC2308 Timing with a Short CONVST Pulse
2308f
17
LTC2308
APPLICATIONS INFORMATION
011...111
111...111
111...110
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
100...001
100...000
011...111
011...110
UNIPOLAR
ZERO
FS = 4.096V
1LSB = FS/2N
1LSB = 1mV
FS = 4.096V
1LSB = FS/2
100...001
100...000
000...001
000...000
N
1LSB = 1mV
–1 0V
1
–FS/2
FS/2 – 1LSB
0V
FS – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2308 F10
2308 F11
Figure 10. LTC2308 Bipolar Transfer
Characteristics (2’s Complement)
Figure 11. LTC2308 Unipolar Transfer
Characteristics (Straight Binary)
2308f
18
LTC2308
PACKAGE DESCRIPTION
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 0.05
4.50 0.05
3.10 0.05
2.45 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
R = 0.115
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
0.75 0.05
4.00 0.10
(4 SIDES)
TYP
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 0.10
1
2
2.45 0.10
(4-SIDES)
(UF24) QFN 0105
0.200 REF
0.25 0.05
0.00 – 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2308f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2308
TYPICAL APPLICATION
Clock Squaring/Level Shifting Circuit Allows Testing with RF Sine Generator,
Convert Re-Timing Flip-Flop Preserves Low Jitter Clock Timing
5V
2.7V TO 5V
10MF
0.1MF
10MF
0.1MF
0.1MF
LTC2308
AV
DV
OV
DD
DD
DD
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SDI
ANALOG
INPUT
MUX
SDO
12-BIT
500ksps
ADC
+
–
SERIAL
PORT
SCK
V
CONVST
CC
NL17SZ74
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
V
REF
PRE
INTERNAL
2.5V REF
2.2MF
Q
Q
D
CLR
CONVERT ENABLE
REFCOMP
GND
0.1MF
10MF
V
CC
RF SIGNAL GENERATOR OR
OTHER LOW-JITTER SOURCE
0.1MF
1k
MASTER
CLOCK
NC7SVU04P5X
507
1k
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MASTER CLOCK
JITTER
•
•
•
•
•
•
CONVERT ENABLE
CONVST
DATA TRANSFER
2308 TA02
RELATED PARTS
PART NUMBER
LTC1417
DESCRIPTION
COMMENTS
14-Bit, 400ksps Serial ADC
20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
LTC1468/LT1469
LTC1609
Single/Dual 90MHz, 22V/μs, 16-Bit Accurate Op Amps Low Input Offset: 75μV/125μV
16-Bit, 200ksps Serial ADC
65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply
LTC1790
Micropower Low Dropout Reference
10-Bit/12-Bit, 8-Channel, 1.25Msps ADC
10-Bit/12-Bit, 8-Channel, 400ksps ADC
12-Bit, 1-/2-Channel, 250ksps ADC in MSOP
60μA Supple Current, 10ppm/°C, SOT-23 Package
LTC1850/LTC1851
LTC1852/LTC1853
LTC1860/LTC1861
Parallel Output, Programmable MUX and Sequencer, 5V Supply
Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply
850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages
450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages
6.5mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
2mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages
450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages
LTC1860L/LTC1861L 3V, 12-Bit, 1-/2-Channel, 150ksps ADC
LTC1863/LTC1867 12-/16-Bit, 8-Channel, 200ksps ADC
LTC1863L/LTC1867L 3V, 12-/16-Bit, 8-Channel, 175ksps ADC
LTC1864/LTC1865 16-Bit, 1-/2-Channel, 250ksps ADC in MSOP
LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel, 150ksps ADC in MSOP
2308f
LT 0807 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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