LTC2321HUFD-12#PBF_技术文档

LTC2321-12

Dual, 12-Bit + Sign, 2Msps

Differential Input ADC with Wide

Input Common Mode Range

DescripTion

FeaTures

The LTC^®2321-12 is a low noise, high speed dual 12-bit +

sign successive approximation register (SAR) ADC with

differential inputs and wide input common mode range.

n

2Msps Throughput Rate

n

0ꢀ5ꢁSꢂ INꢁ ꢃTꢄpꢅ

n

Guaranteed 12-ꢂit, No Missing Codes

n

8V Differential Inputs with Wide Input Common

Operatingfromasingle3.3Vor5Vsupply,theLTC2321-12

P-P

Mode Range

has an 8V differential input range, making it ideal for

P-P

n

73dꢂ SNR ꢃTꢄpꢅ at f = 500kHz

applications which require a wide dynamic range with

high common mode rejection. The LTC2321-12 achieves

±±.5LSꢀ INL typical, no missing codes at 12 bits and

73dꢀ SNR.

IN

–85dꢂ THD ꢃTꢄpꢅ at f = 500kHz

Guaranteed Operation to 125°C

Single 3.3V or 5V Supply

Low Drift (2±ppm/°C Max) 2.±48V or 4.±96V Internal

Reference

TheLTC2321-12hasanonboardlowdrift(2±ppm/°Cmax)

2.±48V or 4.±96V temperature-compensated reference.

The LTC2321-12 also has a high speed SPI-compatible

serial interface that supports CMOS or LVDS. The fast

2Msps per channel throughput with zero cycle latency

makes the LTC2321-12 ideally suited for a wide variety of

high speed applications. The LTC2321-12 dissipates only

3±mW per channel and offers nap and sleep modes to

reduce the power consumption to 5μW for further power

savings during inactive periods.

n

1.8V to 2.5V I/O Voltages

CMOS or LVDS SPI-Compatible Serial I/O

Power Dissipation 3±mW/Ch (Typ)

Small 28-Lead (4mm × 5mm) QFN Package

applicaTions

n

High Speed Data Acquisition Systems

n

Communications

n

Remote Data Acquisition

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

n

Imaging

n

Optical Networking

n

Automotive

n

Multiphase Motor Control

Typical applicaTion

32k Point FFT f_S= 2Msps, f_IN= 500klHz

DIFFERENTIAL INPUTS

3.3V OR 5V

10µF

NO CONFIGURATION REQUIRED

0

+

–

SNR = 72.9dB

IN , IN

THD = –86.1dB

SINAD = 72.8dB

–20

INSTRUMENTATION

DIFFERENTIAL

V

REFOUT1

VBYP1

DD

SFDR = 89.5dB

25Ω

10µF

1µF

A

+

–40

IN1

LTC2321-12

REFOUT2

–60

–80

0V

220pF

10µF

1µF

VBYP2

BIPOLAR

UNIPOLAR

25Ω

–100

–

SDO1

SDO2

CLKOUT

SCK

A

IN1

IN2

TO CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

+

–

–120

–140

0V

CMOS/LVDS

REFINT

GND

V

DD

CNV

OGND OV

1.8V TO 2.5V

DD

0.2

0.4

0.6

0.8

0

1

1µF

FREQUENCY (MHz)

232112 TA01a

232112 TA01b

232112f

1

For more information www.linear.com/LTC2321-12

LTC2321-12

absoluTe MaxiMuM raTings

pin conFiguraTion

ꢃNotes 1, 2ꢅ

Supply Voltage (V )..................................................6V

TOP VIEW

DD

Supply Voltage (OV )................................................3V

DD

Supply ꢀypass Voltage (V

Analog Input Voltage

, V

) .......................3V

ꢀYP1 ꢀYP2

28 27 26 25 24 23

A

, A (Note 3) ................... –±.3V to (V + ±.3V)

–

IN DD

+

IN

–

+

V

1

2

3

4

5

6

7

8

22

21

20

19

18

17

16

15

SCK

DD

REFOUT1,2 ............................. .–±.3V to (V + ±.3V)

DD

A

+

IN2

–

+

CNV (Note 15).......................... –±.3V to (V + ±.3V)

–

SDO2

IN2

29

GND

Digital Input Voltage

GND

–

+

CLKOUT

(Note 3).......................... (GND – ±.3V) to (OV + ±.3V)

DD

A

–

+

CLKOUT

IN1

Digital Output Voltage

–

A

SDO1

IN1

V

(Note 3).......................... (GND – ±.3V) to (OV + ±.3V)

DD

+

SDO1

DD

Power Dissipation...............................................2±±mW

9

10 11 12 13 14

UFD PACKAGE

Operating Temperature Range

LTC2321C ................................................ ±°C to 7±°C

LTC2321I..............................................–4±°C to 85°C

LTC2321H .......................................... –4±°C to 125°C

Storage Temperature Range .................. –65°C to 15±°C

28-LEAD (4mm × 5mm) PLASTIC QFN

T

= 125°C, θ = 43°C/W

JMAX

JA

EXPOSED PAD (PIN 29) IS GND, MUST ꢀE SOLDERED TO PCꢀ

orDer inForMaTion

ꢁEAD FREE FINISH

TAPE AND REEꢁ

PART MARKING*

23212

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC2321CUFD-12#PꢀF

LTC2321IUFD-12#PꢀF

LTC2321HUFD-12#PꢀF

LTC2321CUFD-12#TRPꢀF

LTC2321IUFD-12#TRPꢀF

LTC2321HUFD-12#TRPꢀF

±°C to 7±°C

28-Lead (4mm × 5mm) Plastic QFN

23212

–4±°C to 85°C

–4±°C to 125°C

23212

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

elecTrical characTerisTics ^Thel denotes the specifications which applꢄ over the full operating

temperature range, otherwise specifications are at T_A= 25°C ꢃNote 4ꢅꢀ

SYMꢂOꢁ

PARAMETER

CONDITIONS

(Note 5)

MIN

TYP

MAX

UNITS

V

l

+

–

+

–

+

–

V

Absolute Input Range (A

, A

)

±

V

IN

IN1

IN2

DD

, A

)

(Note 5)

±

V

IN1

–

+

–

= V – V

IN

– V

Input Differential Voltage Range

Common Mode Input Range

Analog Input DC Leakage Current

Analog Input Capacitance

V

–REFOUT1,2

REFOUT1,2

V

IN

+

–

= (V + V )/2

±

V

DD

V

CM

IN

I

–1

1

µA

pF

dꢀ

IN

C

1±

85

IN

CMRR

Input Common Mode Rejection Ratio

External Reference Current

f

= 2.2MHz

IN

I

REFINT = ±V, REFOUT = 4.±96V

31±

µA

REFOUT

232112f

2

For more information www.linear.com/LTC2321-12

LTC2321-12

converTer characTerisTics ^Thel denotes the specifications which applꢄ over the full operating

temperature range, otherwise specifications are at T_A= 25°C ꢃNotes 4, 16ꢅꢀ

SYMꢂOꢁ PARAMETER

CONDITIONS

MIN

12

TYP

MAX

UNITS

ꢀits

l

Resolution

No Missing Codes

12

ꢀits

Transition Noise

±.4

±±.5

±±.4

±

LSꢀ

RMS

l

INL

Integral Linearity Error

Differential Linearity Error

ꢀipolar Zero-Scale Error

ꢀipolar Zero-Scale Error Drift

ꢀipolar Full-Scale Error

ꢀipolar Full-Scale Error Drift

(Note 6)

(Note 7)

–1

1

LSꢀ

DNL

ꢀZE

–±.99

–1.5

±.99

1.5

LSꢀ

±.±±15

±2

LSꢀ/°C

LSꢀ

l

FSE

V

= 4.±96V (REFINT Grounded) (Note 7)

= 4.±96V (REFINT Grounded)

–23

23

REFOUT1,2

15

ppm/°C

REFOUT1,2

DynaMic accuracy The ^ldenotes the specifications which applꢄ over the full operating temperature range,

otherwise specifications are at T_A= 25°C and A_IN= –1dꢂFS ꢃNotes 4, 8ꢅꢀ

SYMꢂOꢁ PARAMETER

CONDITIONS

MIN

TYP

72.8

73

MAX

UNITS

dꢀ

l

SINAD

Signal-to-(Noise + Distortion) Ratio f = 5±±kHz, V

= 4.±96V, Internal Reference

= 5V, External Reference

= 4.±96V, Internal Reference

= 5V, External Reference

= 4.±96V, Internal Reference

= 5V, External Reference

= 4.±96V, Internal Reference

= 5V, External Reference

69.5

IN

REFOUT1,2

f

IN

f

IN

f

IN

f

IN

f

IN

f

IN

f

IN

= 5±±kHz, V

dꢀ

SNR

Signal-to-Noise Ratio

7±

78

73

dꢀ

73.5

–85

–84

88

dꢀ

THD

Total Harmonic Distortion

Spurious Free Dynamic Range

–8±

dꢀ

SFDR

dꢀ

88

dꢀ

–3dꢀ Input Linear ꢀandwidth

Aperture Delay

1±

MHz

ps

5±±

1

Aperture Delay Matching

Aperture Jitter

ps

RMS

Transient Response

Full-Scale Step

3

ns

inTernal reFerence characTerisTics ^Thel denotes the specifications which applꢄ over the

full operating temperature range, otherwise specifications are at T_A= 25°C ꢃNote 4ꢅꢀ

SYMꢂOꢁ

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Internal Reference Output Voltage

4.75V < V < 5.25V

4.±88

2.±44

4.±96

2.±48

4.1±6

2.±53

V

REOUT1,2

DD

3.13V < V < 3.47V

DD

l

V

Temperature Coefficient

(Note 14)

3

2±

ppm/°C

Ω

REFIN

REFOUT1,2 Output Impedance

Line Regulation

±.25

±.3

V

DD

= 4.75V to 5.25V

mV/V

REFOUT1,2

232112f

3

For more information www.linear.com/LTC2321-12

LTC2321-12

DigiTal inpuTs anD DigiTal ouTpuTs ^Thel denotes the specifications which applꢄ over the

full operating temperature range, otherwise specifications are at T_A= 25°C ꢃNote 4ꢅꢀ

SYMꢂOꢁ

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

l

V

IH

V

IL

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

±.8 • OV

DD

±.2 • OV

1±

V

DD

I

V

IN

= ±V to OV

DD

–1±

μA

pF

IN

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leakage Current

Output Source Current

5

IN

l

I = -5±±µA

O

OV – ±.2

DD

V

OH

OL

I = 5±±µA

O

±.2

1±

V

I

V

OUT

V

OUT

V

OUT

= ±V to OV

DD

–1±

µA

mA

mV

V

OZ

= ±V

= OV

–1±

1±

SOURCE

SINK

Output Sink Current

DD

l

V

LVDS Differential Input Voltage

LVDS Common Mode Input Voltage

LVDS Differential Output Voltage

1±±Ω Differential Termination, OV = 2.5V

24±

1

6±±

1.45

3±±

ID

DD

1±±Ω Differential Termination, OV = 2.5V

IS

DD

1±±Ω Differential Load, LVDS Mode,

OV = 2.5V

DD

1±±

15±

1.2

1±±

1.2

mV

OD

l

V

LVDS Common Mode Output Voltage 1±±Ω Differential Load, LVDS Mode,

±.85

75

1.4

25±

1.4

V

mV

V

OS

OV = 2.5V

DD

Low Power LVDS Differential Output

Voltage

1±±Ω Differential Load, Low Power,

LVDS Mode ,OV = 2.5V

OD_LP

OS_LP

DD

Low Power LVDS Common Mode

Output Voltage

1±±Ω Differential Load, Low Power,

LVDS Mode ,OV = 2.5V

±.9

DD

power requireMenTs ^Thel denotes the specifications which applꢄ over the full operating temperature

range, otherwise specifications are at T_A= 25°C ꢃNote 4ꢅꢀ

SYMꢂOꢁ PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

DD

Supply Voltage

5V Operation

3.3V Operation

4.75

3.13

5.25

3.47

V

l

OV

Supply Voltage

Supply Current

1.71

2.63

15

V

DD

+

–

I

2Msps Sample Rate (IN = IN = ±V)

2Msps Sample Rate (C = 5pF)

11.8

mA

VDD

l

CMOS Mode

LVDS Mode

1.8

7.1

2

11

mA

OVDD

L

2Msps Sample Rate (R = 1±±Ω)

L

l

I

Nap Mode Current

Sleep Mode Current

Conversion Done (I

)

2.55

5

mA

NAP

VDD

l

Sleep Mode (I

+ I

)

CMOS Mode

LVDS Mode

1

5

μA

SLEEP

VDD

OVDD

+

–

P

Power Dissipation

Nap Mode

V

= 3.3V 2Msps Sample Rate (IN = IN = ±V) CMOS Mode

37

52

58

86

mW

D_3.3V

DD

= 3.3V 2Msps Sample Rate (IN = IN = ±V) LVDS Mode

V

DD

V

DD

= 3.3V Conversion Done (I

+ I

)

CMOS Mode

LVDS Mode

7.8

26

13

41

mW

VDD

OVDD

Sleep Mode

V

= 3.3V Sleep Mode (I

+ I

)

CMOS Mode

LVDS Mode

5

16.5

μW

DD

VDD

OVDD

+

)

–

P

Power Dissipation

Nap Mode

V

DD

V

DD

= 5V 2Msps Sample Rate (IN = IN = ±V) CMOS Mode

= 5V 2Msps Sample Rate (IN = IN = ±V) LVDS Mode

6±

77

8±

1±2.5

mW

D_5V

+

V

DD

V

DD

= 5V Conversion Done (I

+ I

)

CMOS Mode

LVDS Mode

13

31

25

4±

mW

VDD

OVDD

Sleep Mode

V

DD

V

DD

= 5V Sleep Mode (I

+ I

OVDD

+ I

OVDD

)

CMOS Mode

LVDS Mode

5

25

μW

VDD

)

232112f

4

For more information www.linear.com/LTC2321-12

LTC2321-12

aDc TiMing characTerisTics The l denotes the specifications which applꢄ over the full operating

temperature range, otherwise specifications are at T_A= 25°C ꢃNote 4ꢅꢀ

SYMꢂOꢁ

PARAMETER

CONDITIONS

MIN

TYP

MAX

2

UNITS

Msps

ns

l

f

t

Maximum Sampling Frequency

Time ꢀetween Conversions

Acquisition Time

SMPL

(Note 11)

5±±

3±

1±±±±±±

CYC

ns

ACQ

Conversion Time

22±

25±

25

ns

CONV

READOUT Time

ns

READOUT

DCNVSCKL

DSCKLCNVH

SCK

(Note 11)

ns

SCK Quiet Time from CNV↓

SCK Delay Time to CNV↑

SCK Period

(Note 11)

±

ns

(Notes 12, 13)

15.6

7

ns

SCK High Time

ns

SCKH

SCK Low Time

7

ns

SCKL

SCK to CLKOUT Delay

SDO Data Valid Delay from CLKOUT↓

(Note 12)

2.8

ns

DSCKCLKOUT

DCLKOUTSDOV

HSDO

C = 5pF (Note 12)

L

2.5

ns

SDO Data Remains Valid Delay from

CLKOUT↓

C = 5pF (Note 11)

L

ns

l

t

C = 5pF (Note 11)

2.5

1±

3

ns

SDO Data Valid Delay from CNV↓

ꢀus Relinquish Time After CNV↑

REFOUT1,2 Wake-Up Time

DCNVSDOV

DCNVSDOZ

WAKE

L

(Note 11)

C

= 1±μF

ms

REFOUT1,2

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 8: All specifications in dꢀ are referred to a full-scale ±4.±96V input

with REFOUT = 4.±96V.

Note 9: When REFOUT1,2 is overdriven, the internal reference buffer must

be turned off by setting REFINT = ±V.

Note 2: All voltage values are with respect to ground.

Note 10: f

= 2MHz, I

varies proportionally with sample rate.

SMPL

REFꢀUF

Note 3: When these pin voltages are taken below ground, or above V

DD

Note 11: Guaranteed by design, not subject to test.

Note 12: Parameter tested and guaranteed at OV = 1.71V and

or OV , they will be clamped by internal diodes. This product can handle

DD

input currents up to 1±±mA below ground, or above V or OV , without

DD

OV = 2.5V.

DD

latch-up.

Note 4: V = 5V, OV = 2.5V, REFOUT1,2 = 4.±96V, f = 2MHz.

SMPL

Note 13: t

of 15.6ns maximum allows a shift clock frequency up to

SCK

DD

64MHz for rising edge capture.

Note 14: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

Note 5: Recommended operating conditions.

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 7: ꢀipolar zero error is the offset voltage measured from –±.5LSꢀ

when the output code flickers between ± ±±±± ±±±± ±±±± and 1 1111

1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS un-

trimmed deviation from ideal first and last code transitions and includes

the effect of offset error.

Note 15: CNV is driven from a low jitter digital source, typically at OV

logic levels. This input pin has a TTL style input that will draw a small

amount of current.

DD

12

Note 16: 1LSꢀ = 2 • REFOUT1,2/2

0.8 • OV

DD

t

WIDTH

0.2 • OV

DD

50%

t

DELAY

232112 F01

0.8 • OV

0.2 • OV

DD

0.2 • OV

Figure 1ꢀ Voltage ꢁevels for Timing Specifications

232112f

5

For more information www.linear.com/LTC2321-12

LTC2321-12

Typical perForMance characTerisTics

T_A= 25°C, V_DD= 5V, OV_DD= 2ꢀ5V, REFOUT1,2 =

4ꢀ096V, f_SMPꢁ= 2Msps, unless otherwise noted ꢃNote 16ꢅꢀ

Integral Nonlinearitꢄ

vs Output Code

Differential Nonlinearitꢄ

vs Output Code

DC Histogram

1.0

0.5

1.00

0.80

0.60

0.40

0.20

0

70000

60000

50000

40000

30000

20000

10000

0

–0.20

–0.40

–0.60

–0.80

–1.00

–0.5

–1.0

–4096

–2048

0

2048

4096

–2

–1

0

1

2

–4096

–2048

0

2048

4096

CODE

OUTPUT CODE

232112 G01

OUTPUT CODE

232112 G03

232112 G02

THD, Harmonics vs Input

Frequencꢄ ꢃ50kHz to 1MHzꢅ

32k Point FFT, f_S=2Msps,

f_IN= 500kHz

SNR, SINAD vs Input Frequencꢄ

ꢃ50kHz to 1MHzꢅ

–85

–90

0

–20

74.0

73.5

73.0

72.5

72.0

71.5

71.0

SNR = 72.9dB

THD = –86.1dB

SINAD = 72.8dB

SFDR = 89.5dB

THD

–40

SNR

–95

HD2

HD3

–60

SINAD

–80

–100

–120

–140

–105

–110

0

0.25

0.50

0.75

1

0

0.5

1

0.2

0.4

0.6

0.8

0

1

FREQUENCY (MHz)

232112 G06

232112 G05

232112 G04

THD, Harmonics vs

Input Common Mode

SNR, SINAD vs Reference Voltage,

f_IN= 500kHz

8k Point FFT, IMD, f_S= 2Msps,

V_IN⁺= 100kHz, V_IN^–= 500kHz

–75

–80

0

–20

SNR

73

71

69

67

65

SINAD

–85

–40

THD

–90

–95

–60

HD2

HD3

–80

–100

–105

–100

–120

–140

–110

2.1 2.3 2.5 2.7 2.9

INPUT COMMON MODE (V)

3.3

1.5

2

2.5

3

3.5

5

1.7 1.9

3.1

0.5

1

4

4.5

0.2

0.4

FREQUENCY (MHz)

0

0.6

0.8

1.0

V

REF

(V)

232112 G07

232112 G08

232112 G09

232112f

6

For more information www.linear.com/LTC2321-12

LTC2321-12

Typical perForMance characTerisTics

T_A= 25°C, V_DD= 5V, OV_DD= 2ꢀ5V, REFOUT1,2 =

4ꢀ096V, f_SMPꢁ= 2Msps, unless otherwise noted ꢃNote 16ꢅꢀ

Output Match with Simultaneous

Input Steps at CH1, CH2

5000

Crosstalk vs Input Frequencꢄ

CMRR vs Input Frequencꢄ

–80

–83

–124

–126

–128

–130

4000

3000

2000

1000

0

CH1

–86

CH2

–89

–92

–95

–98

–101

–104

–1000

0

0.5

1

1.5

2

2.5

0

0.2

0.4

0.6

0.8

1.0

0

100

200

300

400

500

FREQUENCY (MHz)

INPUT FREQUENCY (MHz)

TIME (ns)

232112 G10

232112 G11

232112 G12

Offset Error vs Temperature

Gain Error vs Temperature

REFOUT1,2 Output vs Temperature

0.50

0.40

0.30

0.20

0.10

0

0.15

0.10

0.05

0

200

100

0

4.096V

2.048V

–100

–200

–300

–400

–500

CH1

CH2

–0.10

–0.20

–0.30

–0.40

–0.50

–0.05

–0.10

0

25 50 75 100

TEMPERATURE (°C)

150

125

–50 –25

0

25

50

75 100 125

0

50

TEMPERATURE (°C)

–40 –25

–50

150

100

TEMPERATURE (°C)

232112 G14

232112 G13

232112 G15

Reference Current vs Temperature,

V_REF= 4ꢀ096V

Supplꢄ Current

OV_DDCurrent vs SCK Frequencꢄ,

C_ꢁOAD= 10pF

vs Sample Frequencꢄ

8

6

4

2

0

0.350

0.345

0.340

0.335

12.0

11.5

11.0

10.5

10.0

9.5

9.0

8.5

8.0

0

20 40 60 80

TEMPERATURE (°C)

120

100

–40 –20

0

0.5

1

1.5

2

0

10 20 30 40 50 60 70 80 90 100 110

SAMPLE RATE (Msps)

SCK FREQUENCY (MHz)

232112 G16

232112 G17

232112 G18

232112f

7

For more information www.linear.com/LTC2321-12

LTC2321-12

pin FuncTions

+

–

V

ꢃPins 1, 8ꢅ: Power Supply. ꢀypass V to GND with

SDO1 , SDO1 ꢃPins 15, 16ꢅ: Channel 1 Serial Data Out-

DD

a 1±µF ceramic and a ±.1µF ceramic close to the part. The

DD

put. The conversion result is shifted MSꢀ first on each

V

pins should be shorted together and driven from the

falling edge of SCK. In CMOS mode, the result is output

+

same supply.

on SDO1 . The logic level is determined by OV . Do

DD

–

not connect SDO1 . In LVDS mode, the result is output

A

, A ꢃPins 2, 3ꢅ: Analog Differential Input Pins.

+

–

IN2

+

–

differentially on SDO1 and SDO1 . These pins must be

differentially terminated by an external 1±±Ω resistor at

the receiver (FPGA).

Full-scale range (A

– A

) is ±REFOUT2 voltage.

–

IN2

+

IN2

These pins can be driven from V to GND.

DD

GND ꢃPins 4, 5, 10, 29ꢅ: Ground. These pins and exposed

pad (Pin 29) must be tied directly to a solid ground plane.

+

–

CꢁKOUT , CꢁKOUT ꢃPins 17, 18ꢅ: Serial Data Clock

Output. CLKOUT provides a skew-matched clock to latch

the SDO output at the receiver. In CMOS mode, the skew-

A

, A

ꢃPins 6, 7ꢅ: Analog Differential Input Pins.

+

IN1

–

IN1

+

Full-scale range (A

– A

) is ±REFOUT1 voltage.

–

IN1

+

matched clock is output on CLKOUT . The logic level

IN1

–

These pins can be driven from V to GND.

is determined by OV . Do not connect CLKOUT . For

DD

low throughput applications using SCK to latch the SDO

CNV ꢃPin 9ꢅ: Convert Input. This pin, when high, defines

the sampling phase. When this pin is driven low, the con-

version phase is initiated and output data is clocked out.

+

–

output, CLKOUT can be disabled by tying CLKOUT to

OV . In LVDS mode, the skew-matched clock is output

DD

+

–

differentially on CLKOUT and CLKOUT . These pins must

be differentially terminated by an external 1±±Ω resistor

at the receiver (FPGA).

This input pin is a TTL-style input typically driven at OV

DD

levels with a low jitter pulse, but it is bound to V levels.

DD

This pin is unaffected by the CMOS/LVDS pin.

+

–

SDO2 , SDO2 ꢃPins 19, 20ꢅ: Channel 2 Serial Data Out-

REFRTN1 ꢃPin 11ꢅ: Reference ꢀuffer 1 Output Return.

ꢀypass REFRTN1 to REFOUT1. Do not tie the REFRTN1

pin to the ground plane.

put. The conversion result is shifted MSꢀ first on each

falling edge of SCK. In CMOS mode, the result is output

+

on SDO2 . The logic level is determined by OV . Do

DD

–

REFOUT1ꢃPin12ꢅ:Referenceꢀuffer1Output.Anonboard

buffer nominally outputs 4.±96V to this pin. This pin is re-

ferred to REFRTN1 and should be decoupled closely to the

pin (no vias) with a ±.1µF (X7R, ±4±2 size) capacitor and

a 1±μF (X5R, ±8±5 size) ceramic capacitor in parallel. The

internal buffer driving this pin may be disabled by ground-

ing the REFINT pin. If the buffer is disabled, an external

reference may drive this pin in the range of 1.25V to 5V.

not connect SDO2 . In LVDS mode, the result is output

+

–

differentially on SDO2 and SDO2 . These pins must be

differentially terminated by an external 1±±Ω resistor at

the receiver (FPGA).

+

–

SCK , SCK ꢃPins 21, 22ꢅ: Serial Data Clock Input. The

falling edge of this clock shifts the conversion result MSꢀ

+

first onto the SDO pins. In CMOS mode, drive SCK with

a single-ended clock. The logic level is determined by

–

+

VꢂYP1 ꢃPin 13ꢅ: ꢀypass this internally supplied pin to

ground with a 1µF ceramic capacitor. The nominal output

voltage on this pin is 1.6V.

OV . Do not connect SCK . In LVDS mode, drive SCK

DD

–

and SCK with a differential clock. These pins must be

differentially terminated by an external 1±±Ω resistor at

the receiver (ADC).

OV ꢃPin 14ꢅ: I/O Interface Digital Power. The range of

DD

OV is 1.71V to 2.5V. This supply is nominally set to the

DD

OGNDꢃPin23ꢅ:I/OGround.Thisgroundmustbetiedtothe

groundplaneatasinglepoint.OV isbypassedtothispin.

same supply as the host interface (CMOS: 1.8V or 2.5V,

DD

LVDS:2.5V).ꢀypassOV toOGNDwitha±.1μFcapacitor.

DD

VꢂYP2 ꢃPin 24ꢅ: ꢀypass this internally supplied pin to

ground with a 1µF ceramic capacitor. The nominal output

voltage on this pin is 1.6V

232112f

8

For more information www.linear.com/LTC2321-12

LTC2321-12

pin FuncTions

CMOS/ꢁVDS ꢃPin 25ꢅ: I/O Mode Select. Ground this pin

REFRTN2 ꢃPin 27ꢅ: Reference ꢀuffer 2 Output Return.

ꢀypass REFRTN2 to REFOUT2. Do not tie the REFRTN2

pin to the ground plane.

to enable CMOS mode, tie to OV to enable LVDS mode.

DD

Float this pin to enable low power LVDS mode.

REFOUT2ꢃPin26ꢅ:Referenceꢀuffer2Output.Anonboard

buffer nominally outputs 4.±96V to this pin. This pin is

referred to REFRTN2 and should be decoupled closely to

the pin (no vias) with a ±.1µF (X7R, ±4±2 size) capacitor

and a 1±μF (X5R, ±8±5 size) ceramic capacitor in paral-

lel. The internal buffer driving this pin may be disabled

by grounding the REFINT pin. If the buffer is disabled,

an external reference may drive this pin in the range of

REFINT ꢃPin 28ꢅ: Reference ꢀuffer Output Enable. Tie to

V

when using the internal reference. Tie to ground to

DD

disable the internal REFOUT1 and REFOUT2 buffers for

use with external voltage references. This pin has a 5±±k

internal pull-up to V .

DD

Exposed Pad ꢃPin 29ꢅ: Ground. Solder this pad to ground.

1.25V to V .

DD

FuncTional block DiagraM

V

DD

1,8

VBYP1

LDO

13

A

+

–

IN1

+

SDO1

7

+

–

LVDS/CMOS

THREE-STATE

SERIAL OUTPUT

15

16

12-BIT + SIGN

SAR ADC

–

SDO1

S/H

6

REFINT

REFOUT1

28

12

GND

G

4, 5, 10, 29

1.2V REF

OV

DD

14

REFOUT2

26

9

+

CLKOUT

17

18

CNV

TIMING CONTROL

LOGIC

OUTPUT

CLOCK DRIVER

–

CLKOUT

+

SCK

21

22

LVDS/CMOS

RECEIVERS

–

SCK

A

+

–

IN2

+

2

3

+

–

SDO2

LVDS/CMOS

THREE-STATE

SERIAL OUTPUT

19

20

12-BIT + SIGN

SAR ADC

–

S/H

SDO2

A

V

IN2

DD

1,8

VBYP2

24

LDO

232112 BD

232112f

9

For more information www.linear.com/LTC2321-12

LTC2321-12

TiMing DiagraM

ACQUISITION

CONVERSION

READOUT

CNV

1

2

3

4

5

6

10

11

12

13

SCK

HI-Z

SDO

HI-Z

B12

B11

B10

B9

B8

B3

B2

B1

B0

1

2

5

CLKOUT

SERIAL DATA BITS B[12:0] CORRESPOND TO CURRENT CONVERSION

232112 TD

applicaTions inForMaTion

OVERVIEW

CONVERTER OPERATION

The LTC2321-12 is a low noise, high speed 12-bit + sign

dual successive approximation register (SAR) ADC with

differential inputs and wide input common mode range.

Theflexibleanaloginputssupportfullydifferential,pseudo-

differential bipolar and pseudo-differential unipolar drive

without requiring any hardware configuration. The MSꢀ

of the 12-bit + sign two’s complement output indicates

the sign of the differential analog input voltage.

The LTC2321-12 operates in two phases. During the

acquisition phase, the sample capacitor is connected to

the analog input pins A and A

to sample the dif-

–

+

IN

ferential analog input voltage, as shown in Figure 3. A

falling edge on the CNV pin initiates a conversion. Dur-

ing the conversion phase, the 13-bit CDAC is sequenced

through a successive approximation algorithm for each

input SCK pulse, effectively comparing the sampled input

with binary-weighted fractions of the reference voltage

The ADC’s transfer function provides 13-bits of resolu-

(e.g., V

/2, V /4 … V /4±96) using a

REFOUT REFOUT REFOUT

tion across the full-scale span of 2 • V , as shown in

REF1,2

differential comparator. At the end of conversion, a CDAC

output approximates the sampled analog input. The ADC

control logic then prepares the 13-bit digital output code

for serial transfer.

Figure 2. If the analog input spans less than this full-scale,

such as in the case of pseudo-differential drive, the ADC

provides 12-bits of resolution across this reduced span,

with the additional benefit of digitizing over- and under-

range conditions, as shown in Table 1. This unique feature

is particularly useful in control loop applications.

TRANSFER FUNCTION

The LTC2321-12 digitizes the full-scale voltage of 2 • RE-

13

FOUT1,2into2 levels,resultingina13-bitresolutionsize

of 1mV with REFꢀUF = 4.±96V. The ideal transfer function

is shown in Figure 2. The output data is in 2’s compli-

ment format. When driven by fully differential inputs, the

13

transferfunctionspans2 codes.Whendrivenbypseudo

12

differential inputs, the transfer function spans 2 codes.

232112f

10

For more information www.linear.com/LTC2321-12

LTC2321-12

applicaTions inForMaTion

V

DD

0 1111 1111 1111

0 1111 1111 1110

C

IN

R

15Ω

ON

10pF

A

+

IN1

0 0000 0000 0001

0 0000 0000 0000

1 1111 1111 1111

BIAS

VOLTAGE

DD

C

IN

R

15Ω

ON

10pF

2 • REFOUT

8192

1LSB =

1 0000 0000 0001

1 0000 0000 0000

232112 F03

–

IN1

–REFOUT

–1

LSB

0

1

LSB

REFOUT – 1LSB

INPUT VOLTAGE (V)

232112 F02

Figure 3ꢀ The Equivalent Circuit for the Differential

Analog Input of the ꢁTC2321-12

Figure 2ꢀ ꢁTC2321-12 Transfer Function

Single-Ended Signals

Analog Input

Single-ended signals can be directly digitized by the

LTC2321-12. These signals should be sensed pseudo-

differentially for improved common mode rejection. ꢀy

connecting the reference signal (e.g., ground sense) of

The differential inputs of the LTC2321-12 provide great

flexibility to convert a wide variety of analog signals with

no configuration required. The LTC2321-12 digitizes the

difference voltage between the A and A pins while

+

–

IN

the main analog signal to the other A pin, any noise or

IN

supporting a wide common mode input range. The analog

disturbance common to the two signals will be rejected

by the high CMRR of the ADC. The LTC2321-12 flexibility

handles both pseudo-differential unipolar and bipolar sig-

nals, with no configuration required. The wide common

mode input range relaxes the accuracy requirements of

any signal conditioning circuits prior to the analog inputs.

input signals can have an arbitrary relationship to each

other, provided that they remain between V and GND.

DD

The LTC2321-12 can also digitize more limited classes of

analog input signals such as pseudo-differential unipolar/

bipolarandfullydifferentialwithnoconfigurationrequired.

The analog inputs of the LTC2321-12 can be modeled by

the equivalent circuit shown in Figure 3. The back-to-back

diodes at the inputs form clamps that provide ESD protec-

Pseudo-Differential ꢂipolar Input Range

The pseudo-differential bipolar configuration represents

driving one of the analog inputs at a fixed voltage, typically

tion.Intheacquisitionphase,1±pF(C )fromthesampling

IN

capacitorinserieswithapproximately15Ω(R )fromthe

ON

V

/2, and applying a signal to the other A pin. In this

REF

IN

on-resistance of the sampling switch is connected to the

input. Any unwanted signal that is common to both inputs

will be reduced by the common mode rejection of the ADC

sampler. The inputs of the ADC core draw a small current

case the analog input swings symmetrically around the

fixedinputyieldingbipolartwo’scomplementoutputcodes

with an ADC span of half of full-scale. This configuration

is illustrated in Figure 4, and the corresponding transfer

function in Figure 5. The fixed analog input pin need not

spikewhilechargingtheC capacitorsduringacquisition.

IN

Table 1ꢀ Code Ranges for the Analog Input Operational Modes

+

–

MODE

SPAN ꢃV – V

ꢅ

IN

MIN CODE

MAX CODE

IN

Fully Differential

–REFOUT to +REFOUT

–REFOUT/2 to +REFOUT/2

± to REFOUT

1 ±±±± ±±±± ±±±±

1 1±±± ±±±± ±±±±

± ±±±± ±±±± ±±±±

± 1111 1111 1111

± ±111 1111 1111

± 1111 1111 1111

Pseudo Differential ꢀipolar

Pseudo Differential Unipolar

232112f

11

For more information www.linear.com/LTC2321-12

LTC2321-12

applicaTions inForMaTion

V

REF

LT1819

LTC2321-12

25Ω

+

–

0V

A

+

REFOUT1

VBYP1

IN1

10µF

1µF

V

REF

220pF

10k

V

/2

REF

+

–

V

/2

REF

TO CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

–

SDO1

CLKOUT

SCK

IN1

10k

1µF

ONLY CHANNEL 1 SHOWN FOR CLARITY

232112 F04

Figure 4ꢀ Pseudo-Differential ꢂipolar Application Circuit

ADC CODE

full-scale. This configuration is illustrated in Figure 6, and

thecorrespondingtransferfunctioninFigure7.Iftheinput

(2’s COMPLEMENT)

4095

V

REF

LT1818

2047

LTC2321-12

V

REF

25Ω

+

–

0V

A

+

IN1

REFOUT1

0V

A

10µF

1µF

IN

(A + – A –)

IN IN

–V

–V /2

REF

0

V

REF

/2

V

REF

VBYP1

220pF

25Ω

DOTTED REGIONS AVAILABLE

BUT UNUSED

–2048

–4096

TO CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

–

A

IN1

SDO1

CLKOUT

SCK

232112 F05

232112 F06

Figure 5ꢀ Pseudo-Differential ꢂipolar Transfer Function

Figure 6ꢀ Pseudo-Differential Unipolar Application Circuit

be set at V /2, but at some point within the V rails

REF

DD

allowingthealternateinputtoswingsymmetricallyaround

thisvoltage.Iftheinputsignal(A –A )swingsbeyond

ADC CODE

(2’s COMPLEMENT)

+

–

IN

4095

±REFOUT1,2/2, valid codes will be generated by the ADC

and must be clamped by the user, if necessary.

2047

Pseudo-Differential Unipolar Input Range

A

IN

(A + – A –)

IN IN

–V

–V /2

REF

0

V

REF

/2

V

REF

The pseudo-differential unipolar configuration represents

driving one of the analog inputs at ground and applying a

DOTTED REGIONS AVAILABLE

BUT UNUSED

–2048

–4096

signal to the other A pin. In this case, the analog input

IN

swings between ground and V yielding unipolar two’s

REF

232112 F07

complement output codes with an ADC span of half of

Figure 7ꢀ Pseudo-Differential Unipolar Transfer Function

232112f

12

For more information www.linear.com/LTC2321-12

LTC2321-12

applicaTions inForMaTion

signal (A – A ) swings negative, valid codes will be

frequencies of 5±±kHz and less. Data sheet typical perfor-

mancecurvestakenathigherfrequenciesusedaharmonic

rejection filter between the ADC and the signal source to

eliminatetheopampasthedominantsourceofdistortion.

+

–

IN

generated by the ADC and must be clamped by the user,

if necessary.

Single-Ended-to-Differential Conversion

The fully-differential configuration yields an analog input

Whilesingle-endedsignalscanbedirectlydigitizedaspre-

viously discussed, single-ended to differential conversion

circuits may also be used when higher dynamic range is

desired. ꢀy producing a differential signal at the inputs of

the LTC2321-12, the signal swing presented to the ADC is

maximized, thus increasing the achievable SNR.

The LT^®1819 high speed dual operational amplifier is

recommendedforperformingsingle-ended-to-differential

conversions, as shown in Figure 8. In this case, the first

amplifier is configured as a unity-gain buffer and the

single-ended input signal directly drives the high imped-

ance input of this amplifier.

span (A – A ) of ±REFOUT1,2. In this configuration,

+

–

IN

theinputsignalisdrivenoneachAINpin, typicallyatequal

spans but opposite polarity. This yields a high common

mode rejection on the input signals. The common mode

voltageoftheanaloginputcanbeanywherewithintheV

DD

input range, but will be limited by the peak swing of the

full-range input signal. For example, if the internal refer-

ence is used with V = 5V , the full-range input span

DD

DC

will be ±4.±96V. Half of the input span is typically driven

on each AIN pin, yielding a signal span for each AIN pin of

4.±96V . This leaves ~±.9V of common mode variation

P-P

tolerance. When using external references, it is possible

to increase common mode tolerance by compressing the

ADC full-range codes into a tighter range. For example,

Fullꢄ-Differential Inputs

using an external 2.±48V reference with V = 5V the total

DD

To achievethefulldistortionperformanceoftheLTC2321-12,

a low distortion fully-differential signal source driven

through the LT1819 configured as two unity-gain buffers,

as shown in Figure 9, can be used. This circuit achieves

the full data sheet THD specification of –85dꢀ at input

span would be ±2.±48V and each AIN span would be lim-

ited to 2.±48V allowing a common mode range of ~3V.

P-P

Compressing the input span would incur a SNR penalty

of approximately 1dꢀ. Input span compression may be

usefulifsingle-supplyanaloginputdriversareusedwhich

V

REF

0V

LT1819

V

REF

LT1819

V

REF

+

–

V

REF

+

–

0V

V

REF

0V

V

REF

+

–

V

REF

V

REF

/2

+

–

200Ω

0V

232112 F09

200Ω

232112 F08

Figure 8ꢀ Single-Ended to Differential Driver

Figure 9ꢀ ꢁT1819 ꢂuffering a Fullꢄ-Differential Signal Source

232112f

13

For more information www.linear.com/LTC2321-12

LTC2321-12

applicaTions inForMaTion

cannotswingrail-to-rail.Thefully-differentialconfiguration

is illustrated in Figure 1±, with the corresponding transfer

function illustrated in Figure 11.

is important even for DC inputs, because the ADC inputs

draw a current spike when during acquisition.

For best performance, a buffer amplifier should be used to

drive the analog inputs of the LTC2321-12. The amplifier

provides low output impedance to minimize gain error

and allow for fast settling of the analog signal during the

acquisition phase. It also provides isolation between the

signal source and the ADC inputs, which draw a small

current spike during acquisition.

INPUT DRIVE CIRCUITS

A low impedance source can directly drive the high im-

pedance inputs of the LTC2321-12 without gain error. A

high impedance source should be buffered to minimize

settling time during acquisition and to optimize the dis-

tortion performance of the ADC. Minimizing settling time

V

REF

0V

LT1819

LTC2321-12

25Ω

+

–

0V

A

+

REFOUT1

VBYP1

IN1

10µF

1µF

220pF

V

REF

0V

REF

+

–

0V

TO CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

–

A

SDO1

CLKOUT

SCK

IN1

ONLY CHANNEL 1 SHOWN FOR CLARITY

232112 F10

Figure 10ꢀ Fullꢄ-Differential Application Circuit

ADC CODE

(2’s COMPLEMENT)

4095

2047

A

IN

(A + – A –)

INn

–V

–V /2

REF

0

V

REF

/2

V

REF

–2048

–4096

232112 F11

Figure 11ꢀ Fullꢄ-Differential Transfer Function

232112f

14

For more information www.linear.com/LTC2321-12

LTC2321-12

applicaTions inForMaTion

Input Filtering

ADC REFERENCE

The noise and distortion of the buffer amplifier and signal

sourcemustbeconsideredsincetheyaddtotheADCnoise

and distortion. Noisy input signals should be filtered prior

to the buffer amplifier input with a low bandwidth filter

to minimize noise. The simple 1-pole RC lowpass filter

shown in Figure 12 is sufficient for many applications.

Internal Reference

The LTC2321-12 has an on-chip, low noise, low drift

(2±ppm/°C max), temperature compensated bandgap

reference. It is internally buffered and is available at

REFOUT1,2 (Pins 12, 26). The reference buffer gains

the internal reference voltage to 4.±96V for supply volt-

The input resistor divider network, sampling switch on-

ages V = 5V and to 2.±48V for V = 3.3V. ꢀypass

DD

resistance (R ) and the sample capacitor (C ) form a

ON

IN

REFOUT1,2 to REFRTN1,2 with the parallel combination

of a ±.1µF (X7R, ±4±2 size) capacitor and a 1±μF (X5R,

±8±5 size) ceramic capacitor to compensate the reference

buffer and minimize noise. The ±.1µF capacitor should

be as close as possible to the LTC2321-12 package to

secondlowpassfilterthatlimitstheinputbandwidthtothe

ADC core to 11±MHz. A buffer amplifier with a low noise

density must be selected to minimize the degradation of

the SNR over this bandwidth.

Highqualitycapacitorsandresistorsshouldbeusedinthe

RCfilterssincethesecomponentscanadddistortion.NPO

and silver mica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occurduringsoldering.Metalfilmsurfacemountresistors

are much less susceptible to both problems.

minimize wiring inductance. Tie the REFINT pin to V to

enable the internal reference buffer.

Table 2ꢀ REFOUT1,2 Sources and Ranges vs V_DD

DD

REFINT

DIFFERENTIAꢁ

SPAN

V

REFOUT1,2 PIN

Internal 4.±96V

DD

5V

±V

±4.±96V

±1.25V to ±5V

±2.±48V

5V

External (1.25V to 5V)

Internal 2.±48V

3.3V

±V

External (1.25V to 3.3V)

±1.25V to ±3.3V

SINGLE-ENDED

INPUT SIGNAL

50Ω

+

IN

LTC2321

–

IN

SINGLE-ENDED

3.3nF

TO DIFFERENTIAL

DRIVER

232112 F12

BW = 1MHz

Figure 12ꢀ Input Signal Chain

232112f

15

For more information www.linear.com/LTC2321-12

LTC2321-12

applicaTions inForMaTion

External Reference

±4±2 size) ceramic capacitor and a 1±μF ceramic capaci-

tor (X5R, ±8±5 size) close to each of the REFOUT1,2 and

REFRTN1,2 pins.

The internal reference buffer can also be overdriven from

1.25V to 5V with an external reference at REFOUT1,2

as shown in Figure 13 (b and c). To do so, REFINT must

be grounded to disable the reference buffer. A 55k internal

resistance loads the REFOUT1,2 pins when the reference

buffer is disabled. To maximize the input signal swing

and corresponding SNR, the LTC6655-5 is recommended

whenoverdrivingREFOUT.TheLTC6655-5offersthesame

smallsize,accuracy,driftandextendedtemperaturerange

as the LTC6655-4.±96. ꢀy using a 5V reference, a higher

SNR can be achieved. We recommend bypassing the

LTC6655-5 with a parallel combination of a ±.1µF (X7R,

Internal Reference ꢂuffer Transient Response

The REFOUT1,2 pins of the LTC2321-12 draw charge

(Q

) from the external bypass capacitors during each

CONV

conversion cycle. If the internal reference buffer is over-

driven,theexternalreferencemustprovideallofthischarge

with a DC current equivalent to I

= Q

/t

.

REF

CONV CYC

Thus, the DC current draw of REFOUT1,2 depends

on the sampling rate and output code. In applications

where a burst of samples is taken after idling for long

REFINT

V

3.3V TO 5V

DD

REFINT

REFOUT1

0.1µF

LTC2321-12

5V TO 13.2V

10µF

LTC6655-4.096

REFRTN1

REFRTN2

REFRTN1

V

IN

OUT_F

V

OUT_S

REFRTN2

REFOUT2

SHDN

0.1µF

REFOUT2

GND

232112 F13a

232112 F13b

ꢃ13aꢅ ꢁTC2321-12 Internal Reference Circuit

ꢃ13bꢅ ꢁTC2321-12 with a Shared External Reference Circuit

5V TO 13.2V

REFINT

LTC6655-4.096

V

REFOUT1

IN

OUT_F

SHDN

0.1µF

OUT_S

LTC2321-12

0.1µF

10µF

REFRTN1

REFRTN2

REFOUT2

LTC6655-2.048

V

SHDN

V

IN

OUT_F

V

OUT_S

GND

0.1µF

232112 F13c

ꢃ13cꢅ ꢁTC2321-12 with Different External Reference Voltages

Figure 13ꢀ Reference Connection

232112f

16

For more information www.linear.com/LTC2321-12

LTC2321-12

applicaTions inForMaTion

periods, as shown in Figure 14 , I

quickly goes from

DYNAMIC PERFORMANCE

REFꢀUF

approximately~75µAtoamaximumof4±±µAforREFOUT

= 5V at 2Msps. This step in DC current draw triggers a

transient response in the external reference that must be

considered since any deviation in the voltage at REFOUT

will affect the accuracy of the output code. If an external

reference is used to overdrive REFOUT1,2 the fast settling

LTC6655 reference is recommended.

Fast Fourier transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. ꢀy applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2321-12 provides

guaranteed tested limits for both AC distortion and noise

measurements.

CNV

Signal-to-Noise and Distortion Ratio ꢃSINADꢅ

IDLE

PERIOD

232112 F14

The signal-to-noise and distortion ratio (SINAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is bandlimited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure16showsthattheLTC2321-12achieves

a typical SINAD of 72.8dꢀ at a 2MHz sampling rate with

a 5±±kHz input.

Figure 14ꢀ CNV Waveform Showing ꢂurst Sampling

5000

4000

3000

2000

1000

0

CH1

CH2

Signal-to-Noise Ratio ꢃSNRꢅ

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 16 shows

that the LTC2321-12 achieves a typical SNR of 73dꢀ at a

2MHz sampling rate with a 5±±kHz input.

–1000

0

100

200

300

400

500

TIME (ns)

232112 F15

Figure 15ꢀ Transient Response of the ꢁTC2321-12

0

SNR = 72.9dB

THD = –86.1dB

SINAD = 72.8dB

–20

SFDR = 89.5dB

–40

–60

–80

–100

–120

–140

0.2

0.4

0.6

0.8

0

1

FREQUENCY (MHz)

232112 F16

Figure 16ꢀ 32k Point FFT of the ꢁTC2321-12

232112f

17

For more information www.linear.com/LTC2321-12

LTC2321-12

applicaTions inForMaTion

Total Harmonic Distortion ꢃTHDꢅ

the LTC2321-12 to communicate with any digital logic

operating between 1.8V and 2.5V. When using LVDS I/O,

Totalharmonicdistortion(THD)istheratiooftheRMSsum

ofallharmonicsoftheinputsignaltothefundamentalitself.

The out-of-band harmonics alias into the frequency band

the OV supply must be set to 2.5V.

DD

Power Supplꢄ Sequencing

between DC and half the sampling frequency (f

THD is expressed as:

/2).

SMPL

The LTC2321-12 does not have any specific power sup-

ply sequencing requirements. Care should be taken to

adhere to the maximum voltage relationships described

in the Absolute Maximum Ratings section. The LTC2321-

12 has a power-on-reset (POR) circuit that will reset the

LTC2321-12 at initial power-up or whenever the power

supply voltage drops below 2V. Once the supply voltage

re-enters the nominal supply voltage range, the POR will

reinitialize the ADC. No conversions should be initiated

until 1±ms after a POR event to ensure the reinitialization

period has ended. Any conversions initiated before this

time will produce invalid results.

V2²+ V3²+ V4²+…+ V_N²

THD=2±log

V1

where V1 is the RMS amplitude of the fundamental

frequency and V2 through V are the amplitudes of the

N

second through Nth harmonics.

POWER CONSIDERATIONS

The LTC2321-12 requires two power supplies: the 5V

power supply (V ), and the digital input/output interface

DD

power supply (OV ). The flexible OV supply allows

DD

12.0

11.5

11.0

10.5

10.0

9.5

9.0

8.5

8.0

0

0.5

1

1.5

2

SAMPLE RATE (Msps)

232112 F17

Figure 17ꢀ Power Supplꢄ Current of the ꢁTC2321-12 Versus Sampling Rate

232112f

18

For more information www.linear.com/LTC2321-12

LTC2321-12

applicaTions inForMaTion

TIMING AND CONTROꢁ

Nap/Sleep Modes

Nap mode is a method to save power without sacrificing

power-updelaysforsubsequentconversions.Sleepmode

has substantial power savings, but a power-up delay is

incurred to allow the reference and power systems to

become valid. To enter nap mode on the LTC2321-12,

the SCK signal must be held high or low and a series of

two CNV pulses must be applied. This is the case for both

CMOS and LVDS modes. The second rising edge of CNV

initiates the nap state. The nap state will persist until either

asinglerisingedgeofSCKisapplied,orfurtherCNVpulses

are applied. The SCK rising edge will put the LTC2321-12

back into the operational (full-power) state. When in nap

mode, two additional pulses will put the LTC2321-12 in

sleep mode. When configured for CMOS I/O operation, a

single rising edge of SCK can return the LTC2321-12 into

operational mode. A 1±ms delay is necessary after exiting

sleep mode to allow the reference buffer to recharge the

external filter capacitor. In LVDS mode, exit sleep mode

by supplying a fifth CNV pulse. The fifth pulse will return

the LTC2321-12 to operational mode, and further SCK

pulses will keep the part from re-entering nap and sleep

modes. The fifth SCK pulse also works in CMOS mode

as a method to exit sleep. In the absence of SCK pulses,

repetitive CNV pulses will cycle the LTC2321-12 between

operational, nap and sleep modes indefinitely.

CNV Timing

The LTC2321-12 sampling and conversion is controlled

by CNV. A rising edge on CNV will start sampling and the

fallingedgestartstheconversionandreadoutprocess.The

conversion process is timed by the SCK input clock. For

optimum performance, CNV should be driven by a clean

low jitter signal. The Typical Application at the back of the

data sheet illustrates a recommended implementation to

reduce the relatively large jitter from an FPGA CNV pulse

source.Notethelowjitterinputclocktimesthefallingedge

of the CNV signal. The rising edge jitter of CNV is much

less critical to performance. The typical pulse width of the

CNV signal is 3±ns at a 2Msps conversion rate.

SCK Serial Data Clock Input

The falling edge of this clock shifts the conversion result

MSꢀfirstontotheSDOpins. A64MHzexternalclockmust

be applied at the SCK pin to achieve 2Msps throughput.

CꢁKOUT Serial Data Clock Output

The CLKOUT output provides a skew-matched clock to

latch the SDO output at the receiver. The timing skew

of the CLKOUT and SDO outputs are matched. For high

throughput applications, using CLKOUT instead of SCK

to capture the SDO output eases timing requirements at

the receiver. For low throughput applications, CLKOUT

can be disabled by tying CLKOUT to OV .

RefertothetimingdiagramsinFigure18,Figure19,Figure2±

and Figure 21 for more detailed timing information about

sleep and nap modes.

+

–

DD

CNV

1

2

NAP MODE

FULL POWER MODE

SCK

HOLD STATIC HIGH OR LOW

Z

WAKE ON 1ST SCK EDGE

SDO1

SDO2

Z

232112 F18

Figure 18ꢀ CMOS and ꢁVDS Mode NAP and WAKE Using SCK

232112f

19

For more information www.linear.com/LTC2321-12

LTC2321-12

applicaTions inForMaTion

REFOUT

RECOVERY

REFOUT1

REFOUT2

4.096V

t

WAKE

CNV

1

2

3

4

NAP MODE

SLEEP MODE

FULL POWER MODE

SCK

HOLD STATIC HIGH OR LOW

WAKE ON 1ST SCK EDGE

SDO1

SDO2

Z

232112 F19

Figure 19ꢀ CMOS Mode SꢁEEP and WAKE Using SCK

REFOUT

RECOVERY

REFOUT1

REFOUT2

4.096V

t

WAKE

WAKE ON 5TH

CSB EDGE

CNV

1

2

3

4

5

NAP MODE

SLEEP MODE

FULL POWER MODE

SCK

HOLD STATIC HIGH OR LOW

SDO1

SDO2

Z

232112 F20

Figure 20ꢀ ꢁVDS and CMOS Mode SꢁEEP and WAKE Using CNV

t

DSCKHCNVH

CNV

t

SCK

SCKL

3

SCKH

1

2

4

5

6

10

11

12

13

SCK

HI-Z

B12

B11

B10

B9

B8

B3

B2

B1

B0

SDO

t

DCLKOUTSDOV

1

2

3

4

11

CLKOUT

t

READOUT

CNVH

CONV

t

THROUGHPUT

232112 F21

SERIAL DATA BITS B[12:0] CORRESPOND TO CURRENT CONVERSION

Figure 21ꢀ ꢁTC2321-12 Timing Diagram

232112f

20

For more information www.linear.com/LTC2321-12

LTC2321-12

applicaTions inForMaTion

DIGITAL INTERFACE

skew of the CLKOUT and SDO outputs are matched. For

high throughput applications, using CLKOUT instead of

SCK to capture the SDO output eases timing requirements

at the receiver.

The LTC2321-12 features a serial digital interface that

is simple and straight forward to use. The flexible OV

supply allows the LTC2321-12 to communicate with any

digital logic operating between 1.8V and 2.5V. A 64MHz

external clock must be applied at the SCK pin to achieve

2Msps throughput.

DD

+

InCMOSmode, usetheSDO1 , SDO2 andCLKOUT pins

+

as outputs. Use the SCK pin as an input. Do not connect

the SDO1 , SDO2 , SCK and CLKOUT pins, as they each

have internal pull-down circuitry to OGND.

–

InadditiontoastandardCMOSSPIinterface,theLTC2321-

12 provides an optional LVDS SPI interface to support low

noise digital design. The CMOS/LVDS pin is used to select

the digital interface mode.

+

–

+

–

In LVDS mode, use the SDO1 /SDO1 , SDO2 /SDO2 and

+

–

CLKOUT /CLKOUT pins as differential outputs. These

pinsmustbedifferentiallyterminatedbyanexternal100Ω

resistor at the receiver (FPGA). The SCK /SCK pins are

differential inputs and must be terminated differentially by

an external 100Ω resistor at the receiver (ADC).

+

–

ThefallingedgeofSCKoutputstheconversionresultMSB

first on the SDO pins. CLKOUT provides a skew-matched

clock to latch the SDO output at the receiver. The timing

2.5V

LTC2321-12

FPGA OR DSP

OV

DD

+

SDO1

+

–

100Ω

–

+

SDO1

CLKOUT

+

–

100Ω

–

+

CLKOUT

SCK

+

–

2.5V

100Ω

–

+

CMOS/LVDS

SCK

SDO2

+

–

100Ω

–

SDO2

CNV

232112 F22

Figure 22. LTC2321 Using the LVDS Interface

232112f

21

For more information www.linear.com/LTC2321-12

LTC2321-12

applicaTions inForMaTion

BOARD LAYOUT

Recommended Layout

To obtain the best performance from the LTC2321-12,

a printed circuit board is recommended. Layout for the

printed circuit board (PCB) should ensure the digital and

analog signal lines are separated as much as possible.

In particular, care should be taken not to run any digital

clocks or signals adjacent to analog signals or underneath

the ADC.

ThefollowingisanexampleofarecommendedPCBlayout.

A single solid ground plane is used. Bypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

ADC. The analog input traces are screened by ground.

For more details and information, refer to the DC1996,

the evaluation kit for the LTC2321-12.

Figure 1. Layer 1, Top Layer

Figure 3. Layer 3, Power Plane

Figure 2. Layer 2, Ground Plane

Figure 4. Layer 4, Bottom Layer

232112f

22

For more information www.linear.com/LTC2321-12

LTC2321-12

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UFD Package

28-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1712 Rev B)

0.70 ±0.05

4.50 ±0.05

3.10 ±0.05

2.50 REF

2.65 ±0.05

3.65 ±0.05

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

3.50 REF

4.10 ±0.05

5.50 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

2.50 REF

R = 0.115

TYP

R = 0.20 OR 0.35

R = 0.05

TYP

× 45° CHAMFER

0.75 ±0.05

4.00 ±0.10

(2 SIDES)

27

28

0.40 ±0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

5.00 ±0.10

(2 SIDES)

3.50 REF

3.65 ±0.10

2.65 ±0.10

(UFD28) QFN 0506 REV B

0.25 ±0.05

0.200 REF

0.50 BSC

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

232112f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

23

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC2321-12

LTC2321-12

Typical applicaTion

Low Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Retiming Flip-Flop

V

CC

NC7SVUO4P5X

0.1µF

1k

MASTER_CLOCK

V

CC

50Ω

1k

D

PRE

NC7SV74KBX

CONV

Q

CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

CLR

CONV ENABLE

LTC2321-12

CNV

SCK

10Ω

CLKOUT

GND

CMOS/LVDS SDO1

SDO2

232112 TA02

NC7SVU04P5X (× 3)

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

ADCs

LTC2321-16/LTC2321-14 16-Bit/14-Bit, 2Msps Simultaneous Sampling ADC 3.3V/5V Supply Differential Input Common Mode Range, 4mm × 5mm

QFN-28 Package

LTC2314-14

14-Bit, 4.5Msps Serial ADC

3V/5V Supply, 18mW/31mW, 20ppm/°C Max Internal Reference,

Unipolar Inputs, 8-Lead TSOT-23 Package

LTC2370-16/LTC2368-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial,

LTC2367-16/LTC2364-16 Low Power ADC

2.5V Supply, Pseudo-Differential Unipolar Input, 94dB SNR, 5V Input Range,

DGC, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2380-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial,

LTC2377-16/LTC2376-16 Low Power ADC

2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC, Pin-

Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

DACs

LTC2632

Dual 12-/10-/8-Bit, SPI V

Reference

DACs with Internal

DACs with External

2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode,

Rail-to-Rail Output, 8-Pin ThinSOT™ Package

OUT

LTC2602/LTC2612/

LTC2622

Dual 16-/14-/12-Bit SPI V

Reference

300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, 8-Lead

MSOP Package

OUT

References

LTC6655

Precision Low Drift, Low Noise Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 5ppm/°C, 0.25ppm

Peak-to-Peak Noise, MSOP-8 Package

LTC6652

Precision Low Drift, Low Noise Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 5ppm/°C, 2.1ppm

Peak-to-Peak Noise, MSOP-8 Package

Amplifiers

LT1818/LT1819

400MHz, 2500V/µs, 9mA Single/Dual Operational

Amplifiers

–85dBc Distortion at 5MHz, 6nV/√Hz Input Noise Voltage, 9mA Supply

Current, Unity-Gain Stable

LT1806

LT6200

325MHz, Single, Rail-to-Rail Input and Output, Low –80dBc Distortion at 5MHz, 3.5nV/√Hz Input Noise Voltage,

Distortion, Low Noise Precision Op Amps 9mA Supply Current, Unity-Gain Stable

165MHz, Rail-to-Rail Input and Output, 0.95nV/√Hz Low Noise, Low Distortion, Unity-Gain Stable

Low Noise, Op Amp Family

232112f

LT 0514 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

For more information www.linear.com/LTC2321-12

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2321-12

●

 LINEAR TECHNOLOGY CORPORATION 2014


型号：	LTC2321HUFD-12#PBF
厂家：	Linear
描述：	LTC2321-12 - Dual, 12-Bit + Sign, 2Msps Differential Input ADC with Wide Input Common Mode Range; Package: QFN; Pins: 28; Temperature Range: -40°C to 125°C 转换器
文件：	总24页 (文件大小：1109K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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