LTC2323-12_技术文档

LTC2311-16

16-Bit, 5Msps

Differential Input ADC with Wide

Input Common Mode Range

DESCRIPTION

FEATURES

The LTC^®2311-16 is a low noise, high speed 16-bit

successive approximation register (SAR) ADC with

differential inputs and wide input common mode range.

n

5Msps Throughput Rate

n

3LSB INL (Typ), 8LSB INL Guaranteed

n

Guaranteed 16-Bit, No Missing Codes

n

8V Differential Inputs with Wide Input Common

Operating from a single 3.3V or 5V supply, the LTC2311-

P-P

Mode Range

16 has an 8V differential input range, making it ideal

P-P

n

81dB SNR (Typ) at f = 2.2MHz

for applications which require a wide dynamic range with

high common mode rejection. The LTC2311-16 achieves

3LSB INL typical, no missing codes at 16 bits and 81dB

SNR typical.

IN

–90dB THD (Typ) at f = 2.2MHz

Guaranteed Operation –40°C to 125°C

Single 3.3V or 5V Supply

Low Drift (20ppm/°C Max) 2.048V or 4.096V Internal

Reference with 1.25V External Reference Input

1.8V to 2.5V I/O Voltages

TheLTC2311-16hasanonboardlowdrift(20ppm/°Cmax)

2.048Vor4.096Vtemperature-compensatedreferenceand

provides an external 1.25V buffered reference input. The

LTC2311-16 also has a high speed SPI-compatible serial

interface that supports CMOS or LVDS. The fast 5Msps

throughputwithone-cyclelatencymakestheLTC2311-16

ideally suited for a wide variety of high speed applications.

The LTC2311-16 dissipates only 50mW with a 5V supply

and offers nap and sleep modes to reduce the power

consumption to 5μW for further power savings during

inactive periods.

n

CMOS or LVDS SPI-Compatible Serial I/O

Power Dissipation 50mW at V = 5V (Typ)

DD

Small 16-Lead (4mm × 5mm) MSOP Package

APPLICATIONS

n

High Speed Data Acquisition Systems

n

Communications

n

Remote Data Acquisition

n

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Imaging

n

Optical Networking

n

Automotive

n

Multiphase Motor Control

TYPICAL APPLICATION

3.3V OR 5V

1µF

DIFFERENTIAL INPUTS

32k Point FFT f_SMPL= 5Msps, f_IN= 2.2MHz

NO CONFIGURATION REQUIRED

+

–

0

IN , IN

SNR = 81.6dB

THD = –90dB

–20

ARBITRARY

DIFFERENTIAL

SINAD = 81.1dB

SFDR = 96dB

V

REFOUT

DD

25Ω

10µF

–40

A

+

IN

LTC2311-16

–60

0V

REFIN

47pF

–80

–100

–120

–140

10µF

BIPOLAR

UNIPOLAR

LVDS OR CMOS

CONFIGURABLE

I/O

25Ω

SDO

SCK

–

IN

CMOS/LVDS

GND

CNV

0

0.5

1

1.5

2

2.5

OV

1.8V TO 2.5V

1µF

DD

FREQUENCY (MHz)

231116 TA01b

231116 TA01a

231116fa

1

For more information www.linear.com/LTC2311-16

LTC2311-16

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Notes 1, 2)

Supply Voltage (V )..................................................6V

DD

Supply Voltage (OV )................................................3V

DD

Analog Input Voltage

TOP VIEW

A

, A (Note 3) ................... –0.3V to (V + 0.3V)

–

IN DD

+

IN

+

–

1

2

3

4

5

6

7

8

GND

REFIN

16 SCK

15 SCK

REFIN, REFOUT ....................... –0.3V to (V + 0.3V)

DD

+

–

REFOUT

14 SDO

13 SDO

17

GND

CNV (Note 15).......................... –0.3V to (V + 0.3V)

V

DD

GND

12 OV

DD

Digital Input Voltage

+

A

11 GND

IN

–

10 CMOS/LVDS

(Note 3).......................... (GND – 0.3V) to (OV + 0.3V)

DD

GND

9

CNV

Digital Output Voltage

MSE PACKAGE

16-LEAD (4mm × 5mm) PLASTIC MSOP

(Note 3).......................... (GND – 0.3V) to (OV + 0.3V)

DD

T

JMAX

= 150°C, θ = 40°C/W

JA

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

Power Dissipation...............................................200mW

Operating Temperature Range

LTC2311C................................................. 0°C to 70°C

LTC2311I..............................................–40°C to 85°C

LTC2311H .......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

http://www.linear.com/product/LTC2311-16#orderinfo

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING*

231116

PACKAGE DESCRIPTION

16-Lead (4mm × 5mm) Plastic MSOP

TEMPERATURE RANGE

0°C to 70°C

LTC2311CMSE-16#PBF

LTC2311IMSE-16#PBF

LTC2311HMSE-16#PBF

LTC2311CMSE-16#TRPBF

LTC2311IMSE-16#TRPBF

LTC2311HMSE-16#TRPBF

231116

16-Lead (4mm × 5mm) Plastic MSOP

–40°C to 85°C

–40°C to 125°C

231116

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

231116fa

2

For more information www.linear.com/LTC2311-16

LTC2311-16

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL

PARAMETER

CONDITIONS

(Note 5)

MIN

TYP

MAX

UNITS

V

l

+

–

+

–

V

Absolute Input Range (A

)

0

V

DD

V

DD

IN

)

(Note 5)

0

V

IN

–

+

–

= V – V

IN

– V

Input Differential Voltage Range

Common Mode Input Range

Analog Input DC Leakage Current

Analog Input Capacitance

V

–REFOUT

REFOUT

V

IN

+

–

= (V + V )/2

0

V

DD

V

CM

IN

I

IN

–1

1

µA

pF

dB

V

C

IN

10

85

CMRR

Input Common Mode Rejection Ratio

CNV High Level Input Voltage

CNV Low Level Input Voltage

CNV Input Current

f

= 2.2MHz

= 0V to V

IN

l

V

IHCNV

V

ILCNV

V

INCNV

1.3

0.5

10

V

–10

µA

IN

DD

CONVERTER CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL PARAMETER

CONDITIONS

MIN

16

TYP

MAX

UNITS

Bits

l

Resolution

No Missing Codes

16

Bits

Transition Noise

1.7

3

LSB

RMS

l

INL

Integral Linearity Error

Differential Linearity Error

Bipolar Zero-Scale Error

Bipolar Zero-Scale Error Drift

Bipolar Full-Scale Error

Bipolar Full-Scale Error Drift

(Note 6)

(Note 7)

–8

8

LSB

DNL

BZE

–0.99

–12

0.4

0

0.99

12

LSB

0.01

10

15

LSB/°C

LSB

l

FSE

V

= 4.096V (REFIN Grounded) (Note 7)

= 4.096V (REFIN Grounded)

–30

30

REFOUT

ppm/°C

REFOUT

231116fa

3

For more information www.linear.com/LTC2311-16

LTC2311-16

DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C and A_IN= –1dBFS (Notes 4, 8).

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

SINAD

Signal-to-(Noise + Distortion) Ratio f = 2.2MHz, V

= 4.096V, Internal Reference

= 5V, External Reference

76

81

dB

IN

REFOUT

f

= 2.2MHz, V

81.5

IN

SNR

Signal-to-Noise Ratio

f

= 2.2MHz, V

= 4.096V, Internal Reference

= 5V, External Reference

76.5

78

81.6

82.3

dB

IN

REFOUT

THD

Total Harmonic Distortion

Spurious Free Dynamic Range

f

= 2.2MHz, V

= 4.096V, Internal Reference

= 5V, External Reference

–90

–88

–79

dB

IN

REFOUT

SFDR

f

= 2.2MHz, V

= 4.096V, Internal Reference

= 5V, External Reference

95

90

dB

IN

REFOUT

–3dB Input Bandwidth

Aperture Delay

100

500

1

MHz

ps

Aperture Jitter

ps

RMS

Transient Response

Full-Scale Step

3

ns

INTERNAL REFERENCE CHARACTERISTICS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

REFOUT Output Voltage

4.75V < V < 5.25V

4.082

2.042

4.096

2.048

4.110

2.054

V

REFOUT

DD

3.13V < V < 3.47V

DD

l

REFOUT Input Voltage

4.75V < V < 5.25V, REFIN = 0V (Note 5)

0.5

V

DD

3.13V < V < 3.47V, REFIN = 0V (Note 5)

DD

l

REFOUT Temperature Coefficient

REFOUT Short-Circuit Current

REFOUT Line Regulation

(Note 14)

3

20

ppm/°C

mA

V

= 5.25V, Forcing Output to GND

= 4.75V to 5.25V

30

DD

0.3

0.5

60

mV/V

mV/mA

kΩ

DD

REFOUT Load Regulation

I

< 2mA

REFOUT

REFOUT Input Resistance (External Reference REFIN = 0V

Mode)

I

REFOUT Input Current (External Reference

Mode)

REFIN = 0V, REFOUT = 4.096V

(Notes 9, 10)

700

µA

V

REFOUT

l

V

REFIN Output Voltage

3.13V < V < 3.47V

1.245

1.25

1.255

REFIN

DD

4.75V < V < 5.25V

DD

l

REFIN Input Voltage

3.13V < V < 3.47V (Note 5)

1

1.85

1.45

V

DD

4.75V < V < 5.25V (Note 5)

DD

l

REFIN Short-Circuit Current

V

DD

= 5.25V, Forcing Output to GND

250

µA

l

V

(V

)

REFIN Low Level Input Voltage (External

Reference Mode)

3.13V < V < 3.47V

0.5

V

IL REFIN

DD

4.75V < V < 5.25V

DD

231116fa

4

For more information www.linear.com/LTC2311-16

LTC2311-16

DIGITAL INPUTS AND DIGITAL OUTPUTS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL

PARAMETER

CONDITIONS

MIN

0.8 • OV

–10

TYP

MAX

UNITS

CMOS Digital Inputs and Outputs

l

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

V

IH

DD

0.2 • OV

10

IL

DD

I

V

IN

= 0V to OV

DD

μA

pF

V

IN

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leakage Current

Output Source Current

Output Sink Current

5

IN

l

I = –500µA

O

OV – 0.2

DD

OH

OL

I = 500µA

O

0.2

10

V

I

V

OUT

V

OUT

V

OUT

= 0V to OV

DD

–10

µA

mA

OZ

= 0V

= OV

–10

10

SOURCE

SINK

DD

LVDS Digital Inputs and Outputs

l

V

LVDS Differential Input Voltage

LVDS Common Mode Input Voltage

LVDS Differential Output Voltage

100Ω Differential Termination, OV = 2.5V

240

1

600

1.45

300

mV

V

ID

DD

100Ω Differential Termination, OV = 2.5V

IS

DD

100Ω Differential Load, LVDS Mode,

OV = 2.5V

DD

100

250

1.2

mV

OD

l

V

LVDS Common Mode Output Voltage 100Ω Differential Load, LVDS Mode,

0.85

50

1.4

200

1.4

V

mV

V

OS

OV = 2.5V

DD

Low Power LVDS Differential Output

Voltage

100Ω Differential Load, Low Power,

125

1.2

OD_LP

OS_LP

LVDS Mode, OV = 2.5V

DD

Low Power LVDS Common Mode

Output Voltage

100Ω Differential Load, Low Power,

0.9

LVDS Mode, OV = 2.5V

DD

231116fa

5

For more information www.linear.com/LTC2311-16

LTC2311-16

POWER REQUIREMENTS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

DD

Supply Voltage

5V Operation

3.3V Operation

4.75

3.13

5.25

3.47

V

l

OV

Supply Voltage

1.71

2.63

12

V

mA

μA

DD

+

–

I

Supply Current

5Msps Sample Rate (A = A = 0V)

9.5

2.8

0.1

VDD

IN

Nap Mode Current

Sleep Mode Current

Conversion Done (I

)

3.5

10

NAP

VDD

V

DD

= 3.3V, Sleep Mode (I

+ I

)

SLEEP

VDD

OVDD

CMOS I/O Mode

l

I

Supply Current

Power Dissipation

Nap Mode

5Msps Sample Rate (C = 5pF)

1.1

30

1.75

mA

mW

μW

OVDD

L

+

–

P

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

= 3.3V 5Msps Sample Rate (A = A = 0V)

D_3.3V

D_5V

IN

= 3.3V Conversion Done (I

+ I

)

OVDD

7.5

0.3

45

VDD

Sleep Mode

= 3.3V Sleep Mode (I

+ I

)

VDD

OVDD

+

–

l

P

Power Dissipation

Nap Mode

= 5V 5Msps Sample Rate (A = A = 0V)

65

18

60

mW

μW

IN

= 5V Conversion Done (I

+ I

)

OVDD

14

VDD

Sleep Mode

= 5V Sleep Mode (I

+ I

)

OVDD

0.5

VDD

LVDS I/O Mode

l

I

Supply Current

Power Dissipation

Nap Mode

5Msps Sample Rate (R = 100Ω)

2.7

36

4.5

mA

mW

µW

OVDD

L

+

–

P

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

= 3.3V 5Msps Sample Rate (A = A = 0V)

IN IN

D_3.3V

= 3.3V Conversion Done (I

+ I

)

OVDD

14

VDD

Sleep Mode

= 3.3V Sleep Mode (I

+ I

)

0.3

55

VDD

OVDD

+

–

l

P

Power Dissipation

Nap Mode

= 5V 5Msps Sample Rate (A = A = 0V)

72

30

60

mW

µW

D_5V

IN

= 5V Conversion Done (I

+ I

)

OVDD

20

VDD

Sleep Mode

= 5V Sleep Mode (I

+ I

OVDD

)

0.5

VDD

ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS, LVDS I/O Modes

l

f

t

Maximum Sampling Frequency

Time Between Conversions

Acquisition Time

5

Msps

ns

SMPL

(Note 11)

200

28.5

171.5

25

1000000

CYC

ns

ACQ

Conversion Time

ns

CONV

CNV High Time

ns

CNVH

SCK Quiet Time from CNV↓

SCK Delay Time to CNV↑

SCK Period

(Note 11)

9.5

19.1

9.4

4

ns

DCNVSCKL

DSCKLCNVH

SCK

(Note 11)

ns

(Notes 12, 13)

ns

SCK High Time

ns

SCKH

SCK Low Time

4

ns

SCKL

231116fa

6

For more information www.linear.com/LTC2311-16

LTC2311-16

ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL

PARAMETER

CONDITIONS

C = 5pF (Note 11)

MIN

TYP

MAX

UNITS

ns

l

t

SDO Data Valid Delay from SCK↓

4

7.4

DSCKSDOV

HSDO

L

SDO Data Remains Valid Delay from

SCK↓

C = 5pF (Note 11)

L

2

ns

l

t

SDO Data Valid Delay from CNV↓

Bus Relinquish Time After CNV↑

REFOUT Wake-Up Time

C = 5pF (Note 11)

2.5

10

5

ns

DCNVSDOV

DCNVSDOZ

WAKE

L

(Note 11)

C

= 10μF

ms

REFOUT

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

untrimmed deviation from ideal first and last code transitions and includes

the effect of offset error.

Note 8: All specifications in dB are referred to a full-scale 4.096V input

with REFOUT = 4.096V.

Note 2: All voltage values are with respect to ground.

Note 9: When REFOUT is overdriven, the internal reference buffer must be

Note 3: When these pin voltages are taken below ground, or above V

turned off by setting REFIN = 0V.

DD

or OV , they will be clamped by internal diodes. This product can handle

DD

Note 10: f

= 5MHz, I

varies proportionally with sample rate.

SMPL

REFOUT

input currents up to 100mA below ground, or above V or OV , without

DD

Note 11: Guaranteed by design, not subject to test.

Note 12: Parameter tested and guaranteed at OV = 1.71V and

latch-up.

DD

Note 4: V = 5V, OV = 2.5V, REFOUT = 4.096V, f

= 5MHz.

DD

SMPL

OV = 2.5V.

DD

Note 5: Recommended operating conditions.

Note 13: t

of 9.4ns minimum allows a shift clock frequency up to

SCK

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB

when the output code flickers between 0000 0000 0000 0000 and 1111

1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS

105MHz for falling edge capture.

Note 14: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

Note 15: CNV is driven from a low jitter digital source, typically at OV

logic levels. This input pin has a TTL style input that will draw a small

amount of current.

DD

0.8 • OV

DD

t

WIDTH

0.2 • OV

DD

50%

t

DELAY

231116 F01

0.8 • OV

0.2 • OV

DD

0.2 • OV

Figure 1. Voltage Levels for Timing Specifications

231116fa

7

For more information www.linear.com/LTC2311-16

LTC2311-16

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_DD= 5V, OV_DD= 2.5V, REFOUT =

DC Histogram

4.096V, f_SMPL= 5Msps, unless otherwise noted.

Integral Nonlinearity

vs Output Code

Differential Nonlinearity

vs Output Code

1

0.5

0

20000

4

3

σ = 1.7

18000

16000

14000

12000

10000

8000

6000

4000

2000

0

2

1

0

–1

–2

–3

–4

–0.5

–1

–32768

–16384

0

16384

32768

–5 –4 –3 –2 –1

0

1

2

3

4

5

6

–32768

–16384

0

16384

32768

OUTPUT CODE

231116 G02

231116 G03

231116 G01

THD, Harmonics vs Input

32k Point FFT, f_SMPL= 5Msps,

f_IN= 2.2MHz

SNR, SINAD vs Input Frequency

(100kHz to 2.2MHz)

Frequency (100kHz to 2.2MHz)

–85

–90

83.0

82.5

82.0

81.5

81.0

80.5

80.0

0

–20

SNR = 81.6dB

THD = –90dB

SINAD = 81.1dB

SFDR = 96dB

–40

THD

–95

SNR

–60

–80

–100

–105

–110

SINAD

–100

–120

–140

HD2

HD3

0

0.5

1

1.5

2

2.5

0

0.5

1

1.5

2

2.5

0

0.5

1

1.5

2

2.5

FREQUENCY (MHz)

231116 G06

231116 G05

231116 G04

THD, Harmonics vs Input Common

Mode (100kHz to 2.2MHz)

SNR, SINAD vs Reference Voltage,

f_IN= 500kHz

8k Point FFT, IMD, f_SMPL= 5Msps,

A_IN⁺= 100kHz, A_IN^–= 2.2MHz

–80

–85

84

82

80

78

76

74

72

70

68

0

–20

SINAD

SNR

THD

–40

–90

HD3

–60

–95

–80

–100

–105

–110

–100

–120

–140

HD2

1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0.5

1

0

1.5

2

2.5

INPUT COMMON MODE (V)

V

REF

(V)

FREQUENCY (MHz)

231116 G09

231116 G07

231116 G08

231116fa

8

For more information www.linear.com/LTC2311-16

LTC2311-16

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_DD= 5V, OV_DD= 2.5V, REFOUT =

4.096V, f_SMPL= 5Msps, unless otherwise noted.

Offset Error vs Temperature

Gain Error vs Temperature

CMRR vs Input Frequency

2.0

1.5

2.0

1.5

–80

–83

–86

1.0

0.5

–89

0

–92

–0.5

–1.0

–1.5

–2.0

–95

–0.5

–1.0

–1.5

–2.0

–98

–101

–104

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

0

0.5

1

1.5

2

2.5

TEMPERATURE (°C)

FREQUENCY (MHz)

231116 G12

231116 G10

231116 G11

I_REFOUTvs Temperature,

V_REF= 4.096V

REFOUT Output vs Temperature

REFOUT Output Load Regulation

708

706

704

702

700

698

696

4.0970

4.0965

4.0960

4.0955

4.0950

4.0945

4.0940

400

300

2.048V

4.096V

200

100

0

–100

–200

–300

–400

–500

–600

–50 –25

0

25

50

75 100 125

0

0.5

1

1.5

2

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

REFOUT LOAD CURRENT (mA)

TEMPERATURE (°C)

231116 G14

231116 G15

231116 G13

Supply Current

vs Sample Frequency

OV_DDCurrent vs SCK Frequency,

C_LOAD= 10pF

10

9

1.5

1.0

0.5

0

8

7

6

5

0

1

2

3

4

5

0

10 20 30 40 50 60 70 80 90 100 110

SAMPLE FREQUENCY (Msps)

SCK FREQUENCY (MHz)

231116 G16

231116 G17

231116fa

9

For more information www.linear.com/LTC2311-16

LTC2311-16

PIN FUNCTIONS

GND(Pins1,5,8,11):Ground.Thesepinsandtheexposed

OV (Pin 12): I/O Interface Digital Power. The range of

DD

pad (Pin 17) must be tied directly to a solid ground plane.

OV is 1.71V to 2.5V. This supply is nominally set to the

DD

same supply as the host interface (CMOS: 1.8V or 2.5V,

REFIN (Pin 2): Reference Buffer 1.25V Input/Output. An

onboard buffer nominally outputs 1.25V to this pin. This

pin should be decoupled closely to the pin (no vias) with

a 10μF (X5R, 0805 size) ceramic capacitor. The internal

buffer driving this pin may be overdriven with an external

reference. The REFIN pin, when pulled to GND disables

the REFOUT pin buffer allowing an external reference to

drive REFOUT directly.

LVDS: 2.5V). Bypass OV to GND with a 1μF ceramic

DD

capacitor close to the OV pin.

DD

Exposed Pad (Pin 17): Ground. Solder this pad to ground.

CMOS I/O Mode

+

SDO (Pin 14): Serial Data Output. The conversion result

is shifted MSB first on each falling edge of SCK. The result

+

is output on SDO . The logic level is determined by OV .

REFOUT (Pin 3): Reference Buffer Output. An onboard

buffernominallyoutputs4.096Vtothispin.Thispinshould

be decoupled closely to the pin (no vias) with a 10μF (X5R,

0805 size) ceramic capacitor. The internal buffer driving

this pin may be disabled by grounding the REFIN pin. If

the buffer is disabled, an external reference may drive this

DD

–

Do not connect SDO .

+

SCK (Pin 16): Serial Data Clock Input. The falling edge

of this clock shifts the conversion result MSB first onto

+

the SDO pins. Drive SCK with a single-ended clock. The

–

logic level is determined by OV . Do not connect SCK .

DD

pin in the range of 1.25V to V .

DD

LVDS I/O Mode

V

(Pin 4): Power Supply. Bypass V to GND with a

DD

+

–

1µF ceramic capacitor close to the V pin.

DD

SDO , SDO (Pins 14, 13): Serial Data Output. The con-

version result is shifted MSB first on each falling edge of

+

–

A

IN

, A (Pins 6, 7): Analog Differential Input Pins. Full-

IN

+

–

SCK. The result is output differentially on SDO and SDO .

Thesepinsmustbedifferentiallyterminatedbyanexternal

100Ω resistor at the receiver (FPGA).

+

–

scale range (A to A ) is REFOUT voltage. These pins

IN

can be driven from V to GND.

DD

CNV (Pin 9): Convert Input. This pin, when high, defines

the sampling phase. When this pin is driven low, the con-

version phase is initiated and output data is clocked out.

+

–

SCK , SCK (Pins 16, 15): Serial Data Clock Input. The

falling edge of this clock shifts the conversion result MSB

+

–

first onto the SDO pins. Drive SCK and SCK with a dif-

ferentialclock.Thesepinsmustbedifferentiallyterminated

by an external 100Ω resistor at the receiver (ADC).

This input pin is a TTL style input typically driven at OV

DD

levels with a low jitter pulse, but it is bound to V levels.

DD

This pin is unaffected by the CMOS/LVDS pin.

CMOS/LVDS (Pin 10): I/O mode select. Ground this pin

to enable CMOS mode, tie to OV to enable LVDS mode.

DD

Float this pin to enable low power LVDS mode.

231116fa

10

For more information www.linear.com/LTC2311-16

LTC2311-16

FUNCTIONAL BLOCK DIAGRAM

CMOS I/O Mode

V

A

DD

4

6

LDO

+

IN

+

–

LVDS/CMOS

TRI-STATE

SERIAL OUTPUT

+

SDO

16-BIT

SAR ADC

14

S/H

A

–

7

3

GND

1, 5, 8, 11, 17

OV

12

10

DD

REFOUT

1.25V REF

G

CMOS/LVDS

REFIN

2

9

+

CNV

SCK

TIMING CONTROL

LOGIC

LVDS/CMOS

RECEIVERS

16

231116 BDa

LVDS I/O Mode

V

A

DD

4

6

LDO

+

IN

+

SDO

+

–

LVDS/CMOS

TRI-STATE

SERIAL OUTPUT

14

13

16-BIT

SAR ADC

–

SDO

S/H

A

–

7

3

GND

1, 5, 8, 11, 17

OV

12

10

DD

REFOUT

1.25V REF

G

CMOS/LVDS

REFIN

2

9

+

SCK

16

15

CNV

TIMING CONTROL

LOGIC

LVDS/CMOS

RECEIVERS

–

SCK

231116 BDb

231116fa

11

For more information www.linear.com/LTC2311-16

LTC2311-16

TIMING DIAGRAM

CMOS, LVDS I/O Modes

ACQUISITION

CONVERSION AND READOUT

ACQUISITION

CNV

SCK

HI-Z

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

SDO

231116 TD

SERIAL DATA BITS B[15:0] CORRESPOND TO PREVIOUS CONVERSION

231116fa

12

For more information www.linear.com/LTC2311-16

LTC2311-16

APPLICATIONS INFORMATION

OVERVIEW

with binary-weighted fractions of the reference voltage

(e.g., V

/2, V

/4 … V

/65536) using a

REFOUT

The LTC2311-16 is a low noise, high speed 16-bit succes-

sive approximation register (SAR) ADC with differential

inputs and a wide input common mode range. Operating

from a single 3.3V or 5V supply, the LTC2311-16 has an

differentialcomparator.Attheendofconversion,theCDAC

output approximates the sampled analog input. The ADC

control logic then prepares the 16-bit digital output code

for serial transfer.

8V differential input range, making it ideal for applica-

P-P

tionswhichrequireawidedynamicrange.TheLTC2311-16

achieves 3LSB INL typical, no missing codes at 16 bits

and 81dB SNR typical.

TRANSFER FUNCTION

The LTC2311-16 digitizes the full-scale voltage of 2 ×

16

REFOUT into 2 levels, resulting in an LSB size of

The LTC2311-16 has an onboard reference buffer and low

drift (20ppm/°C max) 4.096V temperature-compensated

reference. The LTC2311-16 also has a high speed SPI-

compatible serial interface that supports CMOS or LVDS.

The fast 5Msps throughput with one-cycle latency makes

the LTC2311-16 ideally suited for a wide variety of high

speedapplications.TheLTC2311-16dissipatesonly50mW

operating at a 5V supply. Nap and sleep modes are also

providedtoreducethepowerconsumptionoftheLTC2311-

16 during inactive periods for further power savings.

125µV with REFOUT = 4.096V. The ideal transfer function

is shown in Figure 2. The output data is in 2’s comple-

ment format.

Analog Input

The differential inputs of the LTC2311-16 provide great

flexibility to convert a wide variety of analog signals with

no configuration required. The LTC2311-16 digitizes the

difference voltage between the A and A pins while

+

–

IN

supporting a wide common mode input range. The analog

input signals can have an arbitrary relationship to each

CONVERTER OPERATION

other, provided that they remain between V and GND.

DD

The LTC2311-16 operates in two phases. During the

acquisition phase, the sample capacitor is connected to

The LTC2311-16 can also digitize more limited classes of

analog input signals such as pseudo-differential unipolar/

bipolarandfullydifferentialwithnoconfigurationrequired.

the analog input pins A and A

to sample the dif-

–

+

IN

ferential analog input voltage, as shown in Figure 3. A

falling edge on the CNV pin initiates a conversion. Dur-

ing the conversion phase, the 16-bit CDAC is sequenced

through a successive approximation algorithm for each

input SCK pulse, effectively comparing the sampled input

The analog inputs of the LTC2311-16 can be modeled

by the equivalent circuit shown in Figure 3. The back-to-

back diodes at the inputs form clamps that provide ESD

protection. In the acquisition phase, 10pF (C ) from the

IN

V

DD

011...111

011...110

C

IN

R

15Ω

ON

10pF

A

+

IN

000...001

000...000

111...111

BIAS

VOLTAGE

V

DD

C

IN

R

15Ω

ON

10pF

FSR = +FS – –FS

1LSB = FSR/65535

100...001

231116 F03

–

IN

100...000

–FSR/2

–1

LSB

0

1

LSB

+FSR/2 – 1LSB

INPUT VOLTAGE (V)

231116 F02

Figure 3. The Equivalent Circuit for the Differential

Analog Input of the LTC2311-16

Figure 2. LTC2311-16 Transfer Function

231116fa

13

For more information www.linear.com/LTC2311-16

LTC2311-16

APPLICATIONS INFORMATION

sampling capacitor in series with approximately 15Ω

mode input range relaxes the accuracy requirements of

any signal conditioning circuits prior to the analog inputs.

(R ) from the on-resistance of the sampling switch is

ON

connected to the input. Any unwanted signal that is com-

mon to both inputs will be reduced by the common mode

rejection of the ADC sampler. The inputs of the ADC core

Pseudo-Differential Bipolar Input Range

The pseudo-differential bipolar configuration represents

driving one of the analog inputs at a fixed voltage, typically

draw a small current spike while charging the C capaci-

IN

tors during acquisition.

V

/2, and applying a signal to the other A pin. In this

REF

IN

case the analog input swings symmetrically around the

fixedinputyieldingbipolartwo’scomplementoutputcodes

with an ADC span of half of full-scale. This configuration

is illustrated in Figure 4, and the corresponding transfer

function in Figure 5. The fixed analog input pin need not

Single-Ended Signals

Single-ended signals can be directly digitized by the

LTC2311-16. These signals should be sensed pseudo-

differentially for improved common mode rejection. By

connecting the reference signal (e.g., ground sense) of

be set at V /2, but at some point within the V rails

REF

DD

the main analog signal to the other A pin, any noise or

allowingthealternateinputtoswingsymmetricallyaround

IN

disturbance common to the two signals will be rejected

by the high CMRR of the ADC. The LTC2311-16 flexibility

handles both pseudo-differential unipolar and bipolar sig-

nals, with no configuration required. The wide common

thisvoltage.Iftheinputsignal(A –A )swingsbeyond

+

–

IN

REFOUT/2, valid codes will be generated by the ADC and

must be clamped by the user, if necessary.

V

REF

V

REF

LT1819

LTC2311-16

25Ω

+

–

0V

A

+

REFOUT

REFIN

IN

10µF

V

REF

47pF

10k

V

/2

REF

TO CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

25Ω

+

–

V

/2

REF

–

SDO

SCK

IN

10k

1µF

CNV

231116 F04

Figure 4. Pseudo-Differential Bipolar Application Circuit

ADC CODE

(2’s COMPLEMENT)

32767

16384

A

IN

(A + – A –)

IN IN

–V

–V /2

REF

0

V

REF

/2

V

REF

DOTTED REGIONS AVAILABLE

BUT UNUSED

–16385

–32768

231116 F05

Figure 5. Pseudo-Differential Bipolar Transfer Function

231116fa

14

For more information www.linear.com/LTC2311-16

LTC2311-16

APPLICATIONS INFORMATION

Pseudo-Differential Unipolar Input Range

complement output codes with an ADC span of half of

full-scale. This configuration is illustrated in Figure 6, and

thecorrespondingtransferfunctioninFigure7.Iftheinput

The pseudo-differential unipolar configuration represents

driving one of the analog inputs at ground and applying a

signal (A – A ) swings negative, valid codes will be

+

–

IN

signal to the other A pin. In this case, the analog input

IN

generated by the ADC and must be clamped by the user,

if necessary.

swings between ground and V yielding unipolar two’s

REF

V

REF

LT1818

LTC2311-16

V

REF

25Ω

+

–

0V

A

+

REFOUT

IN

0V

10µF

REFIN

47pF

TO CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

–

A

IN

SDO

SCK

CNV

231116 F06

Figure 6. Pseudo-Differential Unipolar Application Circuit

ADC CODE

(2’s COMPLEMENT)

32767

16384

A

IN

(A + – A –)

IN IN

–V

–V /2

REF

0

V

REF

/2

V

REF

DOTTED REGIONS AVAILABLE

BUT UNUSED

–16385

–32768

231116 F07

Figure 7. Pseudo-Differential Unipolar Transfer Function

231116fa

15

For more information www.linear.com/LTC2311-16

LTC2311-16

APPLICATIONS INFORMATION

Single-Ended-to-Differential Conversion

signal source to eliminate the op amp as the dominant

source of distortion.

Whilesingle-endedsignalscanbedirectlydigitizedaspre-

viously discussed, single-ended to differential conversion

circuits may also be used when higher dynamic range is

desired. By producing a differential signal at the inputs of

the LTC2311-16, the signal swing presented to the ADC is

maximized, thus increasing the achievable SNR.

The LT^®1819 high speed dual operational amplifier is

recommendedforperformingsingle-ended-to-differential

conversions, as shown in Figure 8. In this case, the first

amplifier is configured as a unity-gain buffer and the

single-ended input signal directly drives the high imped-

ance input of this amplifier.

The fully-differential configuration yields an analog input

span (A – A ) of REFOUT. In this configuration, the

+

–

IN

input signal is driven on each A pin, typically at equal

IN

spans but opposite polarity. This yields a high common

mode rejection on the input signals. The common mode

voltageoftheanaloginputcanbeanywherewithintheV

DD

input range, but will be limited by the peak swing of the

full-range input signal. For example, if the internal refer-

ence is used with V = 5V , the full-range input span

DD

DC

will be 4.096V. Half of the input span is typically driven

on each A pin, yielding a signal span for each A pin of

IN

4.096V . This leaves ~0.9V of common mode variation

P-P

tolerance. When using external references, it is possible

to increase common mode tolerance by compressing the

ADC full-range codes into a tighter range. For example,

Fully-Differential Inputs

ToachievethefulldistortionperformanceoftheLTC2311-16,

a low distortion fully-differential signal source driven

through the LT1819 configured as two unity-gain buffers,

as shown in Figure 9, can be used. This circuit achieves a

THDspecificationof–85dBatinputfrequenciesof500kHz

and less. Data sheet typical performance curves are taken

using a harmonic rejection filter between the ADC and the

using an external 2.048V reference with V = 5V the total

DD

span would be 2.048V and each A span would be lim-

IN

ited to 2.048V allowing a common mode range of ~3V.

P-P

Compressing the input span would incur a SNR penalty

of approximately 2dB. Input span compression may be

usefulifsingle-supplyanaloginputdriversareusedwhich

V

REF

LT1819

V

REF

0V

LT1819

V

REF

+

–

0V

V

REF

+

–

0V

V

REF

0V

V

REF

/2

+

–

V

REF

+

–

200Ω

0V

200Ω

231116 F08

231116 F09

Figure 8. Single-Ended to Differential Driver

Figure 9. LT1819 Buffering a Fully-Differential Signal Source

231116fa

16

For more information www.linear.com/LTC2311-16

LTC2311-16

APPLICATIONS INFORMATION

cannotswingrail-to-rail.Thefully-differentialconfiguration

is illustrated in Figure 10, with the corresponding transfer

function illustrated in Figure 11.

is important even for DC inputs, because the ADC inputs

draw a current spike at the start of the acquisition phase.

For best performance, a buffer amplifier should be used to

drive the analog inputs of the LTC2311-16. The amplifier

provides low output impedance to minimize gain error

and allow for fast settling of the analog signal during the

acquisition phase. It also provides isolation between the

signal source and the ADC inputs, which draw a small

current spike during acquisition.

INPUT DRIVE CIRCUITS

A low impedance source can directly drive the high im-

pedance inputs of the LTC2311-16 without gain error. A

high impedance source should be buffered to minimize

settling time during acquisition and to optimize the dis-

tortion performance of the ADC. Minimizing settling time

V

REF

0V

LTC2311-16

25Ω

+

–

0V

A

+

–

REFOUT

REFIN

IN

10µF

47pF

V

REF

0V

REF

TO CONTROL

LOGIC

+

–

0V

SDO

SCK

IN

(FPGA, CPLD,

DSP, ETC.)

CNV

231116 F10

Figure 10. Fully-Differential Application Circuit

ADC CODE

(2’s COMPLEMENT)

32767

16384

A

IN

(A + – A –)

IN

–V

–V /2

REF

0

V

REF

/2

V

REF

–16385

–32768

231116 F11

Figure 11. Fully-Differential Transfer Function

231116fa

17

For more information www.linear.com/LTC2311-16

LTC2311-16

APPLICATIONS INFORMATION

Input Filtering

10µF capacitor should be soldered as close as possible

to the REFOUT pin to minimize wiring inductance. The

REFIN pin produces a 1.25V precision reference which

should also be bypassed with a 10μF (X5R, 0805 size)

ceramic capacitor. The REFIN pin may be overdriven with

an external precision reference as shown in Figure 13a.

The noise and distortion of the buffer amplifier and signal

sourcemustbeconsideredsincetheyaddtotheADCnoise

and distortion. Noisy input signals should be filtered prior

to the buffer amplifier input with a low bandwidth filter

to minimize noise. The simple 1-pole RC lowpass filter

shown in Figure 12 is sufficient for many applications.

5V TO 13.2V

LTC6655-1.25V

V

REFIN

LTC2311-16

IN

OUT_F

V

OUT_S

SINGLE-ENDED

INPUT SIGNAL

SHDN

10µF

0.1µF

+

50Ω

IN

LTC2311

–

IN

3.3nF

REFOUT

SINGLE-ENDED

TO DIFFERENTIAL

DRIVER

231116 F12

BW = 1MHz

GND

231116 F13a

Figure 12. Input Signal Chain

Figure 13a. LTC2311-16 with an External REFIN Voltage

Table 1. Internal Reference with Internal Buffer

The input resistor divider network, sampling switch on-

resistance (R ) and the sample capacitor (C ) form a

secondlowpassfilterthatlimitstheinputbandwidthtothe

ADC core to 110MHz. A buffer amplifier with a low noise

density must be selected to minimize the degradation of

the SNR over this bandwidth.

ON

IN

FULLY

BIPOLAR

DIFFERENTIAL

UNIPOLAR

INPUT

V

DD

REFIN REFOUT INPUT RANGE INPUT RANGE

RANGE

5V 1.25V 4.096V

3.3V 1.25V 2.048V

4.096V

2.048V

0V to 4.096V

0V to 2.048V

2.048V

1.024V

Highqualitycapacitorsandresistorsshouldbeusedinthe

RCfilterssincethesecomponentscanadddistortion.NPO

and silver mica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occurduringsoldering.Metalfilmsurfacemountresistors

are much less susceptible to both problems.

Table 2. External Reference with Internal Buffer

REFIN

FULLY

BIPOLAR

INPUT

(OVER-

DIFFERENTIAL

UNIPOLAR

V

DRIVEN) REFOUT INPUT RANGE INPUT RANGE

RANGE

DD

5V

1V

3.3V

4.096V

4.7V

3.3V

4.096V

4.7V

0V to 3.3V

0V to 4.096V

0V to 4.7V

0V to 1.65V

0V to 2.048V

0V to 3V

1.65V

2.048V

2.35V

0.825V

1.024V

1.5V

1.25V

1.45V

1V

3.3V

1.65V

2.048V

3V

1.65V

2.048V

3V

1.25V

1.85

ADC REFERENCE

Internal Reference

Table 3. External Reference Unbuffered

The LTC2311-16 has an on-chip, low noise, low drift

(20ppm/°Cmax),temperaturecompensatedbandgapref-

erence that is internally buffered and is available at REFIN

(Pin 2). The internal reference buffer gains the REFIN pin

voltage (1.25V) to REFOUT (pin 3) and is 4.096V for a 5V

supply and 2.048V for 3.3V supply. Bypass REFOUT to

GND with a 10μF (X5R, 0805 size) ceramic capacitor. The

FULLY

BIPOLAR

INPUT

DIFFERENTIAL

UNIPOLAR

V

REFIN REFOUT INPUT RANGE INPUT RANGE RANGE

DD

5V

0V

0.5V

5V

0.5V

5V

0V to 0.5V

0V to 5V

0.25V

2.5V

3.3V

0.5V

3.3V

0.5V

3.3V

0V to 0.5V

0V to 3.3V

0.25V

1.65V

231116fa

18

For more information www.linear.com/LTC2311-16

LTC2311-16

APPLICATIONS INFORMATION

External Reference

will affect the accuracy of the output code. Due to the

one-cycle conversion latency, the first conversion result

at the beginning of a burst sampling period will be invalid.

If an external reference is used to buffer/drive the REFOUT

pin, the fast settling LTC6655 reference is recommended.

The internal reference buffer can also be overdriven from

1.25V to 5V with an external reference at REFOUT as

shown in Figure 13b. In this configuration, REFIN must

be grounded to disable the internal reference buffer. A

55kΩ internal resistance loads the REFOUT pin when

the reference buffer is disabled. To maximize the input

signal swing and corresponding SNR, the LTC6655-5 is

recommendedwhenoverdrivingREFOUT.TheLTC6655-5

offers the same small size, accuracy, drift and extended

temperature range as the LTC6655-4.096. By using a 5V

reference, a higher SNR can be achieved. We recommend

bypassing the LTC6655-5 with a 10μF ceramic capacitor

(X5R, 0805 size) as close as possible to the REFOUT pin.

CNV

IDLE

PERIOD

231116 F14

Figure 14. CNV Waveform Showing Burst Sampling

35000

30000

25000

20000

15000

10000

5000

REFIN

LTC2311-16

5V TO 13.2V

LTC6655-4.096

0

V

REFOUT

IN

OUT_F

V

OUT_S

–5000

SHDN

0.1µF

100

0

200

10µF

TIME (ns)

231116 F15

GND

Figure 15. Transient Response of the LTC2311-16

231116 F13b

DYNAMIC PERFORMANCE

Figure 13b. LTC2311-16 with an External REFOUT Voltage

Fast Fourier transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. By applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2311-16 provides

guaranteed tested limits for both AC distortion and noise

measurements.

Internal Reference Buffer Transient Response

TheREFOUTpinoftheLTC2311-16drawscharge(Q

)

CONV

from the external bypass capacitors during each conver-

sion cycle. If the internal reference buffer is overdriven,

the external reference must provide all of this charge

with a DC current equivalent to I

= Q

/t

.

REFOUT

CONV CYC

Thus, the DC current draw of REFOUT depends

on the sampling rate and output code. In applications

where a burst of samples is taken after idling for long

Signal-to-Noise and Distortion Ratio (SINAD)

The signal-to-noise and distortion ratio (SINAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is bandlimited

tofrequenciesfromaboveDCandbelowhalfthesampling

periods, as shown in Figure 14 , I

quickly goes from

REFOUT

approximately~75µAtoamaximumof700µAforREFOUT

= 5V at 5Msps. This step in DC current draw triggers a

transient response in the external reference that must be

considered since any deviation in the voltage at REFOUT

231116fa

19

For more information www.linear.com/LTC2311-16

LTC2311-16

APPLICATIONS INFORMATION

frequency. Figure16showsthattheLTC2311-16achieves

a typical SINAD of 81dB at a 5MHz sampling rate with a

2.2MHz input.

POWER CONSIDERATIONS

The LTC2311-16 requires two power supplies: the 5V

power supply (V ), and the digital input/output interface

DD

power supply (OV ). The flexible OV supply allows

DD

0

SNR = 81.6dB

the LTC2311-16 to communicate with any digital logic

THD = –90dB

–20

operating between 1.8V and 2.5V. When using LVDS I/O,

SINAD = 81.1dB

SFDR = 96dB

the OV supply must be set to 2.5V.

DD

–40

–60

–80

Power Supply Sequencing

The LTC2311-16 does not have any specific power sup-

ply sequencing requirements. Care should be taken to

adhere to the maximum voltage relationships described

in the Absolute Maximum Ratings section. The LTC2311-

16 has a power-on-reset (POR) circuit that will reset the

LTC2311-16 at initial power-up or whenever the power

supply voltage drops below 2V. Once the supply voltage

re-enters the nominal supply voltage range, the POR will

reinitialize the ADC. No conversions should be initiated

until 10ms after a POR event to ensure the reinitialization

period has ended. Any conversions initiated before this

time will produce invalid results.

–100

–120

–140

0

0.5

1

1.5

2

2.5

FREQUENCY (MHz)

231116 F16

Figure 16. 32k Point FFT of the LTC2311-16

Signal-to-Noise Ratio (SNR)

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 16 shows

that the LTC2311-16 achieves a typical SNR of greater

than 81dB at a 5MHz sampling rate with a 2.2MHz input.

10

9

8

Total Harmonic Distortion (THD)

8

Totalharmonicdistortion(THD)istheratiooftheRMSsum

ofallharmonicsoftheinputsignaltothefundamentalitself.

The out-of-band harmonics alias into the frequency band

7

6

between DC and half the sampling frequency (f

THD is expressed as:

/2).

SMPL

5

0

1

2

3

4

5

SAMPLE FREQUENCY (Msps)

231116 G16

V2²+ V3²+ V4²+…+ VN²

THD=20log

Figure 17. Power Supply Current of the LTC2311-16

Versus Sampling Rate

V1

where V1 is the RMS amplitude of the fundamental

frequency and V2 through VN are the amplitudes of the

second through Nth harmonics. The THD specifications

for the LTC2311-16 consider the first seven harmonics

(i.e. N=7). Figure 16 shows that the LTC2311-16 achieves

a typical THD of –90dB at a 5MHz sampling rate with a

2.2MHz input.

231116fa

20

For more information www.linear.com/LTC2311-16

LTC2311-16

APPLICATIONS INFORMATION

TIMING AND CONTROL

incurred to allow the reference and power systems to

become valid. To enter nap mode on the LTC2311-16,

the SCK signal must be held high or low and a series of

two CNV pulses must be applied. This is the case for both

CMOS and LVDS modes. The second rising edge of CNV

initiates the nap state. The nap state will persist until either

asinglerisingedgeofSCKisapplied,orfurtherCNVpulses

are applied. The SCK rising edge will put the LTC2311-16

back into the operational (full-power) state. When in nap

mode, two additional pulses will put the LTC2311-16 in

sleep mode. When configured for CMOS I/O operation, a

single rising edge of SCK can return the LTC2311-16 into

operational mode. A 10ms delay is necessary after exiting

sleep mode to allow the reference buffer to recharge the

external filter capacitor. In LVDS mode, exit sleep mode

by supplying a fifth CNV pulse. The fifth pulse will return

the LTC2311-16 to operational mode, and further SCK

pulses will keep the part from re-entering nap and sleep

modes. The fifth SCK pulse also works in CMOS mode

as a method to exit sleep. In the absence of SCK pulses,

repetitive CNV pulses will cycle the LTC2311-16 between

operational, nap and sleep modes indefinitely.

CNV Timing

The LTC2311-16 sampling and conversion is controlled

by CNV. A rising edge on CNV will start sampling and the

fallingedgestartstheconversionandreadoutprocess.The

conversion process is timed by the SCK input clock. For

optimum performance, CNV should be driven by a clean

low jitter signal. The Typical Application at the back of the

data sheet illustrates a recommended implementation to

reduce the relatively large jitter from an FPGA CNV pulse

source.Notethelowjitterinputclocktimesthefallingedge

of the CNV signal. The rising edge jitter of CNV is much

less critical to performance. The typical pulse width of the

CNV signal is 30ns at a 5Msps conversion rate.

SCK Serial Data Clock Input

The falling edge of this clock shifts the conversion result

MSBfirstontotheSDOpins.A105MHzexternalclockmust

be applied at the SCK pin to achieve 5Msps throughput.

Nap/Sleep Modes

RefertothetimingdiagramsinFigure18,Figure19,Figure20

and Figure 21 for more detailed timing information about

sleep and nap modes.

Nap mode is a method to save power without sacrificing

power-updelaysforsubsequentconversions. Sleepmode

has substantial power savings, but a power-up delay is

CNV

1

2

NAP MODE

FULL POWER MODE

SCK

SDO

HOLD STATIC HIGH OR LOW

Z

WAKE ON 1ST SCK EDGE

Z

231116 F18

Figure 18. CMOS and LVDS Mode NAP and WAKE Using SCK

231116fa

21

For more information www.linear.com/LTC2311-16

LTC2311-16

APPLICATIONS INFORMATION

REFOUT

RECOVERY

REFOUT

4.096V

t

WAKE

CNV

1

2

3

4

NAP MODE

SLEEP MODE

FULL POWER MODE

SCK

SDO

HOLD STATIC HIGH OR LOW

WAKE ON 1ST SCK EDGE

Z

231116 F19

Figure 19. CMOS Mode SLEEP and WAKE Using SCK

REFOUT

RECOVERY

REFOUT

4.096V

t

WAKE

WAKE ON 5TH

CSB EDGE

CNV

1

2

3

4

5

NAP MODE

SLEEP MODE

FULL POWER MODE

SCK

SDO

HOLD STATIC HIGH OR LOW

Z

231116 F20

Figure 20. LVDS and CMOS Mode SLEEP and WAKE Using CNV

t

DSCKLCNVH

CNVH

CNV

t

SCK

DCNVSDOZ

DCNVSCKL

2

SCKL

6

SCKH

1

3

4

5

7

8

9

10

11

12

13

14

15

16

SCK

t

DCNVSDOV

HI-Z

SDO

HI-Z

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

t

DSCKSDOV

HSDO

t

ACQ

t

CONV

t

CYC

SERIAL DATA BITS B[15:0] CORRESPOND TO PREVIOUS CONVERSION

231116 F21

Figure 21. LTC2311-16 Timing Diagram, CMOS, LVDS I/O Modes

231116fa

22

For more information www.linear.com/LTC2311-16

LTC2311-16

APPLICATIONS INFORMATION

DIGITAL INTERFACE

BOARD LAYOUT

The LTC2311-16 features a serial digital interface that

To obtain the best performance from the LTC2311-16, a

four layer printed circuit board is recommended. Layout

for the printed circuit board (PCB) should ensure the

digital and analog signal lines are separated as much as

possible. In particular, care should be taken not to run

any digital clocks or signals adjacent to analog signals or

underneath the ADC.

is simple and straightforward to use. The flexible OV

DD

supply allows the LTC2311-16 to communicate with any

digital logic operating between 1.8V and 2.5V. A 105MHz

external clock must be applied at the SCK pin to achieve

5Msps throughput.

In addition to a standard CMOS SPI interface, the

LTC2311-16 provides an optional LVDS SPI interface to

support low noise digital design. The CMOS/LVDS pin is

used to select the digital interface mode.

A single solid ground plane is used. Bypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

ADC. The analog input traces are screened by ground.

ThefallingedgeofSCKoutputstheconversionresultMSB

+

first on the SDO pins. In CMOS mode, use the SDO pin

+

as the serial data output and the SCK pin as the serial

Reference Design

–

clock input. Do not connect the SDO and SCK pins as

they have internal pull-downs to GND.

Foradetailedlookatthereferencedesignforthisconverter,

including schematics and PCB layout, please refer to the

DC2425, the evaluation kit for the LTC2311-16.

+

–

In LVDS mode, use the SDO /SDO pins as a differential

output. These pins must be differentially terminated by an

+

external 100Ω resistor at the receiver (FPGA). The SCK /

–

SCK pins are a differential input and must be terminated

differentially by an external 100Ω resistor at the receiver

(ADC), see Figure 22.

LTC2311-16

FPGA OR DSP

2.5V

OV

DD

+

SDO

+

–

100Ω

–

+

SDO

SCK

2.5V

+

–

100Ω

CMOS/LVDS

–

SCK

CNV

231116 F22

Figure 22. LTC2311-16 Using the LVDS Interface

231116fa

23

For more information www.linear.com/LTC2311-16

LTC2311-16

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC2311-16#packaging for the most recent package drawings.

MSE Package

16-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1667 Rev F)

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.845 ±0.102

(.112 ±.004)

2.845 ±0.102

(.112 ±.004)

0.889 ±0.127

(.035 ±.005)

1

8

0.35

REF

5.10

(.201)

MIN

1.651 ±0.102

(.065 ±.004)

1.651 ±0.102

(.065 ±.004)

3.20 – 3.45

(.126 – .136)

0.12 REF

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

DETAIL “B”

16

9

0.305 ±0.038

0.50

(.0197)

BSC

NO MEASUREMENT PURPOSE

4.039 ±0.102

(.159 ±.004)

(NOTE 3)

(.0120 ±.0015)

TYP

0.280 ±0.076

(.011 ±.003)

RECOMMENDED SOLDER PAD LAYOUT

16151413121110

9

REF

DETAIL “A”

0.254

(.010)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

0° – 6° TYP

4.90 ±0.152

(.193 ±.006)

GAUGE PLANE

0.53 ±0.152

(.021 ±.006)

1 2 3 4 5 6 7 8

DETAIL “A”

0.86

(.034)

REF

1.10

(.043)

MAX

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 ±0.0508

(.004 ±.002)

MSOP (MSE16) 0213 REV F

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL

NOT EXCEED 0.254mm (.010") PER SIDE.

231116fa

24

For more information www.linear.com/LTC2311-16

LTC2311-16

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

07/16 Updated the max value for REFOUT Short-Circuit Current

Removed power consumption max values

4

6

7

Changed the note for t

DSCKSDOV

231116fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

25

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC2311-16

LTC2311-16

TYPICAL APPLICATION

Low Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Retiming Flip-Flop

V

CC

NC7SVUO4P5X

0.1µF

1k

MASTER_CLOCK

V

CC

50Ω

1k

D

PRE

NC7SV74KBX

CONV

Q

CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

CLR

CONV ENABLE

CNV

SCK

LTC2311-16

CMOS/LVDS

NC7SVUO4P5X

GND

10Ω

SDO

231116 TA02

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PART NUMBER

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DESCRIPTION

COMMENTS

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2.5V Supply, Differential Input, 96.2dB SNR, 5V Input Range, DGC,

Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

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OUT

LTC2602/LTC2612/

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Precision Low Drift, Low Noise Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm

Peak-to-Peak Noise, MSOP-8 Package

LTC6652

Precision Low Drift, Low Power Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 5ppm/°C, 2.1ppm

Peak-to-Peak Noise, MSOP-8 Package

Amplifiers

LT1818/LT1819

400MHz, 2500V/µs, 9mA Single/Dual Operational

Amplifiers

–85dBc Distortion at 5MHz, 6nV/√Hz Input Noise Voltage, 9mA Supply

Current, Unity-Gain Stable

LT1806

LT6200

325MHz, Single, Rail-to-Rail Input and Output, Low –80dBc Distortion at 5MHz, 3.5nV/√Hz Input Noise Voltage,

Distortion, Low Noise Precision Op Amps 9mA Supply Current, Unity-Gain Stable

165MHz, Rail-to-Rail Input and Output, 0.95nV/√Hz Low Noise, Low Distortion, Unity-Gain Stable

Low Noise, Op Amp Family

231116fa

LT 0716 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

26

For more information www.linear.com/LTC2311-16

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2311-16

●

 LINEAR TECHNOLOGY CORPORATION 2016


型号：	LTC2323-12
厂家：	Linear
描述：	16-Bit, 5Msps Differential Input ADC with Wide Input Common Mode Range
文件：	总26页 (文件大小：885K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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