LTC2373 [Linear]
16-Bit/18-Bit, 1.6Msps/1Msps/500ksps 8-Channel, SAR ADCs;型号: | LTC2373 |
厂家: | Linear |
描述: | 16-Bit/18-Bit, 1.6Msps/1Msps/500ksps 8-Channel, SAR ADCs |
文件: | 总12页 (文件大小:1442K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DEMO MANUAL DC2071A
LTC2374/LTC2373/LTC2372
16-Bit/18-Bit, 1.6Msps/1Msps/500ksps
8-Channel, SAR ADCs
DESCRIPTION
Demonstrationcircuit2071AfeaturestheLTC®2373family.
TheLTC2374/LTC2373/LTC2372arelownoise,highspeed,
8-channel, 16-/18-bit successive approximation register
(SAR) ADCs. The following text refers to the LTC2373-18
but applies to all parts in the family, the only differences
being the number of bits and the maximum sample rate.
Operating from a single 5V supply, the LTC2373-18 has a
highly configurable, low crosstalk, 8-channel input multi-
plexer,supportingfullydifferential,pseudo-differentialuni-
polar and pseudo-differential bipolar analog input ranges.
performance such as peak-to-peak noise and DC linearity.
Use the DC890 if precise sampling rates are required or to
demonstrate AC performance such as SNR, THD, SINAD
and SFDR. The demonstration circuit 2071 is intended to
demonstraterecommendedgrounding,componentplace-
ment and selection, routing and bypassing for this ADC.
Several suggested driver circuits for the analog inputs
will be presented.
Design files for this circuit board, including the
schematic and BOM, are available at
http://www.linear.com/demo/DC2071A
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
QuikEval and PScope are trademarks of Linear Technology Corporation. All other trademarks are
the property of their respective owners.
The DC2071 demonstrates the DC and AC performance of
theLTC2373-18inconjunctionwiththeDC590andDC890
data collection boards. Use the DC590 to demonstrate DC
ASSEMBLY OPTIONS
Table 1. DC2071A Assembly Options
Assembly Version
DC2071A-A
DC2071A-B
DC2071A-C
DC2071A-D
DC2071A-E
U1 Part Number
LTC2373CUH-18
LTC2372CUH-18
LTC2374CUH-16
LTC2373CUH-16
LTC2372CUH-16
Max Conversion Rate
1Msps
Number of Bits
Max CLK IN Frequency
62MHz
18
18
16
16
16
0.5Msps
31MHz
1.6Msps
86.4MHz
1Msps
50MHz
0.5Msps
25MHz
dc2071afc
1
DEMO MANUAL DC2071A
BOARD PHOTO
DEFAULT INPUT LEVELS
–ꢀ6V GND +ꢀ6V
0V TO 4.096V
0V TO 4.096V
A
±±.ꢀ9ꢁV
0V TO 4.096V
±4.096V
DC±90
DC590
OR
DCꢁ0ꢁ6
±4.096V
CLK
ꢀ00MHz MAX
3.3V
PP
Figure 1. DC2071A Connection Diagram
dc2071afc
2
DEMO MANUAL DC2071A
DC890 QUICK START PROCEDURE
Check to make sure that all switches and jumpers are
set as shown in the connection diagram of Figure 1. The
default connections configure the ADC to use the onboard
referenceandregulatorstogeneratetherequiredcommon
mode voltages. The analog input is DC coupled. Connect
the DC2071A to a DC890 USB High Speed Data Collec-
tion Board using connector P1. Then, connect the DC890
to a host PC with a standard USB A/B cable. Apply 16V
to the indicated terminals. Then apply a low jitter signal
source to J2–J7. Observe the recommended input voltage
Run the PScope™ software (Pscope.exe version K88 or
later) which can be downloaded from www.linear.com/
designtools/software.
Complete software documentation is available from the
Help menu. Updates can be downloaded from the Tools
menu. Check for updates periodically as new features
may be added.
The PScope software should recognize the DC2071A and
configure itself automatically.
range for each analog input. Connect a low jitter 2.5V
PP
Click the Collect button (See Figure 7) to begin acquiring
data. The Collect button then changes to Pause, which
can be clicked to stop data acquisition.
sine wave or square wave to connector J1. See Table 1
for the appropriate clock frequency. Note that J1 has a
50Ω termination resistor to ground.
DC590 QUICK START PROCEDURE
IMPORTANT! To avoid damage to the DC2071A,
make sure that VCCIO (JP6) of the DC590 is set to
3.3V before connecting the DC590 to the DC2071A.
ribbon cable. Apply a signal source to J2-J7. No clock
is required on J1 when using the DC590. The clock is
provided by the DC590.
Run the QuikEval™ software (quikeval.exe version K109
or later) which is available from www.linear.com/design-
tools/software. The correct control panel will be loaded
automatically. Click the Collect button (Figure 10) to begin
reading the ADC.
To use the DC590 with the DC2071A, it is necessary to
apply 16V and ground to the 16V and GND terminals
on the DC2071A. Connect the DC590 to a host PC with a
standardUSBA/Bcable.ConnecttheDC2071AtoaDC590
USB serial controller using the supplied 14-conductor
dc2071afc
3
DEMO MANUAL DC2071A
DC2071A SETUP
DC Power
desired, the LTC6655-4.096 reference (U9) can be used
by setting the REF jumper (JP1) to the EXT position and
installing a 0Ω resistor in the R19 position.
The DC2071A requires 16VDC and draws +100mA/
–40mA. Most of the supply current is consumed by the
CPLD,opamps,regulatorsanddiscretelogicontheboard.
The+16VDCinputvoltagepowerstheADCthroughLT1763
regulators which provide protection against accidental
reverse bias. Additional regulators provide power for the
CPLD and op amps. See Figure 1 for connection details.
Analog Inputs
The four default driver circuits for the analog inputs of the
LTC2373-18 on the DC2071A are shown in Figures 2 to 5.
The circuit of Figure 2 is a fully differential driver with
0V to 4.096V inputs. The output of this circuit is band
limited to approximately 13MHz. The circuit of Figure 3
is a single-ended to differential driver with an input signal
range of 8.192V. This circuit is band limited to 1.6MHz
at the output. The circuit of Figure 4 is a single-ended to
differential driver with an input range of 0V to 4.096V. The
output bandwidth of this circuit is 1.6MHz. The circuit of
Figure 5 is a single-ended/fully differential input driver
circuit with an input range of 4.096V. The input band-
width of this circuit is 4.8kHz. The output is band limited
Clock Source
You must provide a low jitter 2.5V sine or square wave
PP
to the clock input, J1. The clock input is AC coupled so the
DC level of the clock signal is not important. A generator
like the Rohde & Schwarz SMB100A high speed clock
source is recommended. Even a good generator can start
to produce noticeable jitter at low frequencies. Therefore
it is recommended for lower sample rates to divide down
a higher frequency clock to the desired sample rate. The
ratio of clock frequency to conversion rate is 62:1 for
18-bit parts and 50:1 or 54:1 for 16-bit parts. If the clock
input is to be driven with logic, it is recommended that the
49.9Ωterminator(R3)beremoved.Slowrisingedgesmay
to 3MHz. The default for this circuit is single-ended drive.
–
Drive the A
input to 4.096V. Alternatively, by remov-
IN4
ing R117 and changing R114 to 100Ω this circuit can be
driven fully differentially.
compromise the SNR of the converter in the presence of The A and A driver circuits can be DC or AC coupled.
high-amplitude higher frequency input signals.
IN1
IN3
The default setting is DC coupled. AC coupling the inputs
may degrade the distortion performance of the ADC due
tononlinearityofthecouplingcapacitors. ACcouplingcan
be implemented on the DC2071A by putting the coupling
Data Output
Parallel data output from this board (0V to 2.5V default),
if not connected to the DC890, can be acquired by a logic
analyzer and subsequently imported into a spreadsheet or
mathematical package depending on what form of digital
signal processing is desired. Alternatively, the data can
be fed directly into an application circuit. Use pin-50 of
P1 to latch the data. The data should be latched using the
positive edge of this signal. The data output signal levels
at P1 can also be increased to 0V to 3.3V if the application
circuit requires a higher voltage. This is accomplished by
moving JP3 to the 3.3V position.
jumpers (JP6, JP8 for A and JP7 for A ) in the AC
IN1
IN3
position,andaddingtwo1kΩresistorsattheoptionalresis-
tor locations on the other side of each coupling capacitor
(R91, R97, R106, R110 for A and R93, R100 for A ).
IN1
IN3
Another option available on the demo board is to drive
eachinputsingle-endedandthenconvertthesingle-ended
inputs to fully differential at the MUX outputs. This allows
the user to have eight single-ended inputs but still have
the SNR of a fully differential input. To accomplish this,
remove C31, R8, R15 and R128 then add C15, C24, C27,
C29, R7, R13, R16, R17, R18, R129, R130, R131 and
U7. The values for the passive devices are shown in the
schematic of Figure 6.
Reference
The default reference is the LTC2373-18 internal 4.096V
reference. Alternatively, if an external reference voltage is
dc2071afc
4
DEMO MANUAL DC2071A
DC2071A SETUP
CM2
+
V
C74
C77
10µF
6.3V
10µF
6.3V
R91
R92
OPT
R94
0Ω
R95
24.9Ω
C75
OPT
8
J2
+
A
0.1µF
IN1
5
6
R96
10Ω
0V TO
4.096V
+
C79
OPT
1206
BNC
7
R97
OPT
C80
15pF
LT6237
CH0
U24B
–
C82
4
0.1µF
3
2 1
JP6
+IN1
COUPLING
–
V
AC DC
R101
24.9Ω
C84
OPT
R137
OPT
C86
OPT
CM2
C89
10µF
6.3V
R104
24.9Ω
C91
10µF
6.3V
R106
OPT
R109
0Ω
J3
–
A
IN1
4
0V TO
4.096V
2
3
C92
OPT
1206
R105
10Ω
BNC
–
+
R110
OPT
1
R107
24.9Ω
LT6237
CH1
U24A
C90
15pF
R108
OPT
8
3
2 1
JP8
–IN1
AC DC
COUPLING
Figure 2. 0V to 4.096V Fully Differential AC/DC Coupled Driver
+
OP AMP
C93
10µF
25ꢀ
R112
0Ω
ꢀCM
CH2
J4
0±05
±
3
A
IN2
±±.192ꢀ
R134
20Ω
R113
0Ω
+
–
LT5400-4
BNC
R1
R2
R3
R4
EP
1
2
3
4
±
7
6
5
1
C96
OPT
LT1469
4
C105
0.01µF
C0G
R132, 20Ω
R133, 20Ω
2
U25A
R116
20K
R120
4.99K
C99
10µF
6.3ꢀ
R121
0Ω
C9±
10µF
25ꢀ
CH3
±
5
+
0±05
R135
20Ω
9
7
–
OP AMP
LT1469
4
6
U25B
–
C106
0.01µF
C0G
R125
20K
R126
10K
C102
0.01µF
C0G
Figure 3. ±±.192V Singleꢀ-nded to Differential DC Coupled Driver
dc2071afc
5
DEMO MANUAL DC2071A
DC2071A SETUP
+
V
C72
1µF
C73
0.1µF
CM2
C76
10µF
6.3V
C78
10µF
6.3V
3
+
7
R93
OPT
V
SHDN
R98
0Ω
J5
R99
10Ω
A
IN3
8
+
IN1
+
–
0V TO
4
CH5
CH4
C81
OPT
1206
OUT1
4.096V
BNC
R100
OPT
C83
15pF
1
–
IN1
LT6350
3
2 1
CM
JP7
IN3
COUPLING
R103
10Ω
R102
499Ω
–
+
AC DC
5
OUT2
U27
2
+
IN2
C85
1µF
–
V
6
C87
10µF
6.3V
C88
0.1µF
–
V
Figure 4. 0V to 4.096V Singleꢀ-nded to Differential AC/DC Coupled Driver
C107
0.01µF
R111
1k
VDD
C95
C94
0.1µF
4.7µF
R114
0Ω
R115
1k
10V
J6
J7
+
A
IN4
R118
4.096V
35.7Ω
BNC
BNC
3
C97
+
CH6
CH7
V
8
1
7
0.22µF
C0G
R117
150Ω
+
5
SHDN
LTC6362
–
1812
+
4
R119
35.7Ω
V
OCM
–
–
2
CM
R112
100Ω
R123
1k
V
6
–
U28
A
IN4
4.096V
C100
C101
10µF
6.3V
R124
OPT
0.22µF
C0G
1812
R127
1k
C108
0.01µF
Figure 5. Singleꢀ-nded/Fully Differential Input to Fully Differential DC Coupled Driver
dc2071afc
6
DEMO MANUAL DC2071A
DC2071A SETUP
C6
0.1µF
C7
REFBUF
10µF
25V
0805
E1
REFBUF
BUFOUT
C13
47µF
10V
V
DD
V
CCI0
1210
X7R
8
C10
5
6
C12
0.1µF
10µF
25V
C11
0.1µF
+
7
LT6237
0805
U7B
–
REF
CH0
C8
R129
1k
R7
24.9Ω
4
1
2
3
INT
C9
OPT
1200pF
C19
4.7µF
EXT
C15
1000pF
JP1
CH1
CH2
CH3
CH4
CH5
CH6
CH7
C14
1200pF
R130
0Ω
R131
0Ω
C16
OPT
C17
OPT
31
32
1
2
7
8
9
10
30
16
21
20
22
19
+
–
CH0
CNV
SCK
SDI
SDO
BUSY
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
C20
OPT
LTC237X
24
18
RESET
RDL
C21
3300pF
C22
3300pF
C23
3300pF
R11
1k
R12
1k
U1
C24
1000pF
C25
1500pF
C26
OPT
C27
0.1µF
+
V
R13
0Ω
C28
1500pF
R16
24.9Ω
8
3
2
CM
+
–
1
R17
1k
LT6237
U7A
BUFOUT
C29
4
C103
25pF
0.1µF
–
V
R18
1k
C104
25pF
Figure 6. -ight Singleꢀ-nded Inputs Converted to Fully Differential
dc2071afc
7
DEMO MANUAL DC2071A
DC2071A SETUP
DC±90 Data Collection
at a frequency of approximately 1kHz. The input signal
level is approximately –1dBFS. A typical FFT obtained
with DC2071A is shown in Figure 7. Note that to calculate
the real SNR, the signal level (F1 amplitude = –1.001dB)
has to be added back to the SNR that PScope displays.
With the example shown in Figure 7 this means that the
actualSNRwouldbe100.60dBinsteadofthe99.60dBthat
PScope displays. Taking the RMS sum of the recalculated
SNRandtheTHDyieldsaSINADof100.4dBwhichisfairly
close to the typical number for this ADC.
ForSINAD,THDorSNRtesting,alownoise,lowdistortion
generatorsuchastheB&KType1051orStanfordResearch
SR1 should be used. A low jitter RF oscillator such as the
Rohde & Schwarz SMB100A or DC1216A-A high speed
clock source is used to drive the clock input. This demo
board is tested in-house by attempting to duplicate the
FFT plot shown in the Typical Performance Characteristics
section of the LTC2373-18 data sheet. This involves using
a 62MHz clock source, along with a sinusoidal generator
Figure 7. PScope Screen Shot
dc2071afc
8
DEMO MANUAL DC2071A
DC2071A SETUP
exercise a small subset of the possible output codes.
The proper method is to pick an M/N frequency for the
input sine wave frequency. N is the number of samples
in the FFT. M is a prime number between one and N/2.
Multiply M/N by the sample rate to obtain the input sine
wave frequency. Another scenario that can yield poor
results is if you do not have a signal generator capable of
ppm frequency accuracy or if it cannot be locked to the
clock frequency. You can use an FFT with windowing to
reduce the leakage, or spreading of the fundamental, to
get a close approximation of the ADC performance. If an
amplifier or clock source with poor phase noise is used,
the windowing will not improve the SNR.
To change the default settings for the LTC2373-18 se-
quencer in PScope, click on the Set Demo Bd Options
button in the PScope tool bar shown in Figure 8. This will
open the Configure Sequencer menu of Figure 9. In this
menu it is possible to set the number of sequences up to
16, the channel configuration, format and gain compres-
sion setting for each sequence. There is also a button to
return PScope to the default DC2071 settings which are
optimizedforthedefaulthardwaresettingsoftheDC2071A.
Thereareanumberofscenariosthatcanproducemislead-
ing results when evaluating an ADC. One that is common
is feeding the converter with an input frequency that is
a sub-multiple of the sample rate and which will only
Figure ±. PScope Tool Bar
Figure 9. PScope Configure Sequencer Menu
dc2071afc
9
DEMO MANUAL DC2071A
DC2071A SETUP
DC590 Data Collection
and routing of the various components associated with
the ADC. Here are some things to remember when lay-
ing out a board for the LTC2373-18. A ground plane is
necessarytoobtainmaximumperformance.Keepbypass
capacitors as close to supply pins as possible. Use indi-
vidual low impedance returns for all bypass capacitors.
Use of a symmetrical layout around the analog inputs
will minimize the effects of parasitic elements. Shield
analog input traces with ground to minimize coupling
from other traces. Keep traces as short as possible.
Due to the relatively low and somewhat unpredictable
sample rate of the DC590, its usefulness is limited to
noise measurement and data collection of slowly moving
signals. A typical data capture and histogram are shown in
Figure 10. To change the default settings for the LTC2373-
18 sequencer in QuikEval click on the Sequence Config.
button. This will open the Sequence Configuration menu
of Figure 11. In this menu, it is possible to set the number
of sequences up to 16, the channel configuration, format
and gain compression setting for each sequence. There
is also a button to return QuikEval to the default DC2071
settings which are optimized for the default hardware
settings of the DC2071A.
Component Selection
When driving a low noise, low distortion ADC such as
the LTC2373-18, component selection is important so
as to not degrade performance. Resistors should have
low values to minimize noise and distortion. Metal film
resistors are recommended to reduce distortion caused
by self heating. Because of their low voltage coefficients,
to further reduce distortion, NP0 or silver mica capacitors
should be used. Any buffer used to drive the LTC2373-18
should have low distortion, low noise and a fast settling
time, such as the LT1469, LT6237, LT6350 or LTC6362.
To get the best noise performance from the DC2071 it
is recommended to place the demo board in a grounded
metal enclosure filled with tissue paper.
Layout
As with any high performance ADC, this part is sensitive
to layout. The area immediately surrounding the ADC on
theDC2071Ashouldbeusedasaguidelineforplacement
Figure 10. Quik-val Screen Shot
dc2071afc
10
DEMO MANUAL DC2071A
DC2071A SETUP
Figure 11. Quik-val Sequence Configuration Menu
DC2071A JUMPERS
Definitions
JP5: EEPROM is for factory use only. The default posi-
tion is WP.
JP1: REF Selects INT or EXT reference for the ADC. The
default setting is INT.
JP6: +IN1 COUPLING selects AC or DC coupling of +IN1.
The default setting is DC.
JP2: Selects the common mode voltage for the ADC.
Choices are EXT, 2.5V, 2.048V or GND. The default set-
ting is 2.048V.
JP7: IN3 COUPLING selects AC or DC coupling of IN3.
The default setting is DC.
JP±: –IN1 COUPLING Selects AC or DC coupling of –IN1.
JP3: VCCIO sets the output levels at J2 to either 3.3V or
2.5V. Use 2.5V to interface to the DC890 which is the
default setting. Use 3.3V to interface to the DC590.
The default setting is DC.
JP9: COM sets the DC bias voltage for the COM pin to
either CM or GND. CM is the default setting.
JP4: JTAG is used to program the CPLD. This is for fac-
tory use only.
dc2071afc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
DEMO MANUAL DC2071A
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:
Thisdemonstrationboard(DEMOBOARD)kitbeingsoldorprovidedbyLinearTechnologyisintendedforusefor-NGIN--RINGD-V-LOPM-NT
OR -VALUATION PURPOS-S ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety
measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date
of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU
OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR
ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or
agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance,
customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the D-MO BOARD manual prior to handling the product. Persons handling this product must have electronics training and
observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC applica-
tion engineer.
Mailing Address:
Linear Technology
1630 McCarthy Blvd.
Milpitas, CA 95035
Copyright © 2004, Linear Technology Corporation
dc2071afc
LT 0117 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
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●
LINEAR TECHNOLOGY CORPORATION 2014
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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