LTC2480IMS#TRL [Linear]
A/D Converter, 16-Bit, 1 Func, CMOS, PDSO10;
| 型号： | LTC2480IMS#TRL |
| 厂家： | 
Linear |
| 描述： | A/D Converter, 16-Bit, 1 Func, CMOS, PDSO10 光电二极管 |
| 文件： | 总40页 (文件大小：596K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2480
16-Bit ∆Σ ADC with Easy Drive
Input Current Cancellation
U
FEATURES
DESCRIPTIO
TheLTC®2480combinesa16-bitplussignNoLatency∆ΣTM
analog-to-digitalconverterwithpatentedEasyDriveTM tech-
nology.Thepatentedsamplingschemeeliminatesdynamic
inputcurrenterrorsandtheshortcomingsofon-chipbuff-
ering through automatic cancellation of differential input
current. Thisallowslargeexternalsourceimpedancesand
inputsignals,withrail-to-railinputrangetobedirectlydigi-
tized while maintaining exceptional DC accuracy.
■
Easy Drive Technology Enables Rail-to-Rail Inputs
with Zero Differential Input Current
■
Directly Digitizes High Impedance Sensors with
Full Accuracy
■
Programmable Gain from 1 to 256
■
Integrated Temperature Sensor
■
GND to VCC Input/Reference Common Mode Range
■
Programmable 50Hz, 60Hz or Simultaneous
50Hz/60Hz Rejection Mode
The LTC2480 includes on-chip programmable gain, a
temperaturesensorandanoscillator.TheLTC2480canbe
configured to provide a programmable gain from 1 to 256
in 8 steps, measure an external signal or internal tempera-
ture sensor and reject line frequencies. 50Hz, 60Hz or
simultaneous 50Hz/60Hz line frequency rejection can be
selected as well as a 2x speed-up mode.
■
2ppm (0.25LSB) INL, No Missing Codes
■
1ppm Offset and 15ppm Full-Scale Error
■
Selectable 2x Speed Mode (15Hz Using Internal
Oscillator)
■
No Latency: Digital Filter Settles in a Single Cycle
■
Single Supply 2.7V to 5.5V Operation
Internal Oscillator
■
■
The LTC2480 allows a wide common mode input range
(0V to VCC) independent of the reference voltage. The
reference can be as low as 100mV or can be tied directly
to VCC. The LTC2480 includes an on-chip trimmed oscil-
lator eliminating the need for external crystals or oscilla-
tors. Absolute accuracy and low drift are automatically
maintained through continuous, transparent, offset and
full-scale calibration.
Available in a Tiny (3mm × 3mm) 10-Lead
DFN Package and 10-Lead MSOP Package
U
APPLICATIO S
■
Direct Sensor Digitizer
Weight Scales
■
■
Direct Temperature Measurement
■
Strain Gauge Transducers
, LT, LTC, LTM are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ and Easy Drive are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Patent Pending.
■
Instrumentation
■
Industrial Process Control
■
DVMs and Meters
U
+
–
+FS Error vs R
at IN and IN
SOURCE
TYPICAL APPLICATIO
80
60
40
20
V
V
V
V
= 5V
CC
= 5V
REF
V
CC
+
= 3.75V
= 1.25V
IN
–
IN
1µF
SDI
F
= GND
O
T
A
= 25°C
C
IN
= 1µF
10k
10k
I
= 0
V
V
CC
DIFF
REF
0
+
V
IN
SDO
SCK
4-WIRE
SPI INTERFACE
–20
1µF
SENSE
LTC2480
GND
–
V
IN
–40
–60
–80
CS
2480 TA01
F
O
10
100
10k
1
100k
1k
(Ω)
2480 TA04
R
SOURCE
2480fa
1
LTC2480
ABSOLUTE AXI U RATI GS
W W U W
(Notes 1, 2)
Supply Voltage (VCC) to GND...................... –0.3V to 6V
Analog Input Voltage to GND ....... –0.3V to (VCC + 0.3V)
Reference Input Voltage to GND .. –0.3V to (VCC + 0.3V)
Digital Input Voltage to GND........ –0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... –0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2480C................................................... 0°C to 70°C
LTC2480I ................................................ –40°C to 85°C
Storage Temperature Range ................ –65°C to 125°C
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
SDI
1
2
3
4
5
10
9
F
O
SDI
1
2
3
4
5
10
9
F
O
V
SCK
GND
SDO
CS
CC
V
SCK
GND
SDO
CS
CC
11
V
8
REF
V
8
REF
+
+
IN
7
6
IN
–
7
–
IN
IN
6
MS PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/ W
TJMAX = 125°C, θJA = 120°C/ W
EXPOSED PAD (PIN 11) IS GND MUST BE SOLDERED TO PCB
DD PART MARKING*
DD PART MARKING*
ORDER PART NUMBER
ORDER PART NUMBER
LTC2480CDD
LTC2480IDD
LBJY
LBJY
LTC2480CMS
LTC2480IMS
LTCWB
LTCWB
Order Options Tape and Reel: Add #TRLead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
U W
ELECTRICAL CHARACTERISTICS ( OR AL SPEED)
The
●
denotes specifications which apply
over the full operating temperature range, otherwise specifications are T = 25°C. (Notes 3, 4)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
Integral Nonlinearity
0.1 ≤ V ≤ V , –FS ≤ V ≤ +FS (Note 5)
●
●
16
Bits
REF
CC
IN
5V ≤ V ≤ 5.5V, V
= 5V, V
= 2.5V (Note 6)
2
1
10
ppm of V
CC
REF
IN(CM)
REF
REF
2.7V ≤ V ≤ 5.5V, V = 2.5V, V
= 1.25V (Note 6)
ppm of V
CC
REF
IN(CM)
–
+
Offset Error
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 14)
●
●
0.5
10
2.5
µV
nV/°C
ppm of V
REF
REF
CC
CC
CC
+
–
Offset Error Drift
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V
REF
CC
+
–
Positive Full-Scale Error
Positive Full-Scale Error Drift
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
25
25
REF
CC
REF
REF
+
–
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
0.1
ppm of
REF
CC
REF
REF
V
/°C
REF
+
–
Negative Full-Scale Error
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
●
ppm of V
REF
REF
CC
REF
REF
+
–
Negative Full-Scale Error Drift
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
0.1
15
ppm of
REF
CC
REF
REF
V
/°C
REF
Total Unadjusted Error
5V ≤ V ≤ 5.5V, V = 2.5V, V
= 1.25V
ppm of V
ppm of V
ppm of V
CC
REF
REF
IN(CM)
REF
REF
REF
5V ≤ V ≤ 5.5V, V
= 5V, V
= 2.5V
CC
CC
IN(CM)
2.7V ≤ V ≤ 5.5V, V = 2.5V, V
= 1.25V
REF
IN(CM)
–
+
Output Noise
5V ≤ V ≤ 5.5V, V = 5V, GND ≤ IN = IN ≤ V (Note 13)
0.6
420
1.4
µV
RMS
CC
REF
CC
Internal PTAT Signal
T = 27°C
A
mV
Internal PTAT Temperature Coefficient
Programmable Gain
mV/°C
●
1
256
2480fa
2
LTC2480
ELECTRICAL CHARACTERISTICS (2x SPEED)
The
operating temperature range, otherwise specifications are T = 25°C. (Notes 3, 4)
●
denotes specifications which apply over the full
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
Integral Nonlinearity
0.1 ≤ V ≤ V , –FS ≤ V ≤ +FS (Note 5)
●
●
16
Bits
REF
CC
IN
5V ≤ V ≤ 5.5V, V
= 5V, V
= 2.5V (Note 6)
2
1
10
2
ppm of V
REF
CC
REF
IN(CM)
2.7V ≤ V ≤ 5.5V, V = 2.5V, V
= 1.25V (Note 6)
CC
REF
IN(CM)
–
+
Offset Error
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 14)
●
●
0.5
mV
REF
CC
CC
CC
+
–
Offset Error Drift
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V
100
nV/°C
ppm of V
REF
REF
CC
+
–
Positive Full-Scale Error
Positive Full-Scale Error Drift
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
25
25
REF
CC
REF
REF
+
–
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
0.1
ppm of
REF
CC
REF
REF
V
/°C
REF
+
–
Negative Full-Scale Error
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
●
●
ppm of V
REF
REF
CC
REF
REF
+
–
Negative Full-Scale Error Drift
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
0.1
ppm of
REF
CC
REF
REF
V
/°C
REF
–
+
Output Noise
5V ≤ V ≤ 5.5V, V = 5V, GND ≤ IN = IN ≤ V (Note 13)
0.84
µV
RMS
CC
REF
CC
Programmable Gain
(Note 15)
1
128
U
CO VERTER CHARACTERISTICS
The
●
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Notes 3, 4)
A
PARAMETER
CONDITIONS
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 5)
MIN
140
140
TYP
MAX
UNITS
dB
–
+
Input Common Mode Rejection DC
●
●
REF
CC
CC
–
+
Input Common Mode Rejection
50Hz ±2%
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 5)
dB
REF
CC
CC
–
+
Input Common Mode Rejection
60Hz ±2%
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 5)
●
●
●
●
●
140
110
110
87
dB
dB
dB
dB
dB
REF
CC
CC
–
+
Input Normal Mode Rejection
50Hz ±2%
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Notes 5, 7)
120
120
REF
CC
CC
–
+
Input Normal Mode Rejection
60Hz ±2%
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Notes 5, 8)
REF CC CC
–
+
Input Normal Mode Rejection
50Hz/60Hz ±2%
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Notes 5, 9)
REF CC CC
–
+
Reference Common Mode
Rejection DC
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 5)
120
140
REF
CC
CC
–
+
Power Supply Rejection DC
V
REF
V
REF
V
REF
= 2.5V, IN = IN = GND
120
120
120
dB
dB
dB
–
+
Power Supply Rejection, 50Hz ± 2%
Power Supply Rejection, 60Hz ± 2%
= 2.5V, IN = IN = GND (Notes 7, 9)
–
+
= 2.5V, IN = IN = GND (Notes 8, 9)
U
U
U
U
A ALOG I PUT A D REFERE CE The
●
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 3)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
+
IN
Absolute/Common Mode IN Voltage
GND – 0.3V
GND – 0.3V
V
V
+ 0.3V
V
V
V
CC
CC
–
–
IN
Absolute/Common Mode IN Voltage
+ 0.3V
+
–
FS
Full Scale of the Differential Input (IN – IN )
Least Significant Bit of the Output Code
●
●
●
●
0.5V /GAIN
REF
16
LSB
FS/2
+
–
V
V
Input Differential Voltage Range (IN – IN )
Reference Voltage Range
–FS
0.1
+FS
V
IN
V
V
REF
CC
2480fa
3
LTC2480
U
U
U
U
A ALOG I PUT A D REFERE CE The
●
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 3)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
11
11
11
1
MAX
UNITS
pF
+
+
C (IN )
IN Sampling Capacitance
S
–
–
C (IN )
IN Sampling Capacitance
pF
S
C (V
)
V
Sampling Capacitance
pF
S
REF
DC_LEAK
DC_LEAK
REF
+
+
+
I
I
I
(IN )
IN DC Leakage Current
Sleep Mode, IN = GND
●
●
●
–10
–10
10
10
nA
–
–
–
(IN )
IN DC Leakage Current
Sleep Mode, IN = GND
1
nA
(V
)
V
DC Leakage Current
Sleep Mode, V
= V
–100
1
100
nA
DC_LEAK REF
REF
REF
CC
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS
The
●
denotes specifications which apply over the full
operating temperature range, otherwise specifications are at T = 25°C. (Note 3)
A
SYMBOL
PARAMETER
CONDITIONS
2.7V ≤ V ≤ 5.5V
MIN
TYP
MAX
UNITS
V
V
V
V
High Level Input Voltage
●
●
●
●
●
●
V
V
– 0.5
V
IH
IL
IH
IL
CC
CC
CS, F , SDI
O
Low Level Input Voltage
2.7V ≤ V ≤ 5.5V
0.5
V
V
CC
CS, F , SDI
O
High Level Input Voltage
SCK
2.7V ≤ V ≤ 5.5V (Note 10)
– 0.5
CC
CC
Low Level Input Voltage
SCK
2.7V ≤ V ≤ 5.5V (Note 10)
0.5
10
10
V
CC
I
I
Digital Input Current
0V ≤ V ≤ V
CC
–10
–10
µA
µA
pF
pF
V
IN
IN
CS, F , SDI
O
Digital Input Current
SCK
0V ≤ V ≤ V (Note 10)
IN CC
IN
C
C
V
V
V
V
Digital Input Capacitance
10
10
IN
CS, F , SDI
O
Digital Input Capacitance
SCK
IN
High Level Output Voltage
SDO
I = –800µA
O
●
●
●
●
●
V
V
– 0.5
OH
OL
OH
OL
CC
CC
Low Level Output Voltage
SDO
I = 1.6mA
O
0.4
V
High Level Output Voltage
SCK
I = –800µA
O
– 0.5
V
Low Level Output Voltage
SCK
I = 1.6mA
O
0.4
10
V
I
Hi-Z Output Leakage
SDO
–10
µA
OZ
W U
POWER REQUIRE E TS
The
otherwise specifications are at T = 25°C. (Note 3)
●
denotes specifications which apply over the full operating temperature range,
A
SYMBOL
PARAMETER
Supply Voltage
Supply Current
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
●
2.7
5.5
V
I
Conversion Mode (Note 12)
Sleep Mode (Note 12)
●
●
160
1
250
2
µA
µA
CC
2480fa
4
LTC2480
W U
TI I G CHARACTERISTICS
The
●
denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 3)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
10
TYP
MAX
4000
100
UNITS
kHz
µs
f
t
t
t
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time for 1x Speed Mode
(Note 15)
●
●
●
EOSC
HEO
0.125
0.125
100
µs
LEO
50Hz Mode
60Hz Mode
Simultaneous 50Hz/60Hz Mode
External Oscillator
●
●
●
●
157.2
131.0
144.1
160.3
133.6
146.9
163.5
136.3
149.9
ms
ms
ms
ms
CONV_1
41036/f
(in kHz)
EOSC
t
f
Conversion Time for 2x Speed Mode
Internal SCK Frequency
50Hz Mode
60Hz Mode
Simultaneous 50Hz/60Hz Mode
External Oscillator
●
●
●
●
78.7
65.6
72.2
80.3
66.9
73.6
81.9
68.2
75.1
ms
ms
ms
ms
CONV_2
ISCK
20556/f
(in kHz)
EOSC
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
38.4
kHz
kHz
f
/8
EOSC
D
Internal SCK Duty Cycle
(Note 10)
(Note 10)
(Note 10)
(Note 10)
●
●
●
●
45
55
%
kHz
ns
ISCK
f
t
t
t
External SCK Frequency Range
External SCK Low Period
4000
ESCK
125
125
0.61
LESCK
External SCK High Period
ns
HESCK
DOUT_ISCK
Internal SCK 24-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
●
●
0.625
0.64
ms
ms
192/f
(in kHz)
EOSC
t
t
t
t
t
t
t
t
t
t
t
External SCK 24-Bit Data Output Time
CS↓ to SDO Low
(Note 10)
●
●
●
●
●
●
●
●
●
●
●
24/f
(in kHz)
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DOUT_ESCK
ESCK
0
0
200
200
200
1
CS↑ to SDO High Z
CS↓ to SCK↓
2
Internal SCK Mode
External SCK Mode
0
3
CS↓ to SCK↑
50
4
SCK↓ to SDO Valid
SDO Hold After SCK↓
SCK Set-Up Before CS↓
SCK Hold After CS↓
SDI Setup Before SCK↑
SDI Hold After SCK↑
200
50
KQMAX
(Note 5)
15
50
KQMIN
5
6
7
8
(Note 5)
(Note 5)
100
100
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 8: 60Hz mode (internal oscillator) or f
oscillator).
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or f
280kHz ±2% (external oscillator).
Note 10: The SCK can be configured in external SCK mode or internal SCK
= 307.2kHz ±2% (external
EOSC
=
EOSC
Note 2: All voltage values are with respect to GND.
Note 3: V = 2.7V to 5.5V unless otherwise specified.
mode. In external SCK mode, the SCK pin is used as digital input and the
CC
driving clock is f . In internal SCK mode, the SCK pin is used as digital
V
V
= V /2, FS = 0.5V /GAIN
ESCK
REFCM
REF
REF
+
output and the output clock signal during the data output is f
.
+
–
–
ISCK
= IN – IN , V
= (IN + IN )/2
IN
IN(CM)
Note 11: The external oscillator is connected to the F pin. The external
O
Note 4: Use internal conversion clock or external conversion clock source
with f = 307.2kHz unless otherwise specified.
oscillator frequency, f
, is expressed in kHz.
EOSC
EOSC
Note 12: The converter uses the internal oscillator.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 15: Refer to Applications Information section for performance vs
Note 7: 50Hz mode (internal oscillator) or f
oscillator).
= 256kHz ±2% (external
EOSC
data rate graphs.
2480fa
5
LTC2480
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Integral Nonlinearity
Integral Nonlinearity
Integral Nonlinearity
CC
(V = 5V, V
= 5V)
(V = 5V, V
= 2.5V)
(V = 2.7V, V = 2.5V)
REF
CC
REF
CC
REF
3
2
3
2
3
2
V
V
V
= 5V
V
V
V
= 5V
V
V
V
= 2.7V
CC
CC
CC
= 5V
= 2.5V
= 2.5V
REF
REF
REF
= 2.5V
= 1.25V
= 1.25V
IN(CM)
IN(CM)
= GND
IN(CM)
= GND
F
F
F = GND
O
O
O
1
0
–45°C
1
0
1
0
25°C
–45°C, 25°C, 90°C
–45°C, 25°C, 90°C
85°C
–1
–2
–3
–1
–2
–3
–1
–2
–3
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–1.25 –0.75
–0.25
0.25
0.75
1.25
–1.25 –0.75
–0.25
0.25
0.75
1.25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2480 G06
2480 G04
2480 G05
Total Unadjusted Error
Total Unadjusted Error
Total Unadjusted Error
CC
(V = 5V, V
= 5V)
(V = 5V, V
= 2.5V)
(V = 2.7V, V = 2.5V)
REF
CC
REF
CC
REF
12
8
12
8
12
8
V
V
V
= 5V
V
V
V
= 5V
V
V
V
= 2.7V
CC
CC
CC
= 5V
= 5V
= 2.5V
REF
REF
85°C
REF
= 2.5V
= 1.25V
= 1.25V
IN(CM)
IN(CM)
= GND
IN(CM)
= GND
85°C
F
F
F = GND
O
O
O
85°C
25°C
25°C
25°C
4
0
4
0
4
0
–45°C
–45°C
–45°C
–4
–8
–4
–8
–4
–8
–12
–12
–12
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–1.25 –0.75
–0.25
0.25
0.75
1.25
–1.25 –0.75
–0.25
0.25
0.75
1.25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2480 G01
2480 G02
2480 G03
Noise Histogram (6.8sps)
Noise Histogram (7.5sps)
Long-Term ADC Readings
14
12
14
12
5
4
10,000 CONSECUTIVE
READINGS
V
= 5V, V
= 5V, V = 0V, V
= 2.5V
IN(CM)
10,000 CONSECUTIVE
READINGS
CC
REF
IN
GAIN = 256, T = 25°C, RMS NOISE = 0.60µV
A
RMS = 0.59µV
AVERAGE = –0.19µV
RMS = 0.60µV
AVERAGE = –0.69µV
V
V
V
= 2.7V
= 2.5V
V
V
V
= 5V
= 5V
CC
REF
IN
CC
REF
IN
3
= 0V
= 0V
10
8
10
8
2
GAIN = 256
= 25°C
GAIN = 256
= 25°C
T
A
1
T
A
0
6
6
–1
–2
–3
–4
–5
4
4
2
2
0
0
–1.8 –1.2 –0.6
0
1.8
–3 –2.4
0.6 1.2
–1.8 –1.2 –0.6
0
1.8
–3 –2.4
0.6 1.2
0
10
30
40
50
60
20
OUTPUT READING (µV)
OUTPUT READING (µV)
TIME (HOURS)
2480 G08
2480 G07
2480 G09
2480fa
6
LTC2480
U W
TYPICAL PERFOR A CE CHARACTERISTICS
RMS Noise
vs Input Differential Voltage
RMS Noise vs V
RMS Noise vs Temperature (T )
A
IN(CM)
1.0
0.9
1.0
0.9
0.8
0.7
0.6
0.5
0.4
1.0
0.9
0.8
0.7
V
V
= 5V
= 5V
V
V
V
V
= 5V
= 5V
V
V
V
V
= 5V
= 5V
CC
REF
GAIN = 256
CC
REF
IN
CC
REF
IN
= 0V
= 0V
V
T
= 2.5V
= GND
= GND
IN(CM)
= 25°C
IN(CM)
IN(CM)
GAIN = 256
GAIN = 256
A
0.8
0.7
T
A
= 25°C
0.6
0.5
0.4
0.6
0.5
0.4
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–45
0
30 45 60 75 90
3
5
6
–30 –15
15
–1
0
1
2
4
INPUT DIFFERENTIAL VOLTAGE (V)
TEMPERATURE (°C)
V
(V)
IN(CM)
2480 G10
2480 G12
2480 G11
RMS Noise vs V
RMS Noise vs V
Offset Error vs V
IN(CM)
CC
REF
1.0
0.9
0.3
0.2
0.1
0
1.0
0.9
0.8
0.7
V
V
V
= 5V
= 0V
V
V
V
= 5V
= 5V
V
V
V
= 2.5V
CC
IN
CC
REF
IN
REF
= 0V
IN
IN(CM)
= GND
= 0V
= GND
IN(CM)
GAIN = 256
GAIN = 256
= 25°C
GAIN = 256
= 25°C
T
= 25°C
T
T
A
A
A
0.8
0.7
0.6
0.5
0.4
–0.1
–0.2
–0.3
0.6
0.5
0.4
3
5
6
0
1
2
3
(V)
4
5
–1
0
1
2
4
4.3
(V)
5.1 5.5
2.7 3.1 3.5 3.9
V
4.7
V
REF
V
(V)
IN(CM)
CC
2480 G14
2480 G15
2480 G13
Offset Error vs Temperature
Offset Error vs V
Offset Error vs V
REF
CC
0.3
0.2
0.1
0
0.3
0.2
0.3
0.2
+
V
= 5V
REF = 2.5V
V
V
V
V
= 5V
CC
CC
–
–
REF = GND
REF = GND
= 5V
REF
V
V
= 0V
V
V
= 0V
= 0V
IN
IN(CM)
IN
IN(CM)
IN
IN(CM)
= GND
= GND
= GND
= GND
GAIN = 256
GAIN = 256
= 25°C
F
O
0.1
0.1
0
T
= 25°C
T
A
A
0
–0.1
–0.1
–0.2
–0.3
–0.1
–0.2
–0.3
–0.2
–0.3
4.3
(V)
5.1
5.5
0
1
2
3
4
5
2.7 3.1
3.5 3.9
V
4.7
–45 –30 –15
0
15 30 45 60 75 90
V
(V)
TEMPERATURE (°C)
REF
CC
2480 G17
2480 G18
2480 G16
2480fa
7
LTC2480
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Temperature Sensor
vs Temperature
On-Chip Oscillator Frequency
vs Temperature
Temperature Sensor Error
vs Temperature
310
308
306
304
302
300
0.40
0.35
0.30
0.25
0.20
5
4
V
V
O
= 5V
REF
= GND
V
F
= 5V
CC
CC
O
= 1.4V
= GND
F
3
2
V
= 1.4V
REF
1
0
–1
–2
–3
–4
–5
V
V
V
V
= 4.1V
CC
= 2.5V
REF
= 0V
IN
IN(CM)
= GND
= GND
F
O
–60
–30
0
30
TEMPERATURE (°C)
60
90
120
–45 –30 –15
0
15 30 45 60 75 90
–60
–30
0
30
60
90
120
TEMPERATURE (°C)
TEMPERATURE (°C)
2480 G24
2480 G26
2480 G25
On-Chip Oscillator Frequency
vs V
PSRR vs Frequency at V
PSRR vs Frequency at V
CC
CC
CC
310
308
306
304
0
–20
0
V
V
V
F
= 2.5V
V
V
= 4.1V DC ±1.4V
REF
IN = GND
V
V
= 4.1V DC
= 2.5V
REF
IN
CC
CC
REF
= 0V
= 2.5V
–20
+
–
+
= GND
IN = GND
IN(CM)
–
= GND
IN = GND
IN = GND
O
–40
–40
F
= GND
= 25°C
F
= GND
= 25°C
O
A
O
A
T
T
–60
–60
–80
–80
–100
–120
–100
–120
–140
302
300
–140
2.5
3.5
4.0
(V)
4.5
5.0
5.5
3.0
10k
FREQUENCY AT V (Hz)
1M
0
60
140
200 220
1
10
100
1k
100k
160 180
20 40
80
100 120
V
FREQUENCY AT V (Hz)
CC
CC
CC
2480 G27
2480 G28
2480 G29
Conversion Current
vs Temperature
Sleep Mode Current
vs Temperature
PSRR vs Frequency at V
CC
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
–20
–40
200
180
F = GND
O
CS = V
CC
SCK = NC
SDO = NC
SDI = GND
V
V
= 4.1V DC ±0.7V
REF
IN = GND
F
= GND
O
CC
= 2.5V
CS = GND
SCK = NC
SDO = NC
SDI = GND
+
–
IN = GND
V
= 5V
F
= GND
= 25°C
CC
O
A
T
160
V
= 5V
CC
–60
–80
V
= 2.7V
CC
140
120
100
V
= 2.7V
CC
–100
–120
–140
–45 –30 –15
0
15 30 45 60 75 90
30650
30700
30800
–45 –30 –15
0
30
60 75 90
30600
30750
15
45
TEMPERATURE (°C)
TEMPERATURE (°C)
FREQUENCY AT V (Hz)
CC
2480 G32
2480 G30
2480 G31
2480fa
8
LTC2480
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Conversion Current
vs Output Data Rate
Integral Nonlinearity (2x Speed
Mode; V = 5V, V = 5V)
Integral Nonlinearity (2x Speed
Mode; V = 5V, V
= 2.5V)
CC
REF
CC
REF
500
450
400
350
300
250
200
150
100
3
2
3
2
V
= V
CC
V
V
V
= 5V
V
V
V
= 5V
REF
CC
CC
+
IN = GND
= 5V
= 2.5V
REF
REF
–
IN = GND
= 2.5V
= 1.25V
IN(CM)
IN(CM)
= GND
SCK = NC
SDO = NC
SDI = GND
CS GND
F
F = GND
O
O
V
= 5V
CC
1
0
1
0
90°C
25°C, 90°C
F
= EXT OSC
= 25°C
O
A
T
V
CC
= 3V
–45°C, 25°C
–1
–2
–3
–1
–2
–3
–45°C
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–1.25 –0.75
–0.25
0.25
0.75
1.25
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2480 G33
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2480 G34
2480 G35
Noise Histogram
(2x Speed Mode)
RMS Noise vs V
REF
(2x Speed Mode)
Integral Nonlinearity (2x Speed
Mode; V = 2.7V, V
= 2.5V)
CC
REF
3
2
1.0
0.8
0.6
0.4
0.2
0
16
14
12
10
8
RMS = 0.86µV
10,000 CONSECUTIVE
READINGS
V
V
V
F
= 2.7V
CC
AVERAGE = 0.184mV
= 2.5V
REF
IN(CM)
= GND
V
V
V
= 5V
= 5V
= 1.25V
CC
REF
IN
O
= 0V
1
0
GAIN = 256
= 25°C
90°C
T
A
6
–45°C, 25°C
–1
–2
–3
V
V
V
= 5V
= 0V
CC
IN
4
= GND
IN(CM)
2
F
= GND
O
T
= 25°C
A
0
–1.25 –0.75
–0.25
0.25
0.75
1.25
0
1
2
3
4
5
181.4
183.8
188.6
179
186.2
INPUT VOLTAGE (V)
V
(V)
OUTPUT READING (µV)
REF
2480 G36
2480 G38
2480 G37
Offset Error vs V
Offset Error vs Temperature
(2x Speed Mode)
IN(CM)
(2x Speed Mode)
200
198
196
194
192
190
188
186
184
182
180
240
230
220
210
200
190
180
170
160
V
V
V
= 5V
CC
V
V
V
V
= 5V
REF
CC
= 5V
REF
= 5V
= 0V
IN
= 0V
IN
IN(CM)
= GND
F
= GND
O
= GND
T
= 25°C
A
F
O
–1
1
2
3
(V)
4
5
6
0
15 30
TEMPERATURE (°C)
–45 –30 –15
0
45 60 75 90
V
IN(CM)
2480 G39
2480 G40
2480fa
9
LTC2480
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Offset Error vs V
Offset Error vs V
REF
(2x Speed Mode)
PSRR vs Frequency at V
(2x Speed Mode)
CC
CC
(2x Speed Mode)
250
200
150
100
50
0
–20
240
230
220
210
V
V
V
F
= 2.5V
V
V
V
F
= 5V
= 0V
V
= 4.1V DC
REF
CC
IN
CC
+
= 0V
REF = 2.5V
IN
IN(CM)
–
= GND
= GND
= GND
REF = GND
IN(CM)
+
–
= GND
IN = GND
O
O
–40
T
= 25°C
T = 25°C
A
IN = GND
A
F
= GND
= 25°C
O
A
T
–60
200
190
–80
–100
–120
–140
180
170
160
0
2
2.5
3
3.5
V
4
(V)
4.5
5
5.5
0
1
2
4
5
3
(V)
10k
1M
1
10
100
1k
100k
V
FREQUENCY AT V (Hz)
CC
CC
REF
2480 G41
2480 G42
2480 G43
PSRR vs Frequency at V
(2x Speed Mode)
PSRR vs Frequency at V
(2x Speed Mode)
CC
CC
0
0
V
= 4.1V DC ±1.4V
V
= 4.1V DC ±0.7V
CC
CC
+
+
REF = 2.5V
REF = 2.5V
–20
–40
–
–20
–
REF = GND
REF = GND
IN = GND
+
–
+
–
IN = GND
IN = GND
–40 IN = GND
F
= GND
= 25°C
F
= GND
= 25°C
O
A
O
A
T
T
–60
–80
–60
–80
–100
–120
–100
–120
–140
–140
20 40
80
100 120 140 160 180 200 220
0
60
30600
30650
30700
30750
30800
FREQUENCY AT V (Hz)
CC
FREQUENCY AT V (Hz)
CC
2480 G44
2480 G45
U
U
U
PI FU CTIO S
SDI (Pin 1):Serial Data Input. This pin is used to select the
GAIN, line frequency rejection, input, temperature sensor
and 2x speed mode. Data is shifted into the SDI pin on the
rising edge of serial clock (SCK).
IN+ (Pin 4), IN– (Pin 5): Differential Analog Inputs. The
voltage on these pins can have any value between GND –
0.3V and VCC + 0.3V. Within these limits the converter
bipolar input range (VIN = IN+ – IN–) extends from –0.5 •
VREF /GAINto0.5•VREF/GAIN.Outsidethisinputrangethe
converter produces unique overrange and underrange
output codes.
VCC (Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 8) with a 1µF tantalum capacitor in parallel with 0.1µF
ceramic capacitor as close to the part as possible.
CS (Pin 6): Active LOW Chip Select. A LOW on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion the ADC automatically enters
VREF (Pin 3): Positive Reference Input. The voltage on this
pincanhaveanyvaluebetween0.1VandVCC.Thenegative
reference input is GND (Pin 8).
theSleepmodeandremainsinthislowpowerstateaslong
2480fa
10
LTC2480
U
U
U
PI FU CTIO S
asCSisHIGH. ALOW-to-HIGHtransitiononCSduringthe
Data Output transfer aborts the data transfer and starts a
new conversion.
Input/Output period. In External Serial Clock Operation
mode, SCK is used as the digital input for the external
serialinterfaceclockduringtheDataOutputperiod.Aweak
internal pull-up is automatically activated in Internal Serial
ClockOperationmode.TheSerialClockOperationmodeis
determined by the logic level applied to the SCK pin at
power up or during the most recent falling edge of CS.
SDO (Pin 7): Three-State Digital Output. During the Data
Output period, this pin is used as the serial data output.
When the chip select CS is HIGH (CS = VCC), the SDO pin
is in a high impedance state. During the Conversion and
Sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.
FO (Pin 10): Frequency Control Pin. Digital input that
controls the conversion clock. When FO is connected to
GND the converter uses its internal oscillator running at
307.2kHz. The conversion clock may also be overridden
by driving the FO pin with an external clock in order to
change the output rate or the digital filter rejection null.
GND (Pin 8): Ground. Shared pin for analog ground,
digitalgroundandreferenceground.Shouldbeconnected
directlytoagroundplanethroughaminimumimpedance.
Exposed Pad (Pin 11): This pin is ground and should be
soldered to the PCB ground plane. For prototyping pur-
poses, this pin may remain floating.
SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as the digital
outputfortheinternalserialinterfaceclockduringtheData
U
U
W
FU CTIO AL BLOCK DIAGRA
2
V
REF
V
CC
3
+
IN
IN
SDI
+
4
5
REF
1
9
7
6
+
–
IN
IN
–
SCK
SD0
CS
SERIAL
INTERFACE
3RD ORDER
∆ΣADC
MUX
(1-256)
GAIN
–
REF
F
O
TEMP
SENSOR
AUTOCALIBRATION
AND CONTROL
10
INTERNAL
OSCILLATOR
GND
8
2480 FD
V
CC
TEST CIRCUITS
1.69k
C
SDO
SDO
1.69k
C
LOAD
= 20pF
= 20pF
LOAD
Hi-Z TO V
Hi-Z TO V
OH
OH
OL
V
TO V
V
OH
V
OL
TO V
OL
OL
OH
V
TO Hi-Z
2480 TA02
TO Hi-Z
2480 TA03
2480fa
11
LTC2480
W U
W
TI I G DIAGRA S
Timing Diagram Using Internal SCK
CS
SDO
SCK
t
t
2
1
3
t
KQMIN
t
t
KQMAX
t
8
t
7
SDI
2480 TD1
SLEEP
DATA IN/OUT
CONVERSION
Timing Diagram Using External SCK
CS
t
1
t
2
SDO
t
5
t
KQMIN
t
6
t
4
t
KQMAX
SCK
SDI
t
8
t
7
2480 TD2
SLEEP
DATA IN/OUT
CONVERSION
W U U
U
APPLICATIO S I FOR ATIO
CONVERTER OPERATION
CONVERT
SLEEP
Converter Operation Cycle
The LTC2480 is a low power, delta-sigma analog-to-
digital converter with an easy to use 4-wire serial interface
and automatic differential input current cancellation. Its
operation is made up of three states. The converter oper-
atingcyclebeginswiththeconversion,followedbythelow
power sleep state and ends with the data output (see
Figure 1). The 4-wire interface consists of serial data
output (SDO), serial clock (SCK), chip select (CS) and
serial data input (SDI).
FALSE
CS = LOW
AND
SCK
TRUE
DATA OUTPUT
CONFIGURATION INPUT
2480 F01
Initially, the LTC2480 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
Figure 1. LTC2480 State Transition Diagram
2480fa
12
LTC2480
W U U
APPLICATIO S I FOR ATIO
U
Whileinthissleepstate,powerconsumptionisreducedby
two orders of magnitude. The part remains in the sleep
state as long as CS is HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.
network transparently removes the differential input cur-
rent. This enables external RC networks and high imped-
ance sensors to directly interface to the LTC2480 without
external amplifiers. The remaining common mode input
current is eliminated by either balancing the differential
input impedances or setting the common mode input
equal to the common mode reference (see Automatic
Input Current Cancellation section). This unique architec-
ture does not require on-chip buffers enabling input sig-
nals to swing all the way to ground and up to VCC.
Furthermore, the cancellation does not interfere with the
transparent offset and full-scale auto-calibration and the
absolute accuracy (full scale + offset + linearity) is main-
tained even with external RC networks.
Once CS is pulled LOW, the device exits the low power
modeandentersthedataoutputstate. IfCSispulledHIGH
beforethefirstrisingedgeofSCK,thedevicereturnstothe
low power sleep mode and the conversion result is still
held in the internal static shift register. If CS remains LOW
after the first rising edge of SCK, the device begins
outputting the conversion result. Taking CS high at this
point will terminate the data input and output state and
start a new conversion. The conversion result is shifted
out of the device through the serial data output pin (SDO)
on the falling edge of the serial clock (SCK) (see Figure 2).
The LTC2480 includes a serial data input pin (SDI) in
which data is latched by the device on the rising edge of
SCK (Figure 2). The bit stream applied to this pin can be
used to select various features of the LTC2480, including
an on-chip temperature sensor, programmable GAIN, line
frequencyrejectionandoutputdatarate.Alternatively,this
pin may be tied to ground and the part will perform
conversions in a default state. In the default state (SDI
grounded) the device simply performs conversions on the
user applied input with a GAIN of 1 and simultaneous
rejection of 50Hz and 60Hz line frequencies.
Accessing the Special Features of the LTC2480
The LTC2480 combines a high resolution, low noise ∆Σ
analog-to-digitalconverterwithanon-chipselectabletem-
peraturesensor,programmablegain,programmabledigi-
tal filter and output rate control. These special features are
selectedthroughasingle8-bitserialinputwordduringthe
data input/output cycle (see Figure 2).
The LTC2480 powers up in a default mode commonly
used for most measurements. The device will remain in
this mode as long as the serial data input (SDI) is low. In
this default mode, the measured input is external, the
GAINis1, thedigitalfiltersimultaneouslyrejects50Hzand
60Hz line frequency noise, and the speed mode is 1x
(offset automatically, continuously calibrated).
Through timing control of the CS and SCK pins, the
LTC2480 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require program-
ming configuration registers; moreover, they do not dis-
turbthecyclicoperationdescribedabove. Thesemodesof
operation are described in detail in the Serial Interface
Timing Modes section.
Asimpleserialinterfacegrantsaccesstoanyorallspecial
functions contained within the LTC2480. In order to
changethemodeofoperation, anenablebit(EN)followed
by up to 7 bits of data are shifted into the device (see
Table 1).Thefirst3bits(GS2,GS1,GS0)controltheGAIN
of the converter from 1 to 256. The 4th bit (IM) is used to
select the internal temperature sensor as the conversion
input, while the 5th and 6th bits (FA, FB) combine to
determine the line frequency rejection mode. The 7th bit
(SPD) is used to double the output rate by disabling the
offset auto calibration.
Easy Drive Input Current Cancellation
The LTC2480 combines a high precision delta-sigma ADC
with an automatic differential input current cancellation
front end. A proprietary front-end passive sampling
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CS
BIT 23
EOC
BIT 22
DMY
BIT 21 BIT 20 BIT 19 BIT 18
BIT 4
LSB
BIT 3
GS2
BIT 2
GS1
BIT 1 BIT 0
GS0 IM
SDO
SIG
MSB
B16
Hi-Z
CONVERSION RESULT
PREVIOUS
CONFIGURATION BITS
SCK
SDI
EN
GS2
GS1
GS0
IM
FA
FB
SPD
DON’T CARE
CONVERSION
SLEEP
DATA INPUT/OUTPUT
2480 F02
Figure 2. Input/Output Data Timing
Table 1. Selecting Special Modes
Rejection
Mode
Gain
EN GS2 GS1 GS0 IM FA FB SPD
Comments
Keep Previous Mode
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
External Input, Gain = 1, Autocalibration
External Input, Gain = 4, Autocalibration
External Input, Gain = 8, Autocalibration
External Input, Gain = 16, Autocalibration
External Input, Gain = 32, Autocalibration
External Input, Gain = 64, Autocalibration
External Input, Gain = 128, Autocalibration
External Input, Gain = 256, Autocalibration
External Input, Gain = 1, 2x Speed
External Input, Gain = 2, 2x Speed
External Input, Gain = 4, 2x Speed
External Input, Gain = 8, 2x Speed
External Input, Gain = 16, 2x Speed
External Input, Gain = 32, 2x Speed
External Input, Gain = 64, 2x Speed
External Input, Gain = 128, 2x Speed
External Input, Simultaneous 50Hz/60Hz Rejection
External Input, 50Hz Rejection
Any
Rejection
Mode
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Any
Speed
Any Gain
External Input, 60Hz Rejection
Reserved, Do Not Use
Temperature Input, 50Hz/60Hz Rejection, Gain = 1, Autocalibration
Temperature Input, 50Hz Rejection, Gain = 1, Autocalibration
Temperature Input, 60Hz Rejection, Gain = 1, Autocalibration
Reserved, Do Not Use
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2480 TBL1
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U
Table 2a. The LTC2480 Performance vs GAIN in Normal Speed Mode (V = 5V, V
= 5V)
REF
CC
GAIN
1
±2.5
38.1
65536
5
4
±0.625
9.54
65536
5
8
±0.312
4.77
65536
5
16
±0.156
2.38
65536
5
32
±78m
1.19
65536
5
64
128
±19.5m
0.298
32768
5
256
UNIT
Input Span
LSB
±39m
0.596
65536
5
±9.76m
0.149
16384
8
V
µV
Noise Free Resolution*
Gain Error
Offset Error
Counts
ppm of FS
µV
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Table 2b. The LTC2480 Performance vs GAIN in 2x Speed Mode (V = 5V, V
= 5V)
CC
REF
16
GAIN
1
±2.5
38.1
65536
5
2
4
±0.625
9.54
65536
5
8
±0.312
4.77
65536
5
32
±78m
1.19
65536
5
64
±39m
0.596
45875
5
128
±19.5m
0.298
22937
5
UNIT
V
Input Span
LSB
±1.25
19.1
65536
5
±0.156
2.38
65536
5
µV
Noise Free Resolution*
Gain Error
Offset Error
Counts
ppm of FS
µV
200
200
200
200
200
200
200
200
*The resolution in counts is calculated as the FS divided by LSB or the RMS noise value, whichever is larger.
GAIN (GS2, GS1, GS0)
Rejection Mode (FA, FB)
The input referred gain of the LTC2480 is adjustable from
1 to 256. With a gain of 1, the differential input range is
±VREF/2 and the common mode input range is rail-to-rail.
As the GAIN is increased, the differential input range is
reduced to ±VREF/2 • GAIN but the common mode input
range remains rail-to-rail. As the differential gain is in-
creased, low level voltages are digitized with greater
resolution. At a gain of 256, the LTC2480 digitizes an input
signal range of ±9.76mV with over 16,000 counts.
The LTC2480 includes a high accuracy on-chip oscillator
with no required external components. Coupled with a 4th
order digital lowpass filter, the LTC2480 rejects line fre-
quency noise. In the default mode, the LTC2480 simulta-
neously rejects 50Hz and 60Hz by at least 87dB. The
LTC2480 can also be configured to selectively reject 50Hz
or 60Hz to better than 110dB.
Speed Mode (SPD)
The LTC2480 continuously performs offset calibrations.
Every conversion cycle, two conversions are automati-
cally performed (default) and the results combined. This
result is free from offset and drift. In applications where
the offset is not critical, the autocalibration feature can be
disabled with the benefit of twice the output rate.
Temperature Sensor (IM)
TheLTC2480includesanon-chiptemperaturesensor.The
temperaturesensorisselectedbysetting IM=1intheserial
input data stream. Conversions are performed directly on
the temperature sensor by the converter. While operating
in this mode, the device behaves as a temperature to bits
converter. The digital reading is proportional to the abso-
lute temperature of the device. This feature allows the
convertertolinearizetemperaturesensorsorcontinuously
removetemperatureeffectsfromexternalsensors.Several
applications leveraging this feature are presented in more
detail in the applications section. While operating in this
mode, the gain is set to 1 and the speed is set to normal in-
dependent of the control bits (GS2, GS1, GS0 and SPD).
Linearity, full-scale accuracy and full-scale drift are iden-
tical for both 2x and 1x speed modes. In both the 1x and
2x speed there is no latency. This enables input steps or
multiplexerchannelchangestosettleinasingleconversion
cycle easing system overhead and increasing the effective
conversion rate.
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Output Data Format
Bit 20 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 21 also
provides the underrange or overrange indication. If both
Bit 21 and Bit 20 are HIGH, the differential input voltage is
above +FS. If both Bit 21 and Bit 20 are LOW, the
differential input voltage is below –FS.
The LTC2480 serial output data stream is 24 bits long. The
first 3 bits represent status information indicating the sign
and conversion state. The next 17 bits are the conversion
result, MSB first. The remaining 4 bits indicate the con-
figuration state associated with the current conversion
result. The third and fourth bit together are also used to
indicate an underrange condition (the differential input
voltage is below –FS) or an overrange condition (the
differential input voltage is above +FS).
The function of these bits is summarized in Table 3.
Table 3. LTC2480 Status Bits
BIT 23 BIT 22 BIT 21 BIT 20
INPUT RANGE
EOC
DMY
SIG
MSB
V
≥ 0.5 • V
0
0
0
0
0
1
1
0
1
0
IN
REF
In applications where the processor generates 32 clock
cycles, or to remain compatible with higher resolution
converters, the LTC2480’s digital interface will ignore
extra clock edges seen during the next conversion period
after the 24th and output “1” for the extra clock cycles.
Furthermore, CS may be pulled high prior to outputting all
24 bits, aborting the data out transfer and initiating a new
conversion.
0V ≤ V < 0.5 • V
0
1
IN
REF
–0.5 • V ≤ V < 0V
0
0
REF
IN
V
< –0.5 • V
0
0
IN
REF
Bits 20-4 are the 16-bit plus sign conversion result MSB
first.
Bits 3-0 are the corresponding configuration bits for the
presentconversionresult.Bits3-1arethegainsetbitsand
bit 0 is IM (see Figure 2).
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
DataisshiftedoutoftheSDOpinundercontroloftheserial
clock (SCK) (see Figure 2). Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
In order to shift the conversion result out of the device, CS
mustfirstbedrivenLOW. EOCisseenattheSDOpinofthe
device once CS is pulled LOW. EOC changes in real time
Bit 21 (third output bit) is the conversion result sign indi-
cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW.
Table 4. LTC2480 Output Data Format
DIFFERENTIAL INPUT VOLTAGE BIT 23
IN
BIT 22
DMY
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 17
…
BIT 4
V
*
EOC
V * ≥ FS**
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
…
…
…
…
…
…
…
…
…
…
0
1
0
1
0
1
0
1
0
1
IN
FS** – 1LSB
0.5 • FS**
0.5 • FS** – 1LSB
0
0
0
0
0
–1LSB
0
–0.5 • FS**
–0.5 • FS** – 1LSB
–FS**
0
0
0
V * < –FS**
IN
0
+
–
*The differential input voltage V = IN – IN . **The full-scale voltage FS = 0.5 • V /GAIN.
IN
REF
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16
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U
–80
from HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external
microcontroller. Bit 23 (EOC) can be captured on the first
risingedgeofSCK. Bit22isshiftedoutofthedeviceonthe
first falling edge of SCK. The final data bit (Bit 0) is shifted
out on the falling edge of the 23rd SCK and may be latched
on the rising edge of the 24th SCK pulse. On the falling
edge of the 24th SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 23) for the next conversion cycle. Table 4 summarizes
the output data format.
AslongasthevoltageontheIN+ andIN–pinsismaintained
within the –0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF/GAIN
to +FS = 0.5 • VREF/GAIN. For differential input voltages
greater than +FS, the conversion result is clamped to the
value corresponding to the +FS + 1LSB. For differential
inputvoltagesbelow–FS,theconversionresultisclamped
to the value corresponding to –FS – 1LSB.
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
–12
–8
–4
0
4
8
12
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY f
/5120(%)
2480 F03
EOSC
Figure 3. LTC2480 Normal Mode Rejection When Using
an External Oscillator
synchronized with an outside source, the LTC2480 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the FO pin and turns off the internal oscillator. The
frequency fEOSC of the external signal must be at least
10kHz to be detected. The external clock signal duty cycle
is not significant as long as the minimum and maximum
specifications for the high and low periods tHEO and tLEO
are observed.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonlyimplementedasaSINCorCombfilter).Forhigh
resolution,lowfrequencyapplications,thisfilteristypically
designedtorejectlinefrequenciesof50Hzor60Hzplustheir
harmonics. The filter rejection performance is directly re-
lated to the accuracy of the converter system clock. The
LTC2480incorporatesahighlyaccurateon-chiposcillator.
Thiseliminatestheneedforexternalfrequencysettingcom-
ponents such as crystals or oscillators.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2480 provides better than 110dB
normal mode rejection in a frequency range of fEOSC/5120
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/5120
is shown in Figure 3.
WheneveranexternalclockisnotpresentattheFO pin, the
converterautomaticallyactivatesitsinternaloscillatorand
enters the Internal Conversion Clock mode. The LTC2480
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
notbeaffected.Ifthechangeoccursduringthedataoutput
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Frequency Rejection Selection (FO)
TheLTC2480internaloscillatorprovidesbetterthan110dB
normal mode rejection at the line frequency and all its
harmonics (up to the 255th) for 50Hz ±2% or 60Hz ±2%,
or better than 87dB normal mode rejection from 48Hz to
62.4Hz. The rejection mode is selected by writing to the
on-chip configuration register and the default mode at
POR is simultaneous 50Hz/60Hz rejection.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
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Table 5. LTC2480 State Duration
STATE
OPERATING MODE
DURATION
CONVERT
Internal Oscillator
60Hz Rejection
133ms, Output Data Rate ≤ 7.5 Readings/s for 1x Speed Mode
67ms, Output Data Rate ≤ 15 Readings/s for 2x Speed Mode
50Hz Rejection
160ms, Output Data Rate ≤ 6.2 Readings/s for 1x Speed Mode
80ms, Output Data Rate ≤ 12.5 Readings/s for 2x Speed Mode
50Hz/60Hz Rejection
147ms, Output Data Rate ≤ 6.8 Readings/s for 1x Speed Mode
73.6ms, Output Data Rate ≤ 13.6 Readings/s for 2x Speed Mode
External Oscillator
F = External Oscillator
41036/f
s, Output Data Rate ≤ f
/41036 Readings/s for
O
EOSC
EOSC
with Frequency f
kHz
1x Speed Mode
20556/f s, Output Data Rate ≤ f
2x Speed Mode
EOSC
(f
EOSC
/5120 Rejection)
/20556 Readings/s for
EOSC
EOSC
SLEEP
As Long As CS = HIGH, After a Conversion is Complete
DATA OUTPUT
Internal Serial Clock
F = LOW/HIGH
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 0.62ms
(24 SCK Cycles)
O
F = External Oscillator with
As Long As CS = LOW But Not Longer Than 192/f
(24 SCK Cycles)
ms
EOSC
O
Frequency f
kHz
EOSC
External Serial Clock with
As Long As CS = LOW But Not Longer Than 24/f ms
(24 SCK Cycles)
SCK
Frequency f
kHz
SCK
Table 5 summarizes the duration of each state and the
achievable output data rate as a function of FO.
signal with a duration of approximately 4ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2480 starts a normal conversion cycle and
follows the succession of states described in Figure 1. The
firstconversionresultfollowingPORisaccuratewithinthe
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Ease of Use
The LTC2480 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle.Thereisaone-to-onecorrespondencebetweenthe
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
On-Chip Temperature Sensor
The LTC2480 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
theuserandhasnoeffectonthecyclicoperationdescribed
above. Theadvantageofcontinuouscalibrationisextreme
stabilityofoffsetandfull-scalereadingswithrespecttotime,
supply voltage change and temperature drift.
The LTC2480 contains an on-chip PTAT (proportional to
absolute temperature) signal that can be used as a tem-
perature sensor. The internal PTAT has a typical value of
420mVat27°Candisproportionaltotheabsolutetempera-
turevaluewithatemperaturecoefficientof420/(27+273)
= 1.40mV/°C (SLOPE), as shown in Figure 4. The internal
PTAT signal is used in a single-ended mode referenced to
device ground internally. The GAIN is automatically set to
one (independent of the values of GS0, GS1, GS2) in order
to preserve the PTAT property at the ADC output code and
avoid an out of range error. The 1x speed mode with au-
tomatic offset calibration is automatically selected for the
internal PTAT signal measurement as well.
Power-Up Sequence
The LTC2480 automatically enters an internal reset state
when the power supply voltage VCC drops below approxi-
mately 2V. This feature guarantees the integrity of the
conversionresultandoftheserialinterfacemodeselection.
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
2480fa
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U
When using the internal temperature sensor, if the output
code is normalized to RSDO = VPTAT/VREF, the temperature
is calculated using the following formula:
Reference Voltage Range
The LTC2480 external reference voltage range is 0.1V to
VCC. The converter output noise is determined by the
thermal noise of the front-end circuits, and as such, its
value in nanovolts is nearly constant with reference volt-
age. Since the transition noise (600nV) is much less than
the quantization noise (VREF/217), a decrease in the refer-
ence voltage will increase the converter resolution. A
reduced reference voltage will also improve the converter
performance when operated with an external conversion
clock (external FO signal) at substantially higher output
data rates (see the Output Data Rate section). VREF must
be ≥1.1V to use the internal temperature sensor.
RSDO • VREF
TK =
and
TC =
in Kelvin
SLOPE
RSDO • VREF
SLOPE
– 273 in °C
where SLOPE is nominally 1.4mV/°C.
Since the PTAT signal can have an initial value variation
which results in errors in SLOPE, to achieve better tem-
perature measurements, a one-time calibration is needed
to adjust the SLOPE value. The converter output of the
PTAT signal, R0SDO, is measured at a known temperature
T0 (in °C) and the SLOPE is calculated as:
The negative reference input to the converter is internally
tied to GND. GND (Pin 8) should be connected to a ground
plane through as short a trace as possible to minimize
voltage drop. The LTC2480 has an average operational
current of 160µA and for 0.1Ω parasitic resistance, the
voltage drop of 16µV causes a gain error of 3.2ppm for
VREF = 5V.
R0SDO • VREF
SLOPE =
T0 + 273
This calibrated SLOPE can be used to calculate the
temperature.
Input Voltage Range
If the same VREF source is used during calibration and
temperature measurement, the actual value of the VREF is
not needed to measure the temperature as shown in the
calculation below:
The analog input is truly differential with an absolute/
common mode range for the IN+ and IN– input pins
extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase
rapidly. Within these limits, the LTC2480 converts the
bipolar differential input signal, VIN = IN+ – IN–, from –FS
to +FS where FS = 0.5 • VREF/GAIN. Outside this range, the
converter indicates the overrange or the underrange con-
dition using distinct output codes. Since the differential
input current cancellation does not rely on an on-chip
buffer, current cancellation as well as DC performance is
maintained rail-to-rail.
RSDO • VREF
TC =
– 273
SLOPE
RSDO
R0SDO
=
• T0 + 273 – 273
(
)
600
V
= 5V
CC
IM = 1
F
O
= GND
SLOPE = 1.40mV/°C
500
400
300
200
I
nput signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the perfor-
mance of the devices. The effect of the series resistance
on the converter accuracy can be evaluated from the
curves presented in the Input Current/Reference Current
sections. In addition, series resistors will introduce a
2480fa
–60
–30
0
30
60
90
120
2480 F04
TEMPERATURE (°C)
Figure 4. Internal PTAT Signal vs Temperature
19
LTC2480
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APPLICATIO S I FOR ATIO
temperature dependent offset error due to the input
leakage current. A 1nA input leakage current will develop
a1ppmoffseterrorona5kresistorifVREF =5V. Thiserror
has a very strong temperature dependency.
Whenthedeviceisinthesleepstate,itsconversionresult
is held in an internal static shift register. The device
remainsinthesleepstateuntilthefirstrisingedgeofSCK
is seen while CS is LOW. The input data is then shifted in
via the SDI pin on the rising edge of SCK (including the
first rising edge) and the output data is shifted out of the
SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 24th rising edge of SCK. On the 24th falling edge of
SCK, thedevicebeginsanewconversion. SDOgoesHIGH
(EOC = 1) indicating a conversion is in progress. In
applications where the processor generates 32 clock
cycles, or to remain compatible with higher resolution
converters, the LTC2480’s digital interface will ignore
extra clock edges seen during the next conversion period
after the 24th and outputs “1” for the extra clock cycles.
SERIAL INTERFACE TIMING MODES
The LTC2480’s 4-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes of
operation. These include internal/external serial clock,
3- or 4-wire I/O, single cycle or continuous conversion.
The following sections describe each of these serial inter-
face timing modes in detail. In all these cases, the con-
verter can use the internal oscillator (FO = LOW or FO =
HIGH) or an external oscillator connected to the FO pin.
Refer to Table 6 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
The serial clock mode is selected on the falling edge of CS.
Toselecttheexternalserialclockmode,theserialclockpin
(SCK) must be LOW during each CS falling edge.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CSHIGHanytimebetweenthefirstrisingedgeandthe24th
fallingedgeofSCK(seeFigure6).OntherisingedgeofCS,
the device aborts the data output state and immediately
initiates a new conversion. If the device has not finished
loadingthelastinputbitSPDofSDIbythetimeCSispulled
HIGH, the SDI information is discarded and the previous
configurationiskept. Thisisusefulforsystemsnotrequir-
ingall24bitsofoutputdata,abortinganinvalidconversion
cycle or synchronizing the start of a conversion.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. Independent of CS, the
deviceautomaticallyentersthelowpowersleepstateonce
the conversion is complete.
Table 6. LTC2480 Interface Timing Modes
SCK
CONVERSION
CYCLE
CONTROL
DATA
OUTPUT
CONTROL
CONNECTION
and
WAVEFORMS
CONFIGURATION
SOURCE
External
External
Internal
Internal
External SCK, Single Cycle Conversion
External SCK, 3-Wire I/O
CS and SCK
SCK
CS and SCK
SCK
Figures 5, 6
Figure 7
Internal SCK, Single Cycle Conversion
Internal SCK, 3-Wire I/O, Continuous Conversion
CS↓
CS↓
Figures 8, 9
Figure 10
Continuous
Internal
2480fa
20
LTC2480
W U U
U
APPLICATIO S I FOR ATIO
2.7V TO 5.5V
1µF
2
10
INT/EXT CLOCK
V
V
F
O
CC
LTC2480
3
1
9
REFERENCE
VOLTAGE
0.1V TO V
SDI
REF
SCK
CC
4-WIRE
SPI INTERFACE
7
8
SDO
CS
4
5
6
+
IN
IN
ANALOG
INPUT
–
TEST EOC
(OPTIONAL)
GND
CS
TEST EOC
TEST EOC
BIT 0
BIT 23
EOC
BIT 22
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 4
LSB
SDO
IM
Hi-Z
Hi-Z
Hi-Z
SCK
(EXTERNAL)
SDI*
DON’T CARE
DON’T CARE
EN
GS2
GS1
GS0
IM
FA
FB
DATA OUTPUT
SPD
CONVERSION
CONVERSION
2480 F05
SLEEP
SLEEP
Figure 5. External Serial Clock, Single Cycle Operation
2.7V TO 5.5V
1µF
2
3
10
INT/EXT CLOCK
V
V
F
O
CC
LTC2480
1
9
REFERENCE
VOLTAGE
SDI
REF
SCK
0.1V TO V
CC
4-WIRE
SPI INTERFACE
7
8
SDO
CS
4
5
6
+
IN
IN
ANALOG
INPUT
–
GND
TEST EOC
(OPTIONAL)
CS
TEST EOC
TEST EOC
BIT 0
EOC
BIT 23
EOC
BIT 22
BIT 21
BIT 20
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 9
BIT 8
SDO
SIG
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(EXTERNAL)
SDI*
DON’T CARE
CONVERSION
DON’T CARE
EN
GS2
GS1
GS0
IM
FA
FB
SPD
SLEEP
DATA OUTPUT
CONVERSION
DATA
OUTPUT
2480 F06
SLEEP
SLEEP
Figure 6. External Serial Clock, Reduced Data Output Length
2480fa
21
LTC2480
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U
APPLICATIO S I FOR ATIO
External Serial Clock, 3-Wire I/O
begun. In applications where the processor generates 32
clock cycles, or to remain compatible with higher resolu-
tion converters, the LTC2480’s digital interface will ignore
extra clock edges seen during the next conversion period
after the 24th and outputs “1” for the extra clock cycles.
This timing mode utilizes a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or transmission over an isolation barrier.
Internal Serial Clock, Single Cycle Operation
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
typically4msafterVCC exceedsapproximately2V.Thelevel
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion ends. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. The input data is then shifted in via the SDI
pin on the rising edge of SCK (including the first rising
edge) and the output data is shifted out of the SDO pin on
each falling edge of SCK. EOC can be latched on the first
rising edge of SCK. On the 24th falling edge of SCK, SDO
goes HIGH (EOC = 1) indicating a new conversion has
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
2.7V TO 5.5V
1µF
2
10
INT/EXT CLOCK
V
V
F
O
CC
LTC2480
3
1
9
REFERENCE
SDI
REF
VOLTAGE
SCK
0.1V TO V
3-WIRE
SPI INTERFACE
CC
7
SDO
CS
4
6
8
+
IN
IN
ANALOG
INPUT
5
–
GND
CS
BIT 23
EOC
BIT 22
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 4
LSB
BIT 0
IM
SDO
SCK
(EXTERNAL)
SDI*
DON’T CARE
DON’T CARE
EN
GS2
GS1
GS0
IM
FA
FB
DATA OUTPUT
SPD
CONVERSION
CONVERSION
2480 F07
Figure 7. External Serial Clock, CS = 0 Operation
2480fa
22
LTC2480
W U U
APPLICATIO S I FOR ATIO
U
WhentestingEOC,iftheconversioniscomplete(EOC= 0),
the device will exit the low power mode during the EOC
test. In order to allow the device to return to the low power
sleep state, CS must be pulled HIGH before the first rising
edge of SCK. In the internal SCK timing mode, SCK goes
HIGHandthedevicebeginsoutputtingdataattimetEOCtest
after the falling edge of CS (if EOC = 0) or tEOCtest after EOC
goes LOW (if CS is LOW during the falling edge of EOC).
ThevalueoftEOCtest is12µsifthedeviceisusingitsinternal
oscillator. If FO is driven by an external oscillator of
frequencyfEOSC, thentEOCtest is3.6/fEOSC inseconds. IfCS
is pulled HIGH before time tEOCtest, the device returns to
the sleep state and the conversion result is held in the
internal static shift register.
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result on the 24th rising edge of
SCK. Afterthe24thrisingedge, SDOgoesHIGH(EOC=1),
SCK stays HIGH and a new conversion starts.
CS remains LOW during the data output state. However,
the data output state may be aborted by pulling CS HIGH
anytime between the first and 24th rising edge of SCK (see
Figure 9). On the rising edge of CS, the device aborts the
data output state and immediately initiates a new conver-
sion. Ifthedevicehasnotfinishedloadingthelastinputbit
SPD of SDI by the time CS is pulled HIGH, the SDI
information is discarded and the previous configuration is
stillkept. Thisisusefulforsystemsnotrequiringall24bits
of output data, aborting an invalid conversion cycle, or
synchronizing the start of a conversion. If CS is pulled
HIGH while the converter is driving SCK LOW, the internal
pull-upisnotavailabletorestoreSCKtoalogicHIGHstate.
This will cause the device to exit the internal serial clock
mode on the next falling edge of CS. This can be avoided
by adding an external 10k pull-up resistor to the SCK pin
or by never pulling CS HIGH when SCK is LOW.
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data I/O cycle concludes
after the 24th rising edge. The input data is shifted in via
the SDI pin on the rising edge of SCK (including the first
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
2.7V TO 5.5V
1µF
2
3
10
INT/EXT CLOCK
V
V
F
O
CC
V
CC
10k
LTC2480
1
9
REFERENCE
VOLTAGE
SDI
REF
SCK
0.1V TO V
CC
4-WIRE
SPI INTERFACE
7
8
SDO
CS
4
5
6
+
IN
IN
ANALOG
INPUT
TEST EOC
–
GND
<t
EOCtest
CS
TEST EOC
BIT 23
EOC
BIT 22
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 4
LSB
BIT 0
IM
SDO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
SDI*
DON’T CARE
CONVERSION
DON’T CARE
EN
GS2
GS1
GS0
IM
FA
FB
SPD
DATA OUTPUT
CONVERSION
2480 F08
SLEEP
SLEEP
Figure 8. Internal Serial Clock, Single Cycle Operation
2480fa
23
LTC2480
W U U
U
APPLICATIO S I FOR ATIO
Whenever SCK is LOW, the LTC2480’s internal pull-up at
pin SCK is disabled. Normally, SCK is not externally driven
if the device is in the internal SCK timing mode. However,
certainapplicationsmayrequireanexternaldriveronSCK.
If this driver goes Hi-Z after outputting a LOW signal, the
LTC2480’s internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external10kpull-upresistortoSCK,thispingoesHIGHonce
the external driver goes Hi-Z. On the next CS falling edge,
the device will remain in the internal SCK timing mode.
Internal Serial Clock, 3-Wire I/O,
Continuous Conversion
This timing mode uses a 3-wire interface. The conversion
resultisshiftedoutofthedevicebyaninternallygenerated
serialclock(SCK)signal, seeFigure10. CSmaybeperma-
nently tied to ground, simplifying the user interface or
transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately1msafterVCC exceeds2V. Aninternalweak
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as tEOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGHlevelbeforeCSgoeslowagain. Thisisnotaconcern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
2.7V TO 5.5V
1µF
2
3
10
INT/EXT CLOCK
V
V
F
O
CC
V
CC
LTC2480
1
9
REFERENCE
VOLTAGE
10k
SDI
REF
SCK
0.1V TO V
CC
4-WIRE
SPI INTERFACE
7
8
SDO
CS
4
5
6
+
IN
IN
TEST EOC
(OPTIONAL)
ANALOG
INPUT
–
GND
>t
EOCtest
<t
EOCtest
CS
TEST EOC
TEST EOC
BIT 0
EOC
BIT 23
EOC
BIT 22
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 8
SDO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
SDI*
DON’T CARE
CONVERSION
DON’T CARE
CONVERSION
EN
GS2
GS1
GS0
IM
FA
FB
SPD
SLEEP
DATA OUTPUT
DATA
OUTPUT
2480 F09
SLEEP
SLEEP
Figure 9. Internal Serial Clock, Reduce Data Output Length
2480fa
24
LTC2480
W U U
U
APPLICATIO S I FOR ATIO
2.7V TO 5.5V
1µF
2
10
INT/EXT CLOCK
V
V
F
O
CC
V
CC
10k
LTC2480
3
1
9
REFERENCE
VOLTAGE
0.1V TO V
SDI
REF
SCK
CC
3-WIRE
SPI INTERFACE
7
SDO
CS
4
5
6
8
+
IN
IN
ANALOG
INPUT
–
GND
CS
BIT 23
EOC
BIT 22
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 4
LSB
BIT 0
IM
SDO
SCK
(INTERNAL)
SDI*
DON’T CARE
CONVERSION
DON’T CARE
EN
GS2
GS1
GS0
IM
FA
FB
DATA OUTPUT
SPD
CONVERSION
2480 F10
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
then immediately begins outputting data. The data input/
output cycle begins on the first rising edge of SCK and
ends after the 24th rising edge. The input data is then
shifted in via the SDI pin on the rising edge of SCK
(including the first rising edge) and the output data is
shifted out of the SDO pin on each falling edge of SCK.
The internally generated serial clock is output to the SCK
pin. Thissignalmaybeusedtoshifttheconversionresult
into external circuitry. EOC can be latched on the first
risingedgeofSCKandthelastbitoftheconversionresult
can be latched on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1) indicating a
newconversionisinprogress.SCKremainsHIGHduring
the conversion.
Digital Signal Levels
The LTC2480’s digital interface is easy to use. Its digital
inputs (SDI, FO, CS and SCK in External SCK mode of
operation) accept standard CMOS logic levels and the in-
ternalhysteresisreceiverscantolerateedgetransitiontimes
as slow as 100µs. However, some considerations are re-
quired to take advantage of the exceptional accuracy and
low supply current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(VCC – 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (SDI, FO, CS
and SCK in External SCK mode of operation) is within
this range, the power supply current may increase even
if the signal in question is at a valid logic level. For
micropower operation, it is recommended to drive all
digital input signals to full CMOS levels [VIL < 0.4V and
VOH > (VCC – 0.4V)].
PRESERVING THE CONVERTER ACCURACY
The LTC2480 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line frequency perturba-
tions and so on. Nevertheless, in order to preserve the
24-bit accuracy capability of this part, some simple pre-
cautions are required.
2480fa
25
LTC2480
W U U
U
APPLICATIO S I FOR ATIO
During the conversion period, the undershoot and/or
overshootofafastdigitalsignalconnectedtothepinscan
severely disturb the analog to digital conversion process.
Undershoot and overshoot occur because of the imped-
ance mismatch of the circuit board trace at the converter
pin when the transition time of an external control signal
is less than twice the propagation delay from the driver to
the LTC2480. For reference, on a regular FR-4 board,
signal propagation velocity is approximately 183ps/inch
for internal traces and 170ps/inch for surface traces.
Thus, a driver generating a control signal with a minimum
transition time of 1ns must be connected to the converter
pin through a trace shorter than 2.5 inches. This problem
becomes particularly difficult when shared control lines
are used and multiple reflections may occur. The solution
is to carefully terminate all transmission lines close to
their characteristic impedance.
converter, substantial AC current is flowing in the loop
formedbytheFO connectiontrace, theterminationandthe
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the FO signal as well as the loop area for
the differential input and reference connections. Even
when F0 is not driven, other nearby signals pose similar
EMI threats which will be minimized by following good
layout practices.
Driving the Input and Reference
The input and reference pins of the LTC2480 converter are
directly connected to a network of sampling capacitors.
Depending upon the relation between the differential input
voltage and the differential reference voltage, these ca-
pacitors are switching between these four pins transfer-
ring small amounts of charge in the process. A simplified
equivalent circuit is shown in Figure 11.
ParallelterminationneartheLTC2480pinwilleliminatethis
problem but will increase the driver power dissipation. A
seriesresistorbetween27Ωand56Ωplacednearthedriver
outputpinwillalsoeliminatethisproblemwithoutadditional
powerdissipation. Theactualresistorvaluedependsupon
the trace impedance and connection topology.
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, VREF+ or GND) can be
considered to form, together with RSW and CEQ (see
Figure 11), a first order passive network with a time
constant τ = (RS + RSW) • CEQ. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
An alternate solution is to reduce the edge rate of the con-
trol signals. It should be noted that using very slow edges
willincreasetheconverterpowersupplycurrentduringthe
transition time. The differential input architecture reduces
the converter’s sensitivity to ground currents.
Particular attention must be given to the connection of the
FO signal when the LTC2480 is used with an external
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals can result in DC gain and INL errors.
A normal mode signal of this frequency at the converter
input terminals can result in a DC offset error. Such
perturbations can occur due to asymmetric capacitive
coupling between the FO signal trace and the converter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the FO signal trace and the input/reference sig-
nals. When the FO signal is parallel terminated near the
When using the internal oscillator, the LTC2480’s front-
end switched-capacitor network is clocked at 123kHz
corresponding to an 8.1µs sampling period. Thus, for
settling errors of less than 1ppm, the driving source
impedance should be chosen such that τ ≤ 8.1µs/14 =
580ns. When an external oscillator of frequency fEOSC is
used, the sampling period is 2.5/fEOSC and, for a settling
error of less than 1ppm, τ ≤ 0.178/fEOSC
.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is low
(up to 10kΩ with no external bypass capacitor or up to
500Ωwith0.001µFbypass), completesettlingoftheinput
2480fa
26
LTC2480
W U U
APPLICATIO S I FOR ATIO
occurs. In this case, no errors are introduced and direct
digitization of the sensor is possible.
U
zero, the common mode input current (IIN++ IIN–)/2 is
proportional to the difference between the common mode
input voltage (VINCM) and the common mode reference
voltage (VREFCM).
Formanyapplications,thesensoroutputimpedancecom-
bined with external bypass capacitors produces RC time
constants much greater than the 580ns required for 1ppm
accuracy. For example, a 10kΩ bridge driving a 0.1µF
bypass capacitor has a time constant an order of magni-
tude greater than the required maximum. Historically,
settling issues were solved using buffers. These buffers
led to increased noise, reduced DC performance (Offset/
Drift), limited input/output swing (cannot digitize signals
near ground or VCC), added system cost and increased
power. The LTC2480 uses a proprietary switching algo-
rithm that forces the average differential input current to
zero independent of external settling errors. This allows
accurate direct digitization of high impedance sensors
without the need of buffers. Additional errors resulting
frommismatchedleakagecurrentsmustalsobetakeninto
account.
In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balance bridge type application, both the differ-
ential and common mode input current are zero. The
accuracy of the converter is unaffected by settling errors.
Mismatches in source impedances between IN+ and IN–
also do not affect the accuracy.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between VINCM and VREFCM. For a reference
common mode of 2.5V and an input common mode of
1.5V, the common mode input current is approximately
0.74µA(insimultaneous50Hz/60Hzrejectionmode). This
commonmodeinputcurrenthasnoeffectontheaccuracy
if the external source impedances tied to IN+ and IN– are
matched. Mismatches in these source impedances lead to
a fixed offset error but do not affect the linearity or full-
scale reading. A 1% mismatch in 1kΩ source resistances
leads to a 15ppm shift (74µV) in offset voltage.
The switching algorithm forces the average input current
on the positive input (IIN+) to be equal to the average input
current on the negative input (IIN–). Over the complete
conversion cycle, the average differential input current
(IIN+ – IIN–) is zero. While the differential input current is
V
CC
+
I
REF
R
(TYP)
SW
I
I
LEAK
LEAK
10k
+
V
IN(CM) − VREF(CM)
V
I IN+
= I IN–
=
REF
(
)
(
)
AVG
AVG
0.5• REQ
2
2
1.5VREF + VREF(CM) – V
V
(
IN(CM)
)
1.5• VREF − V
+ VREFCM
0.5• VREF • DT
REQ
V
IN
V
INCM
IN
I REF+
=
−
−
≅
–
CC
+
(
)
I
IN
AVG
0.5• REQ
VREF • REQ
0.5•REQ
VREF •REQ
R
(TYP)
10k
SW
I
I
LEAK
LEAK
where:
+
V
IN
+
C
⎛
⎞
EQ
VREF
2
VREFCM
=
12pF
⎜
⎟
⎝
⎠
(TYP)
V
= IN+ −IN−
CC
V
IN
–
I
IN
R
R
(TYP)
+
IN + IN−
SW
⎛
⎞
I
LEAK
LEAK
V
INCM
=
10k
⎜
⎟
–
2
⎝
⎠
V
IN
REQ = 2.71MΩ INTERNAL OSCILLATOR 60Hz MODE
REQ = 2.98MΩ INTERNAL OSCILLATOR 50Hz AND 60Hz MODE
REQ = 0.833• 1012 / fEOSC EXTERNAL OSCILLATOR
I
V
CC
–
I
REF
(
)
(TYP)
SW
10k
I
I
LEAK
LEAK
DT IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT
WHERE REF IS INTERNALLY TIED TO GND
2480 F11
GND
–
SWITCHING FREQUENCY
f
f
= 123kHz INTERNAL OSCILLATOR
SW
SW
= 0.4 • f
EXTERNAL OSCILLATOR
EOSC
Figure 11. LTC2480 Equivalent Analog Input Circuit
2480fa
27
LTC2480
APPLICATIO S I FOR ATIO
W U U
U
R
SOURCE
common mode input current varies proportionally with
input voltage. For the case of balanced input impedances,
thecommonmodeinputcurrenteffectsarerejectedbythe
large CMRR of the LTC2480 leading to little degradation in
accuracy. Mismatches in source impedances lead to gain
errorsproportionaltothedifferencebetweenthecommon
mode input voltage and the common mode reference
voltage. 1% mismatches in 1kΩ source resistances lead
to worst-case gain errors on the order of 15ppm or 1LSB
(for 1V differences in reference and input common mode
voltage). Table 7 summarizes the effects of mismatched
sourceimpedanceanddifferencesinreference/inputcom-
mon mode voltages.
+
IN
C
PAR
V
+ 0.5V
C
INCM
IN
EXT
≅20pF
LTC2480
R
SOURCE
–
IN
2480 F12
C
PAR
V
– 0.5V
C
INCM
IN
EXT
≅20pF
+
–
Figure 12. An RC Network at IN and IN
80
V
V
V
V
= 5V
CC
REF
IN
–
= 5V
= 3.75V
= 1.25V
60
40
20
+
IN
Table 7. Suggested Input Configuration for LTC2480
F
= GND
O
C
= 0pF
EXT
T
= 25°C
A
BALANCED INPUT
RESISTANCES
UNBALANCED INPUT
RESISTANCES
C
= 100pF
EXT
0
+
Constant
IN(CM)
C
> 1nF at Both
C
> 1nF at Both IN
C
EXT
= 1nF, 0.1µF, 1µF
EXT
+
EXT
–20
–40
–60
–80
–
–
V
– V
IN and IN . Can Take
Large Source Resistance
with Negligible Error
and IN . Can Take Large
Source Resistance.
Unbalanced Resistance
Results in an Offset
Which Can be Calibrated
REF(CM)
REF(CM)
10
100
R
10k
1
100k
1k
+
+
–
Varying
IN(CM)
C
> 1nF at Both IN
Minimize IN and IN
EXT
(Ω)
–
SOURCE
V
– V
and IN . Can Take Large
Source Resistance with
Negligible Error
Capacitors and Avoid
Large Source Impedance
(<5k Recommended)
2480 F13
+
–
Figure 13. +FS Error vs R
at IN or IN
SOURCE
Themagnitudeofthedynamicinputcurrentdependsupon
thesizeoftheverystableinternalsamplingcapacitorsand
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
andpowersupplyrangeistypicallybetterthan0.5%.Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current and offset
will be insignificant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufficient.
80
V
V
V
V
= 5V
CC
= 5V
REF
60
40
20
+
= 1.25V
= 3.75V
IN
–
IN
F
= GND
= 25°C
O
C
= 1nF, 0.1µF, 1µF
EXT
T
A
0
C
= 100pF
EXT
–20
C
= 0pF
EXT
–40
–60
–80
10
100
10k
1
100k
1k
(Ω)
R
SOURCE
2480 F14
+
–
Figure 14. –FS Error vs R
at IN or IN
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1µV typical and 10µV maximum offset voltage.
SOURCE
In applications where the common mode input voltage
varies as a function of input signal level (single-ended
input, RTDs, half bridges, current sensors, etc.), the
2480fa
28
LTC2480
W U U
APPLICATIO S I FOR ATIO
U
–VIN2/(VREF • REQ) – (0.5 • VREF • DT)/REQ in the reference
pin current as expressed in Figure 11. When using internal
oscillatorand60Hzmode, every100Ωofreferencesource
resistance translates into about 0.67ppm additional INL
error.Whenusinginternaloscillatorand50Hz/60Hzmode,
every 100Ω of reference source resistance translates into
about 0.61ppm additional INL error. When using internal
oscillatorand50Hzmode, every100Ωofreferencesource
resistance translates into about 0.56ppm additional INL
error. When FO is driven by an external oscillator with a
frequency fEOSC, every 100Ω of source resistance driving
VREF translates into about 2.18 • 10–6 • fEOSCppm addi-
tional INL error. Figure 19 shows the typical INL error due
to the source resistance driving the VREF pin when large
CREF values are used. The user is advised to minimize the
source impedance driving the VREF pin.
Reference Current
In a similar fashion, the LTC2480 samples the differential
reference pins VREF+ and GND transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gainandINLperformance.Theeffectofthiscurrentcanbe
analyzed in two distinct situations.
Forrelativelysmallvaluesoftheexternalreferencecapaci-
tors (CREF < 1nF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gainperformancewithoutsignificantbenefitsofreference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 1nF) may be
required as reference filters in certain configurations.
Suchcapacitorswillaveragethereferencesamplingcharge
and the external source resistance will see a quasi con-
stant reference differential impedance.
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (VREFCM – VINCM) and a 5V reference,
each Ohm of reference source resistance introduces an
extra (VREFCM – VINCM)/(VREF • REQ) full-scale gain error,
which is 0.074ppm when using internal oscillator and
60Hzmode.Whenusinginternaloscillatorand50Hz/60Hz
mode, the extra full-scale gain error is 0.067ppm. When
using internal oscillator and 50Hz mode, the extra gain
error is 0.061ppm. If an external clock is used, the corre-
sponding extra gain error is 0.24 • 10–6 • fEOSCppm.
In the following discussion, it is assumed the input and
reference common mode are the same. Using internal
oscillator for 60Hz mode, the typical differential refer-
ence resistance is 1MΩ which generates a full-scale
(VREF/2) gain error of 0.51ppm for each ohm of source
resistancedrivingtheVREF pin. For50Hz/60Hzmode, the
related difference resistance is 1.1MΩ and the resulting
full-scale error is 0.46ppm for each ohm of source
resistance driving the VREF pin. For 50Hz mode, the
related difference resistance is 1.2MΩ and the resulting
full-scale error is 0.42ppm for each ohm of source
resistance driving the VREF pin. When FO is driven by an
external oscillator with a frequency fEOSC (external con-
versionclockoperation),thetypicaldifferentialreference
resistance is 0.30 • 1012/fEOSC Ωand each ohm of source
resistance driving the VREF pin will result in 1.67 • 10–6 •
fEOSCppm gain error. The typical +FS and –FS errors for
various combinations of source resistance seen by the
VREF pin and external capacitance connected to that pin
are shown in Figures 15-18.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typically better
than0.5%.Suchaspecificationcanalsobeeasilyachieved
by an external clock. When relatively stable resistors
(50ppm/°C) are used for the external source impedance
seen by VREF+ and GND, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
valueovertheentiretemperatureandvoltagerange). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
The INL is caused by the input dependent terms
Inadditiontothereferencesamplingcharge,thereference
pinsESDprotectiondiodeshaveatemperaturedependent
2480fa
29
LTC2480
W U U
U
APPLICATIO S I FOR ATIO
90
0
V
V
V
V
= 5V
CC
REF
80
70
60
50
40
30
20
10
0
= 5V
+
= 3.75V
= 1.25V
= GND
= 25°C
IN
–
–100
–200
–300
–400
–500
IN
C
= 0.01µF
= 0.1µF
REF
F
O
T
A
C
= 0.01µF
REF
C
= 1µF, 10µF
C
= 0.001µF
REF
REF
C
= 100pF
= 0pF
REF
C
V
V
V
V
= 5V
REF
C
CC
REF
= 5V
REF
+
= 1.25V
= 3.75V
IN
–
IN
F
= GND
O
T
= 25°C
A
–10
0
10
100
1k
10k
100k
0
200
400
600
800
1000
R
(Ω)
R
(Ω)
SOURCE
SOURCE
2480 F15
2480 F18
Figure 15. +FS Error vs R
at V
(Small C )
REF
Figure 18. –FS Error vs R
at V
(Large C
)
REF
SOURCE
REF
SOURCE
REF
10
0
10
V
V
V
A
C
= 5V
CC
8
6
= 5V
REF
IN(CM)
= 25°C
R = 1k
= 2.5V
–10
–20
–30
–40
–50
–60
–70
–80
–90
C
REF
C
= 0.01µF
REF
T
C
= 0.001µF
= 10µF
REF
4
= 100pF
REF
REF
C
= 0pF
2
R = 500Ω
R = 100Ω
0
–2
–4
–6
–8
–10
V
V
V
V
= 5V
= 5V
= 1.25V
= 3.75V
= GND
= 25°C
CC
REF
+
IN
–
IN
F
O
T
A
0
10
100
R
1k
10k
100k
–0.5
–0.3
–0.1
V
0.1
0.3
0.5
(Ω)
/V
(V)
SOURCE
IN REF
2480 F16
2480 F19
Figure 19. INL vs Differential Input Voltage and
Reference Source Resistance for C > 1µF
Figure 16. –FS Error vs R
at V
(Small C )
REF
SOURCE
REF
REF
leakage current. This leakage current, nominally 1nA
(±10nA max), results in a small gain error. A 100Ω source
resistance will create a 0.05µV typical and 0.5µV maxi-
mum full-scale error.
500
V
V
V
V
= 5V
CC
C
= 1µF, 10µF
REF
= 5V
REF
+
= 3.75V
= 1.25V
IN
–
400
300
200
100
0
IN
F
= GND
= 25°C
O
T
C
= 0.1µF
A
REF
Output Data Rate
When using its internal oscillator, the LTC2480 produces
upto7.5samplespersecond(sps)withanotchfrequency
of 60Hz, 6.25sps with a notch frequency of 50Hz and
6.82sps with the 50Hz/60Hz rejection mode. The actual
output data rate will depend upon the length of the sleep
and data output phases which are controlled by the user
and which can be made insignificantly short. When oper-
C
= 0.01µF
REF
0
200
400
R
600
800
1000
(Ω)
SOURCE
2480 F17
atedwithanexternalconversionclock(FO connectedtoan
Figure 17. +FS Error vs R
at V
(Large C
)
REF
SOURCE
REF
2480fa
30
LTC2480
W U U
APPLICATIO S I FOR ATIO
external oscillator), the LTC2480 output data rate can be
increased as desired. The duration of the conversion
phase is 41036/fEOSC. If fEOSC = 307.2kHz, the converter
behaves as if the internal oscillator is used and the notch
is set at 60Hz.
U
50
40
V
V
V
F
= V
REF
IN(CM)
REF(CM)
= 5V
= V
CC
IN
= 0V
= EXT CLOCK
O
30
20
T
= 85°C
A
An increase in fEOSC over the nominal 307.2kHz will
translate into a proportional increase in the maximum
output data rate. The increase in output rate is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
10
0
T
= 25°C
A
–10
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent perfor-
mance degradation can be substantially reduced by rely-
ing upon the LTC2480’s exceptional common mode rejec-
tion and by carefully eliminating common mode to differ-
ential mode conversion sources in the input circuit. The
user should avoid single-ended input filters and should
maintain a very high degree of matching and symmetry in
the circuits driving the IN+ and IN– pins.
2480 F20
Figure 20. Offset Error vs Output Data Rate and Temperature
3500
V
V
F
= V
REF
IN(CM)
CC
REF(CM)
= 5V
= V
3000
2500
= EXT CLOCK
O
T
= 85°C
A
2000
1500
1000
500
T
= 25°C
A
Second, the increase in clock frequency will increase
proportionallytheamountofsamplingchargetransferred
through the input and the reference pins. If large external
inputand/orreferencecapacitors(CIN,CREF)areused,the
previous section provides formulae for evaluating the
effect of the source resistance upon the converter perfor-
manceforanyvalueoffEOSC.Ifsmallexternalinputand/or
reference capacitors (CIN, CREF) are used, the effect of the
external source resistance upon the LTC2480 typical
performance can be inferred from Figures 13, 14, 15 and
0
40
50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
30
10 20
2480 F21
Figure 21. +FS Error vs Output Data Rate and Temperature
0
–500
16 in which the horizontal axis is scaled by 307200/fEOSC
.
–1000
Third, an increase in the frequency of the external oscilla-
torabove1MHz(amorethan3× increaseintheoutputdata
rate) will start to decrease the effectiveness of the internal
autocalibration circuits. This will result in a progressive
degradation in the converter accuracy and linearity. Typi-
cal measured performance curves for output data rates up
to 100 readings per second are shown in Figures 20 to 27.
Inordertoobtainthehighestpossiblelevelofaccuracyfrom
this converter at output data rates above 20 readings per
second, the user is advised to maximize the power supply
voltage used and to limit the maximum ambient operating
T
= 25°C
A
–1500
–2000
–2500
–3000
T
= 85°C
A
V
V
F
= V
REF
IN(CM)
CC
O
REF(CM)
= 5V
= EXT CLOCK
= V
–3500
40
50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
30
10 20
2480 F22
Figure 22. –FS Error vs Output Data Rate and Temperature
2480fa
31
LTC2480
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U
APPLICATIO S I FOR ATIO
24
24
22
T
= 25°C
V
CC
= V
= 5V
REF
A
22
20
T
= 85°C
A
V
= 5V, V
= 2.5V
REF
CC
20
18
16
14
12
18
16
14
12
V
V
V
= V
REF
V
V
O
= V
IN(CM) REF(CM)
IN(CM)
REF(CM)
= 5V
= V
= 0V
CC
IN
IN
= 0V
F
= EXT CLOCK
F
= EXT CLOCK
T
= 25°C
A
O
RES = LOG 2 (V /NOISE
)
RES = LOG 2 (V /NOISE
)
RMS
REF
RMS
REF
10
10
10 20
40
50 60 70 80 90 100
0
30
50 60 70 80 90 100
0
30
40
10 20
OUTPUT DATA RATE (READINGS/SEC)
OUTPUT DATA RATE (READINGS/SEC)
2480 F23
2480 F26
Figure 23. Resolution (Noise
≤ 1LSB)
Figure 26. Resolution (Noise
≤ 1LSB)
RMS
RMS
vs Output Data Rate and Temperature
vs Output Data Rate and Reference Voltage
22
20
18
22
20
18
V
= V
= 5V
REF
T
= 25°C
T
= 85°C
CC
A
A
16
14
12
10
16
14
12
10
V
= 5V, V
= 2.5V
REF
CC
V
V
= V
REF(CM)
IN(CM)
IN
= 0V
–
V
V
F
= V
REF
= EXT CLOCK
REF = GND
= EXT CLOCK
IN(CM)
CC
O
REF(CM)
= V
= 5V
F
O
A
T
= 25°C
RES = LOG 2 (V /INL
)
RES = LOG 2 (V /INL
)
MAX
REF
MAX
REF
10 20
40
50 60 70 80 90 100
0
30
50 60 70 80 90 100
0
30
10 20
40
OUTPUT DATA RATE (READINGS/SEC)
OUTPUT DATA RATE (READINGS/SEC)
2480 F24
2480 F27
Figure 27. Resolution (INL
≤ 1LSB) vs
Figure 24. Resolution (INL
≤ 1LSB)
MAX
MAX
Output Data Rate and Reference Voltage
vs Output Data Rate and Temperature
20
15
10
5
V
V
F
= V
REF(CM)
IN(CM)
IN
O
= 0V
temperature. In certain circumstances, a reduction of the
differential reference voltage may be beneficial.
= EXT CLOCK
= 25°C
T
A
V
= V
= 5V
REF
CC
Input Bandwidth
The combined effect of the internal SINC4 digital filter and
of the analog and digital autocalibration circuits deter-
mines the LTC2480 input bandwidth. When the internal
oscillator is used with the notch set at 60Hz, the 3dB input
bandwidth is 3.63Hz. When the internal oscillator is used
with the notch set at 50Hz, the 3dB input bandwidth is
3.02Hz. If an external conversion clock generator of fre-
quency fEOSC is connected to the FO pin, the 3dB input
0
–5
V
CC
= 5V, V
= 2.5V
REF
–10
40
50 60 70 80 90 100
0
30
10 20
OUTPUT DATA RATE (READINGS/SEC)
2480 F25
Figure 25. Offset Error vs Output
Data Rate and Reference Voltage
bandwidth is 11.8 • 10–6 • fEOSC
.
2480fa
32
LTC2480
W U U
APPLICATIO S I FOR ATIO
U
0
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a first order filter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2480 input bandwidth is shown in
Figure 28. When an external oscillator of frequency fEOSC
is used, the shape of the LTC2480 input bandwidth can be
derived from Figure 28, 60Hz mode curve in which the
horizontal axis is scaled by fEOSC/307200.
–1
–2
–3
–4
–5
–6
50Hz AND
60Hz MODE
50Hz MODE
60Hz MODE
The conversion noise (600nVRMS typical for VREF = 5V)
can be modeled by a white noise source connected to a
noisefreeconverter.Thenoisespectraldensityis47nV√Hz
for an infinite bandwidth source and 64nV√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in
order to reduce the output referred noise and relatively
high bandwidth (at least 500kHz) necessary to drive the
input switched-capacitor network. A possible solution is a
high gain, low bandwidth amplifier stage followed by a
high bandwidth unity-gain buffer.
0
1
2
3
4
5
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2480 F28
Figure 28. Input Signal Bandwidth Using the Internal Oscillator
100
60Hz MODE
50Hz MODE
10
1
When external amplifiers are driving the LTC2480, the
ADC input referred system noise calculation can be sim-
plified by Figure 29. The noise of an amplifier driving the
LTC2480inputpincanbemodeledasabandlimitedwhite
noise source. Its bandwidth can be approximated by the
bandwidth of a single pole lowpass filter with a corner
frequency fi. The amplifier noise spectral density is ni.
FromFigure 29, usingfi asthex-axisselector, wecanfind
on the y-axis the noise equivalent bandwidth freqi of the
input driving amplifier. This bandwidth includes the band
limiting effects of the ADC internal calibration and filter-
ing. The noise of the driving amplifier referred to the
converter input and including all these effects can be
calculated as N = ni • √freqi. The total system noise
(referred to the LTC2480 input) can now be obtained by
summing as square root of sum of squares the three ADC
input referred noise sources: the LTC2480 internal noise,
the noise of the IN+ driving amplifier and the noise of the
IN– driving amplifier.
0.1
0.1
1
10 100 1k
10k 100k 1M
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz)
2480 F29
Figure 29. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
x-axis is scaled by fEOSC/307200. For large values of the
ratio fEOSC/307200, the Figure 29 plot accuracy begins to
decrease, but at the same time the LTC2480 noise floor
rises and the noise contribution of the driving amplifiers
lose significance.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2480 significantly
simplifies antialiasing filter requirements. Additionally,
the input current cancellation feature of the LTC2480
allowsexternallowpassfilteringwithoutdegradingtheDC
performance of the device.
If the FO pin is driven by an external oscillator of frequency
fEOSC, Figure29canstillbeusedfornoisecalculationifthe
2480fa
33
LTC2480
W U U
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APPLICATIO S I FOR ATIO
The SINC4 digital filter provides greater than 120dB nor-
mal mode rejection at all frequencies except DC and
integer multiples of the modulator sampling frequency
(fS). The LTC2480’s autocalibration circuits further sim-
plify the antialiasing requirements by additional normal
modesignalfilteringbothintheanaloganddigitaldomain.
Independent of the operating mode, fS = 256 • fN = 2048
• fOUTMAX where fN is the notch frequency and fOUTMAX is
the maximum output data rate. In the internal oscillator
mode with a 50Hz notch setting, fS = 12800Hz, with
50Hz/60Hz rejection, fS = 13960Hz and with a 60Hz notch
setting fS = 15360Hz. In the external oscillator mode, fS =
In 1x speed mode, the regions of low rejection occurring
at integer multiples of fS have a very narrow bandwidth.
Magnified details of the normal mode rejection curves are
shown in Figure 32 (rejection near DC) and Figure 33
(rejection at fS = 256fN) where fN represents the notch
frequency. These curves have been derived for the exter-
nal oscillator mode but they can be used in all operating
modes by appropriately selecting the fN value.
The user can expect to achieve this level of performance
using the internal oscillator as it is demonstrated by Fig-
ures 34, 35 and 36. Typical measured values of the normal
mode rejection of the LTC2480 operating with an internal
oscillator and a 60Hz notch setting are shown in Figure 34
f
EOSC/20. The performance of the normal mode rejection
is shown in Figures 30 and 31.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
f
2f 3f 4f 5f 6f 7f 8f 9f 10f 11f 12f
0
f 2f 3f 4f 5f 6f 7f 8f 9f 10f
S S S S S S S S S S
S
S
S
S
S
S
S
S
S
S
S
S
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2480 F30
2480 F31
Figure 30. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch Mode
Figure 31. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Notch Mode or External Oscillator
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
f
= f
EOSC/5120
N
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–120
250f 252f 254f 256f 258f 260f 262f
N
0
f
2f
3f
4f
5f
6f
7f
8f
N
N
N
N
N
N
N
N
N
N
N
N
N
N
INPUT SIGNAL FREQUENCY (Hz)
INPUT SIGNAL FREQUENCY (Hz)
2480 F33
2480 F32
Figure 32. Input Normal Mode Rejection at DC
Figure 33. Input Normal Mode Rejection at f = 256f
S N
2480fa
34
LTC2480
W U U
U
APPLICATIO S I FOR ATIO
0
As a result of these remarkable normal mode specifica-
tions, minimal (if any) antialias filtering is required in front
of the LTC2480. If passive RC components are placed in
front of the LTC2480, the input dynamic current should be
considered (see Input Current section). In this case, the
differentialinputcurrentcancellationfeatureoftheLTC2480
allows external RC networks without significant degrada-
tion in DC performance.
–20
5V
V
–40
–60
–80
–100
–120
0
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
Traditional high order delta-sigma modulators, while pro-
viding very good linearity and resolution, suffer from po-
tential instabilities at large input signal levels. The
proprietary architecture used for the LTC2480 third order
modulator resolves this problem and guarantees a pre-
dictablestablebehavioratinputsignallevelsofupto150%
of full scale. In many industrial applications, it is not un-
commontohavetomeasuremicrovoltlevelsignalssuper-
imposed over volt level perturbations and the LTC2480 is
eminently suited for such tasks. When the perturbation is
differential,thespecificationofinterestisthenormalmode
rejection for large input signal levels. With a reference
voltage VREF = 5V, the LTC2480 has a full-scale differen-
tial input range of 5V peak-to-peak. Figures 37 and 38
show measurement results for the LTC2480 normal mode
rejectionratiowitha7.5Vpeak-to-peak(150%offullscale)
input signal superimposed over the more traditional nor-
mal mode rejection ratio results obtained with a 5V peak-
to-peak (full scale) input signal. In Figure 37, the LTC2480
uses the internal oscillator with the notch set at 60Hz (FO
= LOW) and in Figure 38 it uses the internal oscillator with
the notch set at 50Hz. It is clear that the LTC2480 rejection
performance is maintained with no compromises in this
extreme situation. When operating with large input signal
levels, the user must observe that such signals do not
violate the device absolute maximum ratings.
2480 F34
Figure 34. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (60Hz Notch)
0
5V
V
–20
–40
–60
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2480 F35
Figure 35. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (50Hz Notch)
0
V
= 5V
CC
–20
–40
–60
–80
–100
–120
0
20
40
60
80
100
120
140
160
180
200
220
Using the 2x speed mode of the LTC2480, the device
bypasses the digital offset calibration operation to double
the output data rate. The superior normal mode rejection
ismaintainedasshowninFigures30and31. However, the
magnified details near DC and fS = 256fN are different, see
Figures 39 and 40. In 2x speed mode, the bandwidth is
11.4Hz for the 50Hz rejection mode, 13.6Hz for the 60Hz
rejection mode and 12.4Hz for the 50Hz/60Hz rejection
INPUT FREQUENCY (Hz)
2483 F36
Figure 36. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (50Hz/60Hz Mode)
superimposed over the theoretical calculated curve. Simi-
larly, themeasurednormalmoderejectionoftheLTC2480
forthe50Hzrejectionmodeand50Hz/60Hzrejectionmode
are shown in Figures 35 and 36.
2480fa
35
LTC2480
W U U
U
APPLICATIO S I FOR ATIO
0
–20
0
V
= 5V
V
V
V
T
= 5V
= 5V
CC
CC
V
= 5V
V
V
= 5V
IN(P-P)
IN(P-P)
REF
= 7.5V
(150% OF FULL SCALE)
–20
–40
= 2.5V
INCM
= 25°C
A
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
0
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2480 F38
2480 F37
Figure 38. Measured Input Normal Mode Rejection vs
Input Frequency with Input Perturbation of 150% Full
Scale (50Hz Notch)
Figure 37. Measured Input Normal Mode Rejection vs
Input Frequency with Input Perturbation of 150% Full
Scale (60Hz Notch)
0
–20
0
–20
–40
–60
–80
–100
–40
–60
–80
–100
–120
–120
248 250 252 254 256 258 260 262 264
0
f
2f
N
3f
N
4f 5f
6f
N
7f
N
8f
N
N
N
N
INPUT SIGNAL FREQUENCY (f
)
N
INPUT SIGNAL FREQUENCY (f
)
N
2480 F48
2480 F39
Figure 39. Input Normal Mode Rejection 2x Speed Mode
Figure 40. Input Normal Mode Rejection 2x Speed Mode
–70
0
MEASURED DATA
CALCULATED DATA
V
V
V
V
= 5V
CC
= 5V
REF
–80
–20
–40
= 2.5V
INCM
NO AVERAGE
= 5V
IN(P-P)
–90
F
= GND
= 25°C
O
T
A
WITH
RUNNING
AVERAGE
–100
–110
–120
–130
–140
–60
–80
–100
–120
48 50
52
54 56
58
60
62
0
25 50 75 100 125 150 175 200 225
INPUT FREQUENCY (Hz)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2480 F42
2480 F41
Figure 41. Input Normal Mode Rejection vs Input Frequency,
2x Speed Mode and 50Hz/60Hz Mode
Figure 42. Input Normal Mode Rejection 2x Speed Mode
mode. Typical measured values of the normal mode
rejection of the LTC2480 operating with the internal oscil-
lator and 2x speed mode is shown in Figure 41.
When the LTC2480 is configured in 2x speed mode, by
performing a running average, a SINC1 notch is combined
with the SINC4 digital filter, yielding the normal mode
2480fa
36
LTC2480
W U U
APPLICATIO S I FOR ATIO
U
rejection identical as that for the 1x speed mode. The
averaging operation still keeps the output rate with the
following algorithm:
meter,thecoldjunctiontemperaturesensormustbeatthe
same temperature as the junction between the thermo-
couple materials and the copper printed circuit board
traces. The tiny LTC2480 can be tucked neatly underneath
an Omega MPJ-K-F thermocouple socket ensuring close
thermal coupling.
Result 1 = average (sample 0, sample 1)
Result 2 = average (sample 1, sample 2)
……
The LTC2480’s 1.4mV/°C PTAT circuit measures the cold
junction temperature. Once the thermocouple voltage and
coldjunctiontemperatureareknown,therearemanyways
of calculating the thermocouple temperature including a
straight-lineapproximation, lookuptablesorapolynomial
curve fit. Calibration is performed by applying an accurate
500mV to the ADC input derived from an LT®1236 refer-
ence and measuring the local temperature with an accu-
rate thermometer as shown in Figure 43. In calibration
mode,theupanddownbuttonsareusedtoadjustthelocal
temperature reading until it matches an accurate ther-
mometer. Both the voltage and temperature calibration
are easily automated.
Result n = average (sample n – 1, sample n)
The main advantage of the running average is that it
achieves simultaneous 50Hz/60Hz rejection at twice the
effective output rate, as shown in Figure 42. The raw
output data provides a better than 70dB rejection over
48Hz to 62.4Hz, which covers both 50Hz ±2% and 60Hz
±2%. With running average on, the rejection is better than
87dB for both 50Hz ±2% and 60Hz ±2%.
Complete Thermocouple Measurement System with
Cold Junction Compensation
TheLTC2480isidealfordirectdigitizationofthermocouples
andotherlowvoltageoutputsensors.Theinputhasatypical
offset error of 500nV (2.5µV max) offset drift of 10nV/°C
and a noise level of 600nVRMS. The input span may be
optimized for various sensors by setting the gain of the
PGA. Using an external 5V reference with a PGA gain of 64
gives a ±78mV input range—perfect for thermocouples.
The complete microcontroller code for this application is
available on the LTC2480 product webpage at:
http://www.linear.com
It can be used as a template for may different instruments
and it illustrates how to generate calibration coefficients
for the onboard temperature sensor. Extensive comments
detail the operation of the program. The read_LTC2480()
function controls the operation of the LTC2480 and is
listed below for reference.
Figure 44 (last page of this data sheet) is a complete type
K thermocouple meter. The only signal conditioning is a
simple surge protection network. In any thermocouple
5V
C8
1µF
C7
0.1µF
ISOTHERMAL
LT1236
2
6
5
3
2
IN OUT
TRIM
GND
4
R2
2k
6
9
7
1
REF
V
CC
R7
8k
CS
SCK
SDO
SDI
4
5
+
+
–
IN
IN
G1
NC1M4V0
LTC2480
R8
1k
10
F
O
GND GND
8
11
2480 F43
TYPE K
THERMOCOUPLE
JACK
(OMEGA MPJ-K-F)
26.3C
Figure 43. Calibration Setup
2480fa
37
LTC2480
APPLICATIO S I FOR ATIO
W U U
U
/*** read_LTC2480() ************************************************************
This is the function that actually does all the work of talking to the LTC2480.
The spi_read() function performs an 8 bit bidirectional transfer on the SPI bus.
Data changes state on falling clock edges and is valid on rising edges, as
determined by the setup_spi() line in the initialize() function.
A good starting point when porting to other processors is to write your own
spi_write function. Note that each processor has its own way of configuring
the SPI port, and different compilers may or may not have built-in functions
for the SPI port. Also, since the state of the LTC2480’s SDO line indicates
when a conversion is complete you need to be able to read the state of this line
through the processor’s serial data input. Most processors will let you read
this pin as if it were a general purpose I/O line, but there may be some that
don’t.
When in doubt, you can always write a “bit bang” function for troubleshooting
purposes.
The “fourbytes” structure allows byte access to the 32 bit return value:
struct fourbytes // Define structure of four consecutive bytes
{
// To allow byte access to a 32 bit int or float.
//
// The make32() function in this compiler will
// also work, but a union of 4 bytes and a 32 bit int
// is probably more portable.
int8 te0;
int8 te1;
int8 te2;
int8 te3;
};
Also note that the lower 4 bits are the configuration word from the previous
conversion. The 4 LSBs are cleared so that
they don’t affect any subsequent mathematical operations. While you can do a
right shift by 4, there is no point if you are going to convert to floating point
numbers - just adjust your scaling constants appropriately.
*******************************************************************************/
signed int32 read_LTC2480(char config)
{
union
{
// adc_code.bits32
// adc_code.by.te0
// adc_code.by.te1
// adc_code.by.te2
// adc_code.by.te3
all 32 bits
byte 0
byte 1
byte 2
byte 3
signed int32 bits32;
struct fourbytes by;
} adc_code;
output_low(CS);
while(input(PIN_C4)) {}
// Enable LTC2480 SPI interface
// Wait for end of conversion. The longest
// you will ever wait is one whole conversion period
// Now is the time to switch any multiplexers because the conversion is finished
// and you have the whole data output time for things to settle.
adc_code.by.te3 = 0;
// Set upper byte to zero.
adc_code.by.te2 = spi_read(config);
adc_code.by.te1 = spi_read(0);
adc_code.by.te0 = spi_read(0);
// Read first byte, send config byte
// Read 2nd byte, send speed bit
// Read 3rd byte. ‘0’ argument is necessary
// to act as SPI master!! (compiler
// and processor specific.)
output_high(CS);
// Disable LTC2480 SPI interface
// Clear configuration bits and subtract offset. This results in
// a 2’s complement 32 bit integer with the LTC2480’s MSB in the 2^20 position
adc_code.by.te0 = adc_code.by.te0 & 0xF0;
adc_code.bits32 = adc_code.bits32 - 0x00200000;
return adc_code.bits32;
} // End of read_LTC2480()
2480fa
38
LTC2480
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
TYP
6
0.38 ± 0.10
10
0.675 ±0.05
3.50 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PACKAGE
OUTLINE
(DD) DFN 1103
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50
BSC
2.38 ±0.10
(2 SIDES)
2.38 ±0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev A)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
REF
10 9
8
7 6
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
0.889 ± 0.127
(.035 ± .005)
DETAIL “A”
0° – 6° TYP
0.254
(.010)
GAUGE PLANE
5.23
(.206)
MIN
1
2
3
4 5
3.20 – 3.45
(.126 – .136)
0.53 ± 0.152
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.18
(.007)
SEATING
PLANE
RECOMMENDED SOLDER PAD LAYOUT
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ± 0.0508
(.004 ± .002)
0.50
(.0197)
BSC
MSOP (MS) 0207 REV A
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
2480fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
39
LTC2480
U
TYPICAL APPLICATIO
5V
PIC16F73
RC7
C8
C7
0.1µF
20
18
17
16
15
14
13
12
11
28
27
26
25
24
23
22
21
7
5V
V
1µF
DD
C6
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RA5
RA4
RA3
RA2
RA1
RA0
0.1µF
ISOTHERMAL
Y1
3
2
R2
2k
9
6MHz
6
9
7
1
REF
V
CC
CS
SCK
SDO
SDI
OSC1
OSC2
4
5
+
–
IN
IN
10
LTC2480
D1
BAT54
R1
10k
10
TYPE K
THERMOCOUPLE
JACK
F
O
GND GND
1
5V
MCLR
8
11
(OMEGA MPJ-K-F)
5V
D7
D6
D5
D4
EN
RW
RS
V
CC
2 × 16 CHARACTER
LCD DISPLAY
(OPTREX DMC162488
OR SIMILAR)
CONTRAST
GND D0 D1 D2 D3
6
5
4
3
5V
1
3
R6
9
V
V
5k
2
SS
SS
19
2
5V
2480 F44
R3
R4
R5
CALIBRATE
10k 10k 10k
2
1
DOWN
UP
Figure 44. Complete Type K Thermocouple Meter
RELATED PARTS
PART NUMBER
LTC1050
DESCRIPTION
COMMENTS
Precision Chopper Stabilized Op Amp
Precision Bandgap Reference, 5V
Micropower Series Reference
No External Components 5µV Offset, 1.6µV Noise
P-P
LT1236A-5
0.05% Max Initial Accuracy, 5ppm/°C Drift
LT1460
0.075% Max Initial Accuracy, 10ppm/°C Max Drift
LTC2400
24-Bit, No Latency ∆Σ ADC in SO-8
1-/2-Channel, 24-Bit, No Latency ∆Σ ADCs in MSOP
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2401/LTC2402
LTC2404/LTC2408
4-/8-Channel, 24-Bit, No Latency ∆Σ ADCs
with Differential Inputs
LTC2410
24-Bit, No Latency ∆Σ ADC with Differential Inputs
0.8µV
Noise, 2ppm INL
RMS
LTC2411/LTC2411-1 24-Bit, No Latency ∆Σ ADCs with Differential Inputs in MSOP
1.45µV
Noise, 4ppm INL,
RMS
Simultaneous 50Hz/60Hz Rejection (LTC2411-1)
LTC2413
24-Bit, No Latency ∆Σ ADC with Differential Inputs
24-Bit, No Latency ∆Σ ADCs with 15Hz Output Rate
Simultaneous 50Hz/60Hz Rejection, 800nV
Noise
RMS
LTC2415/
LTC2415-1
Pin Compatible with the LTC2410
LTC2414/LTC2418
LTC2420
8-/16-Channel 24-Bit, No Latency ∆Σ ADCs
20-Bit, No Latency ∆Σ ADC in SO-8
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200µA
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
2.8µV Noise, SSOP-16/MSOP Package
LTC2430/LTC2431
20-Bit, No Latency ∆Σ ADCs with Differential Inputs
LTC2435/LTC2435-1 20-Bit, No Latency ∆Σ ADCs with 15Hz Output Rate
3ppm INL, Simultaneous 50Hz/60Hz Rejection
3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs
Pin Compatible with LTC2480/LTC2484
LTC2440
LTC2482
LTC2484
High Speed, Low Noise 24-Bit ∆Σ ADC
16-Bit ∆Σ ADC with Easy Drive Inputs
24-Bit ∆Σ ADC with Easy Drive Inputs
Pin Compatible with LTC2480/LTC2482
2480fa
LT 0307 REV A • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
40
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
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