LTC3561AIDD-PBF [Linear]
1A, 4MHz, Synchronous Step-Down DC/DC Converter; 1A ，为4MHz ，同步降压型DC / DC转换器
| 型号： | LTC3561AIDD-PBF |
| 厂家： | 
Linear |
| 描述： | 1A, 4MHz, Synchronous Step-Down DC/DC Converter |
| 文件： | 总20页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3561A
1A, 4MHz, Synchronous
Step-Down DC/DC Converter
FEATURES
DESCRIPTION
The LTC®3561A is a constant frequency, synchronous
step-down DC/DC converter. Intended for medium power
applications, it operates from a 2.5V to 5.5V input voltage
range and has a user configurable operating frequency up
to 4MHz, allowing the use of tiny, low cost capacitors and
inductors 1mm or less in height. The output voltage is
adjustable from 0.8V to 5.5V. Internal synchronous power
switches provide high efficiency. The LTC3561A’s current
mode architecture and external compensation allow the
transient response to be optimized over a wide range of
loads and output capacitors.
■
Uses Tiny Capacitors and Inductor
■
High Frequency Operation: Up to 4MHz
■
Low R
Internal Switches: 0.15Ω
DS(ON)
■
■
■
High Efficiency: Up to 96%
Stable with Ceramic Capacitors
Current Mode Operation for Excellent Line
and Load Transient Response
Short-Circuit Protected
Low Dropout Operation: 100% Duty Cycle
■
■
■
■
■
■
■
Low Shutdown Current: I ≤ 1μA
Q
Low Quiescent Current: 330μA
Output Voltages from 0.8V to 5V
To further maximize battery life, the P-channel MOSFET
is turned on continuously in dropout (100% duty cycle).
In shutdown, the device draws <1μA.
V : 2.5V to 5.5V
IN
Small 8-Lead 3mm × 3mm DFN Package
, LT, LTC and LTM are registered trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 6580258, 6498466, 6611131.
APPLICATIONS
■
Notebook Computers
■
Digital Cameras
■
Cellular Phones
Handheld Instruments
■
■
Board Mounted Power Supplies
TYPICAL APPLICATION
Efficiency and Power Loss vs Output Current
Step-Down 2.5V/1A Regulator
100
90
80
70
60
50
40
30
20
10
0
1
V
IN
2.5V TO 5.5V
10μF
0.1
PV
SV
IN
IN
SW
2.2μH
22pF
V
2.5V
1A
OUT
0.01
LTC3561A
22μF
I
V
O
= 2.5V
TH
OUT
249k
118k
f
= 1MHz
0.001
SHDN/R
V
FB
T
16.9k
680pF
V
V
V
= 2.7V
= 3.6V
= 4.2V
IN
IN
IN
SGND
PGND
549k
0.0001
10000
1
10
100
1000
3561a TA01a
OUTPUT CURRENT (mA)
3561A TA01b
3561af
1
LTC3561A
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
PV , SV Voltages ..................................... –0.3V to 6V
IN
IN
V , I , SHDN/R Voltages ..........–0.3V to (V + 0.3V)
FB TH
T
IN
SHDN/R
1
2
3
4
8
7
6
5
I
TH
T
SW Voltage ..................................–0.3V to (V + 0.3V)
IN
SGND
SW
V
FB
9
Operating Junction Temperature Range
SV
PV
IN
IN
(Notes 2, 5, 8)........................................ –40°C to 125°C
Storage Temperature Range................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
PGND
DD PACKAGE
8-LEAD (3mm s 3mm) PLASTIC DFN
T
= 125°C, θ = 43°C/W, θ = 3°C/W
JA JC
JMAX
EXPOSED PAD (PIN 9) IS SGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC3561AEDD#PBF
LTC3561AIDD#PBF
TAPE AND REEL
PART MARKING*
LDKB
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3561AEDD#TRPBF
LTC3561AIDD#TRPBF
–40°C to 125°C
–40°C to 125°C
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
LDKB
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, RT = 125k unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Operating Voltage Range
2.5
5.5
V
IN
I
Feedback Pin Input Current
Feedback Voltage
(Note 3)
(Note 3)
0.1
0.816
0.2
μA
V
FB
●
●
V
0.784
0.8
0.04
0.02
300
FB
Reference Voltage Line Regulation
Output Voltage Load Regulation
Error Amplifier Transconductance
V
I
= 2.5V to 5.5V
%/V
%
ΔV
ΔV
IN
LINEREG
= 0.55V to 0.9V
0.2
TH
TH
LOADREG
g
I
Pin Load = 5μA (Note 3)
μS
m(EA)
3561af
2
LTC3561A
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, RT = 125k unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Input DC Supply Current (Note 4)
Active Mode
Shutdown
S
V
V
= 0.75V
330
0.1
450
1
μA
μA
FB
SHDN/RT
= 3.6V
V
Shutdown Threshold High Active
Oscillator Resistor
Oscillator Frequency
V
– 0.6
125k
2.5
V – 0.4
IN
V
SHDN/RT
IN
1M
Ω
f
I
R = 125k
2.25
1.3
2.8
4
MHz
MHz
OSC
T
(Note 7)
Peak Switch Current Limit
Top Switch On-Resistance
Bottom Switch On-Resistance
Switch Leakage Current
V
FB
= 0.5V
2.0
0.15
0.13
0.01
2.1
2.5
0.18
0.16
1
A
LIM
R
(Note 6)
(Note 6)
Ω
DS(ON)
Ω
I
V
IN
V
IN
= 5V, V
= 3.6V, V = 0V or 5V
μA
V
SW(LKG)
SHDN/RT
SW
V
Undervoltage Lockout Threshold
Ramping Down
1.8
0.5
2.4
1
UVLO
t
10% to 90% of Regulation
0.8
ms
SOFT-START
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3561AEDD is guaranteed to meet specified performance
specifications from 0°C to 85°C junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3561AIDD is guaranteed over the full –40°C to 125°C operating
junction temperature range.
Note 5: T is calculated from the ambient T and power dissipation P
according to the following formulas:
J
A
D
T = T + (P • 43°C/W)
J
A
D
Note 6: Switch on-resistance is sampled at wafer level measurements and
assured by design, characterization and correlation with statistical process
controls.
Note 7: 4MHz operation is guaranteed by design but not production tested
and is subject to duty cycle limitations (see Applications Information).
Note 8: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: The LTC3561A is tested in a feedback loop which servos V to the
FB
midpoint for the error amplifier (V = 0.7V).
ITH
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
3561af
3
LTC3561A
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.6V, fO = 1MHz, unless otherwise noted.
Efficiency vs Input Voltage
Efficiency vs Output Current
Efficiency vs Output Current
100
95
90
85
80
75
70
65
60
55
50
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
= 1.8V
V
= 1.8V
V
= 1.5V
OUT
OUT
OUT
I
= 100mA
OUT
I
= 1A
OUT
I
= 10mA
OUT
V
V
V
= 2.7V
= 3.6V
= 4.2V
V
V
V
= 2.7V
= 3.6V
= 4.2V
IN
IN
IN
IN
IN
IN
2.5
3.0
4.0
4.5
5.0
5.5
3.5
1
10
100
1000
10000
1
10
100
1000
10000
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
3561A G02
3561A G03
3561A G01
Efficiency vs Frequency
Load Regulation
Line Regulation
0.4
0.6
95
V
= 1.8V
V
= 1.8V
= 400mA
OUT
V
= 1.8V
= 400mA
OUT
OUT
I
LOAD
I
LOAD
94
93
92
91
90
89
88
0.3
0.2
0.1
0
0.4
0.2
4.7μH
2.2μH
0.0
1μH
–0.2
–0.4
–0.6
–0.1
–0.2
800
4.5
INPUT VOLTAGE(V)
0
200 400 600
1000 1200 1400
2.5
4.0
5.0
5.5
3.0
3.5
4
0
1
2
3
5
OUTPUT CURRENT(mA)
FREQUENCY (MHz)
3561A G06
3561A G07
3561A G05
Reference Voltage vs
Temperature
Frequency Variation vs
Temperature
Frequency Variation vs VIN
6
4
2
6
815
4
2
810
805
800
795
790
785
0
–2
–4
–6
–8
0
–2
–4
–6
4.5
50
2.5
3.0
3.5
4.0
(V)
5.0
5.5
–50 –25
0
25
75 100 125
50
–50 –25
0
25
75 100 125
V
TEMPERATURE(°C)
TEMPERATURE(°C)
IN
3561A G10
3561A G09
3561A G08
3561af
4
LTC3561A
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.6V, fO = 1MHz, unless otherwise noted.
Dynamic Supply Current vs
Input Voltage
RDS(ON) vs Temperature
RDS(ON) vs Input Voltage
0.25
0.20
0.30
0.25
300
290
280
270
V
= 1.8V
= 0A
OUT
I
LOAD
MAIN SWITCH
0.20
0.15
0.10
0.15
0.10
MAIN SWITCH
260
250
SYNCHRONOUS SWITCH
SYNCHRONOUS SWITCH
240
230
220
0.05
0.0
0.05
0.0
4.5
INPUT VOLTAGE (V)
3
3.5
4.5
2.5
3.0
3.5
4.0
5.0
5.5
50
TEMPERATURE (°C)
2.5
5
5.5
–50 –25
0
25
75 100 125
4
V
(V)
IN
3561A G11
3561A G13
3561A G12
Supply Current vs
Temperature
Switch Leakage vs Temperature
Switch Leakage vs Input Voltage
360
600
500
2500
V
LOAD
= 1.8V
= 0A
OUT
I
340
320
2000
1500
1000
MAIN SWITCH
400
300
200
100
0
300
280
260
240
220
SYNCHRONOUS
SWITCH
SYNCHRONOUS
SWITCH
MAIN SWITCH
500
0
200
–25
0
50
75 100 125
–50
25
50
–50 –25
0
25
75 100 125
4
0
1
2
3
5
6
TEMPERATURE (°C)
TEMPERATURE (°C)
INPUT VOLTAGE(V)
3561A G14
3561A G16
3561A G15
Switching Waveforms
Start-Up from Shutdown
SHDN/R
T
SW
2V/DIV
2V/DIV
V
V
OUT
OUT
1V/DIV
50mV/DIV
AC COUPLED
I
I
L
L
1A/DIV
200mA/DIV
3561A G20
3561A G18
4μs/DIV
V
V
= 3.6V
IN
OUT
I
LOAD
200μs/DIV
V
V
LOAD
= 3.6V
IN
= 1.8V
= 5mA
= 1.8V
= 0A
OUT
I
3561af
5
LTC3561A
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.6V, fO = 1MHz, unless otherwise noted.
Load Step
Start-Up from Shutdown
Load Step
SHDN/R
T
V
V
OUT
OUT
2V/DIV
100mV/DIV
100mV/DIV
AC COUPLED
AC COUPLED
V
OUT
I
I
L
L
1V/DIV
1A/DIV
1A/DIV
I
I
LOAD
LOAD
1A/DIV
I
1A/DIV
L
1A/DIV
3561A G23
3561A G21
3561A G24
40μs/DIV
V
V
I
= 3.6V
= 1.8V
200μs/DIV
40μs/DIV
= 1.8V
= 20mA to 1A
V
V
I
= 3.6V
V
V
I
= 3.6V
IN
OUT
IN
OUT
IN
OUT
= 1.8V
= 1A
= 0A to 1A
LOAD
LOAD
LOAD
Load Step
VOUT Short to Ground
V
OUT
V
OUT
100mV/DIV
1V/DIV
AC COUPLED
I
L
1A/DIV
I
L
2A/DIV
I
LOAD
1A/DIV
3561A G25
3561A G26
40μs/DIV
= 1.8V
= 200mA to 1A
V
V
I
= 3.6V
40μs/DIV
V
V
I
= 3.6V
IN
OUT
IN
OUT
= 1.8V
= 0A
LOAD
LOAD
3561af
6
LTC3561A
PIN FUNCTIONS
SHDN/R (Pin 1): Combination Shutdown and Timing
SV (Pin 6): The Signal Power Pin. All active circuitry
T
IN
Resistor Pin. The oscillator frequency is programmed by
is powered from this pin. Must be closely decoupled to
connecting a resistor from this pin to ground. Forcing
SGND. SV must be greater than or equal to PV .
IN
IN
this pin to SV causes the device to be shut down. In
IN
V
(Pin 7): Receives the feedback voltage from the ex-
FB
shutdown all functions are disabled.
ternal resistive divider across the output. Nominal voltage
SGND (Pin 2): Signal Ground. All SGND and PGND pins
must be connected together through a thick copper trace
orgroundplane.
for this pin is 0.8V.
I (Pin8):ErrorAmplifierCompensationPoint.Thecurrent
TH
comparator threshold increases with this control voltage.
SW (Pin 3): The Switch Node Connection to the Inductor.
Nominal voltage range for this pin is 0.4V to 1.4V.
This pin swings from PV to PGND.
IN
Exposed Pad (Pin 9): Signal Ground. All small-signal
components and compensation components should be
connected to this ground (see Board Layout Consider-
ations). Must be soldered to electrical ground on PCB.
All SGND and PGND pins must be connected together
through a thick copper trace or ground plane.
PGND (Pin 4): Power Ground. Connect to the (–) terminal
of C , and (–) terminal of C . All SGND and PGND pins
OUT
IN
must be connected together through a thick copper trace
or ground plane.
PV (Pin 5): Main Supply Pin. Must be closely decoupled
IN
to PGND.
NOMINAL (V)
TYP
ABSOLUTE MAX (V)
PIN
1
NAME
SHDN/R
DESCRIPTION
MIN
MAX
MIN
MAX
Shutdown/Timing Resistor
Signal Ground
–0.3
0.8
0
SV
–0.3
SV + 0.3
T
IN
IN
2
SGND
SW
3
Switch Node
0
PV
–0.3
PV + 0.3
IN
IN
4
PGND
Main Power Ground
Main Power Supply
Signal Power Supply
Output Feedback Pin
Error Amplifier Compensation and Run Pin
0
5
PV
IN
SV
IN
–0.3
2.5
0
5.5
–0.3
–0.3
–0.3
–0.3
SV + 0.3
IN
6
5.5
1.0
1.4
6
7
V
0.8
SV + 0.3
IN
FB
8
I
TH
0.4
SV + 0.3
IN
3561af
7
LTC3561A
BLOCK DIAGRAM
SV
SGND
2
I
PV
IN
IN
TH
6
8
5
0.8V
PMOS CURRENT
COMPARATOR
VOLTAGE
REFERENCE
I
TH
LIMIT
BCLAMP
+
–
+
–
–
+
7
V
FB
ERROR
AMPLIFIER
V
B
BURST
COMPARATOR
SLOPE
COMPENSATION
3
SW
OSCILLATOR
+
LOGIC
–
NMOS
COMPARATOR
–
+
4
PGND
REVERSE
COMPARATOR
1
SHDN/R
3561A BD
T
3561af
8
LTC3561A
OPERATION
The LTC3561A uses a constant frequency, current mode
V decrease slightly. This decrease in V causes the er-
FB FB
architecture. The operating frequency is determined by
ror amplifier to increase the I voltage until the average
TH
the value of the R resistor.
inductor current matches the new load current.
T
The output voltage is set by an external divider returned to
ThemaincontrolloopisshutdownbypullingtheSHDN/R
T
theV pin.Anerroramplifiercomparesthedividedoutput
pin to SV , resetting the internal soft-start. Re-enabling
FB
IN
voltage with the reference voltage of 0.8V and adjusts the
peak inductor current accordingly.
the main control loop by releasing the SHDN/R pin
T
activates the internal soft-start, which slowly ramps the
output voltage over approximately 0.8ms until it reaches
regulation.
Main Control Loop
Duringnormaloperation,thetoppowerswitch(P-channel
MOSFET) is turned on at the beginning of a clock cycle.
Current flows through this switch into the inductor and
theload,increasinguntilthepeakinductorcurrentreaches
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which
is the dropout condition. In dropout, the PMOS switch
is turned on continuously with the output voltage being
equal to the input voltage minus the voltage drop across
the internal P-channel MOSFET and the inductor.
the limit set by the voltage on the I pin. Then the top
TH
switch is turned off, the bottom switch is turned on, and
the energy stored in the inductor forces the current to flow
through the bottom switch, and the inductor, out into the
load until the next clock cycle.
Low Supply Operation
The peak inductor current is controlled by the voltage
TheLTC3561Aincorporatesanundervoltagelockoutcircuit
which shuts down the part when the input voltage drops
below about 2.1V to prevent unstable operation.
on the I pin, which is the output of the error amplifier.
TH
The output is developed by the error amplifier comparing
the feedback voltage, V , to the 0.8V reference voltage.
FB
When the load current increases, the output voltage and
3561af
9
LTC3561A
APPLICATIONS INFORMATION
A general LTC3561A application circuit is shown in
Figure 4.Externalcomponentselectionisdrivenbytheload
requirement, and begins with the selection of the inductor
Inductor Selection
The operating frequency, f , has a direct effect on the
O
inductorvalue, whichinturninfluencestheinductorripple
L1. Once L1 is chosen, C and C
can be selected.
IN
OUT
current, ΔI :
L
Operating Frequency
⎛
⎞
VOUT
fO •L
VOUT
VIN
ΔIL =
• 1−
⎜
⎝
⎟
Selectionoftheoperatingfrequencyisatrade-offbetween
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
⎠
The inductor ripple current decreases with larger induc-
tance or frequency, and increases with higher V or V
.
IN
OUT
Accepting larger values of ΔI allows the use of lower
L
inductances, but results in higher output ripple voltage,
greater core loss and lower output capability.
A reasonable starting point for setting ripple current is
Theoperatingfrequency,f ,oftheLTC3561Aisdetermined
by an external resistor that is connected between the R
pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timingcapacitorwithintheoscillatorandcanbecalculated
by using the following equation:
O
ΔI = 0.4 • I
, where I
is 1A. The largest
L
OUT(MAX)
OUT(MAX)
T
ripple current ΔI occurs at the maximum input voltage.
L
Toguaranteethattheripplecurrentstaysbelowaspecified
maximum, theinductorvalueshouldbechosenaccording
to the following equation:
⎛
⎞
VOUT
fO • ΔIL
VOUT
VIN(MAX)
7
–1.6508
R ≈ 5 × 10 (f )
(kΩ)
L =
• 1−
T
O
⎜
⎟
⎝
⎠
where f is in kHz, or can be selected using Figure 1.
O
Inductor Core Selection
The maximum usable operating frequency is limited by
the minimum on-time and the duty cycle. This can be
calculated as:
Different core materials and shapes will change the
size/current and price/current relationship of an induc-
tor. Toroid or shielded pot cores in ferrite or permalloy
materials are small and don’t radiate much energy, but
generally cost more than powdered iron core inductors
with similar electrical characteristics. The choice of which
style inductor to use often depends more on the price vs
VOUT
fO(MAX) ≈ 6.67 •
(MHz)
V
IN(MAX)
The minimum frequency is internally set at around
200kHz
5000
T
= 25°C
A
4500
4000
3500
3000
2500
2000
1500
1000
500
0
0
400
800
(kΩ)
1200
1600
R
T
3561A F01
Figure 1. Frequency vs RT
3561af
10
LTC3561A
APPLICATIONS INFORMATION
sizerequirementsandanyradiatedfield/EMIrequirements
than on what the LTC3561A requires to operate. Table 1
shows some typical surface mount inductors that work
well in LTC3561A applications.
the diode peak current and average power dissipation
so as not to exceed the diode ratings. The main problem
with Schottky diodes is that their parasitic capacitance
reduces the efficiency, usually negating the possible
benefits for LTC3561A circuits. Another problem that a
Schottky diode can introduce is higher leakage current at
high temperatures, which could reduce the low current
efficiency.
Table 1. Representative Surface Mount Inductors
MANU-
FACTURER PARTNUMBER
MAXDC
VALUE CURRENT DCR HEIGHT
Toko
A914BYW-1R2M=P3:
D52LC
1.2μH 2.15A
44mΩ 2mm
Remember to keep lead lengths short and observe proper
grounding(seeBoardLayoutConsiderations)toavoidring-
ing and increased dissipation when using a catch diode.
A960AW-1R2M=P3:
D518LC
1.2μH
1.8A
46mΩ 1.8mm
DB3015C-1068AS-1R0N 1.0μH
DB3018C-1069AS-1R0N 1.0μH
DB3020C-1070AS-1R0N 1.0μH
2.1A
2.1A
2.1A
43mΩ 1.5mm
45mΩ 1.8mm
47mΩ 2mm
49mΩ 2mm
22mΩ 3mm
80mΩ 1mm
70mΩ 3mm
120mΩ 1mm
72mΩ 3mm
40mΩ 1.2mm
36mΩ 1.5mm
24mΩ 2mm
Input Capacitor (C ) Selection
IN
In continuous mode, the input current of the converter is a
A914BYW-2R2M-D52LC 2.2μH 2.05A
square wave with a duty cycle of approximately V /V .
OUT IN
A915AY-2ROM-D53LC
LPO1704-122ML
D01608C-222
2.0μH
1.2μH
2.2μH
2.2μH
1.0μH
1.0μH
1.2μH
1.1μH
1.0μH
1.1μH
3.3A
2.1A
2.3A
2.4A
2.1A
2.2A
2.2A
2.1A
Topreventlargevoltagetransients, alowequivalentseries
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:
Coilcraft
Sumida
LP01704-222M
CR32-1R0
CR5D11-1R0
VOUT(V − VOUT
)
IN
IRMS ≈ IMAX
CDRH3D14-1R2
CDRH4D18C/LD-1R1
CDRH4D28C/LD-1R0
CDRH4D28C-1R1
CDRH4D28-1R2
CDRH6D12-1R0
CDRH4D282R2
CDC5D232R2
V
IN
where the maximum average output current I
equals
3.0A 17.5mΩ 3mm
3.8A 22mΩ 3mm
MAX
the peak current minus half the peak-to-peak ripple cur-
rent, I = I – ΔI /2.
1.2μH 2.56A 23.6mΩ 3mm
1.0μH 2.80A 37.5mΩ 1.5mm
MAX
LIM
L
This formula has a maximum at V = 2V , where
IN
OUT
2.2μH 2.04A
2.2μH 2.16A
23mΩ 3mm
30mΩ 2.5mm
27mΩ 1.8mm
29mΩ 3.2mm
32mΩ 2.8mm
24mΩ 5mm
80mΩ 1mm
I
≅ I /2. This simple worst case is commonly used
RMS
OUT
to design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple cur-
rent ratings are often based on only 2000 hours lifetime.
This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required.Severalcapacitorsmayalsobeparalleledtomeet
thesizeorheightrequirementsofthedesign.Anadditional
0.1μF to 1μF ceramic capacitor is also recommended on
Taiyo
Yuden
NPO3SB1ROM
N06DB2R2M
1.0μH
2.2μH
2.2μH
2.2μH
0.9μH
2.6A
3.2A
2.9A
3.2A
1.4A
N05DB2R2M
Murata
FDK
LQN6C2R2M04
MIPW3226DORGM
Catch Diode Selection
V for high frequency decoupling, when not using an all
IN
Although unnecessary in most applications, a small im-
provement in efficiency can be obtained in a few applica-
tionsbyincludingtheoptionaldiodeD1showninFigure 4,
which conducts when the synchronous switch is off. In
pulse skip mode, the synchronous switch is turned off at
a low current and the remaining current will be carried by
the optional diode. It is important to adequately specify
ceramic capacitor solution.
Output Capacitor (C ) Selection
OUT
The selection of C
is driven by the required ESR to
OUT
minimizevoltagerippleandloadsteptransients. Typically,
once the ESR requirement is satisfied, the capacitance
3561af
11
LTC3561A
APPLICATIONS INFORMATION
withtraceinductancecanleadtosignificantringing.Other
capacitor types include the Panasonic specialty polymer
(SP) capacitors.
is adequate for filtering. The output ripple (ΔV ) is
OUT
determined by:
⎛
⎞
1
ΔVOUT ≈ ΔI ESR +
⎜
⎟
L
In most cases, 0.1μF to 1μF of ceramic capacitors should
also be placed close to the LTC3561A in parallel with the
main capacitors for high frequency decoupling.
8fOCOUT
⎝
⎠
wheref =operatingfrequency,C
=outputcapacitance
O
OUT
and ΔI = ripple current in the inductor. The output ripple
L
Ceramic Input and Output Capacitors
is highest at maximum input voltage since ΔI increases
L
with input voltage. With ΔI = 0.4 • I
the output
Higher value, lower cost ceramic capacitors are now be-
comingavailableinsmallercasesizes. Thesearetempting
for switching regulator use because of their very low ESR.
Unfortunately, the ESR is so low that it can cause loop
stability problems. Solid tantalum capacitor ESR gener-
ates a loop “zero” at 5kHz to 50kHz that is instrumental in
giving acceptable loop phase margin. Ceramic capacitors
remain capacitive to beyond 300kHz and usually resonate
with their ESL before their ESR becomes effective. Also,
ceramiccapsarepronetotemperatureeffectswhichrequire
the designer to check loop stability over the operating
temperaturerange.Tominimizetheirlargetemperatureand
voltage coefficients, only X5R or X7R ceramic capacitors
should be used. A good selection of ceramic capacitors
is available from Taiyo Yuden, TDK and Murata.
L
OUT(MAX)
ripplewillbelessthan100mVatmaximumV ,aminimum
IN
C
value of 10μF and f = 1MHz with:
OUT
O
ESRC
< 150mΩ
OUT
Once the ESR requirements for C
have been met, the
OUT
RMS current rating generally far exceeds the I
RIPPLE(P-P)
requirement, except for an all ceramic solution.
In surface mount applications, multiple capacitors may
havetobeparalleledtomeetthecapacitance, ESRorRMS
currenthandlingrequirementoftheapplication.Aluminum
electrolytic, special polymer, ceramic and dry tantalum
capacitorsareallavailableinsurfacemountpackages.The
OS-CONsemiconductordielectriccapacitoravailablefrom
Sanyo has the lowest ESR(size) product of any aluminum
electrolytic at a somewhat higher price. Special polymer
capacitors, such as Sanyo POSCAP, offer very low ESR,
but have a lower capacitance density than other types.
Tantalumcapacitorshavethehighestcapacitancedensity,
but it has a larger ESR and it is critical that the capacitors
are surge tested for use in switching power supplies.
An excellent choice is the AVX TPS series of surface
mount tantalums, available in case heights ranging from
2mm to 4mm. Aluminum electrolytic capacitors have a
significantly larger ESR, and is often used in extremely
cost-sensitive applications provided that consideration
is given to ripple current ratings and long term reliability.
Ceramic capacitors have the lowest ESR and cost but also
have the lowest capacitance density, a high voltage and
temperature coefficient and exhibit audible piezoelectric
effects. Inaddition, thehighQofceramiccapacitorsalong
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, suchasfromawalladapter, aloadstepattheoutput
can induce ringing at the V pin. At best, this ringing can
IN
couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
damage the part.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation
3561af
12
LTC3561A
APPLICATIONS INFORMATION
Keeping the current small (<5μA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
components and the output capacitor size. Typically, 3 to
4 cycles are required to respond to a load step, but only
in the first cycle does the output drop linearly. The output
droop, VDROOP, is usually about 2 to 3 times the linear
drop of the first cycle. Thus, a good place to start is with
the output capacitor value of approximately:
Toimprovethefrequencyresponse,afeed-forwardcapaci-
tor C may also be used. Great care should be taken to
F
route the V line away from noise sources, such as the
ΔIOUT
COUT ≈ 2.5
FB
inductor or the SW line.
fO • VDROOP
Shutdown and Soft-Start
More capacitance may be required depending on the duty
cycle and load step requirements.
The SHDN/R pin is a dual purpose pin that sets the oscil-
T
lator frequency and provides a means to shut down the
LTC3561A. This pin can be interfaced with control logic in
several ways, as shown in Figure 2 and Figure 3. In both
configurations, Run = “0” shuts down the LTC3561A and
Run = “1” activates the LTC3561A.
Inmostapplications,theinputcapacitorismerelyrequired
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10μF ceramic capacitor is
usually enough for these conditions.
Setting the Output Voltage
By activating the LTC3561A, an internal soft-start slowly
ramps the output voltage up until regulation. Soft-start
The LTC3561A develops a 0.8V reference voltage between
prevents surge currents from V by gradually ramping
the feedback pin, V , and the signal ground as shown in
IN
FB
theoutputvoltageupduringstart-up.Theoutputwillramp
from zero to full scale over a time period of approximately
0.8ms.ThispreventstheLTC3561Afromhavingtoquickly
charge the output capacitor and thus supplying an exces-
sive amount of instantaneous current.
Figure 4. The output voltage is set by a resistive divider
according to the following formula:
R2
⎠
R1
⎛
⎝
⎞
VOUT ≈ 0.8V 1+
⎜
⎟
SHDN/R
SV
IN
T
SHDN/R
T
R
1M
T
R
T
RUN
RUN
3561A F02
3561A F03
Figure 3. SHDN/RT Pin Activated with a Switch
Figure 2. SHDN/RT Pin Activated with a Logic Input
3561af
13
LTC3561A
APPLICATIONS INFORMATION
Checking Transient Response
ESR is the effective series resistance of C . ΔI
also
OUT LOAD
generating a feedback
begins to charge or discharge C
The OPTI-LOOP® compensation allows the transient re-
OUT
error signal used by the regulator to return V
to its
can
OUT
sponsetobeoptimizedforawiderangeofloadsandoutput
steady-state value. During this recovery time, V
OUT
capacitors. The availability of the I pin not only allows
TH
be monitored for overshoot or ringing that would indicate
a stability problem.
optimizationofthecontrolloopbehaviorbutalsoprovides
a DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling time at this test
point truly reflects the closed loop response. Assuming a
predominantlysecondordersystem,phasemarginand/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C.
If R is increased by the same factor that C is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, a feedforward capacitor
TheI externalcomponentsshowninthecircuitonpage1
TH
ofthisdatasheetwillprovideanadequatestartingpointfor
most applications. The series R-C filter sets the dominant
pole-zero loop compensation. The values can be modified
slightly (from 0.5 to 2 times their suggested values) to
optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
theloopfeedbackfactorgainandphase. Anoutputcurrent
pulse of 20% to 100% of full load current having a rise
C can be added to improve the high frequency response,
F
as shown in Figure 4. Capacitor C provides phase lead by
F
creating a high frequency zero with R2 which improves
the phase margin.
Theoutputvoltagesettlingbehaviorisrelatedtothestability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
time of 1μs to 10μs will produce output voltage and I
TH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
inputvoltageV dropstowardV ,theloadstepcapability
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V
im-
OUT
•ESR,where
IN
OUT
mediatelyshiftsbyanamountequaltoΔI
OPTI-LOOP is a registered trademark of Linear Technology Corporation.
LOAD
V
IN
+
R6
C6
C
IN
SV
IN
PV
IN
C8
SW
V
OUT
PGND
PGND
D1
OPTIONAL
+
LTC3561A
SGND
C
C
C5
OUT
C
F
I
V
FB
TH
PGND
PGND
R2
R
SGND PGND SHDN/R
T
C
ITH
R
T
R1
C
C
3561A F04
SGND
SGND
GND
SGND SGND
Figure 4. LTC3561A General Schematic
3561af
14
LTC3561A
APPLICATIONS INFORMATION
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil-
ity near dropout should use a different topology such as
SEPIC, Zeta or single inductor, positive buck/boost.
the losses in LTC3561A circuits: 1) LTC3561A V current,
IN
2
2) switching losses, 3) I R losses, 4) other losses.
1) The V current is the DC supply current given in the
IN
electrical characteristics which excludes MOSFET driver
Insomeapplications,amoreseveretransientcanbecaused
by switching in loads with large (>1μF) input capacitors.
Thedischargedinputcapacitorsareeffectivelyputinparal-
andcontrolcurrents.V currentresultsinasmall(<0.1%)
IN
loss that increases with V , even at no load.
IN
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
fromswitchingthegatecapacitanceofthepowerMOSFETs.
Each time a MOSFET gate is switched from low to high
lel with C , causing a rapid drop in V . No regulator
OUT
OUT
can deliver enough current to prevent this problem, if the
switchconnectingtheloadhaslowresistanceandisdriven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates cur-
rent limiting, short-circuit protection, and soft-starting.
to low again, a packet of charge dQ moves from V to
IN
ground. The resulting dQ/dt is a current out of V that is
IN
typically much larger than the DC bias current. In continu-
ous mode, I
= f (QT + QB), where QT and QB are
GATECHG
O
the gate charges of the internal top and bottom MOSFET
1
V
V
O
= 3.6V
= 1.2V TO 1.8V
= 1MHz
IN
OUT
switches. The gate charge losses are proportional to V
IN
f
and thus their effects will be more pronounced at higher
supply voltages.
0.1
0.01
2
3) I R Losses are calculated from the DC resistances of
the internal switches, R , and external inductor, R . In
SW
L
continuous mode, the average output current flowing
through inductor L is “chopped” between the internal top
and bottom switches. Thus, the series resistance look-
ing into the SW pin is a function of both top and bottom
0.001
0.1
1
10
100
1000
10000
MOSFET R
and the duty cycle (DC) as follows:
DS(ON)
LOAD CURRENT (mA)
3561A F01
R
= (R
TOP)(DC) + (R
BOT)(1 – DC)
SW
DS(ON)
DS(ON)
Figure 5. Power Loss vs Load Currrent
The R
for both the top and bottom MOSFETs can
DS(ON)
be obtained from the Typical Performance Characteristics
Efficiency Considerations
2
curves. Thus, to obtain I R losses:
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
2
2
I R losses = I
(R + R )
SW L
OUT
4)Other“hidden”lossessuchascoppertraceandinternal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important
to include these “system” level losses in the design of a
system.Theinternalbatteryandfuseresistancelossescan
%Efficiency = 100% – (L1 + L2 + L3 + ...)
beminimizedbymakingsurethatC hasadequatecharge
IN
where L1, L2, etc. are the individual losses as a percent-
age of input power.
storageandverylowESRattheswitchingfrequency.Other
lossesincludingdiodeconductionlossesduringdead-time
and inductor core losses which generally account for less
than 2% total additional loss.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
Hot Swap is a trademark of Linear Technology Corporation.
3561af
15
LTC3561A
APPLICATIONS INFORMATION
Thermal Considerations
Remembering that the above junction temperature is
obtained from an R at 25°C, we might recalculate
DS(ON)
In a majority of applications, the LTC3561A does not
dissipate much heat due to its high efficiency. However,
in applications where the LTC3561A is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
the junction temperature based on a higher R
since
DS(ON)
it increases with temperature. However, we can safely as-
sume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.
Design Example
As a design example, consider using the LTC3561A in
a portable application with a Li-Ion battery. The battery
provides a V = 2.5V to 4.2V. The load requirement is a
IN
ToavoidtheLTC3561Afromexceedingthemaximumjunc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
maximum of 1A, but most of the time it will be in standby
mode, requiring only 10mA. The output voltage is V
OUT
= 1.8V. Since the load still needs power in standby, Burst
Mode operation is selected for good low load efficiency.
First, calculate the timing resistor for 1MHz operation:
7
3 –1.6508
R = 5 • 10 (10 )
= 557.9k
Use a standard value of 549k. Next, calculate the inductor
value for about 40% ripple current at maximum V :
T
= P • θ
JA
T
RISE
D
where P is the power dissipated by the regulator and θ
D
JA
is the thermal resistance from the junction of the die to
IN
the ambient temperature.
1.8V
1MHz • 400mA
1.8V
4.2V
⎛
⎝
⎞
L =
• 1−
= 2.57μH
⎜
⎟
⎠
The junction temperature, T , is given by:
J
T = T
+ T
AMBIENT
J
RISE
Choosing the closest inductor from a vendor of 2.2μH,
results in a maximum ripple current of:
As an example, consider the case when the LTC3561A
is in dropout at an input voltage of 3.3V with a load cur-
rent of 1A. From the Typical Performance Characteristics
graph of Switch Resistance, the R
P-channel switch is 0.17Ω. Therefore, power dissipated
by the part is:
1.8V
1MHz • 2.2μH
1.8V
4.2V
⎛
⎝
⎞
ΔIL =
• 1−
= 468mA
⎜
⎟
⎠
resistance of the
DS(ON)
For cost reasons, a ceramic capacitor will be used. C
OUT
selection is then based on load step droop instead of ESR
2
P = I • R
= 170mW
D
DS(ON)
requirements. For a 5% output droop:
TheDD8packagejunction-to-ambientthermalresistance,
1A
θ , will be in the range of about 43°C/W. Therefore, the
JA
COUT ≈ 2.5
≅ 27μF
1MHz •(5% •1.8V)
junction temperature of the regulator operating in a 70°C
ambient temperature is approximately:
T = 0.17 • 43 + 70 = 77.31°C
J
3561af
16
LTC3561A
APPLICATIONS INFORMATION
The closest standard value is 22μF. Since the output
1. Does the capacitor CIN connect to the power VIN (Pin 5)
andpowerGND(Pin4)ascloseaspossible?Thiscapacitor
provides the AC current to the internal power MOSFETs
and their drivers.
impedance of a Li-Ion battery is very low, C is typically
IN
10μF. In noisy environments, decoupling SV from PV
IN
IN
with an R6/C8 filter of 1Ω/0.1μF may help, but is typically
not needed.
2. Are the C
OUT
and L1 closely connected? The (–) plate of
OUT
For the feedback resistors, choose R1 = 200k, R2 can be
calculated from:
C
returns current to PGND and the (–) plate of C .
IN
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C and a ground line termi-
⎛
⎝
⎞
VOUT
0.8
⎛
⎞
1.8V
0.8V
OUT
R2 =
– 1 •R1=
– 1 • 200k = 250k
⎜
⎝
⎟
⎠
nated near SGND (Exposed Pad). The feedback signal
⎜
⎟
⎠
V
should be routed away from noisy components and
FB
traces, such as the SW line (Pin 3), and its trace should
Choose a standard value of 249k for R2.
be minimized.
The compensation should be optimized for these compo-
nentsbyexaminingtheloadstepresponsebutagoodplace
to start for the LTC3561A is with a 16.9kΩ and 680pF filter.
The output capacitor may need to be increased depending
on the actual undershoot during a load step.
4. Keep sensitive components away from the SW pin. The
input capacitor C , the compensation capacitor C and
IN
C
C
ITH
and all the resistors R1, R2, R , and R should be
T C
routed away from the SW trace and the inductor L1. The
SW pin pad should be kept as small as possible.
Board Layout Considerations
5. A ground plane is preferred, but if not available, route all
small-signal components back to the SGND pin (Exposed
Pad).AllSGNDandPGNDpinsmustbeconnectedtogether
through a thick copper trace or ground plane.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3561A. These items are also illustrated graphically
in the layout diagram of Figure 6. Check the following in
your layout:
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of power
components. These copper areas should be connected to
the Exposed Pad for best results.
C
IN
V
IN
C
OUT
V
PV
SV
PGND
SW
IN
L1
IN
OUT
LTC3561A
SGND
SHDN/R
V
FB
I
TH
T
R2
R1
R
C
R
T
C4
C
C
ITH
C
3561A F06
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 6. LTC3561A Layout Diagram (See Board Layout Checklist)
3561af
17
LTC3561A
TYPICAL APPLICATION
General Purpose Buck Regulator Using Ceramic Capacitors
V
IN
2.5V TO
5.5V
C1
22μF
PV
IN
L1
2.2μH
SV
IN
PGND
V
OUT
SW
1.2V/1.5V/1.8V
AT 1A
LTC3561A
R2 249k
V
FB
I
SHDN/R
T
TH
1.8V
1.5V
1.2V
C2
22μF
SGND
PGND
C4 22pF
R3
16.9k
C3
R4
549k
R1A
200k
R1B
287k
R1C
499k
680pF
3561A TA02a
SGND
GND
SGND
PGND
NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A914BYW-2R2M (D52LC SERIES)
Efficiency vs Output Current
100
V
= 1.2V
OUT
90
80
70
60
50
40
30
20
10
0
V
V
V
= 2.7V
= 3.6V
= 4.2V
IN
IN
IN
1
10
100
1000
10000
OUTPUT CURRENT (mA)
3561A TA02b
V
V
OUT
OUT
100mV/DIV
100mV/DIV
AC COUPLED
AC COUPLED
I
I
L
L
1A/DIV
1A/DIV
I
I
LOAD
LOAD
1A/DIV
1A/DIV
3561A TA02c
3561A TA02d
40μs/DIV
= 20mA TO 1A
V
V
I
= 3.6V
40μs/DIV
V
V
I
= 3.6V
IN
OUT
IN
= 1.2V
= 200mA TO 1A
= 1.2V
OUT
LOAD
LOAD
3561af
18
LTC3561A
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
0.675 0.05
3.5 0.05
2.15 0.05 (2 SIDES)
1.65 0.05
PACKAGE
OUTLINE
0.25 0.05
0.50
BSC
2.38 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
0.38 0.10
TYP
5
8
3.00 0.10
(4 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD) DFN 1203
4
1
0.25 0.05
0.75 0.05
0.200 REF
0.50 BSC
2.38 0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
3561af
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3561A
TYPICAL APPLICATIONS
1mm Height, 2MHz, Li-Ion to 1.8V Converter
V
IN
L1
0.9μH
2.5V
PV
SV
IN
V
OUT
TO 4.2V
SW
1.8V
IN
C1
10μF
C4 22pF
AT 1A
C2
LTC3561A
10μF
s2
I
TH
V
FB
R2
249k
R1
200k
R3
SGND PGND SHDN/R
T
16.9k
R4
178k
C3
470pF
C1, C2: TAIYO YUDEN JMK107BJ106MA
L1: FDK MIPW3226DORGM
3561A TA04a
Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
V
V
OUT
OUT
100mV/DIV
100mV/DIV
AC COUPLED
AC COUPLED
I
I
L
L
1A/DIV
1A/DIV
I
I
LOAD
1A/DIV
LOAD
1A/DIV
V
IN
V
IN
V
IN
= 2.7V
= 3.6V
= 4.2V
3561A TA04c
3561A TA04d
40μs/DIV
V
= 3.6V
= 1.8V
40μs/DIV
= 200mA TO 1A
IN
IN
V
I
OUT
= 30mA TO 1A
LOAD
1
10
100
1000
10000
OUTPUT CURRENT (mA)
3561A TA04b
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
96% Efficiency, V : 2.5V to 5.5V, V
LTC3406/LTC3406B 600mA (I ), 1.5MHz Synchronous Step-Down DC/DC Converters
= 0.6V,
= 0.6V,
= 0.8V,
= 0.8V,
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
™
I = 20μA, I < 1μA, ThinSOT
Q
SD
LTC3407/LTC3407B Dual 600mA/800mA (I ), 1.5MHz/2.25MHz Synchronous
95% Efficiency, V : 2.5V to 5.5V, V
IN
OUT
Step-Down DC/DC Converters
I = 40μA, I < 1μA, MS10E, DFN
Q SD
LTC3410/LTC3410B 300mA (I ), 2.25MHz Synchronous Step-Down DC/DC Converters 95% Efficiency, V : 2.5V to 5.5V, V
OUT
IN
I = 26μA, I < 1μA, SC70
Q
SD
LTC3411A
LTC3412A
1.25A (I ), 4MHz Synchronous Step-Down DC/DC Converter
96% Efficiency, V : 2.6V to 5.5V, V
IN
OUT
I = 60μA, I < 1μA, MS10, 3mm × 3mm DFN
Q
SD
2.5A (I ), 4MHz Synchronous Step-Down DC/DC Converter
96% Efficiency, V : 2.6V to 5.5V, V
= 0.8V,
OUT
IN
OUT(MIN)
I = 62μA, I < 1μA, TSSOP16E, 4mm × 4mm QFN
Q
SD
LTC3531/LTC3531-3 200mA (I ), 1.5MHz Synchronous Buck-Boost DC/DC Converters 95% Efficiency, V : 1.8V to 5.5V, V
= 2V to 5V,
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
LTC3531-3.3
LTC3532
I = 16μA, I < 1μA, ThinSOT, DFN
Q SD
500mA (I ), 2MHz Synchronous Buck-Boost DC/DC Converter
95% Efficiency, V : 2.4V to 5.5V, V
= 2.4V to 5.25V,
= 0.6V,
OUT
IN
I = 35μA, I < 1μA, MS10, DFN
Q
SD
LTC3542
LTC3544
500mA (I ), 2.25MHz Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
IN
OUT
I = 26μA, I < 1μA, 2mm × 2mm DFN
Q
SD
Quad 300mA + 2× 200mA + 100mA, 2.25MHz Synchronous
Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V,
IN
OUT(MIN)
I = 70μA, I < 1μA, 3mm × 3mm QFN
Q
SD
LTC3547/LTC3547B Dual 300mA, 2.25MHz Synchronous Step-Down DC/DC Converters
96% Efficiency, V : 2.5V to 5.5V, V
= 0.6V,
IN
OUT(MIN)
I = 40μA, I < 1μA, 2mm × 3mm DFN
Q
SD
LTC3548/LTC3548-1 Dual 400mA/800mA, (I ), 2.25MHz Synchronous Step-Down
95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V,
OUT
IN
OUT(MIN)
LTC3548-2
LTC3560
DC/DC Converters
I = 40μA, I < 1μA, MS10E, DFN
Q SD
800mA (I ), 2.25MHz Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V,
OUT
IN
OUT(MIN)
I = 16μA, I < 1μA, ThinSOT
Q
SD
ThinSOT is a trademark of Linear Technology Corporation.
3561af
LT 0708 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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