LTC3785EUF [Linear]
10V, High Effi ciency, Synchronous, No RSENSE Buck-Boost Controller; 10V ，高效率艾菲，同步，无检测电阻器降压 - 升压型控制器
| 型号： | LTC3785EUF |
| 厂家： | 
Linear |
| 描述： | 10V, High Effi ciency, Synchronous, No RSENSE Buck-Boost Controller |
| 文件： | 总20页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3785
10V, High Efficiency,
TM
Synchronous, No R
SENSE
Buck-Boost Controller
U
DESCRIPTIO
FEATURES
The LTC®3785 is a high power synchronous buck-boost
controller that drives all N-channel power MOSFETs from
input voltages above, below and equal to the output volt-
age. With an input range of 2.7V to 10V, the LTC3785 is
well suited for a wide variety of single or dual cell Li-Ion
or multi-cell alkaline/NiMH applications.
■
Single Inductor Architecture Allows V Above,
IN
Below or Equal to V
OUT
■
■
■
■
■
■
■
■
■
■
■
2.7V to 10V Input and Output Range
Up to 96% Efficiency
Up to 10A of Output Current
All N-Channel MOSFETs, No R
SENSE
True Output Disconnect During Shutdown
Programmable Current Limit and Soft-Start
Optional Short-Circuit Shutdown Timer
Output Overvoltage and Undervoltage Protection
Programmable Frequency: 100kHz to 1MHz
Selectable Burst Mode® Operation
Available in 24-Lead (4mm × 4mm) Exposed Pad
QFN Package
The operating frequency can be programmed from
100kHz to 1MHz. The soft-start time and current limit are
also programmable. The soft-start capacitor doubles as
the fault timer which can program the IC to latch off or
recycle after a determined off time. Burst Mode opera-
tion is user controlled and can be enabled by driving the
MODE pin high.
Protection features include foldback current limit, short-
circuit and overvoltage protection.
U
APPLICATIO S
, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology
■
Palmtop Computers
Corporation. No R
is a trademark of Linear Technology Corporation.
SENSE
All other trademarks are the property of their respective owners.
■
Handheld Instruments
■
Wireless Modems
Cellular Telephones
■
U
TYPICAL APPLICATIO
V
IN
2.7V
V
OUT
4.7µF
TO 10V
V
IN
V
CC
I
SVIN
TG1
Efficiency vs Input Voltage
22µF
V
SENSE
100
V
= 3.3V
= 500kHz
V
OUT
OSC
BST1
F
SW1
FB
I
SSW1
V
DRV
BG1
95
90
85
4.7µH
I
= 2A
LOAD
LTC3785
I
V
C
I
LOAD
= 1A
V
3.3V
5A
OUT
RT
SVOUT
TG2
MODE
V
BST2
2.5
5.5
7
8.5
10
RUN/SS
SW2
SSW2
4
100µF
I
I
LSET
V
(V)
IN
3785 TA01b
CCM
BG2
GND
3785 TA01a
3785f
1
LTC3785
W W U W
ABSOLUTE AXI U RATI GS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Input Supply Voltage (V )......................... –0.3V to 11V
IN
I
, I
.............................................. –0.3V to 11V
SVOUT SVIN
SW1, SW2, I
, I
Voltage:
24 23 22 21 20 19
SSW1 SSW2
DC............................................................. –1V to 11V
Pulsed, <1µs............................................. –2V to 12V
RUN/SS
1
2
3
4
5
6
18
17
16
I
SSW1
V
C
BG1
V
FB
DRV
RUN/SS, MODE, CCM, V , V Voltages...... –0.3V to 6V
DRV CC
25
V
15 BG2
14
13 SW2
SENSE
TG1, V
Voltages................................... –0.3V to 16V
BST1
I
I
LSET
SSW2
With Respect to SW1............................... –0.3V to 6V
TG2, V Voltages................................... –0.3V to 16V
CCM
BST2
7
8
9 10 11 12
With Respect to SW2............................... –0.3V to 6V
BG1, BG2 Voltage ........................................ –0.3V to 6V
Peak Driver Output Current < 10µs
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
= 125°C, θ = 40°C/W 1 LAYER BOARD, θ = 30°C/W 4 LAYER BOARD
(TG1, TG2, BG1, BG2).................................................3A
T
JMAX
JA
JA
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
V
Average Output Current.................................100mA
CC
Operating Temperature Range ................. –40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
ORDER INFORMATION
LEAD FREE FINISH
LTC3785EUF#PBF
LEAD BASED FINISH
LTC3785EUF
TAPE AND REEL
LTC3785EUF#TRPBF
TAPE AND REEL
LTC3785EUF#TR
PART MARKING
3785
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
24-Lead (4mm × 4mm) Plastic QFN
PACKAGE DESCRIPTION
PART MARKING
3785
TEMPERATURE RANGE
–40°C to 85°C
24-Lead (4mm × 4mm) Plastic QFN
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The
●
denotes the specifications which apply over the full operating
= V = V = V = 3.6V, R = 49.9k, R = 59k.
temperature range, otherwise specifications are at T = 25°C. V = V
A
IN
OUT
DRV
BST1
BST2
T
ILSET
MAX
PARAMETER
Supply
CONDITIONS
MIN
TYP
UNITS
V
IN
●
Input Operating Voltage
Quiescent Current—Burst Mode Operation
Quiescent Current—Shutdown
Quiescent Current—Active
Error Amp
2.7
10
200
25
V
µA
V = 0V, MODE = 3.6V (Note 4)
86
15
0.8
C
RUN/SS = 0V, V
= 0V
µA
OUT
MODE = 0V (Note 4)
1.5
mA
●
Feedback Voltage
(Note 5)
(Note 5)
1.200
1.225
1
1.25
500
V
nA
µA
µA
dB
Feedback Input Current
Error Amp Source Current
Error Amp Sink Current
–500
900
90
Error Amp A
VOL
●
Overvoltage Threshold
V
SENSE
Pin. % Above FB
6
10
14
%
3785f
2
LTC3785
ELECTRICAL CHARACTERISTICS The
●
denotes the specifications which apply over the full operating
= V = V = V = 3.6V, R = 49.9k, R = 59k.
temperature range, otherwise specifications are at T = 25°C. V = V
A
IN
OUT
DRV
BST1
BST2
T
ILSET
MAX
PARAMETER
CONDITIONS
MIN
TYP
–6.5
1
UNITS
%
●
Undervoltage Threshold
V
V
Pin. % Below FB
–3.5
–9.5
500
SENSE
SENSE
V
V
V
V
V
Input Current
= Measured FB Voltage
nA
SENSE
Regulator
CC
CC
CC
CC
●
●
Maximum Regulating Voltage
Regulation Voltage
V
V
V
= 5V, I
= –20mA
4.15
3.3
4.35
3.5
4.55
3.6
V
V
IN
VCC
= 3.6V, I
= –20mA
VCC
IN
Regulator Sink Current
= V = 5V
800
µA
OUT
CC
Run/Soft-Start
●
RUN/SS Threshold
When IC is Enabled
0.35
0.7
1.9
1.1
5
V
V
When EA is at Maximum Boost Duty Cycle
RUN/SS Input Current
RUN/SS Discharge Current
Current Limit
RUN/SS = 0V
–1
1
µA
µA
During Current Limit
●
●
Current Limit Sense Threshold
I
I
to I
to I
, R
SSW1 ILSET
SSW1 ILSET
= 121k
= 59k
20
55
60
105
100
155
mV
mV
SVIN
SVIN
, R
●
●
Reverse Current Limit Sense Threshold
Input Current
I
I
to I
, CCM > 2V
–50
2.2
0.8
–110
–15
–170
–35
mV
mV
SSW2
SSW2
SVOUT
SVOUT
to I
, CCM < 0.4V
I
I
I
80
10
0.1
150
20
5
µA
µA
µA
SVIN
SVOUT
SSW1 SSW2
, I
●
●
CCM Input Threshold (High)
CCM Input Threshold (Low)
CCM Input Current
V
V
0.4
1
0.01
µA
Burst Mode Operation
Mode Threshold
●
1.5
0.01
1.4
2.2
1
V
µA
µs
Mode Input Current
t
ON
Time
Oscillator
●
●
Frequency Accuracy
Switching Characteristics
Maximum Duty Cycle
370
80
509
650
kHz
Boost (% Switch BG2 On)
Buck (% Switch TG1 On)
90
99
%
%
Ω
Ω
TG1, TG2 Driver Impedance
BG1, BG2 Driver Impedance
TG1, TG2 Rise Time
2
2
C
C
C
C
= 3300pF (Note 3)
= 3300pF (Note 3)
= 3300pF (Note 3)
= 3300pF (Note 3)
20
20
20
20
100
100
ns
ns
ns
ns
ns
ns
LOAD
LOAD
LOAD
LOAD
BG1, BG2 Rise Time
TG1, TG2 Fall Time
BG1, BG2 Fall Time
Buck Driver Nonoverlap Time
Boost Driver Nonoverlap Time
TG1 to BG1
TG2 to BG2
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: Specification is guaranteed by design and not 100% tested in production.
Note 4: Current measurements are performed when the outputs are not switching.
Note 5: The IC is tested in a feedback loop to make the measurement.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3785E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over –40°C to 85°C operating
3785f
3
LTC3785
U W
TYPICAL PERFOR A CE CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Li-Ion/9V to 5V V
Load Current
Efficiency vs
Li-Ion to 3.3V Efficiency vs
Load Current
Two Li-Ion to 7V Efficiency vs
Load Current
OUT
100
90
100
90
80
70
60
50
40
30
20
10
0
100
90
Burst Mode
OPERATION
Burst Mode
OPERATION
Burst Mode
OPERATION
80
80
70
70
FIXED
FIXED
FIXED
FREQUENCY
60
50
60
50
FREQUENCY
FREQUENCY
V
V
V
V
= 9V
IN
IN
IN
IN
40
30
20
10
0
40
30
20
10
0
V
= 4.2V
= 3.6V
= 3V
V
V
V
= 8.4V
= 7.2V
= 5.4V
= 4.2V
= 3.6V
= 2.7V
IN
IN
IN
IN
V
IN
V
IN
MOSFET Si7940
MOSFET Si7940
MOSFET Si7940
L = 4.7µH WURTH WE-PD
L = 5.6µH MSS1260
L = 5.6µH MSS1260
f
= 500kHz
f
= 430kHz
f
= 430kHz
OSC
OSC
OSC
0.0001 0.001
0.01
0.1
1
10
0.0001 0.001
0.01
0.1
1
10
0.0001 0.001
0.01
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
3785 G02
3785 G02
3785 G01
Line Transient Response
V
OUT
Load Transient
Burst Mode Ripple
V
OUT
V
OUT
500mV/
DIV
200mV/
DIV
V
OUT
50mV/DIV
AC
COUPLED
V
IN
3V TO
8.5V
I
LOAD
INDUCTOR
CURRENT
1A/DIV
10mATO 2A
3785 G05
I
V
C
= 300mA 500µs/DIV
LOAD
OUT
OUT
3785 G06
V
V
C
= 3.6V
100µs/DIV
= 5V
IN
3785 G04
V
OUT
C
OUT
= 3.3V
= 100µF
5µs/DIV
= 3.3V
= 100µF
OUT
OUT
= 100µF
Normalized Oscillator Frequency
vs Temperature
V
FB
vs Temperature
Oscillator Frequency vs RT
1200
1000
1.2255
1.2250
1.2245
1.2240
1.2235
1.2230
1.2225
1.2220
1.2215
1.2210
1.0
0.8
0.6
0.4
800
600
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
400
200
0
20
40
60
RT (kΩ)
80
100
50
TEMPERATURE (°C)
100
–50 –25
25
50
75
100
–50 –25
0
25
75
0
TEMPERATURE (°C)
3785 G09
3785 G07
3785 G08
3785f
4
LTC3785
U W
TYPICAL PERFOR A CE CHARACTERISTICS (T = 25°C unless otherwise noted)
A
V
Start-Up Voltage vs
V
Burst Quiescent Current vs
OV and UV Thresholds vs
Temperature
IN
IN
Temperature
Temperature
2.490
2.485
2.480
2.475
100
95
90
85
80
12
10
8
OV THRESHOLD
6
4
2
0
–2
–4
–6
–8
2.470
2.465
UV THRESHOLD
–50
0
25
50
75
100
–25
–50 –25
25
50
75
100
0
–50 –25
25
50
75
100
0
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3785 G10
3785 G11
3785 G12
U
U
U
PI FU CTIO S
V
(Pin 4): Overvoltage and Undervoltage Sense.
RUN/SS (Pin 1): Run Control and Soft-Start Input. An
internal 1µA charges the soft-start capacitor and will
charge to approximately 2.5V. During a current limit fault,
the soft-start capacitor will incrementally discharge. Once
the pin drops below 1.225V the IC will enter fault mode,
turning off the outputs for 32 times the soft-start time. If
>5µA (at RUN/SS = 1.225V) is applied externally, the part
will latch off after a fault is detected. If >40µA (at RUN/SS
= 1.225V) is applied externally, current limit faults will not
discharge the SS capacitor.
SENSE
The overvoltage threshold is internally set 10% above
the regulated FB voltage and the undervoltage threshold
is internally set 6.5% below the FB regulated voltage. This
pin can be tied to FB but to optimize the response time it
is recommended that a voltage divider from V
be ap-
OUT
plied. The divider can be skewed from the feedback value
to achieve the desired UV or OV threshold.
I
(Pin 5): Current Limit Set. A resistor from this pin
LSET
to ground sets the current limit threshold from the I
SVIN
and I
pins.
V (Pin 2): Error Amp Output. A frequency compensation
C
SSW1
network is connected from this pin to the FB pin to com-
pensate the loop. See the section “Closing the Feedback
Loop” for guidelines.
CCM (Pin 6): Continuous Conduction Mode Control Pin.
Whensetlow, theinductorcurrentisallowedtogoslightly
negative (–15mV referenced to the I
– I
pins).
SVOUT
SSW2
Whendrivenhigh,thereversecurrentlimitissettothesimi-
lar value of the forward current limit set by the I pin.
FB (Pin 3): Feedback Pin. Connect resistor divider tap
here. The feedback reference voltage is typically 1.225V
The output voltage can be adjusted from 2.7V to 10V ac-
cording to the following formula:
LSET
RT (Pin 7): Oscillator Programming Pin. A resistor from
this pin to GND sets the free-running frequency of the IC.
f
≅ 2.5e10/RT.
OSC
R1+ R2
VOUT = 1.225V •
R2
3785f
5
LTC3785
U
U
U
PI FU CTIO S
MODE (Pin 8): Burst Mode Control Pin.
I
(Pin 18): Forward Current Limit Comparator Non-
SSW1
inverting Input. This pin is normally connected to the
• MODE = High: Enable Burst Mode Operation. In Burst
Mode operation the operation is variable frequency,
which provides a significant efficiency improvement
at light loads. The Burst Mode operation will continue
until the pin is driven low.
source of the N-channel MOSFET A (TG1 driven).
SW1 (Pin 19): Ground Reference for Driver A. Gate drive
from TG1 will reference to the common point of output
switches A and B.
• MODE=Low:DisableBurstModeoperationandmaintain
low noise, constant frequency operation.
TG1, TG2 (Pins 20, 12): Top gate drive pins drive the
top N-channel MOSFET switches A and D with a voltage
swing equal to V – V
superimposed on the SW1
CC
DIODE
NC (Pin 9): No Connect. There is no electrical connection
to this pin inside the package.
and SW2 nodes respectively.
V
(Pin 21): Boosted Floating Driver Supply for the
BST1
I
(Pin 10): Reverse Current Limit Comparator Non-
SVOUT
Buck Switch A. This pin will swing from a diode below
invertingInput. Thispinisnormallyconnectedtothedrain
V
CC
up to V + V – V
.
IN
CC
DIODE
of the N-channel MOSFET D (TG2 driven).
I
(Pin 22): Forward Current Limit Comparator Invert-
SVIN
V
(Pin 11): Boosted Floating Driver Supply for Boost
BST2
ing Input. This pin is normally connected to the drain of
Switch D. This pin will swing from a diode below V up
CC
N-channel MOSFET A (TG1 driven).
to V
+ V – V
.
OUT
CC
DIODE
V
(Pin 23): Internal 4.5V LDO Regulator Output. The
CC
SW2 (Pin 13): Ground Reference for Driver D. Gate drive
from TG2 will reference to the common point of output
switches C and D.
driver and control circuits are powered from this voltage
to limit the maximum VGS drive voltage. Decouple this pin
to power ground with at least a 4.7µF ceramic capacitor.
I
(Pin 14): Reverse Current Limit Comparator Invert-
SSW2
For low V applications, V can be bootstrapped from
IN
CC
ing Input. This pin is normally connected to the source of
V
OUT
through a Schottky diode.
the N-channel MOSFET D (TG2 driven).
V
(Pin 24): Input Supply Pin for the V Regulator. A
CC
IN
V
(Pin 16): Driver Supply for Ground Referenced
DRV
ceramic capacitor of at least 10µF is recommended close
Switches. Connect this pin to V potential.
CC
to the V and GND pins.
IN
BG1, BG2 (Pins 17, 15): Bottom gate driver pins drive
the ground referenced N-channel MOSFET switches B
and C.
Exposed Pad (Pin 25): The GND and PGND pins are con-
nected to the Exposed Pad which must be connected to
the PCB ground for electrical contact and rated thermal
performance.
3785f
6
LTC3785
W
BLOCK DIAGRA
V
IN
2.7V TO 10V
24
V
IN
1.225V
+
–
–
+
FAULT
TSD
100% DUTY
CHARGE PUMP
LOGIC
1.225V
V
4.5V REG
IDEAL DIODE
REF
C
VCC
V
CC
V
+
23
22
BE
RUN UVLO
I
2.4V
–
SVIN
1/25k
I
+
–
LIMIT
g
m
1µA
C
SS
RUN/SS
1
V = 60k/R
ILSET
2µA
TG1
ADRV
MA
C
20
21
19
18
16
17
IN
V
I
+
–
BST1
LIM(OUT)
I
+
–
X10
SW1
I
LIM(OUT)
MAX
C
A
SW1
10µA MAX
V = 90k/R
ILSET
I
SSW1
SAMPLED
TG1
BBM
SW1
DELAY
D1
SW1
PULSE
OPT
V
DRV
–6.5%
+10%
+
–
UV
BG1
UV
OV
V
V
OUT
OUT
BG1
BDRV
MB
–
+
OV
V
OUT
LOW
–
+
V
SENSE
1.8V
4
TG2
BG2
PGND
BBM
SW2
DELAY
SW2
PULSE
15mV
OR
1X I
+
–
L1
1.225V
+
–
R1
100% DUTY
CHARGE PUMP
FB
LIMIT
3
2
I
DISABLE
SVOUT
TG2
C
P1
V
10
R2
OUT
REVERSE
LIMIT
V
C
D2
OPT
V
REV
REVERSE
CURRENT LIMIT
(ZERO LIMIT FOR BURST)
R
T
RT
MD
DDRV
12
11
OSC
7
V
BST2
1 = Burst Mode OPERATION
0 = FIXED FREQUENCY
C
B
SW2
–
+
13
14
1.5V
SW2
MC
BURST
LOGIC
BURST
MODE
I
SSW2
8
5
SAMPLED
V
DRV
SS
BG2
CDRV
15
6
C
OUT
R
ILSET
I
LSET
I
I
COMP
COMP
I
LIM
LIMIT
SET
MAX
PGND
1/2 LIMIT AT V
< 1V
OUT
CCM
0 = 15mV
V
REV
1 = I
LIMIT
GND/PGND
25
3785 BD
3785f
7
LTC3785
U
OPERATIO
MAIN CONTROL LOOP
V
V
OUT
IN
The LTC3785 is a buck-boost voltage mode controller
that provides an output voltage above, equal to or below
the input voltage.
TG1
BG1
D
A
TG2
BG2
L
SW1
SW2
C
B
TheLTCproprietarytopologyandcontrolarchitecturealso
employsdrain-to-sourcesensing(NoR )forforward
SENSE
3785 F01
and reverse current limiting. The controller provides
all N-channel MOSFET output switch drive, facilitating
single package multiple power switch technology along
Figure 1. Output Switch Configuration
90%
MAX
D
with lower R
. The error amp output voltage (V )
DS(ON)
C
BOOST
A ON, B OFF
BOOST REGION
determines the output duty cycle of the switches. Since
PWM C, D SWITCHES
D
the V pin is a filtered signal, it provides rejection of high
MIN
C
BOOST
frequency noise.
FOUR SWITCH PWM
BUCK/BOOST REGION
D
MAX
BUCK
The FB pin receives the voltage feedback signal, which
is compared to the internal reference voltage by the er-
ror amplifier. The top MOSFET drivers are biased from a
floating bootstrap capacitor, which is normally recharged
during each off cycle through an external diode when the
top MOSFET turns off. Optional Schottky diodes can be
connected across synchronous switch B and D to provide
a lower drop during the dead time and eliminate efficiency
loss due to body diode reverse recovery.
D ON, C OFF
BUCK REGION
PWM A, B SWITCHES
D
MIN
BUCK
3785 F02
Figure 2. Operation Mode vs V Voltage
C
theofftimeofswitchA, synchronousswitchBturnsonfor
theremainderoftheswitchingperiod.SwitchesAandBwill
alternate similar to a typical synchronous buck regulator.
As the control voltage increases, the duty cycle of switch
A increases until the max duty cycle of the converter in
The main control loop is shut down by pulling the RUN/
SS pin low. An internal 1µA current source charges the
RUN/SS pin and when the pin voltage is higher than 0.7V
buck mode reaches D
, given by:
MAX_BUCK
D
= 100 – D4(SW)%
MAX_BUCK
the IC is enabled. The V voltage is then clamped to the
C
RUN/SS voltage minus 0.7V while C is slowly charged
where D4(SW) = duty cycle % of the four switch range.
D4(SW) = (300ns • f) • 100%
SS
duringstart-up.This“soft-start”clampingpreventsinrush
current draw from the input power supply.
where f = operating frequency, Hz.
POWER SWITCH CONTROL
Beyond this point the “four switch” or buck-boost region
is reached.
Figure1showsasimplifieddiagramofhowthefourpower
switchesareconnectedtotheinductor,V ,V andGND.
Figure 2 shows the regions of operation for the LTC3785
as a function of duty cycle D. The power switches are
properly controlled so that the transfer between modes
is continuous.
If during the rectification phase (switch pair BD on) the
inductor current becomes discontinuous, then switch B is
turned off and a damping impedance is connected across
the inductor to prevent ringing.
IN OUT
Buck-Boost or Four Switch (V ~ V
)
OUT
IN
Buck Region (V > V
)
IN
OUT
When the error amp output voltage, V , is above ap-
C
Switch D is always on and switch C is always off during
proximately 0.65V, switch pair AD remain on for duty
buck mode. When the error amp output voltage, V , is ap-
cycle D
, and the switch pair AC begin to phase
C
MAX_BUCK
proximately above 0.1V, output A begins to switch. During
in. As switch pair AC phases in, switch pair BD phases out
3785f
8
LTC3785
U
OPERATIO
accordingly. When the V voltage reaches the edge of the
determined by an on time, t , and will terminate at zero
C
ON
buck-boost range, approximately 0.7V, the AC switch pair
completely phase out the BD pair, and the boost phase
begins at duty cycle, D4(SW).
current for each cycle. The on time is given by:
2.4
tON
=
V • f
Theinputvoltage,V ,wherethefourswitchregionbegins
IN
where f is the oscillator frequency.
The peak current is given by:
is given by:
VOUT
1– 300ns • f
V =
IN
V
(
)
V
L
IPEAK
=
IN • tON
the point at which the four switch region ends is given
by:
2.4
f •L
IPEAK
=
V = V (1 – D) = V (1 – 300ns • f) V
IN
OUT
OUT
So the peak current is independent of V and inversely
proportional to the f • L product optimizing the energy
transfer for various applications.
IN
If during the rectification phase (switch pair BD on) the
inductor current becomes discontinuous, then switch D is
turned off and a damping impedance is connected across
the inductor to prevent ringing.
In Burst Mode operation the maximum output current is
given by:
Boost Region (V < V
)
IN
OUT
1.2 • V
IN
Switch A is always on and switch B is always off during
IOUT(MAX,BURST)
≈
A
f •L • VOUT + V
IN
boostmode. Whentheerrorampoutputvoltage, V , isap-
C
proximatelyabove0.7V,switchpairCandDwillalternately
switchtoprovideaboostedoutputvoltage. Thisoperation
is typical to a synchronous boost regulator. The maximum
duty cycle of the converter is limited to 90% typical.
Burst Mode operation is user-controlled by driving the
MODE pin high to enable and low to disable.
V
CC
REGULATOR
If during the rectification phase (switch pair AD on) the
inductor current becomes discontinuous then switch D is
turned off and a damping impedance is connected across
the inductor to prevent ringing.
An internal P-channel low dropout regulator produces
4.35V at the V pin from the V supply pin. V powers
CC
IN
CC
the drivers and internal circuitry of the LTC3785. The V
CC
pin regulator can supply a peak current of 100mA and
must be bypassed to ground with a minimum of 4.7µF
Burst Mode OPERATION
placed directly adjacent to the V and GND pins. Good
CC
bypassing is necessary to supply the high transient cur-
DuringBurstModeoperation,theLTC3785deliversenergy
to the output until it is regulated and then goes into a sleep
state where the outputs are off and the IC is consuming
only 86µA. In Burst Mode operation, the output ripple
has a variable frequency component, which is dependent
upon load current
rent required by the MOSFET gate drivers and to prevent
interactionbetweenchannels. Ifdesired, theV regulator
CC
can be connected to V
through a Schottky diode to
OUT
providehighergatedriveinlowinputvoltageapplications.
The V regulator can also be driven with an external 5V
CC
source directly (without a Schottky diode).
During the period where the converter is delivering en-
ergy to the output, the inductor will reach a peak current
3785f
9
LTC3785
U
OPERATIO
are configured around the amplifier to provide loop com-
pensationfortheconverter.TheRUN/SSpinwillclampthe
TOPSIDE MOSFET DRIVER SUPPLY (V
, V
)
BST1 BST2
The external bootstrap capacitors connected to the V
BST1
error amp output, V , to provide a soft-start function.
C
and V
pins supply the gate drive voltage for the top-
BST2
side MOSFET switches A and D. When the top MOSFET
switch A turns on, the switch node SW1 rises to V and
UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
IN
the V
pin rises to approximately V + V . When the
BST2
IN CC
The LTC3785 incorporates overvoltage (OV) and
undervoltage (UV) functions for fault protection and
transient limitation. Both comparators are connected
bottom MOSFET switch B turns on, the switch node SW1
drops low and the boost capacitor is charged through the
diode connected to V . When the top MOSFET switch D
CC
to the V
pin, which usually has a similar voltage
SENSE
turns on, the switch node SW2 rises to V
pin rises to approximately V
and the V
OUT
BST2
divider as the error amplifier without the compensation.
The overvoltage threshold is 10% above the reference.
The undervoltage threshold is 6.5% below the reference
with both comparators having 1% hysteresis. During an
overvoltage fault, all output switching stops until the fault
ceases.Duringanundervoltagefault,theICiscommanded
to run fixed frequency only (disabled Burst Mode opera-
tion). If the design requires a tightened threshold to one
of the comparator thresholds the voltage divider on the
+ V . When the bottom
OUT
CC
MOSFET switch C turns on, the switch node SW2 drops
low and the boost capacitor is charged through the diode
connectedtoV .Theboostcapacitorsneedtostoreabout
CC
100 times the gate charge required by the top MOSFET
switch A and D. In most applications a 0.1µF to 0.47µF,
X5R or X7R dielectric capacitor is adequate.
V
SENSE
pin can be skewed to achieve the threshold. Since
RUN/SOFT-START (RUN/SS)
the range is a constant, tightening the UV threshold will
loosen the OV threshold and vice versa.
The RUN/SS pin serves as the enable to the LTC3785,
soft-start function, and fault programming. A 1µA current
source charges the external capacitor. Once the RUN/SS
voltageisaboveadiodedrop(~0.7V)theICisenabled.Once
the IC is enabled, the RUN/SS voltage minus a diode drop
FORWARD CURRENT LIMIT
TheLTC3785isdesignedtosensetheinputcurrentbysam-
plingthevoltageacrossMOSFETAduringtheontimeofthe
(RUN/SS – 0.7V) clamps the output of the error amp (V )
C
to limit duty cycle. The range of the duty cycle clamping is
approximately 0.7V to 1.7V. The RUN/SS pin is clamped
to approximately 2.2V. If current limit is reached the pin
will begin to discharge with a current determined by the
magnitude of inductor current overcurrent limit, but not
to exceed 10µA. This function will be described in more
detail in the “Forward Current Limit” section.
switch (TG1 = High). The sense pins are I
and I
. A
SVIN
SSW1
currentsenseresistorcanbeusedifincreasedaccuracyis
required. The current limit threshold can be programmed
with a resistor on the I
pin. Once the desired current
ILSET
LSET
limit has been chosen, R
can be determined by the
following formula:
6000
RDS(ON)A •ILIMIT
RILSET
=
Ω
OSCILLATOR
where R
= R
of N-channel MOSFET switch A
DS(ON)A
DS(ON)
The frequency of operation is set through a resistor from
10
and I
= current limit in Amps.
LIMIT
the RT pin to ground where f ≅ (2.5e /RT)Hz.
Once the voltage between I
and I
exceeds the
SVIN
SSW1
threshold, current will be sourced out of FB to take control
of the voltage loop, resulting in a lower output voltage
to regulate the input current. This fault condition causes
the RUN/SS capacitor to begin discharging. The level of
ERROR AMP
The error amplifier is a voltage mode amplifier with a
reference voltage of 1.225V internally connected to the
non-inverting input. The loop compensation components
3785f
10
LTC3785
U
OPERATIO
the discharge current depends on how much the current
exceeds the programmed threshold. Figure 3 is a simpli-
fied diagram of the current sense and fault circuitry. If the
current limit fault duration is long enough to discharge the
RUN/SS capacitor below 1.225V, the fault latch is set and
will cycle the RUN/SS capacitor 16 times (1µA charging
and1µAdischargingoftheRUN/SScapacitor)tocreatean
off time of 32 times the soft-start time before the outputs
are allowed to switch to restart the output voltage. If the
current limit fault level exceeds 150% of the programmed
V
–0.7dividedbytheresistorvalue. Toignoreallfaults
OUT
sourcegreaterthan40µAintotheRUN/SSpin(At1.225Von
theRUN/SSpin).Sincethemaximumfaultcurrentislimited,
this will prevent any discharging of the RUN/SS capacitor,
the soft-start capacitor will need to be sized accordingly to
accommodatetheextrachargingcurrentatstart-up.
During an output short-circuit or if V
the current limit folds back to 50% of the programmed
level.
is less than 1.8V,
OUT
I
level at any time, the I
comparator is tripped and
LIMIT
MAX
REVERSE CURRENT LIMIT
output switches B and D are turned on to discharge the
inductor current for the remainder of the cycle.
The LTC3785 can be programmed to provide full class D
operation or allowed to source and sink current equal to
the current limit set value. This is achieved by asserting a
high level on the CCM pin. To minimize the reverse output
current, the CCM pin should be driven low or strapped to
ground. During this mode only, –15mV typical is allowed
To have the power converter latch-off on a fault, a pull-up
currentbetween4µAand7µAontheRUN/SSpinwillallow
the RUN/SS capacitor to discharge during an extended
fault,butwillpreventcyclingofthefaultwhichwillcausethe
converter to stay off. One method to implement this is by
placingadiode(anodetiedtoV )andaresistorfromV
totheRUN/SSpin.ThecurrentsourcedintoRUN/SSwillbe
across output switch D and is sensed with the I
and
SVOUT
OUT
OUT
I
pins.
SSW2
THERMAL SD
S FAULT
I
COMP
V
LIMIT
IN
1.225V
+
–
–
+
I
SVIN
TG1
g
= 1/20k
m
S LOGIC
+
–
22
20
g
m
A
V = 60k/R
ILSET
ILSET
WHEN V
0.7V
(15k/R
< 1.8V)
OUT
RUN
SW1
19
18
I
COMP
MAX
1µA
+
–
RUN/SS
TURN
I
+
–
X10
1
1
SSW1
SWITCHES
SAMPLED
C
SS
2.2V
B AND D ON
V = 90k/R
ILSET
1/3 • I
LIM(OUT)
10µA MAX
BG1 17
B
D
2µA
L1
CCM
6
CCM = HIGH = 6k/R
ILSET
CCM = LOW = 15mV
I
LIM(OUT)
30µA MAX
V
I
OUT
R1
SVOUT
TG2
–
+
+
–
V
10
12
OUT
SWITCH D
OFF
ERROR AMP
1.225V
+
–
C
OUT
REVERSE
CURRENT LIMIT
FB
3
2
C
P1
V
C
SW2
13
14
15
R2
I
SSW2
BG2
SAMPLED
I
LSET
I
I
COMP
COMP
I
LIM
LIMIT
SET
6
MAX
C
R
ILSET
3785 F03
Figure 3. Block Diagram of Current Limit Fault Circuitry
3785f
11
LTC3785
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APPLICATIO S I FOR ATIO
INDUCTOR SELECTION
This formula has a maximum at V = 2V , where I =
RMS
IN
OUT
I
/2.Thissimpleworst-caseconditioniscommonly
OUT(MAX)
The high frequency operation of the LTC3785 allows the
use of small surface mount inductors. The inductor cur-
rent ripple is typically set 20% to 40% of the maximum
inductor current. For a given ripple the inductance terms
are given as follows:
usedfordesignbecauseevensignificantdeviationsdonot
offer much relief. Note that ripple current ratings from ca-
pacitormanufacturersareoftenbasedononly2000hours
of life which makes it advisable to derate the capacitor.
In boost mode, the discontinuous current shifts from the
V
2 • VOUT – V
•100
input to the output, so C
must be capable of reducing
(
)
IN(MIN)
IN(MIN)
OUT
L >
, (Boost Mode)
the output voltage ripple. The effects of ESR (equivalent
series resistance) and the bulk capacitance must be
considered when choosing the right capacitor for a given
output ripple voltage. The steady ripple due to charging
and discharging the bulk capacitance is given by:
2
f •IOUT(MAX) • %Ripple • VOUT
VOUT • VIN(MAX) – VOUT •100
(
)
L >
, (Buck Mode)
f •IOUT(MAX) • %Ripple • V
IN(MAX)
where:
f = Operating frequency, Hz
%Ripple = Allowable inductor current ripple, %
= Minimum input voltage (limit to V /2
IOUT(MAX) • V
– V
IN(MIN)
(
)
OUT
VRIPPLE_BOOST
=
COUT • VOUT • f
VOUT • VIN(MAX) – V
(
)
OUT
V
VRIPPLE_BUCK
=
IN(MIN)
OUT
8 •L •COUT • VIN(MAX) • f2
minimum for worst case), V
V
V
= Maximum input voltage, V
where C = output filter capacitor, F
IN(MAX)
OUT
= Output voltage, V
OUT
The steady ripple due to the voltage drop across the ESR
is given by:
I
= Maximum output load current, A
OUT(MAX)
ΔV
= I
• ESR
Forhighefficiencychooseaninductorwithahighfrequency
core material, such as ferrite, to reduce core loses. The
inductorshouldhavelowESR(equivalentseriesresistance)
BOOST,ESR
L(MAX,BOOST)
V
IN(MAX) – VOUT • V
(
)
OUT
∆VBUCK,ESR
=
•ESR
2
L • f • V
to reduce the I R losses, and must be able to handle the
IN
peak inductor current without saturating. Molded chokes
or chip inductors usually do not have enough core to sup-
port the peak inductor currents in the 3A to 6A region. To
minimize radiated noise, use a toroid, pot core or shielded
bobbin inductor.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic
and ceramic capacitors are all available in surface mount
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
Capacitors are now available with low ESR and high ripple
current ratings such as OS-CON and POSCAP.
C AND C
SELECTION
IN
OUT
In boost mode, input current is continuous. In buck mode,
inputcurrentisdiscontinuous.Inbuckmode,theselection
POWER N-CHANNEL MOSFET SELECTION AND
EFFICIENCY CONSIDERATIONS
of input capacitor, C , is driven by the need to filter the
IN
input square wave current. Use a low ESR capacitor, sized
to handle the maximum RMS current. For buck operation,
the maximum RMS capacitor current is given by:
The LTC3785 requires four external N-channel power
MOSFETs, two for the top switches (switches A and D,
shown in Figure 1) and two for the bottom switches
(switches B and C shown in Figure 1). Important param-
⎛
⎞
VOUT
V
IN
VOUT
V
IN
IRMS ~IOUT(MAX)
•
• 1–
⎜
⎝
⎟
⎠
eters for the power MOSFETs are the breakdown voltage
3785f
12
LTC3785
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APPLICATIO S I FOR ATIO
BR(DSS)
V
,thresholdvoltageV
,on-resistanceR
,
Switch C operates in boost mode as the control switch. Its
power dissipation at maximum current is given by:
GS(TH)
DS(ON)
and maximum current
reverse transfer capacitance C
RSS
I
. The drive voltage is set by the 4.5V V supply.
DS(MAX)
CC
V
– V • V
V
IN
(
)
IN
2
OUT
OUT
Consequently,logic-levelthresholdMOSFETsmustbeused
in LTC3785 applications. If the input voltage is expected to
drop below 5V, then sub-logic threshold MOSFETs should
be considered. In order to select the power MOSFETs, the
power dissipated by the device must be known.
PC(BOOST) =
•IOUT(MAX)2 • ρT
IOUT(MAX)
3
• RDS(ON) + k • VOUT
•
•CRSS • f
V
IN
whereC isusuallyspecifiedbytheMOSFETmanufactur-
RSS
For switch A, the maximum power dissipation happens
ers. The constant k, which accounts for the loss caused by
reverse recovery current, is inversely proportional to the
gate drive current and has an empirical value of 1.0.
in boost mode, when it remains on all the time. Its maxi-
mum power dissipation at maximum output current is
given by:
For switch D, the maximum power dissipation happens in
boost mode when its duty cycle is higher than 50%. Its
maximum power dissipation at maximum output current
is given by:
2
⎛
⎜
⎞
VOUT
PA(BOOST) =
•IOUT(MAX) • ρT •RDS(ON)
⎟
⎠
⎝ V
IN
where ρT is a normalization factor (unity at 25°C) ac-
counting for the significant variation in on-resistance with
temperature,typicallyabout0.4%/°CasshowninFigure 4.
For a maximum junction temperature of 125°C, using a
value ρT = 1.5 is reasonable.
VOUT
V
IN
PD BOOST =
•IOUT(MAX)2 • ρT •RDS(ON)
(
)
Typically, switch A has the highest power dissipation and
switch B has the lowest power dissipation unless a short
occurs at the output. From a known power dissipated
in the power MOSFET, its junction temperature can be
obtained using the following formula:
Switch B operates in buck mode as the synchronous
rectifier. Its power dissipation at maximum output current
is given by:
V – VOUT
IN
T = T + P • R
PB(BUCK) =
•IOUT(MAX)2 • ρT •RDS(ON)
J
A
TH(JA)
V
IN
The R
to be used in the equation normally includes
TH(JA)
the R
for the device plus the thermal resistance from
TH(JC)
2.0
1.5
1.0
0.5
the case to the ambient temperature (R
). This value
TH(CA)
of T can then be compared to the original, assumed value
J
used in the iterative calculation process.
SCHOTTKY DIODE (D1, D2) SELECTION
Optional Schottky diodes D1 and D2 shown in the Block
Diagramconductduringthedeadtimebetweentheconduc-
tion of the power MOSFET switches. They are intended to
prevent the body diode of synchronous switches B and D
from turning on and storing charge during the dead time.
In particular, D2 significantly reduces reverse recovery
current between switch D turn off and switch C turn on,
which improves converter efficiency and reduces switch
C voltage stress. In order for D2 to be effective, it must
be located in very close proximity to SWD.
0
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
3785 F04
Figure 4. Normalized R
vs Temperature
DS(ON)
3785f
13
LTC3785
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APPLICATIO S I FOR ATIO
CLOSING THE FEEDBACK LOOP
The unity gain frequency of the error amplifier with the
type 1 compensation is given by:
The LTC3785 incorporates voltage mode control. The
control to output gain is given by:
1
fUG
=
2 • π •R1•CP1
GBuck = 1.6 • V , Buck Mode
IN
Mostapplicationsdemandanimprovedtransientresponse
toallowasmalleroutputfiltercapacitor.Toachieveahigher
bandwidth, type III compensation is required as shown in
Figure 6. Two zeros are required to compensate for the
double pole response.
1.6 • VOUT
GBOOST
=
2 , Boost Mode
V
IN
The output filter exhibits a double-pole response and is
given by:
1
fPOLE1
fZERO1
fZERO2
fPOLE2
≈
=
=
≈
(a very low frequency)
1
2 • π • 32e3 •CP1 •R1
fFILTER_POLE
=
2 • π • L •COUT
is the output filter capacitor.
1
where C
OUT
2 • π •RZ •CP1
The output filter zero is given by:
1
1
2 • π •R1•CZ1
fFILTER_ZERO
=
2 • π •RESR •COUT
1
whereR isthecapacitorequivalentseriesresistance.
ESR
2 • π •RZ •CP2
Atroublesomefeatureinboostmodeistherighthalfplane
zero (RHP), and is given by:
V
OUT
1.225V
+
2
V
R1
C
Z1
IN
ERROR
AMP
fRHPZ
=
FB
2 • π •IOUT •L • VOUT
–
C
P1
R2
V
C
The loop gain is typically rolled off before the RHP zero
frequency.
R
Z
C
P2
3785 F06
A simple type I compensation network (Figure 5) can be
incorporated to stabilize the loop but at a cost of reduced
bandwidthandslowertransientresponse.Toensureproper
phase margin, the loop must cross over almost a decade
before the L-C double pole.
Figure 6. Error Amplifier with Type III Compensation
EFFICIENCY CONSIDERATIONS
The percentage efficiency of a switching regulator is
equal to the output power divided by the input power
times 100%.
V
OUT
1.225V
FB
+
–
ERROR
AMP
R1
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in circuits produce losses, four main sources
account for most of the losses in LTC3785 application
circuits:
C
P1
R2
V
C
3785 F05
Figure 5. Error Amplifier with Type I Compensation
3785f
14
LTC3785
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2
1. DC I R losses. These arise from the resistances of the
Determine the Inductor Value
MOSFETs, sensing resistor (if used), inductor and PC
board traces and cause the efficiency to drop at high
output currents.
SettingtheInductorRippleto40%andusingtheequations
in the Inductor Selection section gives:
2
2.7 • 3.3 – 2.7 • 100
(
)
(
)
2. Transition loss. This loss arises from the brief voltage
transition time of switch A or switch C. It depends upon
theswitchvoltage,inductorcurrent,driverstrengthand
MOSFET capacitance, among other factors.
L >
= 0.67µH
2
500 • 103 • 3 • 40 • 3.3
(
)
3.3 • 10 – 3.3 • 100
500 • 103 • 3 • 40 • 10
(
)
L >
= 3.7µH
2
Transition Loss ~ V
• I • C
• f
SW
L
RSS
where C
is the reverse transfer capacitance.
Sotheworst-caserippleforthisapplicationisduringbuck
mode so a standard inductor value of 3.3µH is chosen.
RSS
3. C and C
loss. The input capacitor has the difficult
IN
OUT
joboffilteringthelargeRMSinputcurrenttotheregula-
tor in buck mode. The output capacitor has the more
difficult job of filtering the large RMS output current
Determine the Proper Inductor Type Selection
The highest inductor current is during boost mode and
is given by:
in boost mode. Both C and C
are required to have
IN
OUT
2
low ESR to minimize the AC I R loss and sufficient
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
VOUT •IOUT
IL(MAX_ AV)
=
V • η
IN
where η = estimated efficiency in this mode (use 80%).
4. Other losses. Optional Schottky diodes D1 and D2 are
responsible for conduction losses during dead time
and light load conduction periods. Core loss is the
predominant inductor loss at light loads. Turning on
switch C causes reverse recovery current loss in boost
mode.Whenmakingadjustmentstoimproveefficiency,
the input current is the best indicator of changes in
efficiency. If you make a change and the input current
decreases, then the efficiency has increased. If there
is no change in input current, then there is no change
in efficiency.
3.3 • 3
2.7 • 0.8
IL(MAX_ AV)
=
= 4.6A
To limit the maximum efficiency loss of the inductor ESR
to below 5% the equation is:
VOUT •IOUT • %Loss
IL(MAX_ AV)2 •100
ESRL(MAX)
~
= 24mΩ
AsuitableinductorforthisapplicationcouldbeaCoiltronics
CD1-3R8 which has a rating DC current of 6A and ESR
of 13mΩ.
5. V regulator loss. In applications where the input
CC
voltage is above 5V, such as two Li-Ion cells, the V
CC
Choose a Proper MOSFET Switch
regulator will dissipate some power due the differential
voltage and the average output current to the drive the
Using the same guidelines for ESR of the inductor, one
suitable MOSFET could be the Siliconix Si7940DP which
is a dual MOSFET in a surface mount package with 25mΩ
at 2.5V and a total gate charge of 12nC.
gates of the output switches. The V pin can be driven
CC
directly from a high efficiency external 5V source if
desired to incrementally improve overall efficiency at
lighter loads.
Checking the power dissipation of each switch will ensure
reliable operation since the thermal resistance of the
package is 60°C/W.
DESIGN EXAMPLE
As a design example, assume V = 2.7V to 10V (3.6V
IN
nominal Li-Ion with 9V adapter), V
= 3.3V (5%),
OUT
I
= 3A and f = 500kHz.
OUT(MAX)
3785f
15
LTC3785
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APPLICATIO S I FOR ATIO
The maximum power dissipation of switch A and C oc-
curs in boost mode. Assuming a junction temperature
Themaximumcurrentisset25%aboveI
toaccount
L(PEAK)
for worst-case variation at 100°C = 6A.
of T = 100°C with ρ
= 1.3, the power dissipation at
J
100C
6e3
RILSET
=
= 42k
V
= 2.7, and using the equations from the Efficiency
IN
0.025 • 6
Considerations section:
2
Choose the Input and Output Capacitance
⎛
⎞
3.3
2.7
PA(BOOST) =
PC(BOOST) =
• 3 • 1.3 • 0.025 = 0.43W
⎜
⎝
⎟
⎠
The input capacitance should filter current ripple which is
worst case in buck mode. Since the input current could
reach 6A, a capacitor ESR of 10mΩ or less will yield an
input ripple of 60mV.
3.3 – 2.7 • 3.3
(
)
• 32 • 1.3 • 0.025
2.72
3
+ 1• 3.33 •
• 0.45 – 9 • 500 • 103
The output capacitance should filter current ripple which
is worst in boost mode, but is usually dictated by the loop
response, the maximum load transient and the allowable
transient response.
2.7
= 0.09W
The maximum power dissipation of switch B and D occurs
in buck mode and is given by:
PC BOARD LAYOUT CHECKLIST
10 – 3.3
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
PB(BUCK) =
• 32 •1.3 • 0.025 = 0.20W
10
3.3
10
PD(BOOST) =
• 32 •1.3 • 0.025 = 0.10W
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
Now to double check the T of the package with 50°C
J
ambient. Since this is a dual NMOS package we can add
switches A + B and C + D worst case. For applications
wheretheMOSFETsareinseparatepackageseachdevice’s
• Place C , switch A, switch B and D1 in one compact
IN
area. Place C , switch C, switch D and D2 in one
OUT
compact area.
maximum T would have to be calculated.
J
• Useimmediateviastoconnectthecomponents(includ-
ing the LTC3785’s GND/PGND pin) to the ground plane.
Use several large vias for each power component.
T
= T + θ (PA + PB)
A JA
J(PKG1)
= 50 + 60 • (0.43 + 0.20) = 88°C
= T + θ (PC + PD)
T
J(PKG2)
A
JA
• Use planes for V and V
to maintain good voltage
OUT
IN
filtering and to keep power losses low.
= 50 + 60 • (0.09 + 0.10) = 60°C
• Floodallunusedareasonalllayerswithcopper.Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to any DC net
Set The Maximum Current Limit
The equation for setting the maximum current limit of the
IC is given by:
(V or GND). When laying out the printed circuit board,
IN
the following checklist should be used to ensure proper
operation of the LTC3785.
6e3
RILSET
=
Ω
RDS(ON)A •ILIMIT
3785f
16
LTC3785
U
W U U
APPLICATIO S I FOR ATIO
• Segregatethesignalandpowergrounds.Allsmall-signal
components should return to the GND pin at one point.
The sources of switch B and switch C should also con-
nect to one point at the GND of the IC.
• Connect the top driver boost capacitor C closely to
A
the V
and SW1 pins. Connect the top driver boost
BST1
capacitor C closely to the V
and SW2 pins.
B
BST2
• Connect the input capacitors C and output capaci-
IN
• Place switch B and switch C as close to the controller
as possible, keeping the PGND, BG and SW traces
short.
tors C
close to the power MOSFETs. These capaci-
OUT
tors carry the MOSFET AC current in boost and buck
mode.
• Keep the high dV/dT SW1, SW2, V
, V
, TG1 and
• Connect FB and V
pin resistive dividers to the (+)
BST1 BST2
SENSE
TG2 nodes away from sensitive small-signal nodes.
terminals of C
and signal ground. If a small V
OUT
SENSE
decoupling capacitor is used, it should be as close as
possible to the LTC3785 GND pin.
• The path formed by switch A, switch B, D1 and the C
IN
capacitorshouldhaveshortleadsandPCtracelengths.
The path formed by switch C, switch D, D2 and the
• Route I
and I
leads together with minimum PC
SSW1
SVIN
C
capacitor also should have short leads and PC
tracespacing.EnsureaccuratecurrentsensingwithKel-
OUT
trace lengths.
vin connections across MOSFET A or sense resistor.
•
Theoutputcapacitor(–)terminalsshouldbeconnected
as close as possible to the (–) terminals of the input
capacitor.
• Route I
and I
leads together with minimum
SSW2
SVOUT
PC trace spacing. Ensure accurate current sensing
with Kelvin connections across MOSFET D or sense
resistor.
• Connect the V decoupling capacitor C
closely to
CC
VCC
the V and PGND pins.
• Connect the feedback network close to IC, between the
CC
V and FB pins.
C
3785f
17
LTC3785
U
TYPICAL APPLICATIO
V
9V REGULATED
WALL ADAPTER
IN
2.7V TO 10V
+
C
VCC
Li-Ion
2.7V TO 4.2V
4.7µF
1nF
V
IN
RUN/SS
V
CC
I
205k
124k
SVIN
C
IN
MA = MB = MC = MD = 1/2 Si7940DY
L1 = SUMIDA CE123-4R6
V
TG1
MA
SENSE
22µF
CMDSH-3
D1 = D2 = PMEG2020EJ
V
C
A
BST1
270pF
0.22µF
SW1
OPTIONAL
D1
R1
205k
1.3k
I
SSW1
V
DRV
BG1
L1
4.7µH
FB
MB
MD
R2
121k
1nF
LTC3785
I
12k
V
C
V
3.3V
3A
OUT
RT
SVOUT
TG2
OPTIONAL
D2
R
T
59k
CMDSH-3
MODE
V
BST2
C
B
R
ILSET
0.22µF
SW2
42.2k
C
OUT
I
I
100µF
LSET
SSW2
CCM
BG2
MC
GND
3785 TA02
3785f
18
LTC3785
U
PACKAGE DESCRIPTIO
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 0.05
4.50 0.05
3.10 0.05
2.45 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
R = 0.115
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
0.75 0.05
4.00 0.10
(4 SIDES)
TYP
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 0.10
1
2
2.45 0.10
(4-SIDES)
(UF24) QFN 0105
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3785f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3785
U
TYPICAL APPLICATIO
Li-Ion/9V Wall Adapter to 5V/2A
V
9V REGULATED
WALL ADAPTER
IN
2.7V TO 10V
+
C
VCC
Li-Ion
2.7V TO 4.2V
4.7µF
1nF
V
IN
RUN/SS
V
CC
I
205k
124k
SVIN
C
IN
MA = MB = MC = MD = 1/2 Si7940DY
L1 = SUMIDA CE123-4R6
V
TG1
MA
SENSE
22µF
CMDSH-3
D1 = D2 = PMEG2020EJ
V
C
A
BST1
270pF
0.22µF
SW1
OPTIONAL
D1
205k
1.3k
I
SSW1
V
DRV
BG1
L1
4.7µH
FB
MB
MD
1nF
LTC3785
I
66.5k
12k
59k
V
C
V
5V
2A
OUT
RT
SVOUT
TG2
OPTIONAL
D2
CMDSH-3
MODE
V
BST2
C
B
0.22µF
SW2
C
42.2k
OUT
I
I
100µF
LSET
SSW2
CCM
BG2
MC
GND
3785 TA03
RELATED PARTS
PART
DESCRIPTION
COMMENTS
NUMBER
LTC3440
LTC3441
LTC3442
LTC3443
LTC3444
600mA I , 2MHz, Synchronous Buck-Boost DC/DC Converter
V : 2.5V to 5.5V, V : 2.5V to 5.5V, I = 25µA, I < 1µA,
OUT
IN
OUT
Q
SD
MS, DFN Packages
1.2A I , 1MHz, Synchronous Buck-Boost DC/DC Converter
V : 2.4V to 5.5V, V : 2.4V to 5.25V, I = 25µA, I < 1µA,
OUT
IN
OUT
Q
SD
DFN Package
1.2A I , 2MHz, Synchronous Buck-Boost DC/DC Converter
V : 2.4V to 5.5V, V : 2.4V to 5.25V, I = 35µA, I < 1µA,
OUT
IN
OUT
Q
SD
DFN Package
1.2A I , 600kHz, Synchronous Buck-Boost DC/DC Converter
V : 2.4V to 5.5V, V : 2.4V to 5.25V, I = 28µA, I < 1µA,
OUT
IN
OUT
Q
SD
MS Package
500mA I , 1.5MHz Synchronous Buck-Boost DC/DC Converter V : 2.7V to 5.5V, V : 0.5V to 5.25V, Optimized for WCDMA RF
OUT
IN
OUT
Amplifier Bias
LTC3531
LTC3531-3
LTC3531-3.3
200mA I , Synchronous Buck-Boost DC/DC Converter
V : 1.8V to 5.5V, V : 2V to 5V, I = 35µA, I < 1µA,
OUT
IN
OUT
Q
SD
MS, DFN Packages
LTC3532
LTC3533
LTC3780
500mA I , 2MHz, Synchronous Buck-Boost DC/DC Converter
V : 2.4V to 5.5V, V : 2.4V to 5.25V, I = 35µA, I < 1µA,
OUT
IN
OUT
Q
SD
MS, DFN Packages
2A Wide Input Voltage Synchronous Buck-Boost DC/DC Converter V : 1.8V to 5.5V, V : 1.8V to 5.25V, I = 40µA, I < 1µA,
IN
OUT
Q
SD
DFN Package
High Efficiency, Synchronous, 4-Switch Buck-Boost Controller
V : 4V to 36V, V : 0.8V to 30V, I = 1.5mA, I < 55µA,
IN OUT Q SD
SSOP-24, QFN-32 Packages
3785f
LT 0907 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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